fast aquisition system for 3d mapping of cosmological
TRANSCRIPT
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BAO project in radio
Fast aquisition systemfor 3D mapping of cosmological
matter distribution in radio
& NEBuLANumEriseur à Bande Large pour
l’Astronomie
NEBuLA ADC ADC
PCIe10
GbE
T&C
Fiber
s
2
BAO : Baryonic Acoustic Oscillations
• Imprints left by the baryon-photon fluid (before recombination) in the distribution of ordinary (baryonic) matter
• Slight modulation of the distribution of matter, (and galaxies as tracers). Structure formation being mainly driven by CDM which dominates structure formation
• In Radio : Use 21 cm HI emission • 3D HI mass distribution measurement through total 21 cm emission intensity mapping (No individual galaxy detection)• Hyperfine transition (spin-orbit) of atomic hydrogen: ν ≈ 1,420405 GHz →λ ≈ 21 cm
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Standard Interferometry
Array: resolution gain /d /D we can observe only some directions sin(N) = N./L For =30cm, () = 1’ D= 1km !!!
Antenna array Array and corrélation
Same gain in resolution With a correlator, all directions are available N(N-1)/2 independant correlations
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LNA
ADCFPGA
LNA
RF Prototype Board
IF
LO=1.2GHZ
IF
Low passFilterPass band
Filter
RF
RF
RFout
1
2
Gain=19DB
Gain=20DB
Gain=20DB 75 Ω40m 50 Ω
1-2m
PLL
Master Frequency
LO Prototype Board
RF Splitter 1/8
LO=1.2GHZ1
2345678
50MHz
Front panel plug-in (3U EuroCard)
RF amplifier, mixerLocal Oscillator
Antenna board
Phase-locked loop
Mixer
IF: Intermediate frequency
RF board: 75/50 inputs 2 channels per board Possibility of by-passing mixer to test the under-sampling approach.
Low-passFilter
Ampli
Ampli
Gain=30DB
Chaîne analogique
5
Système d'acquisition
DMA transfer Disk writing Cpu treatment Multi hardware tested Multi OS tested
PERC 5IController
PCIX
SATA 2
CPU Ram
SATA 2
FSB2000MB/s
x8
South bridge.....
North bridge.....
ALTERAPCIExpress
Ram
FFT 8K &Transfer
ctrl
ADCADC
FFT 8K &Transfer
ctrl
PCIEx bus
6
Test analogique PAON II
50 Ω8m
507/5 75 Ω50m
75 Ω10m
ADC
50 Ω1m
7575Ω
LNA
Ampli Intermédiaire 50 Ω
8m50/75 50 Ω
0.5m
ADC
50 Ω50m
LNA
Ampli Intermédiaire
Version actuelleVersion « améliorée”
Fréquence centrale 1375MhzBande passante 250MhzFréquence échantillonnage 500Mhz
Problématique : transfert d'un signal RF Large bande sur des distances > qq m
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AMPLI
AMPLI
AMPLI
AMPLI
Mixer + LO coaxial
Configuration globale
~ 8m liaison aérienne
~ 300m
~ 8m
Ethernet/USB
Power
Boîtier central
~40m gaineenterrée
8
4
ContainerContainer
Sas
Patch Pannel
PAON IV Configuration globale
Daniel Charlet 06/2016
NEBuLANumEriseur à Bande Large pour l’Astronomie
NEBuLA ADC
ADC
PCIe
10GbE
T&C
Fiber
s
Daniel Charlet 06/2016
PAON & NEBULA System
~300m
Clock & triggerDistribution(WR or custom)
~300m
20GByt/s
PCIExExt /Ethernet
~ 40db
ADC
NEBULA Board
FPGA
~ 40db
ADC
NEBULA Board
FPGA
~ 40db
ADC
NEBULA Board
FPGA
On the feed
Daniel Charlet 06/2016
Pour ce test on va sous-échantillonner un signal centré sur 1375 MHz, sur une largeur de bande de 250 MHz., soit l’intervalle [1250 MHz – 1500 MHz].
Undersampling the [1250 MHz – 1500 MHz] band. Central frequency = 1375 MHz, B.W. = 250 MHz
Fs = 500 MHz
Fs = 500 MHz
S+
S-S+
S- S+
S- S+ S-S+
S-
f (MHz)
S(f)
1250 1375 1500
750250-250
-1500 -1375 -1250
S+
S-
-750
S+
S-
k = 5 translations
Sous-echantillonnage 1
Daniel Charlet 06/2016
1. Signal frequency : F=1490 MHz (high limit)
10 MHz = -1490 MHz + 3 x 500 MHz (on observe dans la bande [0 – 250 MHz] la 3ème ([k+1]/2 = 6/2 = 3) translation de la raie négative. Le spectre est donc retourné par rapport au spectre d’origine [1250 – 1500 MHz]
S- is translated (3 times)
Reversed spectrum
Sous-echantillonnage 2
Daniel Charlet 06/2016
NEBULA Board
PCIExpress4x Gen2
10Gb Ethernet
10Gb Ethernet
Numericalfilter
ADC & systemmanagement
Developingframe
CDR
LocalOscillator
ARRIA V GT
White-RabbitTunable oscillator
Clock & synchro
20Gb/s
10Gb/s
10Gb/s
Input bandwidth : 2Ghz
ADC2x 1GSPS1x 2GSPS
Ethernet 1G
Ethernet 1G
PCIEx 4x(optionnel)
XTCA board
Clock & triggerManagement
& PPS
Testgenerator
Daniel Charlet 06/2016
Bus tree
SFP+X 3
PLLLMK04828
ADC08D1020
ycontrol
Power CTRLDS1014
IPMI
Eth-10G
PCIe
Eth-1G
SPII2C
SPI
FPGA ctrl/cde & conf
JTAG_conf
configSPI
Cde-ctrl & synchro
SSRAMCY7C1470BV25
(CY7C1480BV25)Flach x 2
EPLDMAXV
AM
C c
onne
ctor
iPass+8x
Molex
Ethernet white-Rabbit
Eth-1G
FrequencySynth.SI5326
Daniel Charlet 06/2016
Clock tree
FPGA
Si511125 MHz
DACAD5662
DAC 16bAD5662
VCTCXO25MHz
VCXO20MHz
DACAD5662DAC 16bAD5662
EthernetTxRx
SMA
DAC drive(spi)
125 MHz
20 MHz
SFP WR
EEPROMConfig DT
Mac adREFCLKR
LMK04828
Osc10 MHz
Ext PCIE
REFCLKL125 MHz
Ref CLK3 REFCLKR
ADC08D1020
REFCLKL
1 GHz
500 MHz
100MHz
REFCLKL
156.25 MHz
REFCLKR
Xtal25 MHz
ProgrammablePLL
Si5338AClock
distribution bufferSL18860DC
ArriaV Top
156.25 MHz
125 MHzArriaV BottomMaxV
50 MHz
Daniel Charlet 06/2016
Power tree
EN23FO
Core 1.1vVCC
EN23FO
1.2v
12v
FilterVCCP
EN5329 Filter
VCCL_GXBVCCR_GXB
VCCT_GXB
EN53292.5v
Filter
VCCIOVCPDVCCPGM (fct mod prog)
VCCAUXVCCA_FPLL
MAX8517Filter 2.5V SSRAM
Flash
VCCH_GXBVCCD_FPLLVCC_BAT
1.5v3.6v
1.1v
Seq 2
Seq 3
Seq 4
Transceiver1a max
MAX85271.9v
ADC2w max 0.8A
Filter
VCCA_GXB
3.3v
Iout 15
Iout 15
Iout 3a
Iout 1a
Seq 5
1.8vEN5329MAX5
3.3V Power-management
Vérifier 5339 versus 6347Composant en bibliotheque CPPM
Seq 1
Seq 3/4
Iout 3a
EN53292.2v
MAX8527
Seq 5
MAX8517 PLL 0.7a max3.3v
EN5329 Other component
Daniel Charlet 06/2016
Front side connectic
Connectic PCIe : iPass Molex 40,5mm en topA1-A13 PET0-PET3 Differential PCI Express Transmitter LanesA14-A16 CREFCLK Differential 100 MHz Cable Reference ClockA17 SB_RTN Signal Return for Single-Ended Sideband SignalsA18 CPRSNT# Cable Installed / Downstream Subsystem Powered-upA19 CPWRON Upstream Subsystem’s Power Valid NotificationB1-B13 PER0-PER3 Differential PCI Express Receiver LanesB14-B15 PWR +3.3V Power (Optional)B16-B17 PWR_RTN Return for +3.3V Power (Optional)B18 CWAKE# Power Management Signal for Wakeup Events (Optional)B19 CPERST# Cable PERST#
Ethernet 10G : QSFP+ 22.15mm en bottom
Ethernet 1G : SFP+PCIE 8x : iPass x8 en top
Input ADC : SMA 25mm en bordDe carte
Xtxa hight : 75mm
PCI 10G 10GSMA
40.5 22.15 10 10
SMA140
1G
14.5
Daniel Charlet 06/2016
PCIE over cable
Figure 2. PCIe Express Data Signals Using a PCIe Cable
http://www.onestopsystems.com/cables
http://www.molex.com/molex/products/datasheet.jsp?part=active/0745400201_IO_CONNECTORS.xml
Daniel Charlet 06/2016
White Rabbit
Synchronization with sub-ns accuracy and ps precision Combination of :
•Precision Time Protocol (PTP) Synchronization offset adjustement
•Synchronous Ethernet (SyncE) •Synchronization all network devices have the same frequency
•Digital Dual-Mixer Time Difference •(DDMTD) phase detection
Daniel Charlet 06/2016
Precision Time Protocol (IEEE1558)
• Packet-based synchronization protocol• Synchronizes local clock withthe master clock (all the network device• Link delay evaluated by measuring and exchanging packets tx/rx timestamps
Daniel Charlet 06/2016
Synchronous Ethernet (SyncE)
• All network devices use the same physical layer clock• Clock is encoded in the Ethernet carrier and recovered by the receiver chip (PHY).
Daniel Charlet 06/2016
DDMTD: Phase Tracking
• PTP limitation: timestamping granularity• Solution: take advantage of SyncE and measure phase shift
Daniel Charlet 06/2016
White Rabbit implementation
PHYSFP
DAC
REF clockgenerator
DMTD clockgenerator
GTR
EFC
LK
CLK125M_PLLREF
125 MHz
CLK20M_VCXO
20+ MHzDAC PLL
CLK
_DM
TD
VCXO
VCXO
SPI
Unique-ID(MAC-addr)
(optional)
FPGA
Your ownstuf
DATA(1 Gbps)
Timing(TAI[ns],REFCLK)
Daniel Charlet 06/2016
Conclusion
Carte en cours de design• Routage à la rentrée• Implantions sur PAON IV et RT• Projet sur RadioHéliographe• Tinlai Chine
Daniel Charlet 06/2016
Pour ce test on va sous-échantillonner un signal centré sur 1375 MHz, sur une largeur de bande de 250 MHz., soit l’intervalle [1250 MHz – 1500 MHz].
Undersampling the [1250 MHz – 1500 MHz] band. Central frequency = 1375 MHz, B.W. = 250 MHz
Fs = 500 MHz
Fs = 500 MHz
S+
S-S+
S- S+
S- S+ S-S+
S-
f (MHz)
S(f)
1250 1375 1500
750250-250
-1500 -1375 -1250
S+
S-
-750
S+
S-
k = 5 translations
Sous-echantillonnage 1
Daniel Charlet 06/2016
1. Signal frequency : F=1490 MHz (high limit)
10 MHz = -1490 MHz + 3 x 500 MHz (on observe dans la bande [0 – 250 MHz] la 3ème ([k+1]/2 = 6/2 = 3) translation de la raie négative. Le spectre est donc retourné par rapport au spectre d’origine [1250 – 1500 MHz]
S- is translated (3 times)
Reversed spectrum
Sous-echantillonnage 2
Daniel Charlet 06/2016
PAON & NEBULA System
~300m
Clock & triggerDistribution(WR or custom)
~300m
20GByt/s
PCIExExt /Ethernet
~ 60db
ADC
NEBULA Board
FPGA
~ 60db
ADC
NEBULA Board
FPGA
~ 60db
ADC
NEBULA Board
FPGA
UNIBOARD(Visibilities)
Daniel Charlet 06/2016
Tranceivers pinout
GX
B_L
1G
XB
_L0
GX
B_R
1G
XB
_R0
ch2
ch1
ch0
ch2
ch1
ch0
ch5
ch4
ch3
PCIeHIP
10GbE
10GbEch2
ch1
ch0
ch5
ch4
ch3
ch2
ch1
ch0µTCA 1GbE
WR 1GbE
µTCA PCIe+
PCIe refclk
REFCLK0LREFCLK1LREFCLK2L
REFCLK0LREFCLK1LREFCLK2L
156.25 MHz (10GbE) PLL125 MHz (PCIe) PCIe cable156.25 MHz (WR 10GbE) LMK
REFCLK0RREFCLK1RREFCLK2R
125 MHz (PCIe + 1GbE) PLL125 MHz (WR 1GbE) LMK
125 MHz (backup) Si511
Daniel Charlet 06/2016
10Gb x2
LMK04828 ADC08D1020
ycontrol
Power CTRLDS1014
IPMI
Eth-10G
PCIEpress4x gen2
Eth-1G
SPII2C
SPI
FPGA ctrl/cde & conf
JTAG switchMax V JTAG_conf
config SPI
JTAG
SSRAMCY7C1470BV25
(CY7C1480BV25)Flach x 2
EPLDMAXV
PCIExpress4x
ADC2x 1GSPS1x 2GSPS
Input bandwidth : 2Ghz
PCIEx 4x(optionnel)
PCIE x4
1GbEth-1G