fast-write resistive ram (rram) for embedded applications

Fast-Write Resistive RAM(RRAM) for EmbeddedApplicationsShyh-Shyuan Sheu and Kuo-Hsing Cheng

National Central University

Meng-Fan Chang

National Tsing Hua University

Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee,

Pang-Shiu Chen, Yu-Sheng Chen, Tai-Yuan Wu,

Frederick T. Chen, Keng-Li Su, Ming-Jer Kao,

and Ming-Jinn Tsai

Industrial Technology Research Institute

�EMBEDDED NONVOLATILE MEMORY (NVM) is com-

monly integrated on a chip to store programs and

data for mobile devices. One type of NVM is

embedded ROM,1 which provides low cost, high

speed, and low operational voltage. Another type is

embedded Flash memory (eFlash),2 which provides

a matured solution with flexibility in data program-

ming and erasing but which requires high-voltage de-

vices, has a limited data retention time, and cannot

achieve high-speed operation because of long write

times. High-performance mobile devices, however,

clearly need fast-access embedded NVM. Several

promising next-generation NVMs have been proposed,

therefore, to achieve faster operation speeds than those

offered by conventional eFlash memory (see the

sidebar ‘‘Next-Generation Nonvolatile Memories’’).

In this article, we propose a novel RRAM device

that achieves a faster write time (5 ns) than previous

RRAM, PRAM, and MRAM devices, while retaining

a large R ratio. A 1-Kbit RRAM macro achieves a

120-MHz random-access speed. To our knowledge,

this is the first macro-level RRAM device with full

read-write functionality.

RRAM cell operationsThe proposed RRAM cell consists of

an NMOS switch transistor (cell transis-

tor) and a hafnium-dioxide (HfO2)-

based resistive memory device.3

Figure 1 shows the RRAM cell struc-

ture and the I-V curve of the proposed

360 � 360 nm2 resistive memory de-

vice. The RRAM device employs AlCu (top metal

that connects the up-terminal of the device to the

bitline), TiN (titanium-nitride electrodes), Ti (the

film between the top electrode and the insulator),

HfO2 (as the insulator), and W (contact that con-

nects the drain of MOS and the down-terminal of

the RRAM device. In the initial state, the RRAM de-

vice requires a forming procedure to set the RRAM

cell to a low resistive state before regular read and

write operations.

There are two types of write operations for the

proposed 1T1R (one transistor, one resistor)

RRAM: set (write-0) and reset (write-1). The set op-

eration changes the RRAM device from a high

resistive state (HRS) to a low resistive state (LRS)

by applying a set voltage (VSet) on the bitline

(BL) and 0 V to the source terminal of the NMOS

switch. The reset operation changes the RRAM de-

vice from LRS to HRS by applying a reset voltage

(VReset) to the source terminal of the NMOS switch,

and 0 V to the BL, as shown in Figure 2. Table 1

summarizes the operational conditions for the pro-

posed RRAM device.

Future Landscape of Embedded Memories

Editor’s note:

Especially for microcontroller and mobile applications, embedded nonvola-

tile memory is an important technology offering to reduce power and pro-

vide local persistent storage. This article describes a new resistive RAM

device with fast write operation to improve the speed of embedded non-

volatile memories.

��Leland Chang, IBM T.J. Watson Research Center

0740-7475/11/$26.00 �c 2011 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers64

[3B2-14] mdt2011010064.3d 13/1/011 16:3 Page 64

Next-Generation Nonvolatile Memories

Nonvolatile memories (NVMs) proposed include

phase-change RAM (PRAM),1,2 magnetic RAM

(MRAM),3,4 conductive-bridge RAM (CBRAM),5 and

resistive RAM (RRAM).6�10 PRAM achieves quicker

write times than eFlash11 but, because of long quench

times, requires write time of anywhere from 50 to

300 ns, and has a large write power consumption.

Moreover, PRAM requires extra circuitry, such as a

current cell regulator or multiple set pulse generator,1

to achieve a high resistance ratio (R ratio) for high-

yield sensing. MRAM has fast write speed (20 to

30 ns) and good endurance but suffers from limited

R ratio and so cannot ensure good sensing yield.

RRAM, however, is one of the more promising candi-

dates for next-generation NVMs because of its faster

write time, large R ratio, and smaller write power con-

sumption, and it is the focus of this article.

Table A compares the reported NVMs.

References1. H.-R. Oh et al., ‘‘Enhanced Write Performance of a 64-Mb

Phase-Change Random Access Memory,’’ IEEE J. Solid-

State Circuits, vol. 41, no. 1, 2006, pp. 122-126.

2. K.-J. Lee et al., ‘‘A 90 nm 1.8 V 512 Mb Diode-Switch PRAM

with 266 MB/s Read Throughput,’’ IEEE J. Solid-State Circuits,

vol. 43, no. 1, 2008, pp. 150-162.

3. T. Kawahara et al., ‘‘2 Mb SPRAM (SPin-Transfer Torque RAM)

with Bit-by-Bit Bi-directional Current Write and Parallelizing-

Direction Current Read,’’ IEEE J. Solid-State Circuits, vol. 43,

no. 1, 2008, pp. 109-120.

4. R. Takemura et al., ‘‘A 32-Mb SPRAM with 2T1R Memory Cell,

Localized Bi-directional Write Driver and ‘1’/‘0’ Dual-Array

Equalized Reference Scheme,’’ IEEE J. Solid-State Circuits,

vol. 45, no. 4, 2010, pp. 869-879.

5. S. Dietrich et al., ‘‘A Nonvolatile 2-Mbit CBRAM Memory Core

Featuring Advanced Read and Program Control,’’ IEEE

J. Solid-State Circuits, vol. 42, no. 4, 2007, pp. 839-845.

6. I.G. Baek et al., ‘‘Highly Scalable Non-volatile Resistive Mem-

ory Using Simple Binary Oxide Driven by Asymmetric Unipolar

Voltage Pulses,’’ Proc. Int’l Electron Devices Meeting (IEDM

04), IEEE Press, 2004, p. 587.

7. A. Chen et al., ‘‘Non-volatile Resistive Switching for Advanced

Memory Applications,’’ Proc. Int’l Electron Devices Meeting

(IEDM 05), IEEE Press, 2005, p. 746.

8. D. Lee et al., ‘‘Excellent Uniformity and Reproducible Resis-

tance Switching Characteristics of Doped Binary Metal

Oxides for Non-volatile Resistance Memory Applications,’’

Proc. Int’l Electron Devices Meeting (IEDM 06), IEEE Press,

2006, p. 797.

9. H.-Y. Lee et al., ‘‘Low Power and High Speed Bipolar Switching

with a Thin Reactive Ti Buffer Layer in Robust HfO2 Base

RRAM,’’ Proc. Int’l Electron Devices Meeting (IEDM 08), IEEE

Press, 2008, pp. 297-300.

10. S.-S. Sheu et al., ‘‘A 5 ns Fast Write Multi-Level Non-volatile 1 K

bits RRAM Memory with Advance Write Scheme,’’ Proc. Symp.

VLSI Circuits, IEEE Press, 2009, pp. 82-83.

11. M.-F. Chang and S.-J. Shen, ‘‘A Process Variation Tolerant

Embedded Split-Gate Flash Memory Using Pre-stable Current

Sensing Scheme,’’ IEEE J. Solid-State Circuits, vol. 44, no. 3,

2009, pp. 987-994.

Table A. Comparison of nonvolatile memory (NVM) types.

Type of NVM

Parameter RRAM PRAM2 MRAM4 CBRAM5 eFlash11

Cell area Medium Medium Medium Medium Small

Write time* 5 ns, 5 ns 50 ns, 400 ns 40 ns, 40 ns 50 ns, 50 ns 8 ms, 200 ms

Write voltage* 1.8 V, �1.6 V 5 V 1.8 V �0.2 V, 0.6 V 10 V, 12 V

Write current* �150 mA, 150 mA 300 mA, 200 mA �300 mA, 300 mA �20 mA, 10 mA 10 mA

R ratio >10 >10 2 >100 >10

Endurance 2 � 108 107 Infinite 106 106

CBRAM: conductive-bridge RAM; MRAM: magnetic RAM; PRAM: phase-change RAM; RRAM: resistive RAM

* The first value indicates the time, voltage, or current involved for each NVM to program and erase; the second value indicates

the time, voltage, or current to set and reset.

65January/February 2011

[3B2-14] mdt2011010064.3d 13/1/011 16:3 Page 65

The RRAM device consumes a low write current

(< 25 mA) and achieves a higher R ratio between

the HRS and LRS compared to the R ratio achieved

with PRAM and MRAM. The proposed 1T1R RAM

also has 1,000 times greater endurance (> 108 cycles)

than eFlash, and good data retention time (we have

extrapolated that data can be retained for 10 years

at 200�C).

RRAM macro designsFigure 3 shows the structure of a 1-Kbit RRAM

macro. The RRAM cell array contains eight I/O sec-

tions, each having 128 bit cells and only one selected

BL. All the RRAM cells in a column share the same BL

and vertical source line (SL) to perform cross-point

RRAM cell access with one selected wordline

(horizontal line). To perform set and reset operations,

the proposed macro uses a bidirectional write-control

scheme. In set mode, current flows from the BL volt-

age generator through the BL multiplexer to the SL,

and is grounded by the SL multiplexer. In reset

mode, current flows from the SL voltage generator

through the SL multiplexer to the BL, and is grounded

by the BL multiplexer. Moreover, a current limiter in

the BL voltage generator prevents oversetting of the

RRAM cell.

Figure 3 also shows the read circuit and its oper-

ational waveforms for a single-level RRAM cell (SLC-

RRAM). A reference cell is used to generate a refer-

ence current, which is one-fourth of the read cell

current (ICell) for the LRS RRAM cell. This reference

current generates a reference voltage on the refer-

ence bitline (RBL) for the voltage-mode differential

sense amplifier. Both of the regular BL and RBL

paths have auxiliary current sources to increase

the read speed at read operations. Moreover, the

BL is biased below 0.5 V by a voltage clamper

to prevent read disturbance

occurring on the accessed

RRAM cell.

Multilevel operationThe proposed RRAM can also

achieve higher density through

multilevel operations. Figure 4

shows the resistance of a multi-

level RRAM cell (MLC-RRAM) in

a 150-cycle endurance test.

For multilevel operation,

each resistance state requires

a different maximum current

flowing through the memory

device. By restricting the

cell current through the cell


100

Gnd

TiN

TiN

TiHfO2

SL

Wordline

RRAM cell

VReset

VSet GndBL

Number of switching cycles1 100 10K 1M 100M

10K

Res

ista

nce

(Ohm

s)

1M

100M

(b)(a)

RLow (Set: 1.5 V, 40 ns)RHigh (Reset: –1.4 V, 40 ns)

Figure 2. RRAM operation (a), and resistance of a cycling test from a high resistive

state (HRS) to a low resistive state (LRS) (b).

TiTiN

AlCu

TiNW

DrainGate

Source

HfO2

10–8

–1.5 –1.0 –0.5 0.0

Applied voltage (V)

I-V curves in 1R and 1T1R

(b)(a)

I (A

)

0.5 1.0 1.5

1T1R

VStop

(VReset, IReset,Max)

(VSet, ISet)

1R

10–3

Figure 1. The resistive memory (RRAM) cell structure (a) and

I-V curve (b).

Table 1. Operational conditions of the proposed

RRAM device.

Operational condition

Input

terminal

Forming

voltage

Set

voltage

Reset

voltage

Bitline (BL) 3.3 V 1.8 V 0 V

Wordline (WL) 1.1 V 1.5 V 3.3 V

Source line (SL) 0 V 0 V 1.6 V

66 IEEE Design & Test of Computers

[3B2-14] mdt2011010064.3d 13/1/011 16:3 Page 66

transistor’s gate voltage, the wordline voltage (VWL)

and the resistance state in the RRAM device can be

divided into various levels. This work uses the set0

through set2 operations with three different WL

voltages (Vw0, Vw1, and Vw2) to generate three

different lower resistance states (Level 1, Level 2,

and Level 3). Using the reset operation, the

RRAM cell resistance switches to the fourth level

(Level 4), a high-resistance state. The maximum

WL voltage in this multilevel operation is only

Read waveform

SAOut

SAOut

VBL

VBLVDD

VDD

VReset

VSet

VRBLVBL

VClampVRBL

WL

R_EN

Data“High”

Mux_SL

Mux_BL

GndVSet

WL15

WL1

WL0 RRAM

Set Reset

Block 0128 cells

WL

driv

erTi

min

gco

ntro

l

Block128 cells

Block 7128 cells

8 Blocks

Sel0 Sel7 Rsel

RBL

1

BL7BL0

Read circuit

Writecircuit

RRAMRef. cell

+–

RRAMData cell

WL

VResetGnd

VW

IRef = 4IReadIReadData“Low”

Write and read circuit

VBG

Figure 3. Macro structure (top) and read and write circuits (bottom). In the macro structure, the solid

line is the current flow direction of the set operation, and the dotted line is the current flow direction

of the reset operation. The dotted oval indicates the RRAM cell selected to execute the write

operation (by the control signal).


[3B2-14] mdt2011010064.3d 13/1/011 16:3 Page 67

3.3 V, which is far smaller than that of either MLC

eFlash or NAND-Flash memories.

Figure 5 shows the multilevel read output circuit.

To increase the sensing margin across various resistive

states, a voltage shifter circuit regenerates the BL

voltage to a multilevel BL (MBL) voltage, which has

a larger voltage difference than does the BL voltage

between different resistive states. The three sense

amplifiers then compare the MBL voltage with three

multilevel reference voltages (ref_v1, ref_v2, and

ref_v3). The output encoder takes the output from

the three sense amplifiers to encode two-bit data

output.

Experimental resultsA 1-Kbit RRAM macro was fabricated using a

foundry-provided 0.18-mm CMOS process for

front-end devices and an in-house HfO2-based pro-

cess for the resistive device. Both single-level and

multilevel operations were implemented in the

same macro. Figure 6 is a photograph of the test

chip with a 1-Kbit RRAM macro. The 1-Kbit

RRAM macro has several test modes for device

characterization.

Figure 7a shows the resistance distribution of a

100-cycle single-level operation. LRS resistance is

between 5 KO and 10 KO, and HRS resistance lies be-

tween 100 KO and 100 MO. The

SLC R ratio of this 1-Kbit macro

exceeds 10. The LRS has a nar-

row distribution; the HRS has a

wide distribution.

During the reset operation,

different reset voltages cause var-

ious HRS distributions. A higher

reset voltage generates larger re-

sistance values for HRS. On the

basis of this reset characteristic,

the proposed RRAM can use a

lower reset voltage (i.e., 1.6 V)

with tighter process control for

low-power operation. To relax

resistive-device process control,

a higher reset voltage is

required. Moreover, the reset op-

eration of the proposed RRAM

device can use a program-and-

verification scheme to increase

the R ratio between LRS and

HRS. Figure 7b shows the resis-

tance distribution of quad-level

MLC operation of the 1-Kbit

macro. The windows of the low-

est two resistance levels are very

close in Figure 7b. The resistance


0

1K

10K

100K

Res

ista

nce

(Ohm

s)

1M

20 40 60 80Number of switching cycles

100 120 140

Level 1

Level 2

500 µA, 40 ns

500 µA, 40 ns800 µA, 40 ns

20 µA, 40 ns

150 µA, 40 ns

Level 4

Level 5

Level 3

Figure 4. Resistance of a multilevel RRAM cell (MLC-RRAM) in

a 150-cycle endurance test.

Single_level_outor

Multi_level_Bit2

ref_v1

ref_v2SAout

Multibitencoder

Multi_level_Read path

Single_level_Read path

SAout1

SAout2

RBL

ref_v3Multi_level_Bit1

Multi_level_Read

Voltageamplifier

Single_level_Read

BL

MBL

Mux

SA

SA

SA

RI_E

NR

_EN

RI_E

NR

_EN

RI_E

NR

_EN

ref_outM

uxM

b_en

Figure 5. Multilevel read output circuit.


[3B2-14] mdt2011010064.3d 13/1/011 16:3 Page 68

difference between Levels 1 and 2 is 630 KO; between

Levels 2 and 3, 6.6 KO; and between Levels 3 and 4,

1.4 KO. The sensing window narrows with decreasing

resistance.

Figure 8a shows the write and read operations of

the single-level operation of the 1-Kbit RRAM macro

from address 02AH through 02BH. The first two

cycles perform the set operations. Cycles 3 and

4 perform the reading LRS operations. Cycles 5

and 6 perform the reset operation, and cycles 7

and 8 perform the reading HRS operation. The

set_en or reset_en signal’s 5-ns pulse width can suc-

cessfully switch the RRAM cell between LRS and

HRS. The SLC-mode read access time (R_en to

data output) of the 1-Kbit RRAM test chip is

8.5 ns. Figure 8b shows the measured multilevel

read waveform of the 1-Kbit RRAM test chip. The

quad-level RRAM has a read access time of 20 ns.

THE BIPOLAR-MODE RRAM macro we have described

demonstrates that RRAM is a promising candidate

for next-generation embedded nonvolatile memory.

The proposed HfO2-based RRAM device has

fast write speed, large R ratio, high endurance,

and multilevel-operation capability. For product

application, a memory with large density is needed.

However, such a memory would affect the read and

write speed due to the parasitic capacitance of the

RRAM device. Increasingly, researchers are investi-

gating to find the best solution to enhance read

and write speed in high-density RRAM macros.

Moreover, researchers are analyzing and modeling

the parasitic capacitance effect for new product

designs. �

0.010.1

1

1K 10K1.4K

6.6K

630K

100K 1MResistance (Ohms)

10M

Level 1

Level 2

Level 3

Level 4

100M1K 10K 100K 1MResistance (Ohms)

(b)(a)

10M 100M

5

20

Pro

bab

ility

(%

)

406080

95

99

99.9

0.010.1

1

5

20

Pro

bab

ility

(%

)

406080

95

99

99.9

HRS (VReset = 1.6 V)Pulse width = 40 ns

LRS (Vg = 1.0 V)LRS (Vg = 1.2 V)LRS (Vg = 1.6 V)

(VReset = 1.6 V)(VReset = 1.7 V)

(VReset = 1.8 V)Pulse width = 40 ns

Figure 7. Resistance distribution at 100 cycles: SLC (single-level RRAM cell) mode (a) and MLC

mode (b).

Read and test-key circuit

Read and test-key circuit

WL ArrayWrite andtest-keycircuit

Voltage sourceand

test-key circuit

Figure 6. The experimental 1-Kbit RRAM has several test

modes for device characterization.


[3B2-14] mdt2011010064.3d 13/1/011 16:3 9

�References1. M.-F. Chang et al., ‘‘A 0.29V Embedded NAND-ROM in

90nm CMOS for Ultra-Low-Voltage Applications,’’ Proc.

IEEE Int’l Solid-State Circuits Conf. (ISSCC 10), IEEE

Press, 2010, pp. 266-267.

2. M.-F. Chang and S.-J. Shen, ‘‘A Process Variation Toler-

ant Embedded Split-Gate Flash Memory Using Pre-stable

Current Sensing Scheme,’’ IEEE J. Solid-State Circuits,

vol. 44, no. 3, 2009, pp. 987-994.

3. H.-Y. Lee et al., ‘‘Low Power and High Speed Bipolar

Switching with a Thin Reactive Ti Buffer Layer in Robust

HfO2 Base RRAM,’’ Proc. Int’l Electron Devices Meeting

(IEDM 08), IEEE Press, 2008, pp. 297-300.

Shyh-Shyuan Sheu is an IC designer at the Elec-

tronics and Optoelectronics Research Laboratories of

the Industrial Technology Research Institute (ITRI) in

the Republic of China. He is also pursuing a PhD in

electrical engineering at National Central University,

Taiwan. His research interests include memory,

display, and CMOS image sensor circuit design and

technology.

Kuo-Hsing Cheng is a professor in the Department

of Electrical Engineering at National Central University.

His research interests include low-voltage, low-power,

high-speed mixed-signal ICs and systems, clock syn-

chronization circuits, and ultrahigh-frequency mixed-

signal circuits for wire communications.

Meng-Fan Chang is an assistant professor in the

Department of Electrical Engineering at National

Tsing Hua University, Taiwan. His research interests in-

clude memory circuit and ultralow-voltage circuit

designs. Chang has a PhD in electronics engineering

from National Chiao Tung University.

Pei-Chia Chiang is an IC design engineer at ITRI.

His research interests include memory IC design and

CIS computer information systems (CIS) IC design.


R_EN

Bit2

Bit1

R_EN

Bit2

Bit1

R_EN

Bit2

Bit1

R_EN

Cycle 7

Cycle 8Cycle 78.5 ns

5 nsCycle 6Cycle 5

5 nsCycle 2Cycle 1

Cycle 3 Cycle 4

02AHAddress

Set_EN

Reset_EN

Read

R_EN

(a) (b)

Single_level_outTester CLoad: 30 PF

Read

02BH

20 ns

Cycle 8

Cycle 5 Cycle 6

Cycle 3 Cycle 4

Cycle 1 Cycle 2

“00”Level 1

“10”Level 2

“Read”operation

“Reset”operation1.6 V, 5 ns

“Read”operation

“Set”operation1.8 V, 5 ns

“01”Level 3

“00”Level 4

Bit2

Bit1

Figure 8. Measured waveform of 1-Kbit RRAM chip: SLC mode (a) and MLC mode (b).


[3B2-14] mdt2011010064.3d 13/1/011 16:3 0

He has a master’s in electrical engineering from Na-

tional Tsing Hua University.

Wen-Pin Lin is an IC design engineer at ITRI. His re-

search interests include CMOS analog circuit design

and switching power amplifiers. He has a PhD in elec-

trical engineering from National Sun Yat-Sen Univer-

sity, Taiwan.

Heng-Yuan Lee is a device engineer at ITRI. The

work described in this article was completed while

he was a doctoral student at National Tsing Hua Uni-

versity. His research interests include device develop-

ment of flash, DRAM, and emerging memory

technologies. He has a PhD in electrical engineering

from National Tsing Hua University.

Pang-Shiu Chen is a device engineer at ITRI. He

completed the work described while he was a doctoral

student at MingShin University of Science and Tech-

nology. His research interests include the fabrication

and characterization of the heterostructure of silicon-

germanium and carbon (SiGe:C), strained-silicon

MOSFET devices, germanium nanostructures, and

resistive memory based on transition metal oxide. He

has a PhD in material science and engineering from

National Chiao-Tung University.

Yu-Sheng Chen is a device engineer at ITRI, and he

is pursuing his PhD in electronics engineering at Na-

tional Tsing Hua University. His research interests in-

clude CMOS technology and nonvolatile memory

technology.

Tai-Yuan Wu is a process and integration engineer

at ITRI. His research interests include CMOS pro-

cesses, CMOS technology, and nonvolatile memory

technology. He has an MS in chemical engineering

from National Taiwan University.

Frederick T. Chen is the RRAM group manager

and a deputy director of the Nanoelectronic Technol-

ogy Division at ITRI. His research interests include

advanced memory technologies, metal-insulator transi-

tions, and nanoscale phenomena. He has a PhD in ap-

plied physics from Cornell University.

Keng-Li Su is an IC design engineer at ITRI. His re-

search interests include memory, and RF and CIS IC

design. He has an MS in electrical engineering from

Chung Hua University, Taiwan.

Ming-Jer Kao is a deputy general director at ITRI.

His research interests include device development of

Flash, DRAM, MRAM, and emerging memory technol-

ogies. He has a PhD in electrical engineering from Na-

tional Cheng Kung University, Taiwan.

Ming-Jinn Tsai is a research director at the Elec-

tronics and Optoelectronics Research Laboratories,

ITRI. His research interests include the development

of device and process technologies for new nonvolatile

memory and power electronics. He has a PhD in mate-

rial science and engineering from Massachusetts Insti-

tute of Technology.

�Direct questions and comments about this article to

Shyh-Shyuan Sheu, Dept. of Electrical Engineering,

National Central University, 300 Jhongda Rd., Jhongli

City, Taoyuan County, Taiwan 32001, R.O.C.;

[email protected].


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fast-write resistive ram (rram) for embedded applications

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