faults in digital testing systems

8/2/2019 Faults in Digital Testing Systems

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FAULTS IN DIGITAL

TESTING SYSTEMS


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CONTENTS

Why model faults?

Types of faults

Stuck-at faults Fault detection and Redundancy

Sensitization and Detectability

Conclusion


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Why Model Faults? I/O function tests inadequate for manufacturing

(functionality versus component andinterconnect testing)

A fault model identifies targets for testing.

A fault model makes analysis possible

Models are often easier to work with

Models are portable

Models can be used for simulation, thusavoiding expensive hardware/actual circuitimplementation


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TYPES OF FAULTS

Logical Fault Models

i. Structural faults & Functional faults

ii. Intermittent faults Single and multiple faults


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LOGICAL FAULT

MODELS They represent the effect of physical faults onthe behaviour of the modeled system.

Factors affecting faults

One, that affect the logical function Delay faults that affect the operating speed of

the system. Types

1) Explicit fault model2) Implicit fault model


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Explicit Fault model:A fault universe in which every fault isindividually identified and hence the faults couldbe explicitly enumerated.

Implicit Fault Model:A fault universe got by collectively identifying

the faults of interest typically defining thecharacterizing properties.


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STRUCTURAL AND

FUNCTIONAL FAULTS

Faults defined in conjunction withstructural models are called structural

faults Changes the interconnectionamong components.

Faults defined in conjunction with

functional models are called functionalfaults Change the truth table of acomponent.


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INTERMITTENT

FAULTS They Depend on the frequency and

statistical details of their occurrence

The data is not available and so onlinetesting is the only solution to detectintermittent or transient faults.


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THE SHORT & OPEN

A short is formed by connecting two linesthat are not to be connected.

A short between 2 signal lines creates alogic function.The logical fault representingsuch a short is called bridging fault.

An open is formed by breaking theconnection between the signal lines.


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STUCK AT FAULT If a line is shorted with Power or Gnd

leading to the line taking a fixed logicalvalue then it is a stuck-atfault denoted

by s-a-v, v is in {0,1}.

A line with only one fan-out takes aconstant value and hence appear as astuck fault.


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MULTIPLE STUCK AT

FAULT A multiple stuck-at fault means that any

set of lines is stuck-at some combination

of (0,1) values.

The total number of single and multiplestuck-at faults in a circuit with ksingle fault

sites is 3k-1.


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FAULT DETECTION

AND REDUNDANCYCombinational Circuits - terminologies

Z(x) be a logic function realized by a

combinational circuit N, to an arbitrary inputvector x.

t denotes a specific input vector and Z(t) isthe response of N to t.

For a multiple output function Z(t) is also avector


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CONTD

A circuit with fault f transforms N to Nf.

So the circuit realizes Zf(x) instead of Z(x).

Let tbe a test vector. Then,

A test (vector) t detects a fault f iff Zf(t) isdifferent from Z(t)


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Z: {x1x2,x2x3}Zf : {x1+x2, (x1+x2)x3}


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For a single output circuit, a test t thatdetects a fault f makes Z(t) = 0 and Zf(t) =1 or vice versa.

The set of all tests that detect f is given bythe solutions of the equation

Z(x) EXOR Zf(x) = 1


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Z: (x2+x3)x1 + ~x1x4and let f be x4:s-a-0

Zf: (x2+x3)x1Z EXOR Zf = 1


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SENSITIZATION

A line whose value in the test t changes inthe presence of the fault f is said to besensitized to the fault f by test t.

A path composed of sensitized lines iscalled a sensitized path.


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Y1=~y1x+~y1y2Y2=xy1(~y2)+~xy2+~y1y2


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UNDETECTABLE

BRIDGING FAULTS

CIRCUIT


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CIRCUIT

MINIMIZATION A combinationalcircuit with anundetectable stuck

fault is redundant. We may remove at

least one gate inputor a gate and

continue withsimplification.

Undetectablefault

SimplificationRule

AND(NAND) input s-a-1

AND(NAND) input s-a-0

OR(NOR) input s-a-0

OR(NOR) input s-a-1

Remove Input

Remove gate,replace by 0(1)

Remove Input

Remove gate,

replace by 1(0)


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IRREDUNDANT

CIRCUIT A circuit in which all stuck faults are

detectable is called an irredundant circuit.

Simplification can be in the form ofcombining two inverters into a single lineetc.

Redundancy can also be used to reducehazards in circuits.


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CONCLUSIONSFault analysis becomes logical rather than a

physical problem

Many different physical faults may be

modeled as the same logical fault

decreasein complexity

Most fault models are technology independentand so the models need not change with the

rapidly changing technology.


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REFERENCE

Digital systems testing and testable designby Miron Abramovici


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THANK YOU


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