faulttolerantcircuitdesignusing evolutionaryalgorithmsijcsi.org/papers/ijcsi-10-1-1-230-235.pdfin...

Fault Tolerant Circuit Design Using Evolutionary Algorithms

Hui-CongHui-CongHui-CongHui-Cong WuWuWuWuSchoolSchoolSchoolSchool ofofofof InformationInformationInformationInformation ScienceScienceScienceScience andandandand EngineeringEngineeringEngineeringEngineering,,,, HebeiHebeiHebeiHebei UniversityUniversityUniversityUniversity ofofofof ScienceScienceScienceScience andandandand TechnologyTechnologyTechnologyTechnology

ShijiazhuangShijiazhuangShijiazhuangShijiazhuang 050018,050018,050018,050018, ChinaChinaChinaChina

AbstractAbstractAbstractAbstractWith the rapid development of semiconductor technology and theincreasing proliferation of emission sources, digital circuits arefrequently used in harsh electromagnetic environments.Electrostatic Discharge (ESD) interferences are gradually gainingprominence, resulting in performance degradations, malfunctionsand disturbances in component or system level applications.Conventional solutions to such problem are shielding, filteringand grounding. This paper presents an evolvable hardwareplatform for the automated design and adaptation of a motorcontrol circuit. The platform uses EHW to automate theconfiguration of FPGA dedicated to the implementation of themotor control circuit. The ability of the platform to adapt tocertain number of faults was investigated through introducingsingle logic unit fault and multi-logic unit faults. Results showthat the functionality of circuit can be recovered throughevolution. It also shows that the placement of faulty affect theability of GA to evolve correct circuit, and the evolutionaryrecovery ability of the circuit descends with the number of faultunits increasing.Keywords:Keywords:Keywords:Keywords: Evolvable Hardware, Fault Tolerant, Motor ControlCircuits

1.1.1.1. IntroductionIntroductionIntroductionIntroduction

Brushless motor are frequently employed in the speedregulation of many driving systems. The performance andsustained reliability of the motor control circuit are ofgreat importance. Usually the control circuits designed inSCM or DSP are easy to damage in extreme environmentalconditions, such as electromagnetism interference andhigh-energy radiation.

Recently, fault tolerant systems are widely used in spaceapplications where hardware deteriorates due to damagescaused by aging, temperature drifts and high-energyradiation. In this case, human intervention is difficult orimpossible; the systems must therefore maintainfunctionality themselves. Conventional fault tolerantsystems employ techniques such as redundancy, checking-pointing and concurrent error detection. These techniquesall rely on the presence of additional redundant and addconsiderable cost and design complexity. In most cases, itcan’t satisfy the application requirements [1].

As a newly emerging but promising research field,evolvable hardware (EHW) [2-4] may provide alternative

approaches and new mechanisms for the design of faulttolerant systems. EHW is based on the idea of combiningreconfigurable hardware devices with GA to performreconfiguration autonomously. Which refers to thecharacteristics of self-organization, self-adaptation andself-recovery. With the use of evolutionary computation,evolvable hardware has the capability of autonomouslychanging its hardware architectures and functions. It canmaintain existing function in the context of degradationsor faults in conditions where hardware is subject to faults,temperature drifts, high-energy radiation, or aging.

As to logic or digital circuits, gate-level evolution usuallytakes logic gates as the basic units or building-blocks.Many researchers in this field prefer extrinsic evolution atgate-level because it is generally applicable to variouscircuits and its outcomes are comparatively formal andconsequently analyzable. Many encouraging results forgate-level evolution of logic circuits have beendemonstrated [5]. Nanjing University of Aeronautics andAstronautics has had the online fault tolerant evolution ofdigital circuits and analogy circuits on FPGA and FPTArespectively [6-8]. The Jet Propulsion Laboratory (JPL)performs research in fault tolerant, long life, and spacesurvivable electronics for the National Aeronautics andSpace Administration (NASA). JPL has had experimentsto illustrate evolutionary hardware recovery fromdegradation due to extreme temperatures and radiationhardware environments. Their experiment resultsdemonstrate that the original functions of some evolvedcircuits, such as low-pass filters and the 4-bit DAC, couldbe recovered by reusing the evolutionary algorithm thataltered the circuit topologies [9-11].

This paper presents an evolvable hardware platform for theautomated design and adaptation of brushless controlcircuits. The platform employs a genetic algorithm toautonomously configure the FPGA dedicated to theimplementation of the motor control circuit. The ability ofthe platform to adapt to a certain number of faults wasinvestigated through introducing single logic unit fault andmulti-logic unit faults.

The paper is organised as follows: section 2 presents thearchitecture of the fault tolerant platform. Section 3describes the evolutionary design process, such as the

IJCSI International Journal of Computer Science Issues, Vol. 10, Issue 1, No 1, January 2013 ISSN (Print): 1694-0784 | ISSN (Online): 1694-0814 www.IJCSI.org 230

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chromosome representation, the design of fitness function,and the adaptation strategy for GA parameters. Section 4illustrates experiments on fault tolerance through evolutionof the brushless motor control circuit. Concluding andfuture research are given in section 5.

2.2.2.2. FaultFaultFaultFault TolerantTolerantTolerantTolerant PlatformPlatformPlatformPlatform

The motor control circuit is selected as an initial studyexperiment objects. The motor achieves the phaseschanging operation with electronic circuit. The controlsystem structure is illustrated in Fig. 1. It includes threeparts, the motor control circuit, the drive module and thebrushless motor itself. The brushless motor checks theposition of the rotors by using 3 location sensors. Itproduces three position feedback signal S0, S1 and S2.When the Rotor rotates 360 degrees along the samedirection, the position signal S0, S1 and S3 have a total ofsix states combination as shown in Table 1. The motorcontrol circuit triggers each switch (M0, M1, M2, M3, M4,M5) in the drive module in accordance with the certainorder.

Fig. 1 The motor control system.

The motor control circuit fault tolerant evolutionenvironment is shown in Fig. 2.The platform comprises ofFPGA, GA evolution module, VHDL coding conversionmodule and FPGA development tool softwareenvironment.

Alter EP1K50 FPGA, which is capable of partial dynamicreconfiguration, was adopted as the experiment hardware.It provides a Joint Test Action Group (JTAG) systeminterface connected to the computer parallel port, throughwhich the circuit configuration bits can download toFPGA to validate its functionality.

The evolution module is the core part of the system.Circuit structure is represent by chromosome. Thesimulated evolution is used to evolve a good set ofarchitecture bits that determine the functions andinterconnections of the logic units in FPGA.

The VHDL coding conversion module together withQuartus II integrated software can realize the conversionfrom chromosome representation to circuit structure. The

internal configuration structure of FPGA chips is unknownfor normal users. After the best chromosome is derivedfrom generations of genetic operation in evolution module,it is expressed by VHDL; then Quartus II (which is anintegrated software environment developed by the FPGAproviders) compile and translate the VHDL to FPGAconfiguration bits. In QUARTUS II environment, TCLscript language can be used together with QUARTUScommand to accomplish the whole process fromformulation of VHDL program to download of FPGAconfiguration bits.

3333.... EvolutionaryEvolutionaryEvolutionaryEvolutionary CircuitCircuitCircuitCircuit DesignDesignDesignDesign

Evolutionary algorithms are used for circuit design. Circuitrepresentation, fitness evaluation, and parameters choiceare crucial ingredients of effective evolutionary circuitdesign.

3.1 Chromosome Representation

A correct circuit representation is the base for effectivedesign. There are many approaches to circuit description,such as binary code, min-term code and functional-levelcode. The direct approach to EHW encodes circuit’sarchitecture bits as chromosomes, which specify theconnectivity and functions of different hardwarecomponents (of the gate level) of the circuit.

According to the motor control circuits, there are three bitsinputs S0, S1 and S3 which represent the feedback signalsof the rotors’ position, and six bits outputs (M0, M1, M2,M3, M4, M5) which control the six switches of the drivingmodule to ensure that the rotor can change to next positioncorrectly.

Fig.2 shows the computational model for gate-levelevolution of the brushless motor control circuit. Theevolution area is an array of 8*5. Because the first columnworks as inputs and the last as outputs, the two columnswon’t participate in the evolution. The actual evolutionaryarea is the form of a rectangular array that consists of logicunits in 8 rows by 3 columns. Each logic unit comprisedhas 2 inputs, one output and perform 4 functions AND,OR, NAND, NOR.H0 is the input column, there are 3 logic units whichaccept the primary inputs S0, S1 and S2 respectively，H1,H2,H3 are implication evolution columns，there are 8logic units in each column, the total 24 logic units are theredundancy resources to be evolved. H4 is the outputcolumn, logic units in this column, which act as the 6interfaces, connect to the outputs of the circuit M0, M1,M2, M3, M4, M5.



Fig. 2 The computational model of motor control system.

The configuration array which represents interconnectionsand functions of the logic units is shown as following:

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The configuration array includes two parts, the functionalarray and the connectional array, the functional arrayexpressed as aij in the first two rows represents thefunctions of logic units in each column. The connectionalarray expressed as wij in the rest rows represents theinterconnections of each logic units in current column withthe logic units on its next left column.

Each logic unit comprised 4 functions can be encoded in

column vector formatT

ikik ba ),( ,, , suppose there are Llogic units in each column, the function column vector ofL logic units compose the functional array, which can beexpressed as following:

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The column vectorT

ikik ba ),( ,, express the function of thelogic unit in column k and row i ， 11 −≤≤ Kk ,and

li ≤≤1 。 As outputs interfaces, there is no accordingfunction array in column k.

In formulation (1), C0,1 represents the configuration arraybetween column H0 and H1. Here the value of m is 3according to 3 inputs in column H0; the value of L is 8according to 8 logic units in column H1. Wi,j representsthe connection relationship of logic unit in column H1with each logic unit in previous column H0. the value ofWi,j is ‘1’ or ’0’.

In formulation (2), the configuration array Ck-1,krepresents the configuration array between column Hk-1and Hk. The value of K is 8 according to the total columnnumber. In combinational circuits, feedback is prohibited;and the logic units in column n only receive inputs fromthe next left column n-1 and not allowed to receive inputsfrom others. In the configuration array Ck-1,k, wi,j=’1’represents the logic unit in column k-1and row i isconnected to the logic unit in column k and row j. On thecontrary,’ wi,j=’0’ represents these two logic units aren’tconnected. The value of l is 8 according to 8 logic units ineach column.

In formulation (3), Ck represents the connectional arraybetween column Hk-1 and Hk. Act as outputs interfaces,there is no according function array in column K, the valueof n is 6 according to the 6 outputs.

To ensure that each pair of configuration arraycorresponds with one correct logic circuit, some limitationrules should be observed:

①In the connection array Co,1, it is prohibited that all ofthe elements in each row are ‘0’in order to ensure thatthe primary circuit inputs S0, S1, S2 can be all connectedto the first column H1.②There should be at least two ‘1’ in each column of theconnection array，because each logic unit input is routedto only two units from the next left column.③Since the output layer only achieves the signal outputfunction, the connected matrix in each column must haveonly one element that is ‘1’, in order to ensure that allcomponents of the system output can be connected withthe logic unit.

If the configuration array violates above limitation rules, itcorresponds to a invalidate circuit. In such cases we set thefitness to ‘0’ in the evolution process.

3.2 Fitness Evaluation

For problems of gate-level evolution, design objectivesmainly include expected functions, efficiency of resource



usage (in terms of gate count) and operating speed ofcircuits (estimated with Maximal Propagation-Delay(MPD)). Although a functionally correct circuit with fewerlogic gates and fewer number of gates contained in thelongest signal chain of the circuit is usually preferable, themain purpose in this paper is to investigate the capacity offault recovery using EHW in case of faults. Therefore, thedesign objective only concerns with the expected functionsor behaviors, which have been specified by truth table insection 2. Thus, the functional fitness value of the evolvedcircuit is calculated as

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Where outdata is output value of current evaluated circuit;epdata is output value of expected circuit; the value of theformulation is the numbers of bits of circuit outputsresulted from a specific combination of inputs, whichscores ‘correct’ if its measured value equals that specified.For the brushless motor control circuit which include 3inputs (6 input combinations) and 36 output-bits, in orderto get a smoother landscape that is consequently easier tosearch, each of the output-bits is counted independentlyinstead of treating them as a whole when computingfitness. The biggest fitness value is 36.

3.3 Population initialization and population size

In general, populations of configuration-strings wererandomly generated. In this paper, population seeding andpopulation recall approaches that were proposed in [1]were applied. The method of population seeding involvestaking the fittest solution stored from the previousevolutionary run as the seed, and placing it into apopulation of 29 randomly generated configuration-strings.Population recall simply involves re-introducing the mostrecent population of configuration-strings evolved, andusing this as the initial start point. In the evolution designprocess when errors were introduced, a randomly selectedfinal population, evolved for motor control circuit with nofaults in the FPGA, was used as the initial population forthe recall approach. Both population seeding and recallenable the GA to adapt to the faulty FPGA architectureand produce correct circuits with target fitnessconsiderably faster than when a population ofconfiguration-strings is randomly generated.

A relative large GA population size is desirable foreffective searching because diversity of chromosomes canbe easily preserved in the population. However, in thisexperiment, considering seeding population and recallpopulation is applied, seed chromosome in a smallpopulation has much greater probability of beingoptimized by the GA search compared to a chromosome ina large population. To let the seed chromosome increasing

operating efficiency, we made a compromise and set thepopulation size to 30.

3.4 Adaptation strategy for GA parameters

Some GA parameters, especially probabilities of crossoverand mutation, Pc and Pm, have large effects on GA’sperformances; and their optimal values are usuallyimpossible to be predefined to suit various problems andstates of GA [13]. In our approach, Pc and Pm are variedwith the individuals’ distribution and GA’s geneticprocesses so as to maintain diversity in the population andsustain the convergence capacity of the GA. Diversity inthe population, which measures how diversely theindividuals are distributed in the phenotype space, isestimated .Evolutionary processes of the GA are simply identifiedwith the diversity or distribution of the individuals, whichis represent by δ t. Pc and Pm are designed to adaptthemselves in the following ways

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where, Pc0 and Pm0 are initial values of Pc and Pmrespectively, it is usually feasible to let Pc0 = 0.8 and Pm0 =0.1 due to the above adaptation strategy; According to theabove equations, Pc and Pm will decrease as a wholeduring a GA run; meanwhile they will respond to changesof individuals’ diversity reflected byδ t. In this way, ahigher Pc and a higher Pm to speed up the genetic search atthe first evolution stage, a lower Pc and a higher Pm toimprove the quality of elitist solutions at the final stage,and a lower Pc but a higher Pm, resulted from an increasingδ t, to prevent the GA from premature convergence at allstages.

4444.... ExperimentExperimentExperimentExperiment

The objective of the experiments was to recover thefunctionality of the motor control circuit implemented onFPGA. When one or more logic units can’t be used,evolution was applied to obtain a new circuit solution thatrecovered the circuit’s functionality. In this experiment,faults were introduced by setting all connections with thecorresponding fault logic unit to ‘0’. Different numbers offaults were introduced for experiments. Firstly, we evolveda motor control circuit in case all 24 logic units available;Secondly, single faults in different position of the circuitand multi-faults in column H1 were introducedrespectively; and then evolutionary process was carried out



to recover the circuit topology with the samefunctionalities. In order to investigate the fault-toleranceability, three technical indexes are defined here: theconvergence rate, the average fitness, and the averageevolution generations. The convergence rate is defined ofthe proportion of functionality recovery times in every 10times evolution. The average fitness describes the averagecorrect bits of the actual response corresponding toobjective response in every 10 times evolution. Theaverage evolutionary generations that reflects self-recovery speed to every corresponding type faults denotesthe average generations to implement self-recovery inevery 10 times evolution.

4.1 Single Logic Unit Fault

The aim is to test that the platform has good fault recoveryability for single logic unit fault. When fault is introducedto logic unit in the H1 column, the convergence rate is100%; that is to say, the motor control circuit evolved canrecover from single logic unit fault completely. But whenfault is introduced to H0 and H2 column, the correctcircuit can’t be evolved correctly all the time. That isbecause the fault unit is near the inputs and outputsposition; the placement of fault logic unit has crucialimpact on fault tolerant ability. It will greatly affect theability of the GA to evolve high quality circuit. Faultsclose to the inputs or outputs will have a more detrimentaleffect than those distributed in the centre column. Table 2illustrates the experimental results with single faultintroduced.

Table 2:Experimental results with single fault introduced

PPPPositioositioositioositionnnn ofofofofFaultsFaultsFaultsFaults

AverageAverageAverageAverageEvolutioEvolutioEvolutioEvolutio

nnnnGeneratiGeneratiGeneratiGenerati

onononon

AveraAveraAveraAveragegegege

FitnesFitnesFitnesFitnesssss

EvolutiEvolutiEvolutiEvolutionononon TimeTimeTimeTime

AverageAverageAverageAverageconvergenconvergenconvergenconvergencececece raterateraterate

NumbNumbNumbNumberererer ofofofofLogicLogicLogicLogicUnitsUnitsUnitsUnits

H2 496 30.54 96 100% 17

H1 623 27.4 153 90% 16

H3 637 28.1 151 70% 18

4.3 Multi-Logic Unit Fault

Here increasing number of logic unit faults are introducedto illustrate fault-tolerance ability of the motor controlcircuit respectively. The experiment results are shown intable 3.Table 3 indicates that the fault tolerant ability of FPGAdescends obviously with the number of fault logic unitsincreasing. Especially when four logic units fault occur,the average convergence rate is no more than 30%; theaverage fitness diminishes obviously and the averageevolutionary generations increase rapidly. The average

number of logic units used to implement the circuitreduces as the number of faults increases.

Table 3: Experimental results with increasing numbers of faultsintroduced

NumbNumbNumbNumberererer ofofofofFaultsFaultsFaultsFaults

AverageAverageAverageAverageEvolutionEvolutionEvolutionEvolutionGeneratioGeneratioGeneratioGeneratio

nsnsnsns

AveraAveraAveraAveragegegege

FitnesFitnesFitnesFitnesssss

EvolutiEvolutiEvolutiEvolutiononononTimeTimeTimeTime

AverageAverageAverageAverageconvergenconvergenconvergenconvergencececece raterateraterate

NumbNumbNumbNumberererer ofofofofLogicLogicLogicLogicUnitsUnitsUnitsUnits

2 637 28.1 151 81% 18

3 858 28.85 221 62% 16

4 1575 27.12 315 29% 15

5 3000 20.4 732 0% -

From the experimental results above, we can know that thenumber of fault logic units is closely related to the faulttolerant ability; that is to say, with the number of faultlogic units increasing, evolutionary recovery of the samecircuit needs more evolutionary generations, and theaverage fitness and convergence rate descend evidently.The reason consists in the increasing number of fault logicunits makes the signal paths which are used to accuratelytransfer signals become less; consequently to evolve theobjective circuit topologies become more difficult; so thefault tolerant ability is affected obviously. We also findthat if 4 logic units cause faults, the correct functionalcircuit can’t be evolved; that is to say, the most permissivefaults are 4 logic units.An example configuration of the motor control circuitevolved with 4 logic unit faults is illustrated in Fig. 3. theobjective of this work was not explicitly to design moreefficient circuits but to show that it is possible to evolve analternative circuit in case of fault occur in the originalcircuit, thus the functionality can be recovered.

Fig. 3 The evolved motor control circuit with four logic unit faultsintroduced.



5555.... ConclusionsConclusionsConclusionsConclusions

A fault tolerant hardware platform for the automateddesign of brushless motor control circuit has beenpresented. The platform uses the principle of EHW toautomate the configuration of FPGA dedicated to theimplementation of the motor control circuit. Ourexperiments show that it is possible to recover the functionof motor control circuit through evolution when faults areintroduced, thus the fault tolerant capability has beenapproved. Furthermore, the ability of the platform to adaptto increasing numbers of faults was investigated byintroducing faulty to different locations of the topologystructure. Results show that the functional circuit can bederived from single logic unit fault and multi-logic unitfaults; the most permissive faults are four logic units. Ofcourse the placement of faulty logic units will influencethe ability of GA to evolve high quality circuit, faultdirectly on logic units which are connected to the inputsand outputs will have a more detrimental effect than thosedistributed in the centre of the topology structure. It alsoshows that the evolutionary recovery ability of the motorcontrol circuit descends obviously with the number of faultlogic units increasing.

The real attractiveness and power of EHW comes from itspotential as an adaptive hardware while operating in a realphysical environment. Further work will focus on On-lineevolution in electromagnetism interference environment,which poses a great challenge.

AcknowledgmentsAcknowledgmentsAcknowledgmentsAcknowledgments

The work presented in this paper has been funded byPersonnel Administration Department of Heibei ProvinceResearch Project for People Return after Study Abroad,Research Plan of the Science and Technology Departmentof Hebei Province (12210212), and Hebei University ofScience & Technology Research Foundation for theDoctoral Program.

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FirstFirstFirstFirst AuthorAuthorAuthorAuthorHui-cong Wu get her doctor's degree fromShijiazhunag Mechanical Engineering College in2007, She is an associate professor in HebeiUniversity of Science & Technology. She visitedThe University of Birmingham, UK from 2009 to2010. Her research interests include evolutionarycomputation, software engineering, data mining.



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