February 28 – March 3, 2011

Stepwise Refinement and Reuse: The Key to ESL

Ashok B. Mehta Senior Manager

(DTP/SJDMP) TSMC Technology,

Inc.

Mark GlasserVerification Technologist

Mentor Graphics

Shabtay MatalonESL Market

Development Manager

Mentor Graphics

Dan GardnerTechnical Marketing

EngineerMentor Graphics

Trends …

• 15 billion connected devices by 2015

• Basic + Smart + Enhanced phones = 2 billion phones by 2012

• Mobile processor clock speed > 1 GHz (32 nm HKMG)

• Smart phone > 200 million triangles/sec by 2011

• Highly integrated devices with audio, video, 3D graphics, text

connected to Internet; require long battery life

• Marvell’s ARMADA 628 SoC

– 1.5 GHz tri-core processor

– dual stream 1080p 3D video

– 3D graphics performance with 200 million triangles per second

– for ultra-low-power, long battery life smartphones and tablets2 of 19

Trends …

2010 2012

Rapid proliferation of MP-SoC with multiple concurrent software

applications

Source: Next Generation Embedded Hardware Architecture - VDC 2010

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It’s a struggle …

Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update)

Cost of design tasks per technology

Power requirement vs. power trends

It’s a development struggle It’s a power struggle

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Current Reality …

Source : Semiconductor Industry Association. International Technology Roadmap for Semiconductors

Chip complexity versus design productivity5 of 19

• Transaction-level models (TLM) allow designers to:

– Build platforms for software development and hardware

architecture exploration before committing to RTL

– Manage the complexity of sophisticated large-scale SoCs

– Build and verify SoCs more quickly

– Run simulations orders of magnitude faster than RTL

• Reuse TLM as RTL verification testbench component

• Standards-driven: OSCI TLM, SystemC, C++, OVM,

SystemVerilog

ESL Verification Flow – Why?

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ESL Verification Flow Benefits

• Demonstrates verification methodology early in the design before RTL is created or synthesized– Designers can validate their design specification at the

TLM– Verification engineers can reduce RTL verification effort

by starting validation at the TLM

• Common design and testbench throughout the flow, from C++/SystemC to RTL– Design block and stimulus reuse

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TSMC REFERENCE FLOW 11

MENTOR SOLUTION (release on TSMC-online)

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Design Example – IDCT + AXI

• Inverse Discrete Cosine Transform (IDCT) – design block used in

JPEG/MPEG

• Design example connects IDCT to AXI bus (slave)

IDCT

IDCT_H IDCT_VREGFILEPP1

REGFILEPP0

11-bit signed

8-bit signed

AXI Bus

AXI Slave

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C++IDCTModel

Stage 1: Algorithmic

• Model represented in pure C++

• Verified using C++ testbench

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C++StimulusGenerator

User-created

User-created

Stage 2: Transaction Level Model

• Algorithmic models

transformed to SystemC

transaction-level models

– TLM2.0 for interface

protocol

– Timing/Power policies

added

• TLM assembled to create the

transaction-level platform

SystemC model

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SystemC/TLM2.0 provides standard

interfaces for communication

between models

C++StimulusGenerator

C++IDCTModel

User-created(from Stage1)

User-created(from Stage1)

VistaModel Builder

IDCTTLM

StimulusGeneratorTLM

C++StimulusGenerator

C++IDCTModel

VistaModel Builder

T P

Stage 2: Transaction-Level Validation, Debug, and Coverage

• Vista simulation and debug are used to validate results– Transaction View– SystemC Process

View• Coverage collector

TLM determines if TLM DUT sufficiently exercised

CoverageCollectorTLM

Validate & Debug in TLM Domain

VistaIDCTTLM

StimulusGeneratorTLM

C++StimulusGenerator

C++IDCTModel

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Stage 2: Preparing for Reuse in OVM• TLM1TLM2 translator added

• TLM DUT verified in a TLM1.0

configuration on Vista or Questa

• IDCT TLM is now ready for reuse as a

reference model in OVM

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TLM2.0wrapper

IDCTTLM

TLM1 TLM2 translator

IDCTTLM

C++IDCTModel

StimulusGeneratorTLM

StimulusGeneratorTLM

C++StimulusFunction

TLM1.0wrapper

C++StimulusGenerator

Vista or Questa

Stage 3: High Level Synthesis

and Verification• Starting point of the design

is fixed-point C++ or SystemC

• User-created C++ testbench is reused throughout the flow

• Catapult synthesizes C++ design to RTL and creates transactors

• Transactors convert function calls to pin-level signal activity and vice versa

• Comparator compares RTL DUT output against the C++ model output

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ComparatorGolden results DUT results

C++StimulusGenerator

User-created testbench

C++IDCTModel

User- created IDCT design block

SCVerifyautomated verification flow

Driver

IDCTRTL Block

Monitor

Catapult

Stage 3: OVM Block Testbench• IDCT agent drives the DUT

– Sequence Interface: Host to sequences– Analysis Port: makes available the transactions to components outside the agent – Virtual Interface: interface object that contains the pins that are on the DUT

• Other elements– Sequences: behaviors that generate stimulus for DUT– Scoreboard: determines if DUT provides correct response for a given stimulus

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Stage 4: Bus Integration

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From Stage 2

From Stage 3IDCT Agent in passive mode (active monitor but in-active driver)

• Adds AXI interface to Stage 3

• Reusing IDCT TLM + IDCT agent

• Demonstrates whitebox coverage

Stage 5: System-Level Step

• Adds AXI Switch

• Enables reuse in a

complete system

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The ESL Verification Demo Kit in TSMC RF11 Shows:• Verification of C++ IDCT model

• Construction of TLM from C++ models

• Transaction-level assembly, validation, and debug

• Validation of synthesized IDCT block against original untimed

C++ model using SCVerify flow

• Cross-probe synthesized RTL from original C++ and vice-versa

• Reuse of IDCT TLM and C++ stimulus in OVM RTL block-level

verification

• Reuse of IDCT TLM in OVM RTL block-level verification of the

IDCT with AXI slave adapter

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Benefits to the Verification Engineer

• Early and faster design validation using TLM before RTL

• Design and stimulus reuse throughout the flow from

C++/SystemC to RTL

– No need to maintain different models

• Verification early in the design phase before RTL is

created or synthesized

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Mentor ESL Verification Flow Kit for TSMC RF11 is released on TSMC-

online