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Asynchronous sequential logic state changes occurwhenever state inputs change (elements may be simple wiresor delay elements)

Synchronous sequential logic state changes occur in lockstep across all storage elements (using a clock signal aperiodic waveform)

Clock

Sequential logic

Basis of sequential circuits: the R-S latch

can force output to 0 (reset) or 1 (set)

R

S

Q

QR

S

Q

Cross-coupled NOR gates

0

DD 1

D0

fundamental component of ALL latches and flip-flops

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0

0

Q

R

S

Q

Q

R

S

Q

Q

Two stable states when R=S=0

Q

R

S

Q

Q

R

S

Q

Q

S changes 01

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R

S

Q

Q

R

S

Q

Q

R changes 01

R

S

Q

Q

R

S

Q

Q

S and R =1

Inconsistent

values

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Gated R-S Latch

Q

Q

CLK

S

R

CLKoperates as R-S latch holds value

R and S better notboth be 1 here

Q

\Q

CLK

D

Gated D Latch

0 -- Q(t)

Clk D Q(t+1)

1 0 0

1 1 1

R

S

CLK

D Q

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Latches vs Flip-Flops

behavior is the same unless input changeswhile the clock is high

positive

edge-triggeredflip-flop

transparent(level-sensitive)

latch

D

Clk

Q edge

Q latch

D Q

CLK

D Q

Master Slave Flip-Flops

CLK

D QD QM

D

M

Clk

Clk

Clk

Q

CLK

D Q

Negative edge-triggered Flip-Flop

D Q

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A Smaller Negative edge-triggered flip-flop

Sensitive to inputs only near edge of clock signal

Setup and hold times necessary to successfully latch the input

Characteristic equation: Q(t+1) = D(t)

holds D when

clock goes lowholds D whenclock goes low

Q

R

S

Q

Q

S

R

Q

Q

Clk = 1

D

D

0

0

D

0

4-5 gate delays

D Q

Analysis of negative edge-triggered flip-flop

\Q

R

S

Q

Q

S

R

Q

Q

Clk = 1

DD

D

Clk = 0Q

D

D

D

D

D

Q

Clk = 1

D

Clk = 0 QD

newDQ

D

Clk = 1Clk = 0 QD

newDnewDnewD newDnewDnewDnewD

When Clk=0 two stable states

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S

R

Q

Q

Analysis of negative edge-triggered flip-flop

Q

S

Q

Q

Clk = 1

D

Clk = 0 Q

D

Hold or setup time violation:D changes before the effects of the clock edge havepropagated through flip-flop

S

R

Q

Q

Clocking Requirements

clock: periodic event, causes state of memory element to changecan be rising edge or falling edge or high level or low level

setup time: minimum time before the clocking event by which theinput must be stable ( )

hold time: minimum time after the clocking event until which theinput must remain stable ( )

there is a timing "window" around

the clocking event during which theinput must remain stable andunchanged in order to be recognized

clock

data

clock

data

changingstable

D Q D Q

clock

input suT hT

suT

hT

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Typical timing specificationsPositive edge-triggered D flip-flop

setup and hold timesminimum clock width

propagation delays (low to high, high to low, max and typical)

All measurements are made from the clocking eventIn this case, the rising edge of the clock

D

Clock

Q

suT hT20ns 5ns

suT20ns 5ns

hT

wT25ns

wT25ns

plhT30ns

phlT

20ns

Cascaded Flip-Flops

shift register:new value to first stage while second stage

obtains current value of first stage

IN

CLK

Q0 Q1D

C

Q

Q

D

C

Q

Q

INQ0

Clk

Q1

D1

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Cascaded Flip-Flops (continued)

Setup/hold/propagation delays must be balancedWorks when: propagation delays far exceed hold timesclock period exceeds setup time

(guarantees following stage will latch current valuebefore it is replaced by new value)

assuming perfect clock distribution !!!

IN

D1

Clk

Q0

suTplhT

Q1

hT

phlT

suT

hT

plhT

Timing problems

Setup time violations

must lengthen clock period or speedup signal, get faster logic

Hold time violations

slow down signal, slower logic

Clock skew

shifts relative time clock edge arrives at FFs

may lengthen setup and hold time requirements

Asynchronous signalsreal world interfaces - real world isn't controlled by the same clock

interfaces to other systems with different clocks

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Clock skew

Ideally all storage elements clocked at the same time

Reality -- different wire delay to different points in the

circuit causes skew between clock inputs

Effect of skew on cascaded flip-flops:

IN

D1

Clk

Q0

Q1

Clk2

Clock skew

Can shorten time available for logic propagation

Clk

Clk2

suT

pT

suT

pT

suT

Time for logic

to propagate

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Strategies for minimizing clock skew

Distribute clock signals in general direction of data flow

Wires carrying clock between communicating componentsshould be as short as possible

Make all wires from the clock source the same length

When skew is of same order as FF propagationdelays, problems arise.

Worsens as systems get faster (wire delays don'timprove as fast as circuit delays).

Metastability and asynchronous inputs

Clocked synchronous circuitsInputs, state, and outputs sampled or changed in relation to acommon reference signal (called the clock)

Asynchronous circuitsInputs, state, and outputs sampled or changed independently of acommon reference signal (glitches/hazards a major concern)(e.g., R-S latch)

Asynchronous inputs to synchronous circuitsInputs can change at any time, will not meet setup/hold times

Dangerous, synchronous inputs are greatly preferredUnavoidable (e.g., reset signal, memory wait, user input)

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Handling asynchronous inputs

Never allow asynchronous inputs to be fanned out to morethan one FF

Different FFs could decide differently and the result could beand incorrect or illegal state

adds delay to input into system

Q1Q0InClk

D QQ0

Clock

Clock

Q1

AsyncInput

ClockedSynchronous

System

D Q

AsyncInput

Synchronizer

D QQ0

Clock

Clock

Q1D Q

D Q

Synchronizer failureWhen FF input changes near clock edge, the FF may enter a metastablestate neither a logic 0 nor 1 it may stay in this state an indefiniteamount of time, although this is not likely in real circuits.

small, but non-zero probability thatFF output will get stuck in an

in-between state

oscilloscope traces demonstrating

synchronizer failure and eventualdecay to steady state

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