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Verilog code for clock domain crossingVerilog RTL code for synchronization logic to implement clock

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Verilog code for clock domain crossingVerilog RTL code for synchronization logic to implement clock

domain crossing circuit:-module clk_2_cross ( clock1, clock2, rst_n, data_in, data_out);

input clock1;

input clock2;

input rst_n;

output [7:0] data_out;input [7:0] data_in;

reg [7:0] data_out_meta;

reg [7:0] data_out_reg;

reg [7:0] data_out_reg_r;

wire[7:0] data_out;

// Assign statements

assign data_out = data_out_reg_r;

// Always block to declare synchronous logic from source clock domain

always @ (posedge clock1)

begindata_out_meta

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begindata_out_reg

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reg rst_n;reg writep;reg [7:0] r_count, count, r_packet_in, packet_in;reg wr_en, r_wr_en, rd_en, r_rd_en;reg [1:0] r_rd_count,rd_count;

// Use of initial statement to generate clocks 1fs and1fs_d

initialbegin

clk_1fs = 0; clk_1fs_d = 0; rst_n = 0; #100 rst_n = 1;foreverbegin

#10 clk_1fs = 1; #11 clk_1fs_d = 1; #10 clk_1fs= 0; #11 clk_1fs_d = 0; end end

// Always block to generate synchronous packets in 1fsclock domainalways@(posedge clk_1fs ornegedge rst_n)begin

if (!rst_n) beginr_packet_in

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packet_in = 'hcc; wr_en = 'b1; end13 : begin

packet_in = 'hdd; wr_en= 'b1; end

14 : begin

packet_in = 'hee; wr_en= 'b1; end

15 : beginpacket_in = 'hff; wr_en= 'b1; end

default: beginpacket_in = 'd0; wr_en = 'd0; end

endcaseend

// Instance for clock domain crossing

clk_2_cross u_clock_2_cross(

.clk_1fs(clk_1fs), .clk_1fs_d(clk_1fs_d), .rst_n(rst_n), .data_in(r_packet_in), .data_out() );

endmodule