fig. 3. fast vna pcb #2 schematic - parallel port interface · pdf filepc parallel port bus...

Contents This document provides the fast detector hardware update to the original single detector N2PK VNA as well as dual fast detector Expanded N2PK VNA. With the later addition of the S-Parameter Test Set and new software, the Expanded N2PK VNA will support all of the features shown at: http://users.adelphia.net/~n2pk/VNA/FastADCPreview.html The S-Parameter Test Set is not required to take advantage of dual detectors. The pages that follow are: Fig. A. Block diagram of the single fast detector N2PK VNA Fig. B. Expanded N2PK VNA Block Diagram (without S-Parameter Test Set) Fig. C. Expanded N2PK VNA Block Diagram (with S-Parameter Test Set) Fig. D. Bock Diagram of S-Parameter Test Set with Optional VNA VHF/UHF Transverter Fig. 1. Fast VNA PCB #1 Schematic - DDS Sources Fig. 2. Fast VNA PCB #1 Schematic - Detector #1 Fig. 3. Fast VNA PCB #2 Schematic - Parallel Port Interface Fig. 4. Fast VNA PCB #2 Schematic - Detector #2 Fast Detector #1 Build Notes Fast Detector #2 Build Notes DB25 Parallel Port Pinouts (all current and future pin assignments) Detector #1 and Detector #2 LO Drive Options Component Side PCB #2 Photo Ground Plane Side PCB #2 Photo Blow-up Views of Selected Photo Areas Notes: Figs A-D are intended to aid a potential builder in deciding which VNA configuration best meets requirements. PCB #1 contains the VNA master oscillator, DDS sources, Detector #1, voltage regulators, and the parallel port interface for the DDSs and Detector #1. PCB #2 is the same layout, but is only populated with Detector #2, voltage Regulators, and the parallel port interface for Detector #2. The photos highlight Detector #2 new components, but can be used for Detector #1 on PCB #1.

http://users.adelphia.net/~n2pk/VNA/FastADCPreview.html

.

PCParallel

Port

PCParallel

Port

BusInterface

BusInterface

Fig. A. N2PK VNA Block Diagram - Single DetectorFig. A. N2PK VNA Block Diagram - Single Detector

148.34 MHzCrystalMasterOsc.


LODDS

0/90 deg

LODDS

0/90 deg

Anti-AliasFilter

Anti-AliasFilter

Sync

24 bit(Fast)ADC

24 bit(Fast)ADC

+2.5vRef.

+2.5vRef.

LowPassFilter

&Buffer

LowPassFilter

&Buffer

DetectorDetector

RFDDS0 deg

RFDDS0 deg

Anti-AliasFilter

Anti-AliasFilter

Aux. LODDS OutAux. LODDS Out

Transmission (S21 & S12)Transmission (S21 & S12)

Reflection (S11 & S22)Reflection (S11 & S22)

Bridge

DUT

DUT

50�

50�

50�

50�

RF

LO

FQ_UD

FMO

FMO

FO

FO

FO

FO

DC

F + aliasesO

FO

: 0.05 - 60 MHzFO

: 0.05 - 60 MHz

Opt.Atten.Opt.

Atten.

50�

50�

FO

FO

FO

FO

50�

50�

+4 dBm+4 dBm

-2 dBm-2 dBm

-2 dBm-2 dBm

50�

50�

J170 J210

J211J180

J120

+5v DDS+5v DDS+5v In+5v In

LowPassFilter

LowPassFilter

J100 +5v

-5v+12v In+12v In

LinearRegs.

&Inverter

LinearRegs.

&Inverter

J220

J160

DB25

.

Fig. B. Expanded N2PK VNA Block Diagram (without S-Parameter Test Set)Fig. B. Expanded N2PK VNA Block Diagram (without S-Parameter Test Set)

PCParallel

Port

PCParallel

Port

BusInterface

BusInterface



LODDS

0/90 deg

LODDS

0/90 deg

Anti-AliasFilter

Anti-AliasFilter

+5v In+5v In

Sync

24 bitADC24 bitADC

+2.5vRef.

+2.5vRef.

RFDDS0 deg

RFDDS0 deg

Anti-AliasFilter

Anti-AliasFilter



Bridge DUT

50�

50�

50�

50�

DetectorDetector

RF

LO

FQ_UD

FMOFMO

FOFO

LowPassFilter

&Buffer

LowPassFilter

&Buffer

DC

(F + aliases)O

FO : 0.05 - 60 MHzFO : 0.05 - 60 MHz

Opt.Atten.Opt.

Atten.50�

50�FOFO

FOFO

50�

50�

+4 dBm+4 dBm

-2 dBm-2 dBm

-2 dBm-2 dBm

50�

50�

PCB #1PCB #1

+5v DDS & Bus Interface+5v DDS & Bus Interface

LowPassFilter

LowPassFilter

2-waySplitter2-waySplitter

Det #1Det #1


24 bitADC24 bitADC

+2.5vRef.

+2.5vRef.

DetectorDetector

RF

LO

LowPassFilter

&Buffer

LowPassFilter

&Buffer

DC

BusInterface

BusInterface

Det #2Det #2

PCB #2PCB #2

+5v Det+5v Det

-5v Det-5v Det

LinearRegs.

&Inverter

LinearRegs.

&Inverter

+5v Det+5v Det

-5v Det-5v Det

LinearRegs.

&Inverter

LinearRegs.

&Inverter

+12v In+12v In

+5v Bus Interface+5v Bus Interface

LowPassFilter

LowPassFilter

Opt.Atten.Opt.

Atten.

50�

50�

50�

50�

J160

J360

J170

J120

J180

J211

J210

J100

J300 J420

J220

J410J411

DB25

.

Fig. C. Expanded N2PK VNA Block Diagram (with S-Parameter Test Set)Fig. C. Expanded N2PK VNA Block Diagram (with S-Parameter Test Set)

PCParallel

Port

PCParallel

Port

BusInterface

BusInterface



LODDS

0/90 deg

LODDS

0/90 deg

Anti-AliasFilter

Anti-AliasFilter

+5v In+5v In

Sync

RFDDS0 deg

RFDDS0 deg

Anti-AliasFilter

Anti-AliasFilter



DUT

50�

50�

50�

50�

FQ_UD

FMO

FMO

FO

FO

DC

(F + aliases)O

FO

: 0.05 - 60 MHzFO

: 0.05 - 60 MHz

Opt.Atten.Opt.

Atten.50�

50�

FO

FO

FO

FO

50�

50�

+4 dBm+4 dBm

-2 dBm-2 dBm

-2 dBm-2 dBm

50�

50�

PCB #1PCB #1


LowPassFilter

LowPassFilter

2-waySplitter2-waySplitter

Det #1Det #1


DC

Bus

Interface

Bus

Interface

Det #2Det #2

PCB #2PCB #2

+5v Det+5v Det

-5v Det-5v Det

LinearRegs.

&Inverter

LinearRegs.

&Inverter

+12v In+12v In Opt.Atten.Opt.

Atten.

50�

50�

50�

50�

+2.5vRef.

+2.5vRef.

+2.5vRef.

+2.5vRef.

24 bit(Fast)ADC

24 bit(Fast)ADC

LowPassFilter

&Buffer

LowPassFilter

&Buffer

RF

Detector

LO

RF

Detector

LO

RF

Detector

LO

RF

Detector

LO

LowPassFilter

&Buffer

LowPassFilter

&Buffer

24 bit(Fast)ADC

24 bit(Fast)ADC

FO

FO

FO

+

DC

F+

DC

Port1

Port1

DC Bias 1 (Opt.)DC Bias 1 (Opt.)

S-Parameter Test SetS-Parameter Test Set

BridgeBiasTeeBiasTee

Bus

Interface

Bus

Interface


FO

FO

FO

+

DC

F+

DC

Port2

Port2

0-70 dB

Atten.

0-70 dB

Atten.


50�

50�

50�

50�

+5v Det+5v Det

-5v Det-5v Det

LinearRegs.

&Inverter

LinearRegs.

&Inverter

FO

FO

FO

FO

FO

FO

FO

FO

LowPassFilter

LowPassFilter


DB25

J160

J360

J300

J100 J220

J420

J170

J120

J180

J210

J410J411

J211

Fig. D. S-Parameter Test Set with Optional VNA VHF/UHF TransverterFig. D. S-Parameter Test Set with Optional VNA VHF/UHF Transverter

FO : 0.05 - 60 MHzFO : 0.05 - 60 MHz F1 : 60 - 500 MHz, approx +/- 5% max range around F for each "BPF"1F1 : 60 - 500 MHz, approx +/- 5% max range around F for each "BPF"1F = F +/- FEXT LO 1 0F = F +/- FEXT LO 1 0

PCParallel

Port

PCParallel

Port

DUT

50�

50�

FO

F

+4 dBm+4 dBm FO 1/ FF / F

FO 1/F+

DC

F /F+

DC

Port1

Port1


S-Parameter Test SetS-Parameter Test Set


BusInterface

BusInterface


Port2

Port2

0-70 dBAtten.

0-70 dBAtten.


50�

50�

50�

50�

FO 1/ FF / F

FO 1/ FF / F

FO 1/ FF / F

FO 1/ FF / F

FO 1/F+

DC

F /F+

DC

RF DDSRF DDS

VHF/UHF Transverter - seg. #1VHF/UHF Transverter - seg. #1FO 1/ FF / F

50�

50�

50�

50�

50�

50�

50�

50�

Amp

FO

F

F1

FFO

F

Mixer

Ext LO3Ext LO3

BPF

F = F

BW < 0.1 * F

C 1

1

F = F

BW < 0.1 * F

C 1

1

F1

F

VHF/UHF Transverter - seg. #2VHF/UHF Transverter - seg. #2

Amp PadAmp Pad Ext.LO1Ext.LO1



Pad3-waySplitter3-waySplitter

ExternalLO

ExternalLO

Det #1 RF InDet #1 RF In

FO

FMixer

Pad

Amp

LPF

Ext LO1Ext LO1

VHF/UHFTransverter

seg. #3

VHF/UHFTransverter

seg. #3

FO

F

F1

F

Det #2 RF InDet #2 RF In

FO

FMixer

Pad

Amp

LPF

Ext LO2Ext LO2

VHF/UHFTransverter

seg. #4

VHF/UHFTransverter

seg. #4

FO

F

F1

F

FEXT LOFEXT LO

FEXT LOFEXT LO

FEXT LOFEXT LO

FEXT LOFEXT LO

PadAmp PadPad Pad

BPF is external to the VNA transverterand pluggable to facilitatefrequency range changes

BPF is external to the VNA transverterand pluggable to facilitatefrequency range changes

J170

J210

J410

DB25

+5D

+5D

+5D

+5D

+5D

+5D

+5A+5A

+5D +5A

+5D

+5D

X

X

+5D

X

X

+5D

+5D

+5D

+5D

X

X

+5A

+5A

X

X

+5A

+5A

+5D

+5A+5D

X

X

X

X

X

X

X

X

X

+5A

+5A

X

X +5D

5

17

116

11

12

1

10

28

27

26

5 24 10 19

1

2

3

4

4

3

2

1

1910245

26

27

28

713

12

17

14

20

21

23

20

21

6 8

12

4

10

11

1

15

16

16

15

9

9

6

25

7

7

22

22

6 18

18

2

1

3

4

7

8

9

23

D

AD

A

D

AD

A

D Q

QCLK

CLR

8

8

PRE

CLR

D Q

QCLK1

2.0k

0.1

0.1

200

49.9

R110

C124

D6

D5

D4

Clk In

D7

D3

D2

D1

D0

FQ_UD

Clk In

D7

D3

D2

D1

D0

FQ_UD

Iout

D6

D5

D4

24.9

T110

J170

PRE

C170 C171 C173 C174

L171 L172L170

C17215p

47p47p

1

47p

15p

47p82p82p

L180

C180 C181 C183 C184

L182L181

C182

J120

7

0.1

8

6

4

2

U110

U120

0.1

2.0k

R122R120

R123

W_Clk

W_Clk

1615

3

20

19

18

17

14

13

12

U160

5 9

10k10k

R194

R191 1k

49.9

Q190

10k

2

4

3

J150

MMBT3904-7

VinP

VinP

3

1

4

6

2

3

U130B

74AC74SC

R152

J180

R167

1k

R168

1k

2

C115 C116 C117 C118

25

+

-

5

GroundDB25, 18-25

R164

R163

R162

J160

3,7

9

8

6

4

LO DDS DataDB25, 3(DO 1)

DDS ResetDB25, 6(DO 4)

DDS FQ_UDDB25, 5(DO 3)

DDS W_ClkDB25, 4(DO 2)

100p

C165

100p

100p

100p

C162

C161

R161a221k

100p

R160a221k

C163 R162a221k

R166

R165

100pC166

2

1

10

SN74ACT1284DW

C167

100pR166a221k

R165a221k

1k

R1511k

10 10

10

1

U140 Master Xtal. Osc. (Note 9)

U150 AD8041AR (Note 8)

10

220n 220n 220n

100p 100p

220n 220n 220n

0 (Note 10)

0 (Note 10)

74AC74SC

U130A

R160

R161

AD9851BRS

AD9851BRS

15p

C169

15p

C168

1k

1k

0.1

1k

1k

1k

1k

1k

R192

+

FB101

++5V Ext.FB100

C101

10

2,3

1,4

GND

Iout

0.10.1

C110 C112 C113

C122 C123

0.1

C127

49.9

C125

C185Reset

Reset

IoutB

VinN

RSet

RSet

VinN

IoutB

GND

VCC

VCC

49.9

J100

C10210

0.1

0.1 0.1

C111

(Note 11)

0.1 0.1

0.1

0.1 0.1

10

DACBP

DACBP

C1400.1

C150

C151

C103

2.0k

C120 C121

C128 C126C129

C114

C130

T4-6T

R113

C100

0.1

R112

C160

C164

R193

R150

R153

R190

+4.98

+4.98

+2.501

+2.529

+2.570

+0.495

R124

49.9

+0.496

T110 pins:

1,2,3: +0.496

U110/U120 pins:

12: +1.24217: +2.85R163a

221k

R164a221k

RF DDS Out(Front Panel -1V pp into 50 ohms)

M.O. Out (Optional)Approx. -12 dBminto 50 ohms @M.O. fundamental

+4.98

DC Voltage

Measurement conditions:1. measured thru 10 k res. to 10Meg DVM2. RF & LO DDS @ 10 MHz3. Filt LO DDS Out to Det LO In4. Det. RF In open

Best to probe at resistors or capacitors instead of modules where possible.

Figure 1. N2PK Fast VNA PCB #1 Schematic - DDS Sources

R169surface

RF DDS Data,DET 1 & 2 SDIDB25, 2(DO 0)

DET1 & 2 SCKDB25, 7(DO 5)

DET1 nCSDB25, 8(DO 6)

DET1 nSDODB25, 11(+Busy)

DET1 LTC2410 nCS(U260)

DET1 LTC2410 SCK(U260)

DET1 LTC2440 SDI(U260)

1k (0603 vertical on PCB #1 near pad 19)

Det1 LTC2440 SDO(U260)

Unfilt. LO DDS Out (Optional. For minimumspurs, populate R124 if J120 is not used. Do not populate R124 if J120 is used.)

Filt. LO DDS Out to Det LO In @ J210or to a power splitter for bothDET1 and DET2 usageSee Note 6.

Notes1. Default units are ohms and uF.2. J120, J150, J170, & J180 are semi-rigid/braid coax solder attach sites up to 0.125" dia. 3. J160 is a 10 pin 0.1" SIP header or solder attach site.4. J100 is a 4 pin 0.1" SIP header or solder attach site.5. Wires jumpers, W1-W9(not shown here), are present on the bottom plane to improve ground plane integrity.6. An optional on-board trace can be used instead of J180 & J210 for single Detector usage. For dual detectors, J180 feeds a power splitter such as the MCL PSC-2-1 which, in turn, feeds J210 and J410. 7. "DO n" on Parallel Port lines are origin "0."8. If "MO Out" is not needed, don't populate U150, R150-R153, and C150-C151.9. U140 is a homebrew SM xtal osc at 148.344 MHz. See text and parts list for other option(s).10. C114 and C124 were not required for jitter reduction.11. Each pair of C16X & R16Xa are stacked on edge or on top on the same pad plus the ground plane.

X

X

X

X

X

X

8

10

Sig2

Sig1

32

VEE

8 1

+

3

4

1

14

1

2,3

+

6

Out1

12

Out2

+

-

+

18

+

MMBT3904-7

REF+

F0

IN-

IN+

C221

FB220

4

2

7 6

3

2

6

7

4

+

-

3

2

7

4

+5V Det.

+5V Det.

U240

LT1677CS8

6

R240U260

C260

T210

T211

R211

U210

Q270

0.1

D270

+ +

5

R232

R242

C290

C291

1

40.1

R214

49.9

1

2

2

1

2

6

4

6

4

1

R272

T1-6T

T1-6T

C216

0.01

C222

10

C220

100.1

+12V Int.

+5V Det.

6,7

U280 LM79L05ACM

U290 TC7662BCOA (Note 5)

15p

C212

R215

R21347.5

R212

49.9

49.9

C211(short)

0.1

2

10

C292

10 10

C280

10

C281

1k

R271

J210

3

Gain1 Gain2

Car1

Car2

MC1496D

Bias

5C213

R216

R270

3.32k

C214 C215

R230

0.1C224 U220 LP2951CM+12V Ext.

J220

U230

LT1677CS8R231

0.1

C231

REF-

GND

VCC

C241

0.1

R280

J211

3

C21712p

C210(short)

R241

49.9

10k

10k

0.1

C230

2,3,

10

LM385M3-2.5

+12V Int.

1k0.1%(Note 5)

C223

R210 49.9

5

1k0.1%

5100.1%2.00k

0.1%

+3.109

-1.795

+5V Det

+0.663

+10.06

+4.99

+3.109

+3.109

+3.109

-4.96-9.68

U210 pins:

2: -2.5113: -2.5115: -3.241

DC Voltage



short

C240

14

0.01 0.01

1000p

1000p 100

100

LTC2440CGN

SDO

SCK

nCS

SDI

1,8,9,16

4

11

13

12

BUSY15

7

10

+2.493

3

5

6

C2510.1

2 6

4

U250

LT1460ACS8-2.5

C250

R250(short)

C261

C262

C263C264

0.01(0402)

1000p(0402)

1000p(0402) 15p

(0603)

floating -LIFT PIN 15!

LIFT PIN

surface

10 (1206 or 1210 cer )

2

nEXT

Det1 LO In(J180)See Note 4.

Det1 RF In(Front Panel -1.2V pp max. into 50 ohms)

Figure 2. N2PK Fast VNA PCB #1 Schematic - Detector #1

DET1 LTC2410 SDO(R193)

DET1 LTC2440 SCK(R168)

DET1 LTC2440 nCS(R167)

DET1 LTC2440 SDI(R169)

Notes1. Default units are ohms and uF.2. J210 & J211 are 0.xxx" semi-rigid/braid coax solder attach site up to 0.125" dia. 3. J220 & J290 are 2 pin 0.1" SIP headers or solder attach sites.4. The on-board trace can NOT be used instead of J210 & J180 for Detector #1.5. All 0.1% resistors are 25 ppm/°C.

+5D

+5D

+5D

+5D

X

X

X

X

X

X

X

X

XX

X +5D

5

10

11

6

2

8

9

7

4

3

1

1615

20

18

17

14

13

12

10k10k

1k

49.9

10k

MMBT3904-7

1k

1k

5

GroundDB25, 18-25

3,7

9

8

6

4

100p

100p2

1

10

SN74ACT1284DW

100p

15p

15p

1k

0.1

1k

1k

(Note 5)

++5V Ext.

10

2,3

1,4

0.1

0.1

+4.98+4.98

DC Voltage



19 surface

DET2 nCSDB25, 9(DO 7)

RF DDS Data,DET 1 & 2 SDIDB25, 2(DO 0)

DET2 nSDODB25, 12(PError)

Figure 3. N2PK Fast VNA Detector #2 PCB #2 Schematic - Parallel Port Interface

J360

C360

R360a221k

R361a221k

R369R361

C362

R362a221k

R363a221k

1k (0603 vertical on PCB #2 near pad 19)

R364a221k

U360

R365

C366 R365a221k

R367

C368

C369

R368

DET2 LTC2440 nCS(U460)

DET2 LTC2440 SCK(U460)

DET2 LTC2440 SDI(U460)

R366a221k

C367

R366DET1 & 2 SCKDB25, 7(DO 5)

R390

R391

R392

R393

R394

Q390Det2 LTC2440 SDO(U460)

J300FB300

C303

C301C300

Notes1. Default units are ohms and uF.2. J360 is a 10 pin 0.1" SIP header or solder attach site.3. J300 is a 4 pin 0.1" SIP header or solder attach site.4. "DO n" on Parallel Port lines are origin "0."5. Each pair of C36X & R36Xa are stacked on edge or on top on the same pad plus the ground plane.

X

X

X

X

X

X

8

10

Sig2

Sig1

32

VEE

8 1

+

3

4

1

14

1

2,3

+

6

Out1

12

Out2

+

-

+

18

+

MMBT3904-7

REF+

F0

IN-

IN+

4

2

7 6

3

2

6

7

4

+

-

3

2

7

4

+5V Det.

+5V Det.

LT1677CS8

6

0.1

+ +

5

1

40.1

49.9

1

2

2

1

2

6

4

6

4

1

T1-6T

T1-6T

0.01

10100.1

+12V Int.

+5V Det.

6,7

15p

47.5

49.9

49.9

0.1

2

10

10 10 10

1k

3

Gain1 Gain2

Car1

Car2

MC1496D

Bias

5

3.32k

0.1+12V Ext.

LT1677CS8

0.1

REF-

GND

VCC

0.1

3

49.9

10k

10k

0.1

2,3,

10

LM385M3-2.5

+12V Int.

1k0.1%(Note 5)

49.9

5

1k0.1%

5100.1%2.00k

0.1%

+3.109

-1.795

+5V Det

+0.663

+10.06

+4.99

+3.109

+3.109

+3.109

-4.96-9.68

DC Voltage



short

14

0.01 0.01

1000p

1000p 100

100

LTC2440CGN

SDO

SCK

nCS

SDI

1,8,9,16

4

11

13

12

BUSY15

7

10

+2.493

3

5

6

0.1

2 6

4

LT1460ACS8-2.5

0.01(0402)

1000p(0402)

1000p(0402) 15p

(0603)

floating -LIFT PIN 15!

LIFT PIN

surface

2

nEXT

Det2 RF In(Front Panel -1.2V pp max. into 50 ohms)

Figure 4. N2PK Fast VNA Detector #2 PCB #2 Schematic - Detector #2

J420FB420

C420 C421

C423

C422

U420 LP2951CM

C424

R440

R430

R431

U430

C430

C440

R441

C414 C415

J410

J411

C416

10 (1206 or 1210 cer.)

Det2 LO In(J180 via powersplitter)See Note 4.

Notes1. Default units are ohms and uF.2. J410 & J411 are 0.xxx" semi-rigid/braid coax solder attach site up to 0.125" dia. 3. J420 & J490 are 2 pin 0.1" SIP headers or solder attach sites.4. The on-board trace can NOT be used for Detector #2. DET2 LO IN at J410 is supplied from a suitable power splitter, such as the MCL PSC-2-1, and J180 which also feeds DET1 LO In at J210.5. All 0.1% resistors are 25 ppm/°C.

U410 pins:

2: -2.5113: -2.5115: -3.241

T411

C490

U490 TC7662BCOA (Note 5)

C491

R480

C492 C480

U480 LM79L05ACM

D470

C412

C481

R470

C413

R472

R415

C411(short)

C41712p

R413R414

U410R412R410

C410(short)

R411

T410

R416

R471

Q470

U440

C441

R442

R432C450

R450(short)U450

C451C431

C460

U460

C461

C462

DET2 LTC2410 SDO(R393)

DET2 LTC2440 SCK(R368)

DET2 LTC2440 nCS(R367)

DET2 LTC2440 SDI(R369)C464

C463

Fast Detector #1 Build Notes Fast Detector #1 component changes, additions, deletions are noted herewith respect to parts designated for the original "Slow" Detector #1 inthe "Part 2" PDF. Refer to the Part 2 PDF for the complete parts list as onlythe changes, additions, and deletions are noted here.

Item Designation Type New Value Package Digikey PN(s) ---- ----------- ---- ---------- --------- ------------------------- 1 R169 Add 1 k 0603 P1.00KHCT-ND 2 R250 Del 0/short - - 3 C250 Chg 10 u 1206/1210 PCC1940CT-ND/PCC2169CT-ND 4 C261 Add 0.01 u 0402 PCC2270CT-ND 5 C262 Add 1000 p 0402 PCC1721CT-ND 6 C263 Add 1000 p 0402 PCC1721CT-ND 7 C264 Add 15 p 0603 PCC150ACVCT-ND 8 C214 Chg 0.01 u 0805 PCC103BNCT-ND 9 C215 Chg 0.01 u 0805 PCC103BNCT-ND 10 C230 Chg 1000 p 0805 PCC102BNCT-ND 11 C240 Chg 1000 p 0805 PCC102BNCT-ND 12 R232 Chg 100 0805 P100CCT-ND 13 R242 Chg 100 0805 P100CCT-ND 14 U260 Chg LTC2440CGN SSOP-16 LTC2440CGN-ND 1. The fast (LTC2440) ADC can be used on either Detector #1 or #2 or both. The PCB modifications are identical. The connections to the DB25 determine whether it is Detector #1 or Detector #2.2. See photos for locations of added components. Also refer to website docs if needed for drawings of Detector #1 components.3. R169 stands up vertically off the PCB on pad near U160, pin 19.4. C264 attaches to U260 (gnd) pads 9 & 10 & lays flat on the PCB.5. When U260 is installed, lift pins 7 and 15 so they do not contact the pads below.6. Surface wire from R169 to C264 to U260 pin 7. One wire with an insulation gap @ C264 is easiest. Use hot melt glue wire hold-downs, as shown in the photo.7. C250 in the photo is the 1210 PN and one lead bridges the original location for R250. If C250 is the 1206 PN, then the bridge is not required since C250 can be directly connected only to U250, pin 6. The other side of C250 is grounded.8. The schematics for PCB #1 show all components needed, while the photos show only those components that are required for PCB #2 - i.e. for Detector #2. PCB #1, which contains Detector #1, would be populated with additional components per the parts list in Part 2 of the VNA documentation and the schematics here.

Fast Detector #2 Build Notes Fast Detector #2 component changes, additions, deletions are noted herewith respect to parts designated for the original "Slow" Detector #1 inthe "Part 2" PDF. The format here for Detector #2 under "Designation"is "new / old". A study of all schematics included here should make this clear.Refer to the Part 2 PDF for the complete parts list as only the changes, additions, and deletions are noted here.

Item Designation Type Value Package Digikey PN(s) ---- ----------- ---- ---------- --------- ------------------------- 1 R369 / R169 Add 1 k 0603 P1.00KHCT-ND 2 R450 / R250 Del 0 - - 3 C450 / C250 Chg 10 u 1206/1210 PCC1940CT-ND/PCC2169CT-ND 4 C461 / C261 Add 0.01 u 0402 PCC2270CT-ND 5 C462 / C262 Add 1000 p 0402 PCC1721CT-ND 6 C463 / C263 Add 1000 p 0402 PCC1721CT-ND 7 C464 / C264 Add 15 p 0603 PCC150ACVCT-ND 8 C414 / C214 Chg 0.01 u 0805 PCC103BNCT-ND 9 C415 / C215 Chg 0.01 u 0805 PCC103BNCT-ND 10 C430 / C230 Chg 1000 p 0805 PCC102BNCT-ND 11 C440 / C240 Chg 1000 p 0805 PCC102BNCT-ND 12 R432 / R232 Chg 100 0805 P100CCT-ND 13 R442 / R242 Chg 100 0805 P100CCT-ND 14 U460 / U260 Chg LTC2440CGN SSOP-16 LTC2440CGN-ND 1. The fast (LTC2440) ADC can be used on either Detector #1 or #2 or both. The PCB modifications are identical. The connections to the DB25 determine whether it is Detector #1 or Detector #2.2. See photos for locations of added components. Also refer to website docs if needed for drawings of Detector #1 components.3. R369 stands up vertically off the PCB on pad near U360, pin 19.4. C464 attaches to U460 (gnd) pads 9 & 10 & lays flat on the PCB.5. When U460 is installed, lift pins 7 and 15 so they do not contact the pads below.6. Surface wire from R369 to C464 to U460 pin 7. One wire with an insulation gap @ C464 is easiest. Use hot melt glue wire hold-downs, as shown in the photo.7. C450 in the photo is the 1210 PN and one lead bridges the original location for R450. If C450 is the 1206 PN, then the bridge is not required since C450 can be directly connected only to U450, pin 6. The other side of C450 is grounded.8. The schematics and photos show only those components that are required for Detector #2 PCB.

Planned N2PK VNA Parallel Port Assignments -------------------------------------------------------------- Port Register DB25 Port Name VNA Line Name Type Offset(1) Bit(2) ----- ---------- ----------------- ---- --------- -------- + 1 Strobe* Test Set Sw(2 rx) Out 2 n0 2 D0 RF DDS Data Out 0 0 2 D0 DET1 SDI Out 0 0 2 D0 DET2 SDI Out 0 0 3 D1 LO DDS Data Out 0 1 4 D2 DDS W_CLK Out 0 2 5 D3 DDS FQ_UD Out 0 3 6 D4 DDS Reset Out 0 4 7 D5 DET1 SCK Out 0 5 7 D5 DET2 SCK Out 0 5 8 D6 DET1 nCS(4) Out 0 6 9 D7 DET2 nCS(4) Out 0 7 10 ACK* Unused In 1 6 11 BUSY DET1 nSDO(4) In 1 n7 12 PError DET2 nSDO(4) In 1 5 +13 Select Unused In 1 4 +14 AUTOFD* Atten0 Out 2 n1 15 FAULT* Unused In 1 3 16 INIT* Atten1 Out 2 2 17 SelectIn* Atten2 Out 2 n3 18 Ground Ground 19 Ground Ground 20 Ground Ground 21 Ground Ground 22 Ground Ground 23 Ground Ground 24 Ground Ground +25 Ground Ground (1) Offset Register ------ -------- 0 Data 1 Status 2 Control (2) "n" in this column only signifies that the parallel port line is inverted from the register bit. (3) "+" are DB-25 end pins

(4) Note that assignment of a particular PCB's ADC is totally controlled by which DB25 pins are used for its nCS and its nSDO. This permits the PCBs to be built identically with respect to the ADC, assuming the fast (or the slow) ADC is on both PCBs.-------------------------------------------------------------- The designation of pins as "Unused" is not intended to preclude their futureuse for some yet to be defined feature or function. They are not "reserved"as there are no plans to use them at this point.

Detector #1 and Detector #2 LO Drive Options The original N2PK VNA has only one detector, while the Expanded N2PK VNA has two detectors. The LO DDS, via some combination ot its outputs at J180 and J120 must now drive the LO inputs of both detectors for proper VNA operation. Several options are possible. Here are three that come to mind: 1. Low loss 2-way power splitter from J180 to J210 and J410. A suitable power splitter for this is the MCL SCP-2-1. The splitter "S" port is driven by J180. This incurs approx. 3.2 dB loss over the original single detector configuration. With the lower 3 dB frequency of 100 kHz for the SCP-2-1, accuracy may suffer some at very low frequencies vs. the original configuration. Here is a picture of the SCP-2-1 splitter built by Harold, W4ZCB. A DOC file of the artwork can be made available on request.

2. Resistive power splitter from J180 to J210 and J410. Three 16 ohm resistors in a wye ("Y") configuration can be used. This incurs about 6 dB loss over the original configuration. However, little or no accuracy degradation would be expected over most of the frequency range. Between 50 and 60 MHz, there may be some accuracy loss due to the reduced LO drive. 3. Separate LO paths: J180 to J210 for Detector #1 and J120 through an added anti-alias filter to J410 for Detector #2. The added anti-alias filter components are identical to the those currently used for the J180 output. The new anti-alias filter should not be jury-rigged onto PCB #1 due to coupling between the filter and the near-by RF DDS components. This option provides essentially the same LO drive levels to each detector as the original configuration, so there should be no loss in accuracy due to drive level.

However, coupling at 28 MHz from the RF DDS to J120 is 16 dB higher than the coupling from the RF DDS to J180. At 28 MHz, the RF DDS signal at J180 is approx. 72 dB down from the LO DDS level. At 14 MHz, it's about 6 dB lower so I'd expect it to be about 6 dB worse at 56 MHz. Likely most of the coupling is capacitive which would make the slope 6 dB/octave. To date, I have been using option 3. But, in view of the 16 dB higher cross-DDS coupling for J120 vs. J180, I will likely explore option 2 more in the future. I'll also try to pin down the low frequency accuracy loss a bit better for option 1. In all cases, it is recommended that the LO paths be made via VNA front panel coaxial jumpers to permit the optional use of attenuators for improvements to undesired harmonic mixing, where needed, as noted at: http://users.adelphia.net/~n2pk/TestResult6.html

http://users.adelphia.net/~n2pk/TestResult6.html

fig. 3. fast vna pcb #2 schematic - parallel port interface · pdf filepc parallel port bus...

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