first-pass-silicon radio technology for b3g wireless …
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First-Pass-Silicon Radio Technology for B3G Wireless
Terminals
Mohammed Ismail
Firstpass Technologies
Analog VLSI Lab.
Topics
•Wireless systems and cellular chipset evolution
•Multi-band radio architectures and IPs
•DC offset modeling and compensation in multi band Zero-IF receivers
•A multi-band WLAN/WiMAX Radio Architecture
•Will your first silicon spin be your last?
Abstract
As we move from third generation ( 3G ) to 4G wireless and as we strive to meet the demands for higher data rates and short distance wireless applications, a debate has ensued on whether cellular and WLAN/WMAN are seen as complementary or competing technologies. In either case, wireless services beyond 3G (B3G) are moving to all-IP, always-best connected, convergent wireless solutions requiring access to different wireless infrastructures from the same wireless device, be it a cell phone, a laptop or a PDA for a multitude of services including voice, data and multimedia applications. For future handheld wireless devices, this requires low power, low cost multi-standard multi-band chipsets, the radio part of which will be increasingly complex with stringent demands on power consumption and cost as the two main differentiators.
We will present radio design IPs at the system, architectural and block levels for emerging always-best-connected wireless applications and with focus on smart power, first-pass-silicon radio transceiver design in deep sub-micron CMOS. We will highlight both the challenges and the opportunities for innovation in this area.
Radios for 3G and 4G Wireless
2G - 3G - 4G
4G
All-IP migration convergenceBackward compatibleFuture proof
AlwaysBestConnected
SIP protocalVoIP, VoWLANUMTS/WLANCompeting or complementary?
WiMax
WiMax (Worldwide Interoperability Microwave Access)Broadband Wireless Access in Metropolitan Area
NEC, Motorola partner on Wi-Fi/cellular connectivityBy Patrick Mannion, EE TimesAug 5, 2003 (12:46 PM)URL: http://www.commsdesign.com/story/OEG20030805S0037MANHASSET, N.Y. — NEC America Inc. (Irving, TX) and Motorola Inc. (Arlington Heights, IL) have announced their intent to collaborate on an enterprise communications solution that converges a wireless LAN voice over Internet protocol (VoIP) network with cellular phone systems. Motorola's components include a dual system Wi-Fi/cellular phone and a mobility manager that controls the hand-off between a local (WLAN) and cellular networks and dispatch functions. The Wi-Fi/cellphone is still under construction, according to Nicholas Labun, vice president and general manager of Motorola's seamless mobility solutions group. It will combine 802.11a/b/g WLAN technology from TI with Motorola's GSM/CDMA cellular expertise, with unspecified hand-off functionality included.
According to Labun, the client device will be managed by the Motorola mobility manager that is integrated into NEC's enterprise equipment and will use the session initiation protocol (SIP). When it roams outside the WLAN network, the enterprise IP-PBX will initiate the transfer to the wide-area cellular network via a call directly to the cellular provider or via a land-line connection. The mobility manager will then make the switch from a VoIP call to a regular cellular network call. The companies expect user efficiencies to come from increased accessibility to the business network and greater mobility through seamless wireless access within or outside the enterprise network. The announcement comes six months after Motorola announced a similar partnership with Avaya Inc. to also enable seamless roaming between enterprise Wi-Fi networks via Avaya's IP-PBX equipment and cellular networks. That deal also included Proxim Corp. as a WLAN infrastructure provider. The new deal with NEC is similar in many respects in that it integrates Motorola's core seamless mobility components with NEC's WLAN infrastructure and NEAX family of enterprise communication platforms. Financial details of the agreement are not being disclosed. General availability for the solution is targeted for the second half of 2004.
“WANDA,” for Wireless Any-Network Digital Assistant
4G Wireless
WAN
WPAN
Cellular - km wide WLAN Pico cell:- 802.11 a/b/g- 100 m radius
WPAN Pico cell:- Bluetooth & 802.15.3- 10 m radius
WLAN
Micro cell
- Short Distance- Unregulated bands- Proliferating
• WLAN experiencing tremendous growth in the public, home, retail and enterprise market segments
– P-WLAN Hotspot users to surpass 75m by 2008 (Gartner) – WLAN to reach 50m homes by 2006 (BCWS) and 80% of US businesses by 2008
(InfoTech)– Driven by major chip vendors, OEMs, consumers and service providers
• Broadband access becoming the norm– Surpass 290m subscribers globally by 2008 (ABI)
• VoIP to replace circuit-switched telphony– Service providers (globally) accelerating their deployments of high quality SIP-based
VoIP service and enterprise segment on the verge of mass adoption– ”The most significant paradigm shift in the entire history of modern communications” -
Michael Powell, chairman of the US FCC
4G Wireless
Wireless Standards Snapshot I
Wireless Standards
Mobile Frequency
Range (MHz)
Multiple Access Method
Duplex Method
Number of Channels
Channel Spacing
Modulation Scheme
User Data Rate Chip Rate
AMPS 824~849 (Tx) 869~894 (Rx) FDMA FDD 416 30 kHz FM N/A N/A
GSM-900 890~915 (Tx) 935~960 (Rx) TDMA FDD 124 (8 users
per channel) 200 kHz GMSK 9.6 kbps 270.833 kbps
E-GSM 880~915 (Tx) 925~960 (Rx) TDMA FDD 174 200 kHz GMSK 9.6 kbps 270.833 kbps
DCS-1800 1710~1785 (Tx) 1805~1850 (Rx) TDMA FDD 374 200 kHz GMSK 9.6 kbps 270.833 kbps
PCS-1900 1850~1910 (Tx) 1930~1990 (Rx) TDMA FDD 299 200 kHz GMSK 9.6 kbps 270.833 kbps
IS-95A 824~849 (Tx) 869~894 (Rx) CDMA FDD 20 (768 users
per channel) 1.25 MHz QPSK/OQPSK 14.4 kbps 1.2288 Mbps
GPRS
824~849 (Tx) 869~894 (Rx); 890~915 (Tx) 935~960 (Rx); 880~915 (Tx) 925~960 (Rx)
TDMA FDD 124 200 kHz GMSK 115 kbps 270.833 kbps
EDGE
876~915 (Tx) 921~960 (Rx);
1710~1785 (Tx) 1805~1850 (Rx); 1850~1910 (Tx) 1930~1990 (Rx)
TDMA FDD 124 200 kHz 8-PSK 384 kbps 270.833 kbps
WCDMA 1920~1980 (Tx) 2110~2170 (Rx)
DS-CDMA FDD 12 5 MHz QPSK 2M bps 3.84 Mbps
CDMA2000 /1xEV-DO
824~849 (Tx) 869~894 (Rx) CDMA FDD 20 1.25 MHz QPSK / 8PSK /
16QAM 2.458 Mbps 1.2288M bps
Wireless Standards Snapshot II
6,9,12,1824,36,48,54
BPSK/QPSK16/64 QAM
OFDM5.250GHz5.775GHz
5GHz OFDM
5.5Mbps11Mbps
CCKDSSS2.4GHz2.4GHz DSSS High Data Rate
1Mbps 2Mbps
2GFSK 4GFSKFHSS2.4GHz2.4GHz FHSS
1Mbps 2Mbps
DBPSK DQPSKDSSS2.4GHz2.4GHz DSSSIEEE
802.11 WLAN
Standards
Standards
1Mbps 3Mbps
2GFSK8-DPSK
FHSS
Data RateModulationMultiple Access
Frequency Range
Short-Range Wireless Standards
2.4GHz
IEEE 802.11n MIMO OFDM Above
100Mbps2.4GHz5GHz
QAM
higher performance/price ratios
Wireless Chipset Technology Drivers
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Technology choices
• Compatible with baseband circuits
• Low cost due to high volumes
• More aggressive process scaling
• Rapidly improving fT
CMOS Technology
Smaller transistors and faster CMOS
Ft is no problem in CMOS
FT ≈ 1 / LG
0
25
50
75
100
125
150
175
200
0.01 0.10 0.20 0.30 0.40 0.50 0.60 0.70
F T(G
Hz)
Effective Gate Length (um)
FT = gm / 2 π CIN
FT ≈ 1 / LG2
4.0
5.0
6.0
7.0
8.0
0.0
1.0
2.0
3.0
Maxim
um Supply Voltage (V)
V DD(max) ∝
T OX∝ L G
FT ≈ 1 / L
GSiO2
Ta2O5
CMOS Vs Bipolar
CMOS Bipolar
• Symmetric behaviour• Better Linearity (higher signal swing)• Higher ft at submicron feature size• Better scaling properties• Low static power (no DC gate current)
• Higher gm for same bias• High ft• Low thermal and 1/f noise, but produces input current noise• Lower DC offset• No body effect• Lower overdrive (VCEsat)
• Top metal layers – larger pitches – thicker lines : for power handling and reduce losses
• Interconnect dielectric thickness is twice the metal thickness
• Hence top metal layers are far from the silicon substrate thus minimizing substrate losses
CMOS Reverse Interconnect Scaling
CMOS Reverse Interconnect Scaling
• Distance between top metal layer and silicon substrate currently about 1.5um per metal layer
• 10 metal layer technology by the end of the decade
* ”Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design”, B.Kleveland, C.H.Diaz etal., JSSC, Oct 2001
Optimized CMOS RF
Performance Noise Power Area
Architecture-Reduced complexity
Block-High speeddesign
Transistor-Leverage CMOSperformanceft > 75GHz
Process & temperature
Architecture-Set designgoals based onapplication
Block-Noise shaping(sigma-delta,chopping, etc)
Transistor-Noise optimizedtransistors
Architecture-Reduced complexity-Power managementBlock-Innovative biasing-Rail-to-rail designs-Folded cascode-AB CMOS biasing for OTAs and amplifiers
-use fully differential unity gain buffers
-DC current re-useTransistor- operate transistors in linear region
Architecture-Hardware share
-Maximizedigital
Block-Multi-Layerpassives
-Hand optimizedlayout
Transistor-Optimizedlayout
Architecture-Maximizedigital
Block-Selfregulatingbiasing
Transistor-Interdigitizedlayout
-statistical modeling(Monte Carlo)
Wireless System Example
Radio/Baseband/MAC
The Bluetooth SIG
Bluetooth was introduced in 1998 by Ericsson, IBM, Intel, Nokia and Toshiba.Currently, more than 2000 adoptersBluetooth enabled devices have started to appear on the market (2001)Visit www.bluetooth.com
• Radio interface, operating in the2.45 GHz "free" ISM band.
• Transmitting power less than 1 mW, typical operating range up to10 meters (30 ft)
• Up to 730 kbit/s user data rates, both circuit and packet switched connection
• Very cost effective design! Integration into computer and phone chipsets is foreseen
• The initial creator group consists of these companies
Bluetooth TechnologyBluetooth Technology
Bluetooth in 3G
The technology
• Short range wireless technology • Range up to 100 meters• Operate at the unlicensed 2.4 ISM band • Form small ad hoc networks called piconets
– One master and 7 active slaves• 1 Mb/s rate• Robust and reliable transmission using frequency hop spectrum• Support link level security including authentication and encryption• Plug-and-play service discovery• Supports legacy applications• Enable cheap single chip implementation at low power
Bluetooth usage scenarios
• Cable replacement
SDPBNE
Protocol architecture
RF
Baseband
Link Manager
• Bluetooth core consists of Link Manager, Baseband and RF
• L2CAP, SDP, RFCOMM, BNE constitute the host stack
RFCOMMIP
Aud
io
L2CAP
Cont
rol
Applications
Bluetooth radio
• frequency hopping spread spectrum– 2.402 GHz + k MHz, k=0, …, 78– 1,600 hops per second
• GFSK modulation– 1 Mb/s symbol rate
• transmit power– 0 dbm (up to 20dbm with power control)
. . .
1Mhz
1 2 3 79
83.5 Mhz
SDPBNE
RF
Baseband
Link Manager
RFCOMMIP
Aud
io
L2CAP
Cont
rol
Applications
Baseband
SDPBNE
RF
Baseband
Link Manager
RFCOMMIP
Aud
io
L2CAP
Cont
rol
Applications
• Form Piconets and Scatternets• Use paging and inquiry procedures to synchronize
transmission hop frequency and clock of the devices
• Implement channel access control based on Time Division Duplex (TDD)
• Support data and voice links• Provide flow and error control• Voice coding including the error
resistant voice coding scheme CVSD (Continuous Variable Slope Delta)
Link Manager
SDPBNE
RF
Baseband
Link Manager
RFCOMMIP
Aud
io
L2CAP
Cont
rol
Applications
Establish links between devices Piconet managementSecurity support including authentication, encryption and key managementLink commands configuration and information
L2CAP
SDPBNE
RF
Baseband
Link Manager
RFCOMMIP
Aud
io
L2CAP
Cont
rol
Applications
Link Layer and Connection Adaptation Protocol (L2CAP)Adapt upper layers protocols over the BasebandSet up both connectionless and connection-oriented logical channelsProvide quality of service as well as packet segmentation and reassembly
Other protocols
SDPBNE
RF
Baseband
Link Manager
RFCOMMIP
Aud
io
L2CAP
Cont
rol
Applications
RFCOMM Emulate serial lines used by many legacy applications (e.g. dial-up networking, LAN access)Provide reliable and in sequence delivery of byte streamSupport multiple concurrent connections to one or more BT devices
SDP (Service Discovery Protocol)searches for services by service class or attributessupports service browsing
Bluetooth Network Encapsulation (BNE)Encapsulate Ethernet over Bluetooth for the transport of IP
ProfilesMain tool for interoperability between BT devices for a specificusage model (application and devices)Define the set of procedures (from different protocols) and the messages requiredSpecify the order in which the procedures are combined Define the roles of involved devices Four general profiles have been specified
Generic Access profile Serial Port ProfileService Discovery Application ProfileGeneric Object Exchange Profile
A number of application profiles has been specified e.g. LAN Access, Dial-up Networking, File Transfer, Headset.
The profile tree
Telephony Profiles
File Transfer
Synchronization
Object Push
Generic Bluetooth Access Profiles
TransportProfiles
Dial-up networking
Headset
Fax
Serial Port
Cordless Telephony
Intercom
LAN Access
Networking Profiles
Service discovery application
Generic Object Exchange
Generic access
Object ExchangeProfiles
Bluetooth HW
Bluetooth radioBluetooth radio
Ericsson Bipolar radio• One fully tested unit-easy to use• Radio IC, filters and baluns are matched together• Ideal for embedded applications and applications requiring a flexible
form factor
Smallest size• RF IC flipchip mounted-No package • Filter,impedance matched baluns and switch integrated into
LTCC substrate
Lowest height• Self shielding design!
Output power/receiver sensitivity• Class 2 ("10m"), -70dBm at BER 0.1%
Modules
Ericsson Bluetooth™ Module• Radio, Baseband and Flash memory• Firmware: Supports all Bluetooth protocol layers up
to HCI• UART and USB interfaces for high speed data
transfer rates • PCM and USB interfaces for voice• Low energy consumption• Point to multi-point operation• Built-in shield• FCC and ETSI type approved
Bluetooth radio and baseband architectures
Radio Architectures
Discrete IR and IF filters not amenable for IntegrationChannel selection done at IFLow dynamic range baseband circuitsMulti-Standard programmability in IF stage is difficult to achieve
Super Heterodyne Receivers
Eliminates the need for discrete IR and IF filtersSignal + Blockers are translated to basebandChannel selection done at basebandHigh dynamic range baseband circuits requiredMulti-standard programmability in baseband circuits
Integrated Receivers
Digital servo loop implementation using DSP (for offset cancellation)Baseband Filter programmability for multi-standard supportDigitally programmable variable gain amplifiers
Direct Conversion Receiver
Multi-standardADC
DACMulti-band
Frequency Synth.
WCDMA
GSM
DECT
Baseband
Signal
Processor
90 o
TransmitterSignal
Duplexer
AntennaDCS1800
Band Filter
DECTBand Filter
WCDMABand Filter
DCS1800LNA
DECTLNA
WCDMALNA
I Mixer
Q Mixer
Channel/Anti-aliasing Filter
Channel/Anti-aliasing Filter
VGA
VGA
DC OffsetCancellation
DC OffsetCancellation
Multi-standardADC
DAC
Zero-IF receiver architectureMultiple narrow-band LNAs are used to get the high gain and low noise figure with low power.I/Q Mixers, low-pass analog filters, analog-to-digital converters are shared for all the standardsAdvanced Offset cancellation algorithm is needed to solve the DC offset problem
WCDMA/GSM/DECTMulti-standard Receiver
90 o
I
Q
1710~1785MHz
1880~1897MHz
1900~1920MHz
DECT
TDD andBand Switch 90 o
FromTransmitter
I
Q
1880~1897MHz
DCS1800
DECT
WCDMA
TDD andBand Switch
FrequencySynthesizer
M ulti-band
Standard-switching Signal
Single-pole-four-throw switch controlled by Standard-switching Signal. (MURATA Filter and Switch)Only one LNA of the three works to save power controlled by the Standard-switching signalTwo I/Q mixers are shared by all.
WCDMA/GSM/DECTMulti-standard Receiver
Bluetooth, HomeRF, IEEE 802.11b(FHSS)Image Rejection by Hartley MethodQuadrature Detector for Demodulator
FSK low-IF Receiver
A Radio Receiver Architecture:3G
A Radio Receiver Architecture: WLAN
A Radio Receiver Architecture: Low-IF/Zero-IF
Signal Power
ω
First downconversion to High-IF => no IR problemsSub-sampled at rate fs, where fIF = (n + ¼fs). Signal subsamples and centres at fs/4. I/Q separation and mixing done easily in discrete domain. Sampling jitter noise is multiplied due to sub-sampling.IF filters must be high-Q if used for narrow-channel.
ωRFωHigh-IFωfs/4 ωfs ω2fs ω3fs
IF Filter
Subsampling Receiver
A Radio Receiver Architecture: Subsampling
2.4 2.42 2.46 2.482.442.437 2.4 2.42 2.46 2.482.442.437
AFH
Frequency (G Hz) Frequency (G Hz)
Employed in the next generation of BluetoothFree of Interferers in the Bluetooth and Wi-Fi ChannelsConcurrent Reception without degrading QoS
Adaptive Frequency Hopping
Concurrent Receiver Architecture with AFH
0/90
2
PPFADC
AFH Control
WLAN PLL
Bluetooth PLL fref
LO1=1600 MHz
LO2= 2400 MHz
800 MHz
Wi- Fi Digital Baseband
Bluetooth Digital
Baseband
DSP
0/90
T/R
Features of the Concurrent Architecture
LNA shared between the signal paths
Two separate PLLs to generate LO signals for Wi-Fi and Bluetooth receiversTwo VCO outputs separated at least 800 MHz to avoid interaction between LOs
Signal separation by the channel select filter
GSM, WCDMA, Wi-Fi Standards Review
GSM 900
Tx band: 890M-915MHz
Rx band: 935-960MHz
Duplex: FDD
Multiple Access: TDMA
Modulation: GMSK BT=0.3
Chip rate: 270.833 kbps
Channel Spacing: 200 kHz
CNR: 9dB
Sensitivity: -102 dBm
Intermodulation Test: -99dBm signal, -49dBm at 800k 1.6MHz
Adjacent Channel Test:
-82dBm signal, -73dBm 1st adj channel, -41dBm 2nd adj channel
Spurious Response Test: -99dBm signal, -31dBm @>6MHz
In-band & out-of-band blocker test:
GSM 900 - continued
WCDMA
Tx band: 1920M-1980MHz
Rx band: 2110-2170MHz
Duplex: FDD
Multiple Access: CDMA
Modulation: QPSK, RRC filter (rolloff=0.22)
Chip rate: 3.84M bps
Channel Spacing: 5M Hz
CNR: 7dB
Sensitivity: -117 dBm
Intermodulation Test: -114dBm signal, -46dBm at 10, 20MHz
Adjacent Channel Test:
-103dBm signal, -52dBm 1st adj channel
Spurious Response Test: -114dBm signal, -44dBm @>15MHz
In-band & out-of-band blocker test:
WCDMA - continued
WLAN 802.11b
Tx & Rx band: 2.4-2.4835 GHz
Duplex: TDD
Multiple Access: CSMA/CA
Modulation: DBPSK, DQPSK, CCK
Chip rate: 11M bps
Channel Spacing: 25M Hz, 5MHz raster
CNR: 14dB (for 11M bps rate)
Sensitivity: -76 dBm
Intermodulation Test: -73dBm signal, -35dBm at 25, 50MHz
Adjacent Channel Test:
-61dBm signal, -35dBm 1st adj channel
Spurious Response Test: -73dBm signal, -35dBm @>25MHz
In-band & out-of-band blocker test:
WLAN 802.11b - continued
Tri-Standard Receiver Architecture and Specifications
• Receiver Architectures
• Frequency Synthesizer Architectures
• Receiver Tests primary parameters for whole receiver
• Excel Sheet primary parameters for each blocks
Tri-Standard Transceiver Architecture
Antenna
System SelectSwitch
Duplex Filter
T/R Switch
802.11 b
Balun
LNA90o
Balun
LNA90o
DC notch VGASigma Delta
ADC
DSP
WCDMA RX
WCDMA
GSM RX
WCDMA TX
Duplex FilterGSM 900
GSM TX
PPF/LPF
or
RF Filter
Sigma DeltaADC
I
Q
BB filter
BB filter
DAC_I 3
DAC_Q 3+
PGC
PA
RF FilterLO2
0o
90o
I
Q
BB filter
BB filter
DAC_I 2
DAC_Q 2+
PGC IF FilterLO1
0o
90oPA
LO2
PGC RF Filter
LO2
LO2
off-chip component
not shared PLL
shared PLL
modulator
Data_I
Data_Q
DAC_I 1DAC_I 2
DAC_I 3
DAC_Q 1DAC_Q 2
DAC_Q 3
modeselect
I
Q
BB filter
BB filter
DAC_I1
DAC_Q1+
PGC
PA0o
90o40 MHz
PFDFilterVCO
LO2
LO3
Tri-Standard TX/RX Architecture
/4PFD CP VCOLPF
PFD CP VCO
M/(M+1)
LPF
fout1= 380 MHz
2nd orderSigma Delta Modulator
/5
40M Hz
GSM8MHz
WCDMAWLAN10MHz
To WCDMA Tx LO1-
- fout2
M1
M1=38
GSM/WCDMA/WI-FiMode Select
(N+1)/N
Prescalar(N=16)
S
Swallow Counter(5 bit)
P
Program Counter(5 bit)
k b(t)
/2
S1
Swallow Counter(S1=3)
(N1+1)/N1
Prescalar(N1=7)
P1
Program Counter(P1=5)
LO1
LO2
WCDMA/WLAN
GSM
LO3
fref N P S k M=NP+SGSM Tx 8MHz 16 29 1~13 1/10 ~ 9/10 465 ~ 477GSM Rx 8MHz 16 29 3~16 1/20 ~ 19/20 467 ~ 480WCDMA 10MHz 16 26 6~18 0 422 ~ 434
Wi-Fi 10MHz 16 30 2~12 0.4 482 ~ 492
/2
/2
Tri-standard frequency synthesizer
Receiver Tests
• Sensitivity Test => NF
• Intermodulation Test => IIP3, selectivity, PN
• Spurious Response Test => IIP2, selectivity, PN
•Adjacent Channel Test => selectivity, PN
• Inband & out-of-band Blocker Test => selectivity,
ADC DR
Receiver Specs:
NF IIP3 IIP2 Phase Noise Selectivity
GSM-900 9.8 dB IIP3 (800k, 1600kHz)=-15.5dBm
IIP2 (Δf=600k~1.6MHz)=28dBm IIP2 (Δf=1.6M~3M)=48dBm,
IIP2 (Δf=>3M)=68dBm, IIP2 (out-of-band)=114dBm
PN (Δf=100kHz) = -84dBc/Hz, PN (Δf=300kHz) = -116dBc/Hz, PN (Δf=500kHz) = -138dBc/Hz, PN (Δf=1.5MHz) = -148dBc/Hz, PN (Δf=2.9MHz) = -158dBc/Hz, PN (out-of-band) = -181dBc/Hz
21dB @ Δf=200kHz, 53dB @ Δf=400kHz, 71dB @ Δf=600kHz, 81dB @ Δf=1.6MHz, 91dB @ Δf=3MHz,
114dB @ out-of-banc
WCDMA 9 dB IIP3 (10M, 20M)=-17dBm
IIP2 (Δf=10MHz) = -10dBm, IIP2 (Δf=15MHz) = 14dBm,
IIP2 (2050MHz~2095MHz) = 14dBm, IIP2 (2185MHz~2230MHz) = 14dBm, IIP2 (2025MHz~2050MHz) = 42dBm, IIP2 (2230MHz~2255MHz) = 42dBm,
IIP2 (< 2025MHz, > 2255MHz)=72dBm
PN (Δf=3MHz) = -109dBc/Hz, PN (Δf=8MHz) = -129dBc/Hz,
PN (Δf=13MHz) = -138dBc/Hz, PN (2095MHz) = -138dBc/Hz, PN (2185MHz) = -138dBc/Hz, PN (2050MHz) = -152dBc/Hz, PN (2230MHz) = -152dBc/Hz, PN (2025MHz) = -167dBc/Hz, PN (2255MHz) = -167dBc/Hz
33dB @ Δf=5MHz, 58dB @ Δf=10MHz
Wi-Fi 10.4dB IIP3 (25M, 50MHz) = -5dBm IIP2 (Δf=25MHz) = 23dBm, IIP2 (Δf=50MHz) = 53dBm, IIP2 (out-of-band) = 73dBm
PN (Δf=14MHz) = -145dBc/Hz, PN (Δf=39MHz) = -160dBC/Hz, PN (out-of-band) = -170dBc/Hz
60dB @ Δf=25MHz, 73dB @ Δf=50MHz, 83dB @ out-of-band
Block Level Specs:A ssum e Loss for O ff-C hip C om ponents: A ntenna: 1 .5dB , D uplexer: 1 .5dB , B alun: 1 .5dB
LNA M ixer DC notch LPF/PPF VG A ADC Com bined RequiredG ain (dB) 10 5 0 0 0~40 0
Δ f = 25M Hz 30 15 45* > 60Selectivity (dB)Δ f = 50M Hz 55 25 80 > 73
NF (dB) 3 15 15 15 20 20 8.7 <10.4
IIP3 (dBm ) (25M , 50M Hz) -5 12 30 30 20 20 -4.5 >-5
Δ f = 25M Hz 57.5 >23
W I-Fi
IIP2 (dBm )Δ f = 50M Hz
60 70 90 90 90 9057.7 >53
G ain (dB) 10 5 0 0 14~40 0
Δ f = 5M Hz 25* 25* > 33Selectivity (dB)Δ f = 10M Hz 45 10 55* > 58
NF (dB) 3 15 15 15 20 20 8.7 <9
IIP3 (dBm ) (10M , 20M Hz) -5 12 30 30 20 20 -4.5 >-17
Δ f = 10M Hz 57.5 >-10
W CDM A
IIP2 (dBm )Δ f = 15M Hz
60 70 90 90 90 9057.7 >14
G ain (dB) 10 10 0 0 0~40 0Δ f = 200kHz 30 15 45 > 21Δ f = 400kHz 45 25 70 > 53Δ f = 600kHz 60 25 85 > 71Δ f = 1.6M Hz 90 40 130 > 81
Selectivity (dB)
Δ f = 3M Hz 110 50 160 > 91NF (dB) 3 15 25 25 30 30 9.2 < 9.8
IIP3 (dBm ) (800k, 1.6M Hz) -5 10 30 15 20 20 -11.8 > -15.5Δ f = 600kHz 68 > 28Δ f = 1.6M Hz 68 > 48
G SM
IIP2 (dBm )Δ f = 3M Hz
80 80 90 90 90 9068.7 > 68
* Extra attenuations are needed in the d ig ita l filter to m eet the selectiv ity requirem ent.
Sys switch RF Filter BALUN LNA Mixer DC notch PPF VGA ADC200kHz blocker -90.0 -91.5 -93.0 -94.5 -74.5 -64.5 -64.5 -82.1 -49.2400kHz blocker -58.0 -59.5 -61.0 -62.5 -42.5 -32.5 -32.5 -72.3 -48.2600kHz blocker -43.0 -44.5 -46.0 -47.5 -27.5 -17.5 -17.5 -71.9 -53.71.6MHz blocker -33.0 -34.5 -36.0 -37.5 -17.5 -7.5 -7.5 -100.4 -97.63MHz blocker -23.0 -24.5 -26.0 -27.5 -7.5 2.5 2.5 -126.5 -134.1out-of-band blocker 0.0 -1.5 -26.5 -28.0 -8.0 2.0 2.0 -145.9 -165.3min signal -102 -103.5 -105 -106.5 -86.5 -76.5 -76.5 -76.5 -36.5max signal -15 -16.5 -18 -19.5 -9.5 0.5 0.5 0.5 0.5input noise floor -121.0 -121.0 -121.0 -121.0 -98.0 -87.4 -86.8 -86.3 -46.3
GSM Signal Levels @ input of the block
-200.0
-180.0
-160.0
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
Sysswitch
RF Filter BALUN LNA Mixer DC notch PPF VGA ADC
Blocks
Leve
ls (d
Bm
)
200kHz blocker
400kHz blocker
600kHz blocker
1.6MHz blocker
3MHz blocker
out-of-bandblocker
min signal
max signal
input noise floor
RX Signal Levels: GSM
S ys sw itch R F F ilte r B A L U N L N A M ixe r D C n o tch L P F V G A A D C m in s igna l -117 -118 .5 -120 -121 .5 -101 .5 -96 .5 -96 .5 -96 .50 -56 .50 m ax s igna l -25 -26 .5 -28 -29 .5 -19 .5 -14 .5 -14 .5 -14 .50 -0 .50 5M H z o ffse t b lock e r -63 -64 .5 -66 -67 .5 -47 .5 -42 .5 -42 .5 -66 .58 -24 .62 10M H z o ffse t b lock er -56 -57 .5 -59 -60 .5 -40 .5 -35 .5 -35 .5 -83 .66 -53 .75 15M H z o ffse t b lock er -44 -45 .5 -47 -48 .5 -28 .5 -23 .5 -23 .5 -85 .75 -62 .88 2185 M H z b locke r -44 -45 .5 -47 -48 .5 -28 .5 -23 .5 -23 .5 -133 .9 2 -135 .1 3 2230 M H z b locke r -30 -31 .5 -43 -44 .5 -24 .5 -19 .5 -19 .5 -142 .0 2 -141 .1 8 2255 M H z b locke r -15 -16 .5 -33 .5 -35 -15 -10 -10 -10 .00 -102 .0 2 inp u t n o ise flo o r -107 .0 1 -107 .0 1 -107 .0 1 -107 .0 1 -84 .01 -78 .39 -78 .21 -78 .04 -37 .87 (b ) fo r W C D M A M o de
RX Signal Levels: WCDMA
Sys switch RF Filter BALUN LNA Mixer DC notch LPF VGA ADC min signal -76 -77.5 -79 -80.5 -60.5 -55.5 -55.5 -55.5 -15.5 max signal -10 -11.5 -13 -14.5 -4.5 0.5 0.5 0.5 0.5 25MHz offset blocker -35 -36.5 -38 -39.5 -19.5 -14.5 -14.5 -46.34 -46.34 50MHz offset blocker -20 -21.5 -23 -24.5 -4.5 0.5 0.5 -55.42 -55.42 out of band blocker -10 -11.5 -13 -14.5 5.5 10.5 10.5 -63.85 -63.85 input noise floor -100.99 -100.99 -100.99 -100.99 -77.99 -72.37 -72.19 -72.02 -31.85 (c) for WiFi Mode
RX Signal Levels: Wi-Fi
Channel noise levelat ADC
Channel signal levelat ADC
Max Interferer at ADC
ADC noise
10~20dB
ADC full Scaleheadroom6~10dB
ADC DR
Channel signal levelat antenna
Channel gain
ADC DR Requirement:
Standards Channel Bandwidth
DR requirements in the Triple-standard receiver
IIP3 requirement
GSM 200 kHz 70 dB WCDMA 3.84 MHz 60 dB WLAN 22 MHz 52 dB
20 dBm
CMOS Radio Challenges : Circuits
Good RF characterization and modeling is needed scalable models, passives, varactors
Process technology with better substrate isolation
Good modeling of substrate coupling effects, fully incorporated in the design process
Better design kits for RF design
CMOS Radio Challenges : System I
Adopt system partitioning and mixed-signal strategy that lend themselves naturally to deep-submicron CMOS
Maximize digital content
Requires high speed ADCs/DACs with good DR
Incorporate antenna and front-end passives (RF filters, Balun, switches) very early in the design process
Adopt pragmatic SOC and SOP (System On Package) strategies
CMOS Radio Challenges : System II
Good package models, fully incorporated in the design porcess
Mapping strategy for system to block specifications that is amenable to CMOS design capability
Complete understanding of the wireless system standards to optimize the system and avoid unnecessary over design
Test verification, qualification and certification
Architecture :
-System architectures geared towards full integration -Orders of magnitude power saving with the right architecture for the application
Strategy:
- Power management- power-efficient radio frequency planning - Avoid driving 50-Ohm loads
- No power hungry driving buffers, and matching network- Optimum system partitioning
-Maximize digital content -Optimize interface to DSP, single chip solutions
- Power efficient transmitters - Bring the PA on chip ,saves power of PA buffers - Adopt a system design exploiting a nonlinear PA
- Chip-package and package-board co-design
Low Power RF CMOS Radio Design
Block and Circuit :
Digital solutions to analog problemsFew folds of power savings with the right design
Strategy:
Optimize and avoid over-design Exploit merged LNA/Mixer design and current mode Mixer/Baseband interface Bias current reuse Adaptive class AB biasing Exploit MOS symmetry and operation in triode region Digitally programmable RX gain control,TX power control implemented in RFSmart power Data converters ,power scales with speed and/or resolutionDigital self-calibration to relax analog/RF performance requirements
Low Power RF CMOS Radio Design
RF CMOS Circuit Design
LNA
•• First stage in the receiver chain
• sensitivity of the system
• determines the overall NF of the system
• Input matching
•Provide enough gain to overcome the noise of subsequent stages (Sensitivity)
• Add as little noise as possible
• Accomodate a large dynamic range without distortion
LNA
LsLs
LgLg
LdLd
CgsCgs
Typical single ended CMOS LNA
LNA Design
Common Source
• Amplifying device must be large and biased at high current to reduce noise
• Large input device => large input capacitance thereby attenuating the input signal thus magnifyinging ’noise’.
• Hence NF is minimized by proper choice of transistor size and bias current at the operating frequency of interest.
• Min. NF is achieved varies with bias current and device size
NFmin ≅ 1+2.3(ω/ωT)
optimum device width Wopt ≅ 1/(3ωLsCoxRs)
LNA Design
•• Zin = (gm.Cgs /Ls) + s(Lg+Ls) + 1/(s.Cgs)
Input matched with proper choice of gm,Cgs, Ls and Lg
Power constraints and minimum noise figure determine the transistor size and hence gm and Cgs.
Choose Ls to achieve 50 Ohm match
Design Lg to tune out the additional capacitance at the operating frequency
• Gain depends on the parasitics of Q1 and load.
• Cascode device improves reverse isolation.
•Additional stage may be needed to drive a 50 Ohm load (heterodyne architectures).
LNA
Common Gate
• Input matching is simpler
Zin = 1/ (gm+sCgs)
• Higher linearity.
• Better reverse isolation.
• However, higher NF due to limitations on the choice of gm.
VVinin
VVbiasbias
Mixer
•• Frequency translation by multiplying two signals
• cos(ωct). cos(ωst) = cos(ωc+ ωs)t + cos(ωc- ωs)tupconversion downconversion
• Is NOT Linear Time Invariant (LTI)
• LTI systems cannot produce spectral components that are not in the input
• To ’MIX’, system has to be Non-Linear or Time Variant
• Important properties
• Conversion Gain
• Noise Figure – SSB vs DSB
• Linearity
• Port Isolation
Mixer
•• ’Nonlinearity’ based Mixers provide frequency translation through indirect multiplication.
• Assuming the nonlinearity is characterized by,
Vout = Σ An (Vin)n
If Vin = Vc cos(ωct) + Vs cos(ωst)
Second order nonlinearity would result in a cross modulation component,
Vout(cross) = A2 Vc Vs [cos(ωc- ωs)t + cos(ωc+ ωs)t ]
VVS S cos(wcos(wSSt)t)
VVC C cos(wcos(wCCt)t)
Mixer
VVIFIF
VVLOLO
VVRFRF
•• Gilbert multiplier based mixers• Switching transistors => multiply by square wave
Basic Oscillator Theory
Oscillator Circuits
• RC Oscillators
- easy to realise
- low, medium frequency
- poor phase noise performance
• LC Oscillators
- high frequency
- good phase noise performance
- suited for RF wireless applications
Voltage Controlled Oscillators (VCO)
• Wireless applications require that oscillators be tunable by a control signal
• Control signal is usually in the form of a voltage
VCOVcontωo
Vcont
ω2
ω
ω1
V2V1
VCO Design Parameters
LC VCO Design
Multi Band VCO
IF 300MHz 900MHz
GSM band
1200MHz 1500MHz 1800MHz
GSM band
300MHz 300MHzVCO band 1 VCO band 2
f f1600MHz
GPS
1800MHz
GSM/PCS/CDMA
200MHz
(a) (b)
IF 300MHz 900MHz
GSM band
1200MHz 1500MHz 1800MHz
GSM band
300MHz 300MHzVCO band 1 VCO band 2
f f1600MHz
GPS
1800MHz
GSM/PCS/CDMA
200MHz
(a) (b)
• Multi-band operation is accomplished by tuning LC VCO with two control lines, one for continuous tuning and the other for digital band selection. The continuous tuning is used for PLL control and channel select. The digital tuning is used for RF band selection using MOSFET varactors.
Examples:1. A synthesizer for 900MHz/1800MHz GSM transceiver using wide-band IF
double conversion architecture with a fixed IF of 300MHz. A multi-band VCO can be designed to operate in the bands of 1200MHz and 1500MHz. Fig. (a)
2. The VCO can be shared between 1800MHz frequency band (GSM, PCS, WCDMA) and the GPS band 1600MHz. Fig. (b)
A Dual-Mode Frequency Synthesizerfor 3G
A fully integrated dual mode frequency synthesizer for GSM and WCDMA with maximum hardware sharing:
A Dual-Mode Frequency Synthesizerfor 3G (cont’)
Shared components Non-shared components
VCOInteger frequency
dividerPFD, CP, loop filter
Crystal oscillator
GSM 1580-1630MHz
Divided by246-254
Loop filter ω3dB ~
320kHz
80MHz /2 output divider, /32 input divider,2nd ΔΣ modulator
WCDMA 1785-1845MHz
Divided by357-369
/25 input divider
Frequency divider:• Integer frequency divider for GSM
• Fractional frequency divider for WCDMA
Dual band VCO:• NMOS accumulation mode varactor for band-to-band switching
• PN junction varactor for in-band tuning
Shared components:•PFD, CP, integer frequency divider, loop filter, VCO, reference signal, 70% of total die area
Performance Specifications ofFrequency synthesizers
• Frequency range
• Frequency resolution
• Lock time
• Spectral purity
phase noise
harmonics
spur
Broadband Synthesizer
Frequency Synthesizer
Example of a Wireless
Transceiver Front-End
Frequency synthesizer
implemented as a
phase-locked loop (PLL)
General role of a
frequency synthesizer for wireless applications
Frequency generation scheme
Challenges due to
incompatible specifications in the design
of PLLs
Spur level
Frequency range
Phase noise
Power consumption
Area
Locking time
Goal
Specs
Challenges addressed in this work
Frequency generation scheme II
By running the VCO at high frequencies and using fixed dividers before the output, we can theoretically lower the phase noise floor by a maximum of
30log(n)
where n is the division ratio
This is mainly due to:• The reduced VCO tank parallel resistance at higher
frequencies• The division factor
Frequency generation scheme III
Proposed scheme:
VCOwith switchablecapacitors and inductors
Advantages:• Low phase noise• Wide frequency range• Small area due to the smaller inductors at high frequencies
Standards chosen
Standard
Start Freq.
Original (MHz)
End Freq.
Original (MHz)
Start Freq.
×2 (MHz)
End Freq.
×2 (MHz)
Start Freq.
×4 (MHz)
End Freq.
×4 (MHz)
DCS1800 1710 1880 3420 3760 6840 7520
WCDMA II 1850 1990 3700 3980 7400 7960
WCDMA III 1710 1880 3420 3760 6840 7520
DECT 1881.792 1897.344 3763.584 3794.688 7527.168 7589.376
IEEE802.11b/g 2412 2472 4824 4944 9648 9888
IEEE802.11a 5150 5825 10300 11650 20600 23300
Bluetooth 2402 2480 4804 4960 9608 9920
Implementation of the VCO
Vtune
Vcap
Vind
• PMOS transistors to reduce 1/f noise• L1: L=320pH and Q=16• L2: L=280pH and Q=24• The RF switch acts as a filter and its loss is
less than 1dB when it is ON.• Frequency ranges:
– When only L1 is selected, the frequency range is 6.8GHz to 8GHz
– When all the inductors are selected, the frequency range is 4.8GHz to 6GHz
• The resistors are used for DC biasing of the source/drain terminals of the MOS switch devices.
L1
L2
L1
L2
Implementation of the frequency divider
• Input frequency range is 4.5GHz to 8GHz
• Differential prescaler implementation designed to divide by 2 and by 4 and to generate quadrature signals at the same time.
• The design is not fully-differential which allows the circuit to operate with a wide frequency range and makes it less sensitive to variations in the input voltage.
One divider core
Oscillator startup
Inductor switchON - OFF
VCO @ 5.3 GHz
VCO @ 7.4 GHz
tr tftset tset
tp
Simulation results of the combination VCO-dividers
Switching the inductors:• Control signal has a period tp of
5ns and a rise time tr and a fall time tf of 0.5ns.
• Steep rise or fall flanks of the switch do not influence much the performance of the VCO due to the parallel-serial placement of the switch over the inductors.
• A settling time (tset) of 1.1ns is observed, which is due to the loop-back of the VCO signal.
• The output amplitudes differ due to the unequal losses at 7.4GHz and 5.3GHz.
Layout of the complete design
• 0.18µm CMOS• Careful floor planning was made. For
example, the layout of the dividers was done in a symmetrical manner so as to avoid I/Q imbalances.
• Blocks:1. VCO2. buffers for 50Ω matching with ESD
protection and for driving the divider input load
3. dividers by 2 and 4 with 50Ωbuffers and ESD protection
1.5mm
1.6
mm 2
1 3
Analog Baseband Chains
Goals/Motivation
• Develop baseband chains for 3G Integrated Wireless receivers– Tailored for Integrated Cellular,cordless and Indoor applications– Based on regular modules for short design time
• Investigate and propose new CMOS circuits and techniques suitable for integrated receivers– Low Power Consumption– Digitally Programmable– Simple and Robust Filter/VGA/OTA circuit structures
Digitally Programmable CMOS Filter/VGAfor wireless base stations
Specifications• Signal of Interest : 12MHz - 23MHz
• Pass Band of Filter : 12MHz - 23MHz (-0.5dB corner points)
• Pass Band Ripple : < 0.5dB
• Stop Band : 0MHz - 5MHz and after 40MHz
• Stop Band Attenuation : > 25dB
• Programmable Gain : -10 dB to 30 dB in steps of 1 dB
• Linearity (IMD) : > 53 dBc
• Signal to Noise Ratio : > 57 dB (noise integrated over 5MHz Bandwidth)
6dB step
(-12~0) dB+6 dB (-12~0) dB +6 dB
2nd order LPF
1st orderHPF 6dB step 3dB step
(-12~0) dB
2nd orderLPF
+6 dBattenuator attenuator attenuator
+6 dB
2nd order HPF6dB step
(-12~0) dBattenuator
2nd orderLPF
2nd orderHPF
2nd orderLPF1dB step
(-4~0) dBattenuator +6 dB 0 dB
*LPF: Low pass filter *HPF: High pass filter
Vin+
Vin-
Vout+
Vout-
Proposed Filter/VGA Chain
• 6 dB gain buffers in 5 filter stages provide fixed 30 dB gain.• Use filter stages with voltage gain to eliminate the need for VGA stages.• 5 digitally programmable attenuators attenuate 30 dB gain in 1 dB steps of gain
Vin+
Buffer
Vin-
Vout+
Vout-
+
_
+
_
Vin+
Buffer
Vin-
Vout+
Vout-
+
_
+
_
R R
R R
C1
C1
C2
C2
Use the buffer circuit to implement fully differential Sallen-Key filter sections.
Filter tuning is achieved by 4 bit binary weighted capacitor array.
Use resistive chain to attenuate the gainIn 1/3/6 dB steps.
Programmable gain variation: -10 – 30 dB
5 bit digital control
The frequency response of VGA/Filter chain
RFFilter
RFFilter
RFFilter
RFFilter
LNA
LNA
LNA
LNA
LO
LO
LO
LO
VGA
VGA
DC offsetcontrol
Gain ControlBandwidth control
ADC
ADC
DSP
Multi-Standard Receiver
DSP controls•DC Offset•Gain of VGA•Bandwidth of LPF
How to make Multi-Standard Receiver digitally programmable in CMOS?
1) R-2R ladders
2) Digitally Controlled Current Follower by applying CDN.
3) Digitally Controlled Filter by applying R-2R ladders and DCCF
R-2R ladders
R
β
V I
2R 2R 2R 2R 2R
Ir Ir/2 Ir/4 Ir/8
R R R R
2R
b1
Ir Ir/2 Ir/4 Ir/8
b2 b3 bnb4
I
R-2R
•Digital control word is applied through MOS switches and the resistors are implemented by poly layers in CMOS process.
•The total resistance of the ladder is controlled by closing or opening the switches to realize binary-weighted currents with a resistance ratio of 2.
Vdd
Iin/2 Iin/4
d1 d1 d2
Io(Virtual ground)
Iin/(2n)
dn dnd2
Current Division Network (CDN)
Iin
•Due to the geometrical symmetry of MOS device, The linear current inter relationships in the resistive network are maintained in the MOS implementation.
•Digital control word is applied through MOS Switches and the current flowing is controlled
Izp
α
Digitally Controlled Current Follower
VDD
Vb
M1
M2
M3
Mc
M12 M4
M5 M6
M8M7
M10M9M13
M11
Vc
Isb
VDD
VSS
X Z
X DCCF ZIx
Ibp
CDN
•The DCCF is a current follower with programmable gain that can be controlled digitally
•Use a CDN to provide precise gain characteristics by precise digital trimming.
Digitally Programmable Fully Differential Filter
x DCCF z
CMFB
x DCCF z
1x
1x
R2R
R2R
x DCCF z
CMFB
x DCCF z
1x
1x
R2R
R2R
R2R
R2R
R2R
Vcm
Vcm
C2
C2
VoVi
R2
R2
R1
R1
R3
R3Rin
Rin
α2
α2
α1
α1
C1
C1 R2R
•The filter is used for channel selection in a multi-standard wireless receiver•Cuff-off frequency and DC gain are controlled digitally
The die photo of 6th order digitally programmable filter
Measured AC response: PDC and IS-54
Measured AC response: GSM
Measured AC response: WCDMA
Filter 6th-order Butterworth
Technology 0.5 um CMOS
Chip area 1.25 mm2
Supply voltage 2.7 V
Current consumption 2.25 mA
Frequency tuning range 5kHz-5MHz
Gain 18 dB
Statistical gain variation(25 chips) 0.44 dB
IIP3(Inband)PDC(IS-95)/GSM/IS-95/WCDMA
28.3/25.6/23.7/21.9 dBm
IIP3(stopband)PDC(IS-95)/GSM/IS-95/WCDMA
61/59.5/56/51.4 dBm
Input referred noisePDC(IS-95)/GSM/IS-95/WCDMA
30/45/69/85 uV
Stopband rejectionPDC(IS-95)/GSM/IS-95/WCDMA
80/80/76/70 dB
SFDRPDC(IS-95)/GSM/IS-95/WCDMA
92/89/84/80 dB
Passband ripple 0.2 dB
PSRR (passband) 40.3 dB
Summary of Multi-Standard Channel Select Filter Performance
Compact TDD Wireless Radio Transceiver
Motivation
• Silicon estate!– Baseband circuitry processing I/Q signals for both
RX and TX paths could occupy up to 50% of the total die area
– Especially for a multistandard transceiver in a single chip and for a sensor node in a sensor network
Sample Die Photo
R. Ahola et al, “A Single-Chip CMOS Transceiver for 802.11a/b/g Wireless LANs”, IEEE J. Solid-State Circuits, vol.39, no.12, pp2250-2258, Dec.2004
Direct Conversion Transceiver
LPFVGA
VGA LPF
LPF VGA
VGA
ADC
ADC
Q
LPF
PA
LNA
Frequency
Synthesizer
I
DAC
I
Q
DAC
DC Offset Cancellation
DC Offset Cancellation
fRFf
0f
T/RSwitch
Idea
• Design one programmable baseband chain• Share one baseband chain with receiver and
transmitter– Time-Division Duplexing (TDD) systems only
Compact TDD Wireless Transceiver
Q
I
DAC
DAC
Q
ADC
ADC
DC Offset Cancellation
DC Offset Cancellation
Synthesizer
Frequency
LNA
PA
LPF VGA
VGALPF
I
Compact TDD Wireless Transceiver:Receive Mode
VGA
VGA
DC Offset Cancellation
LPF
LNA
Frequency
Synthesizer
LPF
DC Offset Cancellation
I
ADC
ADC
Q
Compact TDD Wireless Transceiver:Transmit Mode
VGA
DC Offset Cancellation
DC Offset Cancellation
DAC
VGAPA
Frequency
Synthesizer
LPF
LPFI
Q
DAC
Design Issues
• TDD systems only• Dynamic behavior due to switches
– Settling time• DC feedback loop• Automatic Gain Control (AGC) loop
– Synchronization with RF T/R switches
DC Offset Cancellation in Direct Conversion
Multistandard Wireless Receivers
Possible WiMAX/Super 3G Radio
• DC offset corrupts the signal and may saturate the analog baseband stages
Generation of DC Offsets in DCR
• Transistor mismatches in the signal path• Second-order intermodulation (IM2) of the
components such as LNAs, mixers, and filters…
• Self-mixing of LO signal leaking into LNA input and mixer RF input
• Self-mixing of LO signal leaking into, radiated from, and reflected back to antenna
• Self-mixing of strong in-band interferers leaking into mixer LO input
LNA
LO Leakage
LNA
LO Leakage
LNA
Interferer Leakage
Self-mixing due to interferer leakage
Self-mixing due to LO leakage Self-mixing due to LO leakage radiated
DC Offsets Generated by Three Self-Mixing Mechanisms
Modeling of DC Offsets
• Goal: Identifying static (time-invariant) and dynamic (time-varying) DC offsets generated by three self-mixing mechanisms:– Self-mixing due to LO leakage (2 cases)– Self-mixing due to interferer leakage
• Assumption: components (e.g. LNA, mixer, filter) are ideal (No nonlinearities)
• I-branch only
Ideally…
u(t) x(t)s(t) y(t)LPFLNA
l(t)
Using complex envelop representation…
Received signal:
LO signal:
A: LNA gain
b(t): information signalfc: carrier frequency
Self-Mixing due to LO Leakage
LNA
LO Leakage
l(t)
y(t)s(t) x(t)
12K K
LNA LPFu(t)
Self-Mixing due to LO Leakage
l(t)
y(t)s(t) x(t)
12K K
LNA LPFu(t)
Static DC offset
LNA
LO Leakage
3K
x(t)s(t) y(t)
l(t)
Doppler Shift
LNA LPFu(t)
Self-Mixing due to LO Leakage Radiated
Doppler Effect
fDS: Doppler shiftv: relative speedfc: carrier frequencyc: speed of lightα: angle of arrival
Maximum Doppler shift (α = 0) whenAverage human walking speed: 3.5 mphAverage vehicle driving speed: 60 mph
Self-Mixing due to LO Leakage Radiated
3K
x(t)s(t) y(t)
l(t)
Doppler Shift
LNA LPFu(t)
Dynamic DC offset
Self-Mixing due to Interferer Leakage
LNA
Interferer Leakage
u(t) x(t)y(t)s(t)
K 4
LNA LPF
l(t)
Self-Mixing due to Interferer Leakage
( fi: interferer frequency )
( fo= fi – fc )
u(t) x(t)y(t)s(t)
K 4
LNA LPF
l(t)
Static DC offset
Dynamic DC offset
Static and dynamic DC offsets
Static DC offset
Dynamic DC offset
( fo= fi – fc )Static DC offset
Dynamic DC offset
DC offsets in Frequency Domain
Static DC offsetDynamic DC offsetat unknown frequency foDesired signal
ffo0
To cancel static DC offset High-pass filter
To cancel dynamic DC offset Tunable Notch filter
DC Offset Cancellation in Analog Domain
VGALPFI
Q
ADC
ADCVGA
o90
LNABPF
LPF
Canceller
Canceller
DC Offset Canceller in Analog Domain
• AC Coupling• High Pass Filter• DC Feedback Loop
A1
H(s) A2
Good for static DC offset cancellationDifficult to remove dynamic DC offset
Transfer function:
DC Offset Cancellation in Digital Domain
I
Q
ADCVGA
DAC
90o
LNABPF
VGA ADC
LPF
DAC
LPF
DSP
DC Offset Canceller in Digital Domain
• Measure DC offset in digital domain and subtract it• For TDMA burst mode system:
– Measure DC offset using short known symbols in preamble– Subtract the measured value during reception using DAC
• For TDMA burst mode QPSK system:– Accumulate DC offset corrupted signals for a predetermined time
period to obtain the average of DC offset– Subtract the average value using DAC
Good for dynamic DC offset cancellationStill difficult to remove fast varying dynamic DC offsetNeed DAC for subtractingFor specific systems only, e.g. TDMA systems
For Multistandard DCR…
• The most concern is losing information…• The most important factor to consider
Information is at/near DC?• Modulation schemes!
– FSK: no information at DC– PSK: considerable energy around DC
• But in wideband systems HPF won’t degrade the performance much even in PSK• Most of WLAN and 3G standards use wideband systems
Wireless LAN Standards
3G Standards
DC Offset Cancellation for Multistandard DCR
• Static DC offset cancellation– Should be done in analog domain– Tunable HPF or DC feedback loop– To avoid significant degradation, cutoff frequency of HPF
should be about 0.1% of data rate [1]• Dynamic DC offset cancellation
– Should be done in digital domain– Should be working for most of systems
Adaptive filtering technique! (adaptive noise canceller)
[1] B. Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE Transactions on Circuits and Systems II, vol. 44, no. 6, June 1997
Multistandard DCR with DC Offset Cancellation I
DSPControl
Signals
HPF
HPF
Static DC OffsetCanceller
Canceller
Dynamic
CancellerDC Offset
DC OffsetCanceller
Dynamic
LPF
o90
LNA
LPFQ
IADCVGA
VGA ADC
Static DC Offset
Using tunable high-pass filters for static DC offset cancellation
Multistandard DCR with DC Offset Cancellation II
DC OffsetCanceller
Dynamic
DSPControl
Signals
Dynamic
CancellerDC Offset
FeedbackDC
FeedbackDC
Static DC OffsetCanceller
Canceller
o90
LNA
LPF
LPFQ
IADCVGA
VGA ADC
Static DC Offset
Using tunable DC feedback loops for static DC offset cancellation
Tunable DC Feedback Loop as Static DC offset canceller
Transfer function:
Gm
CR
AVoutVin
Frequency Response for Two Standards
101
102
103
104
105
106
107
30
35
40
45
50
55
60
Mag
nitu
de (
dB)
Blutooth 802.11b
Bode Diagram
Frequency (rad/sec)
Adaptive Noise Canceller (ANC) asDynamic DC offset canceller
• To track/cancel the dynamic DC offset in real-time, ANC would be the best choice!– ANC need both primary signal and reference signal
y(n)
e(n)
u(n) Adaptive
Filter
d(n)
w(n)
By adapting w(n), y(n) ≈ n1(n)
Primary signal:d(n) = s(n) + n1(n)
Reference signal:u(n) = n2(n)
e(n) = d(n) - y(n)≈ s(n)
signal (s(n)) and noises (n1,2(n)) are uncorrelatednoises (n1(n) and n2(n)) are correlated
Dynamic DC offsets
Dynamic DC offset
( fo= fi – fc )
Dynamic DC offset
Dynamic DC offset sinusoid at fo and fDS
Will be cancelled by static DC offset canceller as fDS is very low
Will be cancelled by dynamic DC offset canceller
ANC as Dynamic DC offset canceller
s(n): broadband signal containing informationo(n): sinusoidal dynamic DC offset at frequency fo
y(n)
e(n)
u(n)
s(n) + o(n) d(n)
Adaptive
Filter
Delay
(Δ)
Adaptive Noise Canceller
w(n)
u(n) = s(n - Δ) + o(n - Δ)
s(n) and s(n - Δ) are uncorrelated because s(n) is a broadband signalo(n) and o(n - Δ) are correlated because o(n) is a sinusoid
e(n) = d(n) - y(n)≈ s(n)
By adapting w(n), y(n) ≈ o(n)
ANC without external reference source(= Adaptive linear forward predictor)
How to Adapt the FIR Filter w(n)
• Least Mean Square (LMS)– Better tracking
w(n+1) = w(n) + μ u(n) e*(n)– Normalized LMS (NLMS)
w(n+1) = w(n) + μNLMS u(n) e*(n)μNLMS = 1/(μ-1 + ||u(n)||2)
• Recursive Least Square (RLS)– Better convergence
Simulation Setup
• Desired signal: 1 Mbps BPSK signal • Dynamic DC offset: 1 MHz and magnitude
bigger than signal by 30dB• Adaptive filter length: 9• Delay: 5• Adaptation using NLMS algorithm:
w(n+1) = w(n) + μNLMS u(n) e*(n)μNLMS = 1/(μ-1 + ||u(n)||2), μ = 0.001
1000-Symbol with Ideal Channel
0 2000 4000 6000 8000 10000 12000−40
−30
−20
−10
0
10
20
30
40AFP input signal d(n) corrupted by offset
0 2000 4000 6000 8000 10000 12000−25
−20
−15
−10
−5
0
5
10
15
20corrected signal and desired signal
es
DC offset corrupted input d(n) : DC offset canceller output e(n)( : when no DC offset applied)
1000-Symbol with Ideal Channel
100 200 300 400 500 600 700 800 900 1000−1
−0.5
0
0.5
1
1.5
2(raw data − demodulated data)2
100 200 300 400 500 600 700 800 900 1000−1
−0.5
0
0.5
1
1.5
2(raw data − demodulated data)2
Squared error of demodulated datawithout cancellation
Squared error of demodulated datawith cancellation
BER Performance with AWGN Channel
0 1 2 3 4 5 6 7 8 9 1010
−6
10−5
10−4
10−3
10−2
10−1
100
BER − BPSK
Eb/N0 [dB]
BE
R
theory w/o offsetoffset with cancellationoffset w/o cancellation
Without dynamic DC offset canceller
With dynamic DC offset canceller
Theory without DC offset
TripleTraCTM 802.11 a/b/gWLAN Radio Transceiver
– Fully integrated 802.11a, 802.11g and 802.11b WLAN radio transceiver
– Multi standard programmable bandwidth
– Front end configurable for all frequency bands
– Minimum external components• Integrated VCO, LNA and filters
– Manufactured in 0.18µm CMOS – 48 QFN/MLF packaging, 7x7mm
footprint– Analog I/Q interface– Lowest power consumption– Partners for complete chip-set
Tx/Rx
Con
figur
able
RF
Dig
itally
P
rogr
amm
able
Anal
og B
aseb
and
DSP
/Mod
em
Rx Rx Rx
Tx Tx
Tx
Band Select(5GHz / 2.4GHz)
Bandwidth Select
Multi-standard WLAN chipset
PA2.4GHz
PA5.8GHz5.2GHz
RF2.4GHz
RF5.8GHz5.2GHz
Analog Base-band
ModemDSSS
ModemOFDM
802.11MAC
MAC,Modempartner
TripleTraCTMPApartner
Frequency Plan for Multi-band Operation
2400 2485 5150 5350 5825
f (MHz)3840 4320
RF Spectrum
Local Oscillator ( LO1)
IF
1310 1565 f (MHz)
Local Oscillator (LO2)
f (MHz)
Baseband
f (MHz)0
0
5470 5725
4160
2400 2485 5150 5350 5825
f (MHz)3840 4320
1310 1565 f (MHz)
f (MHz)
f (MHz)0
0
5470 5725
4160
f (MHz)
I
Q
I
Q
I
Q
I
Q
5GHz LNA
LO1 LO2
RX IF Mixers
2GHz LNA
TX IF Mixers
5GHz LNA
LO1 LO2
RX RF Mixer RX IF Mixers
2GHz LNA
TX IF Mixers
TX RF 5G Mixer
TX RF 2G Mixer2G Preamp
5G Preamp
LPF
LPF
LPF
LPF
5GHz/2.4GHz Multi-Band Transceiver Without Image Rejection
Die photo of multi-standard WLAN radio
3.6mm
3.3m
m
• Die area ~12mm2
• 48-pin QFN pkg• 0.18µm 1P6M
CMOS
RX5 5240MHZ
RX2 2437MHZ
Radio test results
Radio test results
Radio test results
Phase Noise at PA output
Radio test results
Radio test results
Measured PerformanceSummary
ScannerIC™
• Highly-integrated single-chip Discovery/Mobility device that enables users to detect 802.11b/g Access Points (AP) and find an optimum location for connectivity
– Monitors beacon frames and extracts SSID – Measures the signal quality of the WLAN medium, and the network condition including
available bandwidth and channel access delays– Enables seamless AP hand-off
• Implements the 802.11b receiver chain and baseband, as well as a small portion of the standard MAC
– Only external receiver components required are a balun and a bandpass filter– Pin Count: 20– Low Power Consumption: <150 mW– High Sensitivity: -82dBm– 0.18um CMOS Process
HWD
MURATS™
• Single-chip MUlti Radio Access Technology Scanner targeting next generation multi-standard communication appliances– GSM, WCDMA and WLAN scanning and radio measurement
solution– Supports fast and seamless handover/roaming between
heterogeneous radio technologies– “Always Best Connected” - ensuring that users are always
connected to the best RAT (Radio Access Technology) through cell/channel selection or reselection
• Implements the receive chain only operating on low rate broadcast channels– Several complex functions not needed including power control,
security, channel demultiplexing, variable spreading, channel synthesizer
– High block sharing including micro-controller, equalizer, channel decoder, CRC check, ADC, analog RF blocks
– Other RATs added in the future making the device a universal scanner
SWIP™
• Single-chip WLAN Internet Phone targeting the high volume residential/SOHO market
– VoIP based on SIP standardized by IETF in RFC 2543/3261 & TIA/TR41. Supports SIP voice and instant messaging. Implements the emerging 802.11e QoS standard
– Optimized to support the basic rates of 802.11 WLANs, particularly 1-2 Mbit/s
• Contains all the blocks required to build a low-cost VoIP/WLAN handset:
– Low power CPU core, voice codec, embedded memory, various user interface blocks and 802.11 PHY (including PA)
– Pin Count: 96
– Low power consumption: <300mW
– High sensitivity: -82dBm
– 20dBm transmit power
– 0.18um CMOS Process– Supports several low power mode operations
SWIP Hardware Architecture
SWAP™
• Single-chip WLAN Application Platform optimized for low power, small form factor and low cost
• Targeting highly-portable multimedia and IP telephony appliances • Same hardware as SWIP™, but excludes the voice codec & the VoIP
engine– 802.11 MAC, Baseband, RF Front-end and PA– Supports WLAN basic rates of 1-2 Mbit/s via UART interface – Pin Count: 56
– Low power consumption: <250mW
– High sensitivity: -82dBm
– 20dBm transmit power
– 0.18um CMOS Process
– Supports several low power mode operations– Underlying design is 11 Mbits/s capable
Over-Design and Yield Loss in RFICs
Parasitic Effects Random Process Variations
Element Mismatches
Inaccurate Models
Substrate Noise Coupling
Capacitive/Electromagnetic on-chip Coupling
Loading & Interconnects
Degrade Performance Decrease in Yield
Over-design, Non-optimal Power Solutions
Is only one silicon spin important?
• YES!• Three reasons
– NRE costs– Mask set costs– Time to market
NRE Costs
• NRE stands for nonrecurring engineering• It is the cost of paying the design team’s salaries and
overhead for the project duration• Typical design cycle
Specification2-4 weeks
Design3-6 months
Layout2-4 months
Fabrication8 weeks
Test1-3 months6-9 months for 1 design cycle!
Mask Set Costs
$0
$500,000
$1,000,000
$1,500,000
$2,000,000
$2,500,000
$3,000,000
0.35 0.25 0.18 0.13 0.09 0.065
Feature Size (um)
Mask Set Cost
Source: http://www.m2000.fr/products.htm
Total Cost Per Spin
• The cost for a team of 10 people for 9 months is over $500,000
• For a common 0.18 process, the cost of a single mask set is $250,000
• So the dollar cost for the first spin is over $750,000.
• Additional spins take less time and cost less, but can still cost more than $400,000
• However, they can have an impact on the business
Time for Extra Spins
• Even if the dollar cost for the extra spin is not great, the time cost can be the biggest expense
• If the error is small and can be fixed in 1 month, it still takes the 8 weeks to fabricate the new chip
• Then the new chip has to be tested again, which is another month slip
• So in the best case, a respin costs about 4 extra months
• This 4 months is time missed in the market, and time the engineers are not working on the next product
Developing a new methodology in designing radio systems based on:
Study of the key system parameters (BER, EVM,…)
Study of the effect of each block non-ideality on the specific system parameter (sensitivity analysis).
Developing self awareness
Monitoring block performance
Developing self calibration)
Global control of parameters
Proposed Methodology
Rx
Con
figur
able
RF
Dig
itally
Prog
ram
mab
leA
nalo
g B
aseb
and
DSP
Rx
Digital Band Select Digital Data Rate &Channel Select
Freq
uenc
y Sy
nthe
size
r
Calibration
off chip passives
Block/Sub-System
Analog / RF Block
CircuitControl
Parameters
AdaptiveDSP Algorithm
A/D
Proposed Methodology
Master ControlInitializationSchedule Supervision and correction
Shared ResourcesA/D and D/A
System
Adaptive DSP, Digital Auto-Calibration
Our Vision for a First-Pass Multi-Mode Receiver
RxC
onfig
urab
le R
F
Dig
itally
Pr
ogra
mm
able
Ana
log
Bas
eban
d
Rx
Digital Band Select
Freq
uenc
y Sy
nthe
size
r
Calibration
DSPGSM,
WCDAM,
WLAN WiMAX,….
AGC,I/Q balance,
DC Offset,….
“Smarts”for
First Pass
Digital Data Rate &Channel Select
off chip passives
Chip under testMulti-standard radio receiver (WiMAX/WLAN,
OFDM UWB) implemented on TSMC0.13 um technology.
Focus on RF RX System Parameters
• Robust – A mature design methodology
• DSP– Enables use of sophisticated signal
processing algorithms– Can be part of a digital baseband in a
wireless chipset• Mature
– Significantly more mature design methodology compared to RF/Analog
• scalable and Flexible• Minimum risk, 1st time-right.
Why Digital Calibration?
FPGA
Demo a First-Time-Right radio
Conclusion I
• Design Techniques achieving maximum hardware share at minimum power consumption (configurable radio, programmable analog baseband)
• Improvement in technology, characterization, packaging techniques are needed
• Migration to future wireless standards for higher data rates and multimedia applications
• Eventual convergence of LAN, WAN, PAN infrastructures for seamless wireless communication
•Need for higher levels of integration, available only in CMOS technologies
• Technology scaling favors multi GHz RFCMOS
• New challenges, careful system partitioning, good mixed signal strategy, maximize digital content
Conclusions II
• As we migrate to high data rates beyond 3G, radio design will become more complex
• CMOS has adequate performance to meet the challenge
• Innovations in frequency planning and radio architecture design will make it happen
• Low power design must be incorporated at all levels, architecture, block and circuit
Thank You!