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AN617

Fixed Point Routines

INTRODUCTION

This application note presents an implementation of thefollowing fixed point math routines for the PICmicromicrocontroller families:

• Multiplication• Division

Routines for the PICmicro microcontroller families areprovided in a variety of fixed point formats, includingboth unsigned and signed two’s complement arith-metic.

Author: Frank J. TestaFJT Consulting

1996 Microchip Technology Inc.

FIXED POINT ARITHMETIC

Unsigned fixed point binary numbers, A, can berepresented in the form

where n is the number of bits, a(k) is the kth bit witha(0) = LSb, and r indicates the location of the radixpoint. For example, in the case where A is an integer,r = 0 and when A is a fraction less than one, r = n. Thevalue of r only affects the interpretation of the numbersin a fixed point calculation, with the actual binaryrepresentation of the numbers independent of thevalue of r. Factoring out of the above sum, it simplylocates the radix point of the representation and isanalogous to an exponent in a floating point system.

Using the notation Qi.j to denote a fixed point binarynumber with i bits to the left of the radix point and j tothe right, the above n-bit format is in Qn-r.r. With care,fixed point calculations can be performed on operandsin different Q formats. Although the radix point must bealigned for addition or subtraction, multiplicationprovides an illustrative example of the simpleinterpretive nature of r. Consider the unsigned productof a Q20.4 number with a Q8.8. After calling theappropriate unsigned 24x16 bit multiply for these fixedpoint arguments, the 40-bit fixed point result is inQ28.12, where the arguments of the Q notation aresummed respectively.

Similar arguments can be made for two’s complementarithmetic, where the negative representation of a pos-itive number is obtained by reversing the value of eachbit and incrementing the result by one. Producing aunique representation of zero, and covering the range-2n-1 to 2n-1 - 1, this is more easily applied in additionand subtraction operations and is therefore the mostcommonly used method of representing positive andnegative numbers in fixed point arithmetic.

The above analysis in Q notation can be employed tobuild dedicated fixed point algorithms, leading toimproved performance over floating point methods incases where the size of the arguments required for therange and precision of the calculations is not largeenough to destroy gains made by fixed point methods.

A a k( ) 2k rÐ

2rÐ

a k( ) 2k⋅

k 0=

n 1Ð

∑=⋅k 0=

n 1Ð

∑= ,

DS00617B-page 1

AN617

FIXED POINT FORMATS

The fixed point library routines supports 8-,16-, 24- and32-bit formats in the combinations shown in Table 1.

These general format combinations are implementedin both signed and unsigned versions. Additionalunsigned routines are implemented with arguments

DS00617B-page 2

reduced by one bit to accommodate the case ofoperations on signed numbers, with arguments knownto be nonnegative, thereby, resulting in someperformance improvement.

TABLE 1: FIXED POINT LIBRARY ROUTINE SUMMARY TABLE

Division Library Names Format Multiplication Library Names Format

PIC16C5X/PIC16CXXX Routines

FXD0808S, FXD0808U, FXD0807U, FXD0707U

8/8 FXM0808S, FXM0808U, FXM0807U 8x8


16/8 FXM1608S, FXM1608U, FXM1607U, FXM1507U

16x8

FXD1616S, FXD1616U, FXD1515U 16/16 FXM1616S, FXM1616U, FXM1515U 16x16






PIC17CXXX Functions


8/8 FXM0808S, FXM0808U 8x8


16/8 FXM1608S, FXM1608U 16x8


16/16 FXM1616S, FXM1616U 16x16


24/16 FXM2416S, FXM2416U 24x16


24/24 FXM2424S, FXM2424U 24x24


32/16 FXM3216S, FXM3216U 32x16


32/24 FXM3224S, FXM3224U 32x24


32/32 FXM3232S, FXM3232U 32x32

Note: U - unsigned math operation, S - signed math operation


AN617

DATA RAM REQUIREMENTS

Table 2 shows the contiguous data RAM locations thatare used by the library.

TABLE 2: DATA RAM REQUIREMENTSAARGB7 = REMB3AARGB6 = REMB2AARGB5 = REMB1AARGB4 = REMB0 remainder MSBAARGB3AARGB2AARGB1 AARGB0 AARG MSBAEXP AARG exponentSIGN signFPFLAGS exception flags and option bitsBARGB3BARGB2BARGB1BARGB0 BARG MSBBEXP BARG exponentTEMPB3TEMPB2TEMPB1TEMPB0 temporary storage

These definitions are identical with those used by theIEEE 754 compliant floating point library[5], AN575.

USAGE

Multiplication assumes the multiplicand in AARG,multiplier in BARG, and produces the result in AARG.Division assumes a dividend in AARG, divisor inBARG, and quotient in AARG with remainder in REM.

ADDITION/SUBTRACTION

Because of the generally trivial nature of addition andsubtraction, the call and return overhead outweighs theneed for explicit routines and so they are not includedin the library. However, the PIC16C5X/PIC16CXXXfamilies do not have an add with carry or subtract withborrow instruction, leading to subtleties regardingproduction of a correct carry-out in a multiple byte addor subtract. In the case of a two byte add or subtract,the most elegant solution to these difficulties, requiring6 cycles, appears to be given by the following code inExample 1.


EXAMPLE 1: TWO BYTE ADDITION/SUBTRACTION ROUTINES

ADD MOVF AARGB1,W ADDWF BARGB1

MOVF AARGB0,W BTFSC _C INCFSZ AARGB0,W ADDWF BARGB0

SUB MOVF AARGB1,W SUBWF BARGB1

MOVF AARGB0,W BTFSS _C INCFSZ AARGB0,W SUBWF BARGB0

The four instructions after the initial add/subtract, canbe easily concatenated for operations involving morethan two bytes. Because addition and subtraction arerequired in standard algorithms for multiplication anddivision, these issues permeate the implementation ofboth fixed and floating point algorithms for thePIC16C5X/PIC16CXXX families.

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AN617

MULTIPLICATION

The existing library of fixed point math routines for thePICmicro families of microcontrollers contains multipli-cation routines in the following format combinations:

¥ 8x8

¥ 16x8

¥ 16x16

¥ 24x16

¥ 24x24

¥ 32x16

¥ 32x24

¥ 32x32

The fixed point multiply routine FXMxxyy, takes anxx-bit multiplicand in AARG, a yy-bit multiplier in BARGand returns the (xx+yy)-bit product in AARG.

For the PIC17 family, both unsigned and signed algo-rithms use extended precision application of the 8x8hardware multiply currently available. The essence ofan extended precision interpretation is to view eachargument as a concatenation of bytes of differentorders of magnitude and evaluate the product by eval-uating all 8x8 terms in the algebraic expansion. Forexample, the 24x16 multiply yields a 40-bit product andcontains 6 individual 8x8 terms in its expansion.

(AARGB0⋅216+AARGB1⋅28+AARGB2⋅20) ⋅ (BARGB0⋅28+BARGB1⋅20) =

AARGB0⋅BARGB0⋅224 +

(AARGB0⋅BARGB1+AARGB1⋅BARGB0)⋅216 +

(AARGB1⋅BARGB1+AARGB2⋅BARGB0)⋅28 +

AARGB2⋅BARGB1⋅20

This is completely analogous to arithmetic in base28 = 256, where the respective digit products must bealigned according to their orders of magnitude beforesummation. It is important to note that no carryoutbeyond the sum of the lengths of the arguments canoccur[1]. This fact is helpful in constructing algorithmsfor cases with a large number of terms. For example,the 32x16 case containing 8 individual 8x8 terms, canbe viewed as a 24x16 product between the 3 least sig-nificant bytes of AARG with BARG, producing no carry-out, followed by augmentation with the remaining twoterms. This philosophy has been applied in optimizingthe unsigned algorithms, using the shorter products asbuilding blocks for the larger ones.

DS00617B-page 4

The signed fixed point multiply routines require properhandling of the fact that the 8x8 hardware multiply isunsigned. It can be proven (see Appendix C) that theproduct of signed numbers in two’s complement repre-sentation can be obtained by computing their productas if they were unsigned and for each negative argu-ment, subtract the opposite argument from the mostsignificant bits of the product. In most cases, the opti-mal algorithm is to simply apply this at the end of thecorresponding unsigned method to achieve the signedproduct.

The implementation for the PIC16CXXX family uses astandard sequential add-shift algorithm, negating bothfactors if BARG < 0, to produce the positive multiplierrequired by the method. Analogous to simple longhandbinary multiplication, the multiplier bits are sequentiallytested, with one indicating an add-shift and zero simplya shift. The shift is required to align the partial productfor the next possible add[1]. Two examples are shownin Example 2.

EXAMPLE 2: MULTIPLICATION EXAMPLES

FXM2416S(0xC11682,0x608B)

= FXM2416S(-4123006,24715)

= 0xE84647F896

= -101900093290

FXM1616U(0x0458,0x822C)

= FXM1616U(1112,33324)

= 0x02356F20

= 37056288


AN617

Table 3 shows PIC17CXXX Fixed Point multiplicationperformance data. The listed routines can be found inAppendix F.


TABLE 3: PIC17CXXX FIXED POINT MULTIPLY PERFORMANCE DATA

Routine Max Cycles Min Cycles Average Cycles Program Memory Data Memory

FXM0808S 14 14 14 10 3

FXM0808U 9 9 9 5 3

FXM1608S 24 21 23 20 4

FXM1608U 15 15 15 11 4

FXM1616S 42 34 38 38 8

FXM1616U 29 29 29 25 7

FXM2416S 59 49 54 55 10

FXM2416U 43 43 43 39 8

FXM2424S 84 72 78 80 12

FXM2424U 68 68 68 64 12

FXM3216S 76 64 70 72 12

FXM3216U 57 57 57 53 9

FXM3224S 111 97 104 107 15

FXM3224U 93 93 93 89 15

FXM3232S 148 132 140 144 18

FXM3232U 128 128 128 124 18

DS00617B-page 5

AN617

Table 4 shows the PIC16C5X/PIC16CXXX Fixed PointMultiply performance data. The listed routines can befound in Appendix D.

DS00617B-page 6

TABLE 4: PIC16C5X/PIC16CXXX FIXED POINT MULTIPLY PERFORMANCE DATA


FXM0808S 91 9 85 33 5

FXM0808U 76 57 74 21 4

FXM0707U 70 51 67 23 4

FXM1608S 110 11 85 44 7

FXM1608U 129 61 105 31 7

FXM1507U 86 27 64 35 7

FXM1616S 284 11 235 74 9

FXM1616U 259 110 214 58 9

FXM1515U 247 105 205 63 9

FXM2416S 353 132 281 92 12

FXM2416U 328 113 260 70 12

FXM2315U 321 108 248 76 12

FXM2424S 533 241 432 126 13

FXM2424U 497 258 401 98 13

FXM2323U 481 230 390 107 13

FXM3216S 440 48 327 98 9

FXM3216U 415 116 304 84 9

FXM3115U 395 111 291 91 9

FXM3224S 656 253 502 152 15

FXM3224U 620 201 470 151 15

FXM3123U 587 255 457 129 15

FXM3232S 841 411 686 189 17

FXM3232U 794 443 645 168 17

FXM3131U 787 392 631 168 17


AN617

DIVISION

The fixed point divide routine FXPDxxyy, takes anxx-bit dividend in AARG, a yy-bit divisor in BARG andreturns the xx-bit quotient in AARG and yy-bit remain-der in REM. Unlike multiplication, division is notdeterministic, requiring a trial-and-error sequential shiftand subtract process. Binary division is lesscomplicated than decimal division because thepossible quotient digits are only zero or one. If thedivisor is less than the partial remainder, thecorresponding quotient bit is set to one followed by ashift and subtract. Otherwise, the divisor is greater thanthe partial remainder, the quotient bit is set to zero andonly a shift is performed. The intermediate partialremainder may be restored at each stage as inrestoring division, or corrected at the end as innonrestoring division. Implementation dependenttrade-offs between worst case versus averageperformance affect the choice between these twoapproaches, and therefore, macros for each methodare provided.

The results of the division process for AARG/BARG,satisfy the relation

AARG = BARG ⋅ QUOTIENT + REMAINDER,

where the remainder has the same sign as thequotient, and represents the fraction of the result inunits of the denominator BARG. Some simpleexamples are given in Example 3.

EXAMPLE 3: DIVISION EXAMPLES

FXD1608S(0xC116,0x60) = 0xFF59, 0xB6

FXD1616U(0x9543,0x4AA1) = 0x0002, 0x0001

Note: A test for divide by zero exception is notperformed and must be explicitly providedby the user.

DS00617B-page 7

AN617

Table 5 shows the PIC17CXXX Fixed Point Divide per-formance data. The listed routines can be found inAppendix G

DS00617B-page 8

TABLE 5: PIC17CXXX FIXED POINT DIVIDE PERFORMANCE DATA


FXD0808S 91 85 89 77 4

FXD0808U 78 74 77 74 3

FXD0807U 69 69 69 65 3

FXD0707U 64 64 64 60 3

FXD1608S 162 44 156 146 5

FXD1608U 196 170 183 195 4

FXD1607U 133 133 133 129 4

FXD1507U 128 128 128 124 4

FXD1616S 219 200 211 241 7

FXD1616U 247 227 244 243 6

FXD1615U 188 182 184 216 6

FXD1515U 182 177 179 218 6

FXD2416S 315 291 305 353 8

FXD2416U 352 342 347 453 8

FXD2415U 283 272 277 339 8

FXD2315U 275 266 270 330 8

FXD2424S 387 361 377 482 10

FXD2424U 422 415 419 577 10

FXD2423U 352 344 347 460 9

FXD2323U 344 337 341 448 9

FXD3216S 415 382 400 476 9

FXD3216U 468 459 463 608 9

FXD3215U 375 363 369 451 8

FXD3115U 368 357 362 442 8

FXD3224S 514 477 496 639 11

FXD3224U 566 553 560 769 11

FXD3223U 476 459 465 612 10

FXD3123U 466 451 457 600 10

FXD3232S 610 572 593 800 13

FXD3232U 665 650 655 930 13

FXD3231U 567 555 560 773 12

FXD3131U 558 547 552 758 12


AN617

Table 6 shows the PIC16C5X/PIC16CXXX Fixed PointDivide performance data. The listed routines can befound in Appendix E.


TABLE 6: PIC16C5X/PIC16CXXX FIXED POINT DIVIDE PERFORMANCE DATA

REFERENCES

1. Cavanagh, J.J.F., “Digital Computer Arithmetic,” McGraw-Hill,1984.2. Hwang, K., “Computer Arithmetic,” John Wiley & Sons, 1979.3. Scott, N.R., “Computer Number Systems & Arithmetic,” Prentice Hall, 1985.4. Knuth, D.E., “The Art of Computer Programming, Volume 2,” Addison-Wesley, 1981.5. F.J.Testa, “IEEE 754 Compliant Floating Point Routines,” AN575, Embedded Control Handbook, Microchip Tech-

nology Inc., 1995.


FXD0808S 131 36 109 41 5

FXD0808U 103 95 102 15 4

FXD0807U 91 91 91 21 4

FXD0707U 83 83 83 44 4

FXD1608S 181 49 159 67 6

FXD1608U 297 237 269 41 7

FXD1607U 177 177 177 41 5

FXD1507U 169 169 169 44 5

FXD1616S 334 302 315 74 8

FXD1616U 376 316 371 27 7

FXD1515U 292 277 280 45 7

FXD2416S 447 408 427 140 8

FXD2416U 524 504 510 172 8

FXD2315U 402 382 388 120 7

FXD2424S 570 528 549 253 12

FXD2424U 641 624 630 226 13

FXD2323U 520 502 508 211 12

FXD3216S 584 67 561 201 10

FXD3216U 694 671 680 243 9

FXD3115U 534 509 518 160 9

FXD3224S 747 695 722 280 11

FXD3224U 853 830 838 299 11

FXD3123U 692 668 676 232 10

FXD3232S 909 855 885 357 13

FXD3232U 1012 990 998 364 13

FXD3131U 851 828 836 304 13

DS00617B-page 9

AN617

APPENDIX A: ALGORITHMSSeveral algorithms for decimal to binary conversion aregiven below. The integer and fractional conversionalgorithms are useful in both native assembly as wellas high level languages.

A.1 Integer conversion algorithm[3]:

Given an integer I, where d(k) are the bit values of itsn- bit binary representation with d(0) = LSB,

k=0

I(k) = I

while I(k) = ! 0

d(k) = remainder of I(k)/2

I(k+1) = I(k)/2

k = k + 1

endw

where denotes the greatest integer function (orceiling function).

I d k( ) 2k⋅

k 0=

n 1Ð

∑=

DS00617B-page 10

A.2 Fractional conversion algorithm[3]:

Given a fraction F, where d(k) are the bit values of its nbit binary representation with d(1) = MSB,

k=0

F(k) = F

while k <= n

d(k) = F(k)⋅ 2

F(k+1) = fractional part of F(k) ⋅ 2

k = k + 1

endw

F d k( ) 2kÐ⋅

k 1=

n

∑=


AN617

APPENDIX B: FLOWCHARTS

FIGURE B-1: MULTIPLICATION FLOWCHART FOR PIC16CXX

FXMxxU

i = 0clear high orderpartial product

multiplierbit i = 1?

add multiplicandto high order

partial product

right shiftpartial product

i = i + 1

i < n?

Return

FXMxxS

i = 0clear high orderpartial product

negate multiplierand multiplicand

save sign of result

multiplierbit i = 1?

add multiplicandto high order

partial product

right shift partialproduct with

sign extensioni = i + 1

i < n - 1?

Yes

No

Yes

No

Yes

Yes

Yes

No

No

No

multiplier < 0?

and indicateno error

Returnand indicate

no error

1996 Microchip Technology Inc. DS00617B-page 11

AN617

FIGURE B-2: MULTIPLICATION FLOWCHART FOR PIC17CXXX

FXMxxU

Compute, addaligned byte products of

FXMxxS

subtract BARGfrom most

significant bytes of

Yes

Yes

No

No

AARG < 0?

BARG < 0?

AARG * BARG

Compute, addaligned byte products of

AARG * BARG

product

subtract AARGfrom most

significant bytes ofproduct

Returnand indicate

no error

Returnand indicate

no error

DS00617B-page 12 1996 Microchip Technology Inc.

AN617

FIGURE B-3: DIVISION FLOWCHART

FXDxxU

i = 0clear remainderpartial quotient

i < n?No

Yes

= dividend

left shift(remainder,

quotient)

subtract divisionfrom partialremainder

result > 0?

restore partialquotient,LSb = 0


Yes

No

FXDxxS

compute signof quotient

divisor < 0?

negatedivisor

dividend < 0?

negatedividend

i = 0clear remainderpartial quotient

= dividend

i < n - 1? A

A

Yes

No

No

Yes

Yes

No

left shift(remainder,

quotient)

subtract divisorfrom partialremainder

result > 0?

partial quotientLSb = 1


Yes

No

Returnand indicate

no error

Returnand indicate

no error


AN617

APPENDIX C:Consider arguments to a two’s complement multiply expressed in the form

where

Then

with

being the unsigned product of the two’s complement representations and the correction term c given by

Case 1:

For this case with both arguments negative we obtain

where

and

yielding the bounds .

The bounded quantity can then be expressed in the form ,

where is the result of truncating the above bounded quantity to m+n bits. This gives the final value for the correction term in the form

where the

term has been cancelled by the carry during the evaluation of

leading to the result

Case 2:

The case with one or both arguments positive gives the simpler result

where

and therefore a carry out is not possible.

A am 1Ð 2m

Ð Au+= B bn 1Ð 2n

Ð Bu+=,

Au ai2i

i 0=

m 1Ð

∑≡ Bu bi2i

i 0=

n 1Ð

∑≡,

p A B⋅ p ′ c+= =

p ′ Au Bu⋅≡

c am 1Ð bn 1Ð 2m n+

am 1Ð Bu2m

bn 1Ð Au2n }+

Ð≡

am 1Ð bn 1Ð 1= =

c 2m n+

Bu2m

Au2n }+

Ð=

2n 1Ð

Bu 2n<≤

2m 1Ð

Au 2m<≤

2m n+

Bu2m

Au2n

+ 2m n 1+ +<≤

Bu2m

Au2n

+

Bu2m

Au2n

2m n+

Tu+≡+

Tu 2m n+<

c TuÐ=

2m n+

Bu2m

Au2n

+

p p ′ c+ p ′ TuÐ= =

am 1Ð bn 1Ð⋅ 0=

c am 1Ð Bu2m

bn 1Ð Au2n }+

Ð=

c 2m n+<


AN617

APPENDIX D: MULTIPLY ROUTINES FOR THE PIC16C5X/PIC16CXXXTable of Contents for Appendix DD.1 32x32 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 15D.2 32x24 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 37D.3 32x16 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 55D.4 24x24 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 69D.5 24x16 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 85D.6 16x16 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 97D.7 16x8 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 108D.8 8x8 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines .......................................................................... 116

D.1 32x32 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines; RCS Header $Id: fxm22.a16 2.3 1996/10/16 14:23:23 F.J.Testa Exp $

; $Revision: 2.3 $

; 32x32 PIC16 FIXED POINT MULTIPLY ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: product AARGxBARG in AARG;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed multiply application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXM3232S 889 32x32 -> 64 bit signed fixed point multiply;; FXM3232U 856 32x32 -> 64 bit unsigned fixed point multiply;; FXM3131U 836 31x31 -> 62 bit unsigned fixed point multiply;; The above timings are based on the looped macros. If space permits,; approximately 128-168 clocks can be saved by using the unrolled macros.;

;**********************************************************************************************;**********************************************************************************************

; 32x32 Bit Multiplication Macros

SMUL3232L macro

; Max Timing: 2+13+6*26+25+2+7*27+26+2+7*28+27+2+6*29+28+9 = 851 clks

; Min Timing: 2+7*6+5+1+7*6+5+1+7*6+5+2+6*6+5+6 = 192 clks

; PM: 31+25+2+26+2+27+2+28+9 = 152 DM: 17

MOVLW 0x8 MOVWF LOOPCOUNT

LOOPSM3232A RRF BARGB3, F BTFSC _C

Please check the Microchip BBS for the latest version of the source code. For BBS access information,see Section 6, Microchip Bulletin Board Service information, page 6-3.


AN617

GOTO ALSM3232NA DECFSZ LOOPCOUNT, F GOTO LOOPSM3232A

MOVWF LOOPCOUNT

LOOPSM3232B RRF BARGB2, F BTFSC _C GOTO BLSM3232NA DECFSZ LOOPCOUNT, F GOTO LOOPSM3232B

MOVWF LOOPCOUNT

LOOPSM3232C RRF BARGB1, F BTFSC _C GOTO CLSM3232NA DECFSZ LOOPCOUNT, F GOTO LOOPSM3232C


LOOPSM3232D RRF BARGB0, F BTFSC _C GOTO DLSM3232NA DECFSZ LOOPCOUNT, F GOTO LOOPSM3232D

CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 RETLW 0x00

ALOOPSM3232 RRF BARGB3, F BTFSS _C GOTO ALSM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALSM3232NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO ALOOPSM3232


AN617


BLOOPSM3232 RRF BARGB2, F BTFSS _C GOTO BLSM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLSM3232NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F DECFSZ LOOPCOUNT, F GOTO BLOOPSM3232


CLOOPSM3232 RRF BARGB1, F BTFSS _C GOTO CLSM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

CLSM3232NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F DECFSZ LOOPCOUNT, F GOTO CLOOPSM3232

MOVLW 0x7


AN617

MOVWF LOOPCOUNT

DLOOPSM3232 RRF BARGB0, F BTFSS _C GOTO DLSM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

DLSM3232NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F DECFSZ LOOPCOUNT, F GOTO DLOOPSM3232

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

endm

UMUL3232L macro

; Max Timing: 2+15+6*25+24+2+7*26+25+2+7*27+26+2+7*28+27 = 842 clks

; Min Timing: 2+7*6+5+1+7*6+5+1+7*6+5+1+7*6+5+6 = 197 clks

; PM: 38+24+2+25+2+26+2+27+9 = 155 DM: 17


LOOPUM3232A RRF BARGB3, F BTFSC _C GOTO ALUM3232NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM3232A

MOVWF LOOPCOUNT


AN617

LOOPUM3232B RRF BARGB2, F BTFSC _C GOTO BLUM3232NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM3232B

MOVWF LOOPCOUNT

LOOPUM3232C RRF BARGB1, F BTFSC _C GOTO CLUM3232NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM3232C

MOVWF LOOPCOUNT

LOOPUM3232D RRF BARGB0, F BTFSC _C GOTO DLUM3232NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM3232D

CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 RETLW 0x00 ALUM3232NAP BCF _C GOTO ALUM3232NA BLUM3232NAP BCF _C GOTO BLUM3232NA CLUM3232NAP BCF _C GOTO CLUM3232NA DLUM3232NAP BCF _C GOTO DLUM3232NA

ALOOPUM3232 RRF BARGB3, F BTFSS _C GOTO ALUM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALUM3232NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F


AN617

RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO ALOOPUM3232


BLOOPUM3232 RRF BARGB2, F BTFSS _C GOTO BLUM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLUM3232NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F DECFSZ LOOPCOUNT, F GOTO BLOOPUM3232


CLOOPUM3232 RRF BARGB1, F BTFSS _C GOTO CLUM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

CLUM3232NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F


AN617

RRF AARGB6, F DECFSZ LOOPCOUNT, F GOTO CLOOPUM3232


DLOOPUM3232 RRF BARGB0, F BTFSS _C GOTO DLUM3232NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

DLUM3232NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F DECFSZ LOOPCOUNT, F GOTO DLOOPUM3232

endm

UMUL3131L macro

; Max Timing: 2+15+6*25+24+2+7*26+25+2+7*27+26+2+6*28+27+8 = 822 clks

; Min Timing: 2+7*6+5+1+7*6+5+1+7*6+5+2+6*6+5+6 = 192 clks

; PM: 39+24+2+25+2+26+2+27+8 = 155 DM: 17



MOVWF LOOPCOUNT

LOOPUM3131B RRF BARGB2, F BTFSC _C GOTO BLUM3131NAP


AN617

DECFSZ LOOPCOUNT, F GOTO LOOPUM3131B

MOVWF LOOPCOUNT



LOOPUM3131D RRF BARGB0, F BTFSC _C GOTO DLUM3131NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM3131D

CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 RETLW 0x00 ALUM3131NAP BCF _C GOTO ALUM3131NA BLUM3131NAP BCF _C GOTO BLUM3131NA CLUM3131NAP BCF _C GOTO CLUM3131NA DLUM3131NAP BCF _C GOTO DLUM3131NA


ALUM3131NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F


AN617

GOTO ALOOPUM3131





CLOOPUM3131 RRF BARGB1, F BTFSS _C GOTO CLUM3131NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

CLUM3131NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F DECFSZ LOOPCOUNT, F GOTO CLOOPUM3131


AN617


DLOOPUM3131 RRF BARGB0, F BTFSS _C GOTO DLUM3131NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

DLUM3131NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F DECFSZ LOOPCOUNT, F GOTO DLOOPUM3131

RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

endm

SMUL3232 macro

; Max Timing: 9+7*22+8*23+8*24+7*25+9 = 723 clks

; Min Timing: 62+6 = 68 clks

; PM: 68+6+7*22+8*23+8*24+7*25+9 = 788 DM: 16

variable i = 0 while i < 8 BTFSC BARGB3,i GOTO SM3232NA#v(i)

variable i = i + 1


AN617

endw

variable i = 8 while i < 16 BTFSC BARGB2,i-8 GOTO SM3232NA#v(i)

variable i = i + 1

endw


variable i = i + 1

endw


variable i = i + 1

endw

CLRF AARGB0 ; if we get here, BARG = 0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 RETURN

SM3232NA0 RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = 1

while i < 8

BTFSS BARGB3,i GOTO SM3232NA#v(i)SM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C


AN617

INCFSZ TEMPB0,W ADDWF AARGB0, FSM3232NA#v(i) RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB2,i-8 GOTO SM3232NA#v(i)SM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM3232NA#v(i) RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

variable i = i + 1

endw

variable i = 16

while i < 24

BTFSS BARGB1,i-16 GOTO SM3232NA#v(i)SM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM3232NA#v(i) RLF SIGN,W


AN617

RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F

variable i = i + 1

endw

variable i = 24

while i < 31

BTFSS BARGB0,i-24 GOTO SM3232NA#v(i)SM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM3232NA#v(i) RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

variable i = i + 1

endw

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

endm

UMUL3232 macro

; Max Timing: 9+8*21+8*22+8*23+8*24 = 729 clks


; PM: 69+6+8*21+8*22+8*23+8*24 = 795 DM: 16


AN617

variable i = 0

BCF _C ; clear carry for first right shift while i < 8 BTFSC BARGB3,i GOTO UM3232NA#v(i)

variable i = i + 1

endw

variable i = 8 while i < 16 BTFSC BARGB2,i-8 GOTO UM3232NA#v(i)

variable i = i + 1

endw


variable i = i + 1

endw


variable i = i + 1

endw


UM3232NA0 RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = 1

while i < 8

BTFSS BARGB3,i GOTO UM3232NA#v(i)


AN617

UM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3232NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB2,i-8 GOTO UM3232NA#v(i)UM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3232NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

variable i = i + 1

endw

variable i = 16

while i < 24

BTFSS BARGB1,i-16 GOTO UM3232NA#v(i)UM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W


AN617

ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3232NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F

variable i = i + 1

endw

variable i = 24

while i < 32

BTFSS BARGB0,i-24 GOTO UM3232NA#v(i)UM3232A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3232NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

variable i = i + 1

endw

endm

UMUL3131 macro

; Max Timing: 9+7*21+8*22+8*23+7*24+9 = 693 clks


; PM: 68+6+7*22+8*23+8*24+7*25+9 = 788 DM: 16


AN617

variable i = 0

BCF _C ; clear carry for first right shift

while i < 8 BTFSC BARGB3,i GOTO UM3131NA#v(i)

variable i = i + 1

endw

variable i = 8

while i < 16 BTFSC BARGB2,i-8 GOTO UM3131NA#v(i)

variable i = i + 1

endw

variable i = 16


variable i = i + 1

endw

variable i = 24


variable i = i + 1

endw



variable i = 1

while i < 8

BTFSS BARGB3,i


AN617

GOTO UM3131NA#v(i)UM3131A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3131NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 8

while i < 16


variable i = i + 1

endw

variable i = 16

while i < 24

BTFSS BARGB1,i-16 GOTO UM3131NA#v(i)UM3131A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C


AN617

INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3131NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F

variable i = i + 1

endw

variable i = 24

while i < 31

BTFSS BARGB0,i-24 GOTO UM3131NA#v(i)UM3131A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3131NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

variable i = i + 1

endw

RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F RRF AARGB6, F RRF AARGB7, F

endm


AN617

;**********************************************************************************************;********************************************************************************************** ; 32x32 Bit Signed Fixed Point Multiply 32x32 -> 64

; Input: 32 bit signed fixed point multiplicand in AARGB0; 32 bit signed fixed point multiplier in BARGB0

; Use: CALL FXM3232S

; Output: 64 bit signed fixed point product in AARGB0

; Result: AARG <-- AARG x BARG

; Max Timing: 15+851+2 = 868 clks B > 0; 36+851+2 = 889 clks B < 0


; PM: 36+152+1 = 189 DM: 17

FXM3232S CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF AARGB6 CLRF AARGB7 CLRF SIGN MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00 MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB COMF SIGN,F

BTFSS BARGB0,MSB GOTO M3232SOK

COMF BARGB3, F COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB3, F BTFSC _Z INCF BARGB2, F BTFSC _Z INCF BARGB1, F BTFSC _Z INCF BARGB0, F

COMF AARGB3, F COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F INCF AARGB3, F BTFSC _Z INCF AARGB2, F BTFSC _Z INCF AARGB1, F BTFSC _Z INCF AARGB0, F


AN617

BTFSC BARGB0,MSB GOTO M3232SX

M3232SOK MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

SMUL3232L

RETLW 0x00

M3232SX CLRF AARGB4 CLRF AARGB5 CLRF AARGB6 CLRF AARGB7 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F

RETLW 0x00

;**********************************************************************************************;********************************************************************************************** ; 32x32 Bit Unsigned Fixed Point Multiply 32x32 -> 64

; Input: 32 bit unsigned fixed point multiplicand in AARGB0; 32 bit unsigned fixed point multiplier in BARGB0

; Use: CALL FXM3232U

; Output: 64 bit unsigned fixed point product in AARGB0


; Max Timing: 12+842+2 = 856 clks


; PM: 12+155+1 = 168 DM: 17

FXM3232U CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF AARGB7 CLRF AARGB6 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

UMUL3232L

RETLW 0x00


AN617

;**********************************************************************************************;********************************************************************************************** ; 31x31 Bit Unsigned Fixed Point Divide 31x31 -> 62





; Max Timing: 12+822+2 = 836 clks


; PM: 12+155+1 = 168 DM: 17

FXM3131U CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF AARGB7 CLRF AARGB6 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

UMUL3131L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.4 $


;**********************************************************************************************;**********************************************************************************************


SMUL3224L macro

; Max Timing: 2+13+6*26+25+2+7*27+26+2+6*28+27+8 = 618 clks

; Min Timing: 2+7*6+5+1+7*6+5+2+6*6+5+6 = 146 clks

; PM: 25+25+2+26+2+27+8 = 115 DM: 15


LOOPSM3224A RRF BARGB2,F BTFSC _C GOTO ALSM3224NA DECFSZ LOOPCOUNT,F GOTO LOOPSM3224A

MOVWF LOOPCOUNT

LOOPSM3224B RRF BARGB1,F BTFSC _C GOTO BLSM3224NA DECFSZ LOOPCOUNT,F GOTO LOOPSM3224B



AN617

LOOPSM3224C RRF BARGB0,F BTFSC _C GOTO CLSM3224NA DECFSZ LOOPCOUNT,F GOTO LOOPSM3224C


ALOOPSM3224 RRF BARGB2,F BTFSS _C GOTO ALSM3224NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

ALSM3224NA RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F DECFSZ LOOPCOUNT,F GOTO ALOOPSM3224


BLOOPSM3224 RRF BARGB1,F BTFSS _C GOTO BLSM3224NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

BLSM3224NA RLF SIGN,W RRF AARGB0,F RRF AARGB1,F


AN617

RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F DECFSZ LOOPCOUNT,F GOTO BLOOPSM3224


CLOOPSM3224 RRF BARGB0,F BTFSS _C GOTO CLSM3224NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

CLSM3224NA RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F DECFSZ LOOPCOUNT,F GOTO CLOOPSM3224

RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

endm

UMUL3224L macro

; Max Timing: 2+15+6*25+24+2+7*26+25+2+7*27+26 = 617 clks

; Min Timing: 2+7*6+5+1+7*6+5+1+7*6+5+6 = 151 clks

; PM: 31+24+2+25+2+26+2+27 = 139 DM: 15


LOOPUM3224A RRF BARGB2,F BTFSC _C GOTO ALUM3224NAP


AN617

DECFSZ LOOPCOUNT,F GOTO LOOPUM3224A

MOVWF LOOPCOUNT

LOOPUM3224B RRF BARGB1,F BTFSC _C GOTO BLUM3224NAP DECFSZ LOOPCOUNT,F GOTO LOOPUM3224B

MOVWF LOOPCOUNT

LOOPUM3224C RRF BARGB0,F BTFSC _C GOTO CLUM3224NAP DECFSZ LOOPCOUNT,F GOTO LOOPUM3224C

CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 RETLW 0x00 ALUM3224NAP BCF _C GOTO ALUM3224NA BLUM3224NAP BCF _C GOTO BLUM3224NA CLUM3224NAP BCF _C GOTO CLUM3224NA

ALOOPUM3224 RRF BARGB2,F BTFSS _C GOTO ALUM3224NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

ALUM3224NA RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F DECFSZ LOOPCOUNT,F GOTO ALOOPUM3224



AN617

BLOOPUM3224 RRF BARGB1,F BTFSS _C GOTO BLUM3224NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

BLUM3224NA RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F DECFSZ LOOPCOUNT,F GOTO BLOOPUM3224


CLOOPUM3224 RRF BARGB0,F BTFSS _C GOTO CLUM3224NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

CLUM3224NA RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F DECFSZ LOOPCOUNT,F GOTO CLOOPUM3224

endm


AN617

UMUL3123L macro

; Max Timing: 2+15+6*25+24+2+7*26+25+2+6*27+26+7 = 597 clks

; Min Timing: 2+7*6+5+1+7*6+5+2+6*6+5+6 = 146 clks

; PM: 31+24+2+25+2+26+7 = 117 DM: 15


LOOPUM3123A RRF BARGB2,F BTFSC _C GOTO ALUM3123NAP DECFSZ LOOPCOUNT,F GOTO LOOPUM3123A

MOVWF LOOPCOUNT

LOOPUM3123B RRF BARGB1,F BTFSC _C GOTO BLUM3123NAP DECFSZ LOOPCOUNT,F GOTO LOOPUM3123B


LOOPUM3123C RRF BARGB0,F BTFSC _C GOTO CLUM3123NAP DECFSZ LOOPCOUNT,F GOTO LOOPUM3123C

CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 RETLW 0x00 ALUM3123NAP BCF _C GOTO ALUM3123NA BLUM3123NAP BCF _C GOTO BLUM3123NA CLUM3123NAP BCF _C GOTO CLUM3123NA

ALOOPUM3123 RRF BARGB2,F BTFSS _C GOTO ALUM3123NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W


AN617

ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

ALUM3123NA RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F DECFSZ LOOPCOUNT,F GOTO ALOOPUM3123


BLOOPUM3123 RRF BARGB1,F BTFSS _C GOTO BLUM3123NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F

BLUM3123NA RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F DECFSZ LOOPCOUNT,F GOTO BLOOPUM3123


CLOOPUM3123 RRF BARGB0,F BTFSS _C GOTO CLUM3123NA MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C


AN617

INCFSZ TEMPB0,W ADDWF AARGB0,F

CLUM3123NA RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F DECFSZ LOOPCOUNT,F GOTO CLOOPUM3123

RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

endm

SMUL3224 macro

; Max Timing: 9+7*22+8*23+7*24+8 = 523 clks


; PM: 46+6+7*22+8*23+7*24+8 = 566 DM: 14


variable i = i + 1

endw


variable i = i + 1

endw


variable i = i + 1


AN617

endw


SM3224NA0 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F

variable i = 1

while i < 8

BTFSS BARGB2,i GOTO SM3224NA#v(i)SM3224A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FSM3224NA#v(i) RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB1,i-8 GOTO SM3224NA#v(i)SM3224A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,F


AN617

SM3224NA#v(i) RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F

variable i = i + 1

endw

variable i = 16

while i < 23

BTFSS BARGB0,i-16 GOTO SM3224NA#v(i)SM3224A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FSM3224NA#v(i) RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

variable i = i + 1

endw

RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

endm

UMUL3224 macro

; Max Timing: 9+8*21+8*22+8*23 = 537 clks


; PM: 47+6+8*21+8*22+8*23 = 581 DM: 14


AN617

variable i = 0


variable i = i + 1

endw


variable i = i + 1

endw


variable i = i + 1

endw


UM3224NA0 RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F

variable i = 1

while i < 8

BTFSS BARGB2,i GOTO UM3224NA#v(i)UM3224A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W


AN617

ADDWF AARGB0,FUM3224NA#v(i) RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB1,i-8 GOTO UM3224NA#v(i)UM3224A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FUM3224NA#v(i) RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F

variable i = i + 1

endw

variable i = 16

while i < 24

BTFSS BARGB0,i-16 GOTO UM3224NA#v(i)UM3224A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FUM3224NA#v(i) RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F


AN617

RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

variable i = i + 1

endw

endm

UMUL3123 macro

; Max Timing: 9+7*21+8*22+7*23+7 = 500 clks


; PM: 47+5+7*22+8*23+7*24+7 = 565 DM: 14

variable i = 0



variable i = i + 1

endw

variable i = 8


variable i = i + 1

endw

variable i = 16


variable i = i + 1

endw


UM3123NA0 RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F


AN617

variable i = 1

while i < 8

BTFSS BARGB2,i GOTO UM3123NA#v(i)UM3123A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FUM3123NA#v(i) RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB1,i-8 GOTO UM3123NA#v(i)UM3123A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FUM3123NA#v(i) RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F

variable i = i + 1

endw

variable i = 16

while i < 23


AN617

BTFSS BARGB0,i-16 GOTO UM3123NA#v(i)UM3123A#v(i) MOVF TEMPB3,W ADDWF AARGB3,F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2,F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1,F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0,FUM3123NA#v(i) RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

variable i = i + 1

endw

RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F RRF AARGB5,F RRF AARGB6,F

endm ;**********************************************************************************************;********************************************************************************************** ; 32x24 Bit Signed Fixed Point Multiply 32x24 -> 56

; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3

; 24 bit signed fixed point multiplier in BARGB0, BARGB1,; BARGB2






; PM: 36+115+1 = 152 DM: 15

FXM3224S CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF AARGB6 CLRF SIGN


AN617

MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00 MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB COMF SIGN,F


COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB2, F BTFSC _Z INCF BARGB1, F BTFSC _Z INCF BARGB0, F




SMUL3224L

RETLW 0x00

M3224SX CLRF AARGB4 CLRF AARGB5 CLRF AARGB6 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F RRF AARGB4,F

RETLW 0x00

;**********************************************************************************************


AN617

;********************************************************************************************** ; 32x24 Bit Unsigned Fixed Point Multiply 32x24 -> 56

; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3

; 24 bit unsigned fixed point multiplier in BARGB0, BARGB1,; BARGB2




; Max Timing: 11+617+2 = 630 clks


; PM: 11+139+1 = 151 DM: 15

FXM3224U CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF AARGB6 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

UMUL3224L

RETLW 0x00


; Input: 31 bit unsigned fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3

; 23 bit unsigned fixed point multiplier in BARGB0, BARGB1,; BARGB2




; Max Timing: 11+597+2 = 610 clks


; PM: 11+117+1 = 129 DM: 15

FXM3123U CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF AARGB6


AN617

MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

UMUL3123L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $


;**********************************************************************************************;**********************************************************************************************


SMUL3216L macro

; Max Timing: 2+13+6*26+25+2+6*27+26+7 = 393 clks

; Min Timing: 2+7*6+5+2+6*6+5+6 = 98 clks

; PM: 19+60 = 79 DM: 11


LOOPSM3216A RRF BARGB1, F BTFSC _C GOTO ALSM3216NA DECFSZ LOOPCOUNT, F GOTO LOOPSM3216A



CLRF AARGB0 CLRF AARGB1


AN617

CLRF AARGB2 CLRF AARGB3 RETLW 0x00

ALOOPSM3216 RRF BARGB1, F BTFSS _C GOTO ALSM3216NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALSM3216NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO ALOOPSM3216


BLOOPSM3216 RRF BARGB0, F BTFSS _C GOTO BLSM3216NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLSM3216NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F DECFSZ LOOPCOUNT, F GOTO BLOOPSM3216

RLF TEMPB0,W RRF AARGB0, F


AN617

RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

endm

UMUL3216L macro

; Max Timing: 2+15+6*25+24+2+7*26+25 = 400 clks

; Min Timing: 2+7*6+5+1+7*6+5+6 = 103 clks

; PM: 73 DM: 11



MOVWF LOOPCOUNT



BLUM3216NAP BCF _C GOTO BLUM3216NA

ALUM3216NAP BCF _C GOTO ALUM3216NA

ALOOPUM3216 RRF BARGB1, F BTFSS _C GOTO ALUM3216NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W


AN617

ADDWF AARGB0, F

ALUM3216NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO ALOOPUM3216




endm

UMUL3115L macro

; Max Timing: 2+15+6*25+24+2+6*26+25+6 = 380 clks

; Min Timing: 2+7*6+5+2+6*6+5+6 = 96 clks

; PM: 80 DM: 11



MOVLW 0x7


AN617

MOVWF LOOPCOUNT






ALUM3115NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO ALOOPUM3115


BLOOPUM3115 RRF BARGB0, F BTFSS _C GOTO BLUM3115NA MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C


AN617

INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F


RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

endm

SMUL3216 macro

; Max Timing: 5+8+7*20+7*21+5 = 305 clks

; Min Timing: 5+24+21+7 = 57 clks

; PM: 5+24+21+6+5+7*20+7*21+5 = 353 DM: 10

variable i = 0

BTFSC SIGN,MSB COMF AARGB4, F MOVF AARGB4,W MOVWF AARGB5 RLF SIGN,W while i < 8 BTFSC BARGB1,i GOTO SM3216NA#v(i) BCF AARGB4,7-i

variable i = i + 1

endw

variable i = 8 while i < 15 BTFSC BARGB0,i-8 GOTO SM3216NA#v(i) BCF AARGB5,15-i

variable i = i + 1

endw


AN617

CLRF AARGB0 ; if we get here, BARG = 0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 CLRF AARGB5 RETURN

SM3216NA0 RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = 1

while i < 8

BTFSS BARGB1,i GOTO SM3216NA#v(i)SM3216A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM3216NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 8

while i < 15

BTFSS BARGB0,i-8 GOTO SM3216NA#v(i)SM3216A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F


AN617

SM3216NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

variable i = i + 1

endw


endm

UMUL3216 macro

; Max Timing: 1+8+7*21+8*22 = 332 clks

; Min Timing: 1+2*8+2*8+6 = 39 clks

; PM: 1+2*8+2*8+6+7*21+8*22 = 362 DM: 10

variable i = 0

BCF _ C ; clear carry for first right shift while i < 8 BTFSC BARGB1,i GOTO UM3216NA#v(i)

variable i = i + 1

endw


variable i = i + 1

endw




AN617

variable i = 1

while i < 8

BTFSS BARGB1,i GOTO UM3216NA#v(i)UM3216A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3216NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 8

while i < 16


variable i = i + 1

endw

endm


AN617

UMUL3115 macro

; Max Timing: 9+7*21+7*22+6 = 316 clks

; Min Timing: 1+30+6 = 37 clks

; PM: 1+30+10+7*21+7*22+6 = 348 DM: 10

variable i = 0



variable i = i + 1

endw

variable i = 8


variable i = i + 1

endw



variable i = 1

while i < 8

BTFSS BARGB1,i GOTO UM3115NA#v(i)UM3115A#v(i) MOVF TEMPB3,W ADDWF AARGB3, F MOVF TEMPB2,W BTFSC _C INCFSZ TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM3115NA#v(i) RRF AARGB0, F


AN617

RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 8

while i < 15


variable i = i + 1

endw









AN617


; PM: 18+79+1 = 98 DM: 9

FXM3216S CLRF AARGB4 ; clear partial product CLRF AARGB5 CLRF SIGN MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00 MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB COMF SIGN,F


COMF BARGB1, F COMF BARGB0, F INCF BARGB1, F BTFSC _Z INCF BARGB0, F




SMUL3216L

RETLW 0x00

M3216SX CLRF AARGB4 CLRF AARGB5 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F


AN617

RRF AARGB4,F

RETLW 0x00






; Max Timing: 10+400+2 = 412 clks


; PM: 10+73+1 = 84 DM: 9

FXM3216U CLRF AARGB4 ; clear partial product CLRF AARGB5 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

UMUL3216L

RETLW 0x00






; Max Timing: 10+380+2 = 392 clks


; PM: 10+80+1 = 91 DM: 9

FXM3115U CLRF AARGB4 ; clear partial product CLRF AARGB5 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W


AN617

MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2 MOVF AARGB3,W MOVWF TEMPB3

UMUL3115L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $


;**********************************************************************************************;**********************************************************************************************


SMUL2424L macro

; Max Timing: 2+12+6*21+20+2+7*22+21+2+6*23+22+7 = 506 clks

; Min Timing: 2+7*6+5+1+7*6+5+2+6*6+5+5 = 145 clks

; PM: 24+20+2+21+2+22+7 = 98 DM: 13



MOVWF LOOPCOUNT




AN617

LOOPSM2424C RRF BARGB0, F BTFSC _C GOTO CLSM2424NA DECFSZ LOOPCOUNT, F GOTO LOOPSM2424C

CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 RETLW 0x00

ALOOPSM2424 RRF BARGB2, F BTFSS _C GOTO ALSM2424NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALSM2424NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F DECFSZ LOOPCOUNT, F GOTO ALOOPSM2424


BLOOPSM2424 RRF BARGB1, F BTFSS _C GOTO BLSM2424NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLSM2424NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO BLOOPSM2424



AN617

CLOOPSM2424 RRF BARGB0, F BTFSS _C GOTO CLSM2424NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

CLSM2424NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F DECFSZ LOOPCOUNT, F GOTO CLOOPSM2424

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

endm

UMUL2424L macro

; Max Timing: 2+14+6*20+19+2+7*21+20+2+7*22+21 = 501 clks

; Min Timing: 2+7*6+5+1+7*6+5+1+7*6+5+5 = 150 clks

; PM: 23+20+2+21+2+22 = 88 DM: 13



MOVWF LOOPCOUNT


MOVWF LOOPCOUNT

LOOPUM2424C


AN617

RRF BARGB0, F BTFSC _C GOTO CLUM2424NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM2424C


CLUM2424NAP BCF _C GOTO CLUM2424NA



ALOOPUM2424 RRF BARGB2, F BTFSS _C GOTO ALUM2424NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALUM2424NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F DECFSZ LOOPCOUNT, F GOTO ALOOPUM2424


BLOOPUM2424 RRF BARGB1, F BTFSS _C GOTO BLUM2424NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLUM2424NA RRF AARGB0, F


AN617

RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO BLOOPUM2424


CLOOPUM2424 RRF BARGB0, F BTFSS _C GOTO CLUM2424NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

CLUM2424NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F DECFSZ LOOPCOUNT, F GOTO CLOOPUM2424

endm

UMUL2323L macro

; Max Timing: 2+15+6*20+19+2+7*21+20+2+6*22+21+6 = 486 clks

; Min Timing: 2+7*6+5+1+7*6+5+2+6*6+5+5 = 145 clks

; PM: 24+20+2+21+2+22+6 = 97 DM: 13



MOVWF LOOPCOUNT



AN617




CLUM2323NAP BCF _C GOTO CLUM2323NA






BLOOPUM2323 RRF BARGB1, F BTFSS _C GOTO BLUM2323NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C


AN617

INCFSZ TEMPB0,W ADDWF AARGB0, F

BLUM2323NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO BLOOPUM2323


CLOOPUM2323 RRF BARGB0, F BTFSS _C GOTO CLUM2323NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

CLUM2323NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F DECFSZ LOOPCOUNT, F GOTO CLOOPUM2323


endm

SMUL2424 macro

; Max Timing: 8+7*17+8*18+7*19+7 = 411 clks


; PM: 51+4+7*17+8*18+7*19+7 = 466 DM: 12



AN617

variable i = i + 1

endw


variable i = i + 1

endw


variable i = i + 1

endw

CLRF AARGB0 ; if we get here, BARG = 0 CLRF AARGB1 CLRF AARGB2 RETURN

SM2424NA0 RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = 1

while i < 8

BTFSS BARGB2,i GOTO SM2424NA#v(i)SM2424A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM2424NA#v(i) RLF SIGN,W, F RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw

variable i = 8


AN617

while i < 16

BTFSS BARGB1,i-8 GOTO SM2424NA#v(i)SM2424A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM2424NA#v(i) RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 16

while i < 23

BTFSS BARGB0,i-16 GOTO SM2424NA#v(i)SM2424A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM2424NA#v(i) RLF TEMPB0,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

variable i = i + 1

endw

RLF TEMPB0,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

endm

UMUL2424 macro


AN617

; Max Timing: 8+8*17+8*18+8*19 = 440 clks


; PM: 54+4+8*17+8*18+8*19 = 490 DM: 12

variable i = 0


variable i = i + 1

endw


variable i = i + 1

endw


variable i = i + 1

endw


UM2424NA0 RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = 1

while i < 8

BTFSS BARGB2,i GOTO UM2424NA#v(i)UM2424A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C


AN617

INCFSZ TEMPB0,W ADDWF AARGB0, FUM2424NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB1,i-8 GOTO UM2424NA#v(i)UM2424A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM2424NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

variable i = 16

while i < 24

BTFSS BARGB0,i-16 GOTO UM2424NA#v(i)UM2424A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM2424NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

variable i = i + 1

endw

endm


AN617

UMUL2323 macro

; Max Timing: 8+7*17+8*18+7*19+7 = 411 clks


; PM: 51+4+7*17+8*18+7*19+7 = 466 DM: 12

variable i = 0



variable i = i + 1

endw

variable i = 8


variable i = i + 1

endw

variable i = 16


variable i = i + 1

endw



variable i = 1

while i < 8

BTFSS BARGB2,i GOTO UM2323NA#v(i)UM2323A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C


AN617

INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM2323NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw

variable i = 8

while i < 16


variable i = i + 1

endw

variable i = 16

while i < 23

BTFSS BARGB0,i-16 GOTO UM2323NA#v(i)UM2323A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM2323NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F RRF AARGB5, F

variable i = i + 1


AN617

endw









; PM: 27+98+1 = 126 DM: 13

FXM2424S CLRF AARGB3 ; clear partial product CLRF AARGB4 CLRF AARGB5 CLRF SIGN MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W BTFSC _Z RETLW 0x00 MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB COMF SIGN,F



COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F INCF AARGB2, F BTFSC _Z INCF AARGB1, F


AN617

BTFSC _Z INCF AARGB0, F


M2424SOK MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2

SMUL2424L

RETLW 0x00

M2424SX CLRF AARGB3 CLRF AARGB4 CLRF AARGB5 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F

RETLW 0x00






; Max Timing: 9+501+2 = 512 clks


; PM: 9+88+1 = 98 DM: 13

FXM2424U CLRF AARGB3 ; clear partial product CLRF AARGB4 CLRF AARGB5 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2

UMUL2424L

RETLW 0x00

;**********************************************************************************************


AN617

;********************************************************************************************** ; 23x23 Bit Unsigned Fixed Point Divide 23x23 -> 46







; PM: 9+97+1 = 107 DM: 13

FXM2323U CLRF AARGB3 ; clear partial product CLRF AARGB4 CLRF AARGB5 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2

UMUL2323L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $


;**********************************************************************************************;**********************************************************************************************


SMUL2416L macro

; Max Timing: 2+12+6*21+20+2+6*22+21+6 = 321 clks

; Min Timing: 2+7*6+5+2+6*6+5+5 = 97 clks

; PM: 19+20+2+21+6 = 68 DM: 12







AN617

CLRF AARGB2 RETLW 0x00

ALOOPSM2416 RRF BARGB1, F BTFSS _C GOTO ALSM2416NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALSM2416NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F DECFSZ LOOPCOUNT, F GOTO ALOOPSM2416


BLOOPSM2416 RRF BARGB0, F BTFSS _C GOTO BLSM2416NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLSM2416NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F DECFSZ LOOPCOUNT, F GOTO BLOOPSM2416

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

endm

UMUL2416L macro

; Max Timing: 2+14+6*20+19+2+7*21+20 = 324 clks


AN617

; Min Timing: 2+7*6+5+1+7*6+5+5 = 102 clks

; PM: 18+20+2+21 = 61 DM: 12



MOVWF LOOPCOUNT








BLOOPUM2416 RRF BARGB0, F


AN617

BTFSS _C GOTO BLUM2416NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F


endm

UMUL2315L macro

; Max Timing: 2+15+6*20+19+2+6*21+20+5 = 309 clks

; Min Timing: 2+7*6+5+1+6*6+5+5 = 96 clks

; PM: 19+20+2+21+5 = 67 DM: 12







ALUM2315NAP BCF _C


AN617

GOTO ALUM2315NA




BLOOPUM2315 RRF BARGB0, F BTFSS _C GOTO BLUM2315NA MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F



endm

SMUL2416 macro

; Max Timing: 8+7*17+7*18+6 = 259 clks


AN617


; PM: 30+4+7*17+7*18+6 = 285 DM: 11


variable i = i + 1

endw


variable i = i + 1

endw


SM2416NA0 RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = 1

while i < 8

BTFSS BARGB1,i GOTO SM2416NA#v(i)SM2416A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM2416NA#v(i) RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw

variable i = 8


AN617

while i < 15

BTFSS BARGB0,i-8 GOTO SM2416NA#v(i)SM2416A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM2416NA#v(i) RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

variable i = i + 1

endw

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F RRF AARGB4, F

endm

UMUL2416 macro

; Max Timing: 8+8*17+8*18 = 288 clks


; PM: 37+4+8*17+8*18 = 321 DM: 11

variable i = 0


variable i = i + 1

endw


variable i = i + 1


AN617

endw



variable i = 1

while i < 8

BTFSS BARGB1,i GOTO UM2416NA#v(i)UM2416A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM2416NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw

variable i = 8

while i < 16


variable i = i + 1

endw

endm


AN617

UMUL2315 macro

; Max Timing: 8+7*17+7*18+6 = 259 clks


; PM: 35+4+7*17+7*18+6 = 290 DM: 11

variable i = 0



variable i = i + 1

endw

variable i = 8


variable i = i + 1

endw



variable i = 1

while i < 8

BTFSS BARGB1,i GOTO UM2315NA#v(i)UM2315A#v(i) MOVF TEMPB2,W ADDWF AARGB2, F MOVF TEMPB1,W BTFSC _C INCFSZ TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM2315NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1


AN617

endw

variable i = 8

while i < 15


variable i = i + 1

endw









; PM: 23+68+1 = 92 DM: 12

FXM2416S CLRF AARGB3 ; clear partial product CLRF AARGB4 CLRF SIGN MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W BTFSC _Z RETLW 0x00


AN617

MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB COMF SIGN,F



COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F INCF AARGB2, F BTFSC _Z INCF AARGB1, F BTFSC _Z INCF AARGB0, F


M2416SOK MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2

SMUL2416L

RETLW 0x00

M2416SX CLRF AARGB3 CLRF AARGB4 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F RRF AARGB3,F

RETLW 0x00









AN617

; PM: 8+61+1 = 70 DM: 12

FXM2416U CLRF AARGB3 ; clear partial product CLRF AARGB4 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2

UMUL2416L

RETLW 0x00








; PM: 8+67+1 = 76 DM: 12

FXM2315U CLRF AARGB3 ; clear partial product CLRF AARGB4 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1 MOVF AARGB2,W MOVWF TEMPB2

UMUL2315L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $


;**********************************************************************************************;**********************************************************************************************


SMUL1616L macro

; Max Timing: 2+11+6*16+15+2+6*17+16+5 = 249 clks

; Min Timing: 2+7*6+5+2+6*6+5+4 = 96 clks

; PM: 55 DM: 9







AN617

RETLW 0x00

ALOOPSM1616 RRF BARGB1, F BTFSS _C GOTO ALSM1616NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALSM1616NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F DECFSZ LOOPCOUNT, F GOTO ALOOPSM1616


BLOOPSM1616 RRF BARGB0, F BTFSS _C GOTO BLSM1616NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLSM1616NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F DECFSZ LOOPCOUNT, F GOTO BLOOPSM1616

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

endm

UMUL1616L macro

; Max Timing: 2+13+6*15+14+2+7*16+15 = 248 clks

; Min Timing: 2+7*6+5+1+7*6+5+4 = 101 clks

; PM: 51 DM: 9


LOOPUM1616A RRF BARGB1, F BTFSC _C GOTO ALUM1616NAP DECFSZ LOOPCOUNT, F


AN617

GOTO LOOPUM1616A

MOVWF LOOPCOUNT





ALOOPUM1616 RRF BARGB1, F BTFSS _C GOTO ALUM1616NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALUM1616NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F DECFSZ LOOPCOUNT, F GOTO ALOOPUM1616


BLOOPUM1616 RRF BARGB0, F BTFSS _C GOTO BLUM1616NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLUM1616NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F DECFSZ LOOPCOUNT, F GOTO BLOOPUM1616

endm


AN617

UMUL1515L macro

; Max Timing: 2+13+6*15+14+2+6*16+15+4 = 236 clks

; Min Timing: 2+7*6+5+2+6*6+5+4 = 97 clks

; PM: 56 DM: 9








ALOOPUM1515 RRF BARGB1, F BTFSS _C GOTO ALUM1515NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

ALUM1515NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F DECFSZ LOOPCOUNT, F GOTO ALOOPUM1515


BLOOPUM1515 RRF BARGB0, F BTFSS _C GOTO BLUM1515NA


AN617

MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, F

BLUM1515NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F DECFSZ LOOPCOUNT, F GOTO BLOOPUM1515


endm

SMUL1616 macro

; Max Timing: 5+6+7*11+7*12+4 = 176 clks

; Min Timing: 5+24+21+5 = 55 clks

; PM: 5+3*8+3*7+6+7*11+7*12+4 = 221 DM: 8

variable i = 0

BTFSC SIGN,MSB COMF AARGB2, F MOVF AARGB2,W MOVWF AARGB3 RLF SIGN,W while i < 8 BTFSC BARGB1,i GOTO SM1616NA#v(i) BCF AARGB2,7-i

variable i = i + 1

endw

variable i = 8 while i < 15 BTFSC BARGB0,i-8 GOTO SM1616NA#v(i) BCF AARGB3,15-i

variable i =i + 1

endw

CLRF AARGB0 ; if we get here, BARG = 0 CLRF AARGB1 RETURN


AN617

SM1616NA0 RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = 1

while i < 8

BTFSS BARGB1,i GOTO SM1616NA#v(i)SM1616A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM1616NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = i + 1

endw

variable i = 8

while i < 15

BTFSS BARGB0,i-8 GOTO SM1616NA#v(i)SM1616A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM1616NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw


endm

UMUL1616 macro

; Max Timing: 1+6+7*11+8*12 = 180 clks

; Min Timing: 1+2*8+2*8+4 = 37 clks

; PM: 1+2*8+2*8+4+7*11+8*12 = 210 DM: 8


AN617

variable i = 0


variable i = i + 1

endw


variable i = i + 1

endw


UM1616NA0 RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = 1

while i < 8

BTFSS BARGB1,i GOTO UM1616NA#v(i)UM1616A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM1616NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = i + 1

endw

variable i = 8

while i < 16

BTFSS BARGB0,i-8 GOTO UM1616NA#v(i)UM1616A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM1616NA#v(i) RRF AARGB0, F RRF AARGB1, F


AN617

RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw

endm

UMUL1515 macro

; Max Timing: 7+7*11+7*12+4 = 172 clks

; Min Timing: 1+16+14+4 = 35 clks

; PM: 1+2*8+2*7+6+7*11+7*12+4 = 202 DM: 8

variable i = 0



variable i = i + 1

endw

variable i = 8


variable i = i + 1

endw



variable i = 1

while i < 8



AN617

variable i = i + 1

endw

variable i = 8

while i < 15

BTFSS BARGB0,i-8 GOTO UM1515NA#v(i)UM1515A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM1515NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F RRF AARGB3, F

variable i = i + 1

endw









; PM: 18+55+1 = 74 DM: 9

FXM1616S CLRF AARGB2 ; clear partial product CLRF AARGB3 CLRF SIGN MOVF AARGB0,W IORWF AARGB1,W BTFSC _Z RETLW 0x00 MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB


AN617

COMF SIGN,F



COMF AARGB1, F COMF AARGB0, F INCF AARGB1, F BTFSC _Z INCF AARGB0, F


M1616SOK MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1

SMUL1616L

RETLW 0x00

M1616SX CLRF AARGB2 CLRF AARGB3 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F

RETLW 0x00








; PM: 6+51+1 = 58 DM: 9

FXM1616U CLRF AARGB2 ; clear partial product CLRF AARGB3 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1


AN617

UMUL1616L

RETLW 0x00








; PM: 6+56+1 = 63 DM: 9

FXM1515U CLRF AARGB2 ; clear partial product CLRF AARGB3 MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1

UMUL1515L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $


;**********************************************************************************************;**********************************************************************************************


SMUL1608L macro

; Max Timing: 2+11+5*16+15+4 = 112 clks

; Min Timing: 2+6*6+5+4 = 47 clks

; PM: 29 DM: 7


LOOPSM1608A RRF BARGB0, F BTFSC _C GOTO LSM1608NA DECFSZ LOOPCOUNT, F GOTO LOOPSM1608A


LOOPSM1608 RRF BARGB0, F BTFSS _C GOTO LSM1608NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C


AN617

INCFSZ TEMPB0,W ADDWF AARGB0, F

LSM1608NA RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F DECFSZ LOOPCOUNT, F GOTO LOOPSM1608

RLF SIGN,W RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

endm

UMUL1608L macro

; Max Timing: 2+13+6*15+14 = 119 clks

; Min Timing: 2+7*6+5+4 = 54 clks

; PM: 26 DM: 7


LOOPUM1608A RRF BARGB0, F BTFSC _C GOTO LUM1608NAP DECFSZ LOOPCOUNT, F GOTO LOOPUM1608A


LUM1608NAP BCF _C GOTO LUM1608NA

LOOPUM1608 RRF BARGB0, F BTFSS _C GOTO LUM1608NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FLUM1608NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F DECFSZ LOOPCOUNT, F GOTO LOOPUM1608

endm

UMUL1507L macro

; Max Timing: 2+13+5*15+14+3 = 107 clks


AN617

; Min Timing: 2+6*6+5+4 = 47 clks

; PM: 29 DM: 7





LOOPUM1507 RRF BARGB0, F BTFSS _C GOTO LUM1507NA MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FLUM1507NA RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F DECFSZ LOOPCOUNT, F GOTO LOOPUM1507

RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

endm

SMUL1608 macro

; Max Timing: 3+6+6*11+3 = 78 clks


; PM: 3+3*7+7+6*11+3 = 100 DM: 6

variable i =0

BTFSC SIGN,MSB COMF AARGB2, F RLF SIGN,W while i < 7 BTFSC BARGB0,i GOTO SM1608NA#v(i) BCF AARGB2,7-i


AN617

variable i = i + 1

endw


SM1608NA0 RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = 1

while i < 7

BTFSS BARGB0,i GOTO SM1608NA#v(i)SM1608A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FSM1608NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = i + 1

endw


endm

UMUL1608 macro

; Max Timing: 1+6+7*11 = 84 clks

; Min Timing: 1+2*8+4 = 21 clks

; PM: 1+2*8+4+6*7 = 63 DM: 4

variable i = 0


variable i = i + 1

endw

CLRF AARGB0 ; if we get here, BARG = 0 CLRF AARGB1


AN617

RETURN


variable i = 1

while i < 8


variable i = i + 1

endw

endm

UMUL1507 macro

; Max Timing: 7+6*12+4 = 83 clks


; PM: 2*7+7+6*12+4 = 97 DM: 6

variable i = 0



variable i = i + 1

endw



variable i = 1

while i < 7

BTFSS BARGB0,i GOTO UM1507NA#v(i)UM1507A#v(i) MOVF TEMPB1,W ADDWF AARGB1, F


AN617

MOVF TEMPB0,W BTFSC _C INCFSZ TEMPB0,W ADDWF AARGB0, FUM1507NA#v(i) RRF AARGB0, F RRF AARGB1, F RRF AARGB2, F

variable i = i + 1

endw









; PM: 14+29+1 = 44 DM: 7

FXM1608S CLRF AARGB2 ; clear partial product CLRF SIGN MOVF AARGB0,W IORWF AARGB1,W BTFSC _Z RETLW 0x00 MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMPB0 BTFSC TEMPB0,MSB COMF SIGN,F


COMF BARGB0,F ; make multiplier BARG > 0 INCF BARGB0,F




AN617

M1608SOK MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1

SMUL1608

RETLW 0x00

M1608SX CLRF AARGB2 RLF SIGN,W RRF AARGB0,F RRF AARGB1,F RRF AARGB2,F

RETLW 0x00








; PM: 5+26+1 = 31 DM: 7

FXM1608U CLRF AARGB2 ; clear partial product MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1

UMUL1608L

RETLW 0x00









AN617

; PM: 5+29+1 = 35 DM: 7

FXM1507U CLRF AARGB2 ; clear partial product MOVF AARGB0,W MOVWF TEMPB0 MOVF AARGB1,W MOVWF TEMPB1

UMUL1507

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $


;**********************************************************************************************;**********************************************************************************************


SMUL0808L macro

; Max Timing: 3+10+5*9+8+3 = 69 clks

; Min Timing: 3+6*6+5+3 = 47 clks

; PM: 21 DM: 5


MOVF AARGB0,W

LOOPSM0808A RRF BARGB0, F BTFSC _C GOTO LSM0808NA DECFSZ LOOPCOUNT, F GOTO LOOPSM0808A


LOOPSM0808 RRF BARGB0, F BTFSC _C ADDWF AARGB0, FLSM0808NA RLF SIGN, F RRF AARGB0, F RRF AARGB1, F DECFSZ LOOPCOUNT, F


AN617

GOTO LOOPSM0808

RLF SIGN, F RRF AARGB0, F RRF AARGB1, F

endm

UMUL0808L macro

; Max Timing: 3+12+6*8+7 = 70 clks

; Min Timing: 3+7*6+5+3 = 53 clks

; PM: 19 DM: 4

MOVLW 0x08 MOVWF LOOPCOUNT MOVF AARGB0,W




LOOPUM0808 RRF BARGB0, F BTFSC _C ADDWF AARGB0, FLUM0808NA RRF AARGB0, F RRF AARGB1, F DECFSZ LOOPCOUNT, F GOTO LOOPUM0808

endm

UMUL0707L macro

; Max Timing: 3+12+5*8+7+2 = 64 clks

; Min Timing: 3+6*6+5+3 = 47 clks

; PM: 21 DM: 4

MOVLW 0x07 MOVWF LOOPCOUNT MOVF AARGB0,W



AN617



LOOPUM0707 RRF BARGB0, F BTFSC _C ADDWF AARGB0, FLUM0707NA RRF AARGB0, F RRF AARGB1, F DECFSZ LOOPCOUNT, F GOTO LOOPUM0707


endm

SMUL0808 macro

; Max Timing: 1+6+6*5+3 = 40 clks


; PM: 1+2*7+5+6*5+3 = 53 DM: 5

variable i = 0

MOVF AARGB0,W while i < 7 BTFSC BARGB0,i GOTO SM0808NA#v(i)

variable i = i + 1

endw

CLRF AARGB0 ; if we get here, BARG = 0 RETURN

SM0808NA0 RLF SIGN RRF AARGB0 RRF AARGB1

variable i = 1

while i < 7

BTFSC BARGB0,i ADDWF AARGB0SM0808NA#v(i) RLF SIGN RRF AARGB0 RRF AARGB1

variable i = i + 1

endw


AN617

RLF SIGN RRF AARGB0 RRF AARGB1

endm

UMUL0808 macro

; Max Timing: 2+5+7*4 = 35 clks


; PM: 2+2*8+4+7*4 = 50 DM: 3

variable i = 0

BCF _C ; clear carry for first right shift MOVF AARGB0,W while i < 8 BTFSC BARGB0,i GOTO UM0808NA#v(i)

variable i = i + 1

endw


UM0808NA0 RRF AARGB0, F RRF AARGB1, F

variable i = 1

while i < 8

BTFSC BARGB0,i ADDWF AARGB0, FUM0808NA#v(i) RRF AARGB0, F RRF AARGB1, F

variable i = i + 1

endw

endm

UMUL0707 macro

; Max Timing: 2+5+6*4+2 = 33 clks


; PM: 2+2*7+4+6*4+2 = 46 DM: 3

variable i = 0

BCF _C ; clear carry for first right shift MOVF AARGB0,W

while i < 7


AN617

BTFSC BARGB0,i GOTO UM0707NA#v(i)

variable i = i + 1

endw


UM0707NA0 RRF AARGB0, F RRF AARGB1, F

variable i = 1

while i < 7

BTFSC BARGB0,i ADDWF AARGB0, FUM0707NA#v(i) RRF AARGB0, F RRF AARGB1, F

variable i = i + 1

endw








; Min Timing: 12+47 = 59 clks; 6 clks A = 0

; PM: 17+21+1 = 39 DM: 5

FXM0808S CLRF AARGB1 ; clear partial product CLRF SIGN MOVF AARGB0,W BTFSC _Z RETLW 0x00 XORWF BARGB0,W MOVWF TEMPB3 BTFSC TEMPB3,MSB COMF SIGN, F

BTFSS BARGB0,MSB


AN617

GOTO M0808SOK COMF BARGB0, F ; make multiplier BARG > 0 INCF BARGB0, F COMF AARGB0, F INCF AARGB0, F


M0808SOK

SMUL0808L

RETLW 0x00

M0808SX CLRF AARGB1 RLF SIGN, W RRF AARGB0, F RRF AARGB1, F

RETLW 0x00








; PM: 1+19+1 = 21 DM: 4

FXM0808U CLRF AARGB1 ; clear partial product

UMUL0808L

RETLW 0x00









AN617

; PM: 1+21+1 = 23 DM: 4

FXM0707U CLRF AARGB1 ; clear partial product

UMUL0707L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

APPENDIX E: PIC16C5X/PIC16CXX DIVIDE ROUTINESTable of Contents for Appendix EE.1 32/32 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 123E.2 32/24 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 145E.3 32/16 PIC16C5X/PIC16CXX Fixed Point Divide Routines ........................................................................... 163E.4 24/24 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 178E.5 24/16 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 193E.6 16/16 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 205E.7 16/8 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ........................................................................... 216E.8 8/8 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ............................................................................. 228

E.1 32/32 PIC16C5X/PIC16CXXX Fixed Point Divide Routines; RCS Header $Id: fxd22.a16 2.4 1997/02/27 03:03:17 F.J.Testa Exp $

; $Revision: 2.4 $

; 32/32 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD3232S 929 32 bit/32 bit -> 32.32 signed fixed point divide;; FXD3232U 1031 32 bit/32 bit -> 32.32 unsigned fixed point divide;; FXD3131U 869 31 bit/31 bit -> 31.31 unsigned fixed point divide;;**********************************************************************************************;**********************************************************************************************

; 32/32 Bit Division Macros

SDIV3232L macro

; Max Timing: 17+6*27+26+26+6*27+26+26+6*27+26+26+6*27+26+16 = 863 clks

; Min Timing: 17+6*26+25+25+6*26+25+25+6*26+25+25+6*26+25+3 = 819 clks

; PM: 17+7*38+16 = 299 DM: 13

MOVF BARGB3,W SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W



AN617

BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB0, F

MOVLW 7 MOVWF LOOPCOUNT

LOOPS3232A RLF AARGB0,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB0,LSB GOTO SADD22LA

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22LA

SADD22LA ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK22LA RLF AARGB0, F

DECFSZ LOOPCOUNT, F GOTO LOOPS3232A

RLF AARGB1,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB0,LSB GOTO SADD22L8

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W


AN617

BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22L8

SADD22L8 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK22L8 RLF AARGB1, F


LOOPS3232B RLF AARGB1,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB1,LSB GOTO SADD22LB

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22LB

SADD22LB ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F


AN617

SOK22LB RLF AARGB1, F

DECFSZ LOOPCOUNT, F GOTO LOOPS3232B


SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22L16



LOOPS3232C RLF AARGB2,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB2,LSB GOTO SADD22LC

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F


AN617

MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22LC

SADD22LC ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK22LC RLF AARGB2, F

DECFSZ LOOPCOUNT, F GOTO LOOPS3232C


SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22L24


MOVLW 7


AN617

MOVWF LOOPCOUNT

LOOPS3232D RLF AARGB3,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB3,LSB GOTO SADD22LD

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK22LD

SADD22LD ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C

INCFSZ BARGB0,W ADDWF REMB0, F SOK22LD RLF AARGB3, F

DECFSZ LOOPCOUNT, F GOTO LOOPS3232D

BTFSC AARGB3,LSB GOTO SOK22L MOVF BARGB3,W ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FSOK22L

endm


AN617

UDIV3232L macro

; Max Timing: 24+6*32+31+31+6*32+31+31+6*32+31+31+6*32+31+16 = 1025 clks

; Min Timing: 24+6*31+30+30+6*31+30+30+6*31+30+30+6*31+30+3 = 981 clks

; PM: 359 DM: 13

CLRF TEMP

RLF AARGB0,W RLF REMB3, F MOVF BARGB3,W SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F

CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F RLF AARGB0, F


LOOPU3232A RLF AARGB0,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB3,W BTFSS AARGB0,LSB GOTO UADD22LA

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK22LA

UADD22LA ADDWF REMB3, F


AN617

MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK22LA RLF AARGB0, F

DECFSZ LOOPCOUNT, F GOTO LOOPU3232A

RLF AARGB1,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB3,W BTFSS AARGB0,LSB GOTO UADD22L8

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK22L8

UADD22L8 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C


AN617

MOVLW 1 ADDWF TEMP, F UOK22L8 RLF AARGB1, F


LOOPU3232B RLF AARGB1,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB3,W BTFSS AARGB1,LSB GOTO UADD22LB

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK22LB

UADD22LB ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK22LB RLF AARGB1, F

DECFSZ LOOPCOUNT, F GOTO LOOPU3232B

RLF AARGB2,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F


AN617

MOVF BARGB3,W BTFSS AARGB1,LSB GOTO UADD22L16


UADD22L16 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK22L16 RLF AARGB2, F


LOOPU3232C RLF AARGB2,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB3,W BTFSS AARGB2,LSB GOTO UADD22LC

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W


AN617

BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK22LC

UADD22LC ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK22LC RLF AARGB2, F

DECFSZ LOOPCOUNT, F GOTO LOOPU3232C

RLF AARGB3,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB3,W BTFSS AARGB2,LSB GOTO UADD22L24


UADD22L24 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F


AN617

MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK22L24 RLF AARGB3, F


LOOPU3232D RLF AARGB3,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB3,W BTFSS AARGB3,LSB GOTO UADD22LD

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK22LD

UADD22LD ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK22LD RLF AARGB3, F


AN617

DECFSZ LOOPCOUNT, F GOTO LOOPU3232D

BTFSC AARGB3,LSB GOTO UOK22L MOVF BARGB3,W ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK22L

endm

UDIV3131L macro

; Max Timing: 17+6*27+26+26+6*27+26+26+6*27+26+26+6*27+26+16 = 863 clks

; Min Timing: 17+6*26+25+25+6*26+25+25+6*26+25+25+6*26+25+3 = 819 clks

; PM: 17+7*38+16 = 299 DM: 13

MOVF BARGB3,W SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB0, F


LOOPU3131A RLF AARGB0,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB0,LSB GOTO UADD11LA

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F


AN617

MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11LA

UADD11LA ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK11LA RLF AARGB0, F


RLF AARGB1,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB0,LSB GOTO UADD11L8

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11L8

UADD11L8 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F


AN617

UOK11L8 RLF AARGB1, F


LOOPU3131B RLF AARGB1,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB1,LSB GOTO UADD11LB

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11LB

UADD11LB ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK11LB RLF AARGB1, F



SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W


AN617

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11L16

UADD11L16 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK11L16 RLF AARGB2, F


LOOPU3131C RLF AARGB2,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB2,LSB GOTO UADD11LC

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11LC

UADD11LC ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK11LC RLF AARGB2, F


AN617



SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11L24

UADD11L24 ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK11L24 RLF AARGB3, F


LOOPU3131D RLF AARGB3,W RLF REMB3, F RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB3,W BTFSS AARGB3,LSB GOTO UADD11LD

SUBWF REMB3, F MOVF BARGB2,W BTFSS _C INCFSZ BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C


AN617

INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK11LD

UADD11LD ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C

INCFSZ BARGB0,W ADDWF REMB0, F UOK11LD RLF AARGB3, F


BTFSC AARGB3,LSB GOTO UOK11L MOVF BARGB3,W ADDWF REMB3, F MOVF BARGB2,W BTFSC _C INCFSZ BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FUOK11L

endm

;**********************************************************************************************;********************************************************************************************** ; 32/32 Bit Signed Fixed Point Divide 32/32 -> 32.32

; Input: 32 bit fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3

; Use: CALL FXD3232S

; Output: 32 bit fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit fixed point remainder in REMB0, REMB1, REMB2, REMB3

; Result: AARG, REM <-- AARG / BARG

; Max Timing: 28+863+5 = 896 clks A > 0, B > 0; 38+863+28 = 929 clks A > 0, B < 0; 38+863+28 = 929 clks A < 0, B > 0; 48+863+5 = 916 clks A < 0, B < 0; 12 clks A = 0

; Min Timing: 28+819+5 = 852 clks A > 0, B > 0


AN617

; 38+819+28 = 885 clks A > 0, B < 0; 38+819+28 = 885 clks A < 0, B > 0; 48+819+5 = 872 clks A < 0, B < 0

; PM: 48+299+27+67 = 441 DM: 15

FXD3232S CLRF SIGN CLRF REMB0 ; clear partial remainder CLRF REMB1 CLRF REMB2 CLRF REMB3 MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00

MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMP BTFSC TEMP,MSB COMF SIGN,F

CLRF TEMPB3 ; clear exception flag

BTFSS BARGB0,MSB ; if MSB set, negate BARG GOTO CA3232S

COMF BARGB3, F COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB3, F BTFSC _Z INCF BARGB2, F BTFSC _Z INCF BARGB1, F BTFSC _Z INCF BARGB0, F

CA3232S BTFSS AARGB0,MSB ; if MSB set, negate AARG GOTO C3232SX


C3232SX MOVF AARGB0,W IORWF BARGB0,W MOVWF TEMP BTFSC TEMP,MSB GOTO C3232SX1

C3232S SDIV3232L

BTFSC TEMPB3,LSB ; test exception flag GOTO C3232SX4


AN617

C3232SOK BTFSS SIGN,MSB RETLW 0x00


COMF REMB3, F COMF REMB2, F COMF REMB1, F COMF REMB0, F INCF REMB3, F BTFSC _Z INCF REMB2, F BTFSC _Z INCF REMB1, F BTFSC _Z INCF REMB0, F

RETLW 0x00

C3232SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C3232SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C3232SX2 MOVF AARGB0,W MOVWF REMB0 ; quotient = 0, remainder = AARG MOVF AARGB1,W MOVWF REMB1 MOVF AARGB2,W MOVWF REMB2 MOVF AARGB3,W MOVWF REMB3 CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 GOTO C3232SOKC3232SX2 CLRF AARGB0 ; quotient = 1, remainder = 0 CLRF AARGB1 CLRF AARGB2 CLRF AARGB3 INCF AARGB3,F RETLW 0x00

C3232SX3 COMF AARGB0,F ; numerator = 0x7FFFFFFF + 1 COMF AARGB1,F COMF AARGB2,F COMF AARGB3,F INCF TEMPB3,F GOTO C3232S

C3232SX4 INCF REMB3,F ; increment remainder and test for BTFSC _Z ; overflow INCF REMB2,F BTFSC _Z INCF REMB1,F


AN617

BTFSC _Z INCF REMB0,F MOVF BARGB3,W SUBWF REMB3,W BTFSS _Z GOTO C3232SOK MOVF BARGB2,W SUBWF REMB2,W BTFSS _Z GOTO C3232SOK MOVF BARGB1,W SUBWF REMB1,W BTFSS _Z GOTO C3232SOK MOVF BARGB0,W SUBWF REMB0,W BTFSS _Z GOTO C3232SOK CLRF REMB0 ; if remainder overflow, clear CLRF REMB1 ; remainder, increment quotient and CLRF REMB2 CLRF REMB3 INCF AARGB3,F ; test for overflow exception BTFSC _Z INCF AARGB2,F BTFSC _Z INCF AARGB1,F BTFSC _Z INCF AARGB0,F BTFSS AARGB0,MSB GOTO C3232SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;********************************************************************************************** ; 32/32 Bit Unsigned Fixed Point Divide 32/32 -> 32.32

; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3

; Use: CALL FXD3232U

; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3


; Max Timing: 4+1025+2 = 1031 clks


; PM: 4+359+1 = 364 DM: 13

FXD3232U CLRF REMB0 CLRF REMB1 CLRF REMB2 CLRF REMB3

UDIV3232L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

; 31/31 Bit Unsigned Fixed Point Divide 31/31 -> 31.31

; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 31 bit unsigned fixed point divisor in BARGB0, BARGB1, BARBB2, BARGB3


; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 31 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3




; PM: 4+299+1 = 304 DM: 13

FXD3131U CLRF REMB0 CLRF REMB1 CLRF REMB2 CLRF REMB3

UDIV3131L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $

; 32/24 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD3224S 759 32 bit/24 bit -> 32.24 signed fixed point divide;; FXD3224U 867 32 bit/24 bit -> 32.24 unsigned fixed point divide;; FXD3123U 705 31 bit/23 bit -> 31.23 unsigned fixed point divide;

;**********************************************************************************************;**********************************************************************************************


SDIV3224L macro

; Max Timing: 13+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+12 = 700 clks

; Min Timing: 13+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 660 clks

; PM: 11+3*58+43 = 228 DM: 10

MOVF BARGB2,W SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F RLF AARGB0,F


LOOPS3224A RLF AARGB0,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO SADD24LA

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C


AN617

INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO SOK24LA

SADD24LA ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F SOK24LA RLF AARGB0,F

DECFSZ LOOPCOUNT,F GOTO LOOPS3224A

RLF AARGB1,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO SADD24L8

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO SOK24L8

SADD24L8 ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F SOK24L8 RLF AARGB1,F


LOOPS3224B RLF AARGB1,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO SADD24LB

SUBWF REMB2,F


AN617

MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO SOK24LB

SADD24LB ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F SOK24LB RLF AARGB1,F

DECFSZ LOOPCOUNT,F GOTO LOOPS3224B





LOOPS3224C RLF AARGB2,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB2,LSB GOTO SADD24LC


AN617

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO SOK24LC

SADD24LC ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F SOK24LC RLF AARGB2,F

DECFSZ LOOPCOUNT,F GOTO LOOPS3224C





LOOPS3224D RLF AARGB3,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W


AN617

BTFSS AARGB3,LSB GOTO SADD24LD

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO SOK24LD

SADD24LD ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F SOK24LD RLF AARGB3,F

DECFSZ LOOPCOUNT,F GOTO LOOPS3224D

BTFSC AARGB3,LSB GOTO SOK24L MOVF BARGB2,W ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,FSOK24L

endm

UDIV3224L macro

; Max Timing: 20+6*27+26+26+6*27+26+26+6*27+26+26+6*27+26+12 = 862 clks

; Min Timing: 20+6*26+25+25+6*26+25+25+6*26+25+25+6*26+25+3 = 822 clks

; PM: 18+3*75+40+12 = 295 DM: 11

CLRF TEMP

RLF AARGB0,W RLF REMB2,F MOVF BARGB2,W SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W


AN617

SUBWF REMB0,F

CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F RLF AARGB0,F


LOOPU3224A RLF AARGB0,W RLF REMB2,F RLF REMB1,F RLF REMB0,F RLF TEMP,F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD24LA

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24LA

UADD24LA ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C MOVLW 1 ADDWF TEMP,F UOK24LA RLF AARGB0,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3224A

RLF AARGB1,W RLF REMB2,F RLF REMB1,F RLF REMB0,F RLF TEMP,F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD24L8

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C


AN617

INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24L8

UADD24L8 ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C MOVLW 1 ADDWF TEMP,F UOK24L8 RLF AARGB1,F


LOOPU3224B RLF AARGB1,W RLF REMB2,F RLF REMB1,F RLF REMB0,F RLF TEMP,F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD24LB

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24LB

UADD24LB ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C


AN617

MOVLW 1 ADDWF TEMP,F UOK24LB RLF AARGB1,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3224B


SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24L16

UADD24L16 ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C MOVLW 1 ADDWF TEMP,F UOK24L16 RLF AARGB2,F


LOOPU3224C RLF AARGB2,W RLF REMB2,F RLF REMB1,F RLF REMB0,F RLF TEMP,F MOVF BARGB2,W BTFSS AARGB2,LSB GOTO UADD24LC

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W


AN617

BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24LC

UADD24LC ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C MOVLW 1 ADDWF TEMP,F UOK24LC RLF AARGB2,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3224C


SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24L24

UADD24L24 ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C MOVLW 1 ADDWF TEMP,F


AN617

UOK24L24 RLF AARGB3,F


LOOPU3224D RLF AARGB3,W RLF REMB2,F RLF REMB1,F RLF REMB0,F RLF TEMP,F MOVF BARGB2,W BTFSS AARGB3,LSB GOTO UADD24LD

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F CLRW BTFSS _C MOVLW 1 SUBWF TEMP,F GOTO UOK24LD

UADD24LD ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F CLRW BTFSC _C MOVLW 1 ADDWF TEMP,F UOK24LD RLF AARGB3,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3224D

BTFSC AARGB3,LSB GOTO UOK24L MOVF BARGB2,W ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F

UOK24L

endm

UDIV3123L macro


AN617

; Max Timing: 13+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+12 = 700 clks

; Min Timing: 13+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 660 clks

; PM: 11+3*58+43 = 228 DM: 10

MOVF BARGB2,W SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F RLF AARGB0,F


LOOPU3123A RLF AARGB0,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD13LA

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13LA

UADD13LA ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F UOK13LA RLF AARGB0,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3123A

RLF AARGB1,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD13L8

SUBWF REMB2,F MOVF BARGB1,W


AN617

BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13L8

UADD13L8 ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F UOK13L8 RLF AARGB1,F


LOOPU3123B RLF AARGB1,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD13LB

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13LB

UADD13LB ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F UOK13LB RLF AARGB1,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3123B

RLF AARGB2,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD13L16


AN617

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13L16



LOOPU3123C RLF AARGB2,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB2,LSB GOTO UADD13LC

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13LC

UADD13LC ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F UOK13LC RLF AARGB2,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3123C

RLF AARGB3,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB2,LSB


AN617

GOTO UADD13L24

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13L24



LOOPU3123D RLF AARGB3,W RLF REMB2,F RLF REMB1,F RLF REMB0,F MOVF BARGB2,W BTFSS AARGB3,LSB GOTO UADD13LD

SUBWF REMB2,F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1,F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0,F GOTO UOK13LD

UADD13LD ADDWF REMB2,F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,F UOK13LD RLF AARGB3,F

DECFSZ LOOPCOUNT,F GOTO LOOPU3123D

BTFSC AARGB3,LSB GOTO UOK13L MOVF BARGB2,W ADDWF REMB2,F


AN617

MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1,F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0,FUOK13L

endm


; Input: 32 bit fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 24 bit fixed point divisor in BARGB0, BARGB1, BARGB2


; Output: 32 bit fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 24 bit fixed point remainder in REMB0, REMB1, REMB2



; Min Timing: 27+660+5 = 692 clks A > 0, B > 0; 34+660+25 = 719 clks A > 0, B < 0; 34+660+25 = 749 clks A < 0, B > 0; 44+660+5 = 709 clks A < 0, B < 0

; PM: 44+228+24+62 = 358 DM: 13

FXD3224S CLRF SIGN CLRF REMB0 ; clear partial remainder CLRF REMB1 CLRF REMB2 MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00




COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB2, F


AN617

BTFSC _Z INCF BARGB1, F BTFSC _Z INCF BARGB0, F




C3224S SDIV3224L




COMF REMB2, F COMF REMB1, F COMF REMB0, F INCF REMB2, F BTFSC _Z INCF REMB1, F BTFSC _Z INCF REMB0, F

RETLW 0x00

C3224SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C3224SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C3224SX2 MOVF AARGB1,W MOVWF REMB0 MOVF AARGB2,W MOVWF REMB1 MOVF AARGB3,W


AN617

MOVWF REMB2 BCF REMB0,MSB RLF AARGB1,F RLF AARGB0,F MOVF AARGB0,W MOVWF AARGB3 CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 GOTO C3224SOKC3224SX2 CLRF AARGB3 ; quotient = 1, remainder = 0 INCF AARGB3,F CLRF AARGB2 CLRF AARGB1 CLRF AARGB0 RETLW 0x00


C3224SX4 INCF REMB2,F ; increment remainder and test for BTFSC _Z INCF REMB1,F BTFSC _Z INCF REMB0,F MOVF BARGB2,W ; overflow SUBWF REMB2,W BTFSS _Z GOTO C3224SOK MOVF BARGB1,W SUBWF REMB1,W BTFSS _Z GOTO C3224SOK MOVF BARGB0,W SUBWF REMB0,W BTFSS _Z GOTO C3224SOK CLRF REMB0 ; if remainder overflow, clear CLRF REMB1 CLRF REMB2 INCF AARGB3,F ; remainder, increment quotient and BTFSC _Z INCF AARGB2,F BTFSC _Z INCF AARGB1,F ; test for overflow exception BTFSC _Z INCF AARGB0,F BTFSS AARGB0,MSB GOTO C3224SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2


AN617


; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2




; PM: 3+295+1 = 299 DM: 11

FXD3224U CLRF REMB0 CLRF REMB1 CLRF REMB2

UDIV3224L

RETLW 0x00


; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARBB2


; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2




; PM: 3+228+1 = 232 DM: 10


UDIV3123L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************

END


AN617

E.3 32/16 PIC16C5X/PIC16CXX Fixed Point Divide Routines; RCS Header $Id: fxd26.a16 2.3 1996/10/16 14:23:57 F.J.Testa Exp $

; $Revision: 2.3 $

; 32/16 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD3216S 595 32 bit/16 bit -> 32.16 signed fixed point divide;; FXD3216U 703 32 bit/16 bit -> 32.16 unsigned fixed point divide;; FXD3115U 541 31 bit/15 bit -> 31.15 unsigned fixed point divide;;**********************************************************************************************;**********************************************************************************************


SDIV3216L macro

; Max Timing: 9+6*17+16+16+6*17+16+16+6*17+16+16+6*17+16+8 = 537 clks

; Min Timing: 9+6*16+15+15+6*16+15+15+6*16+15+15+6*16+15+3 = 501 clks

; PM: 157 DM: 9

MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB0, F


LOOPS3216A RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO SADD26LA

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK26LA

SADD26LA ADDWF REMB1, F MOVF BARGB0,W


AN617

BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK26LA RLF AARGB0, F


RLF AARGB1,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO SADD26L8

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK26L8

SADD26L8 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK26L8 RLF AARGB1, F


LOOPS3216B RLF AARGB1,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB1,LSB GOTO SADD26LB

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK26LB

SADD26LB ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK26LB RLF AARGB1, F




AN617




LOOPS3216C RLF AARGB2,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO SADD26LC

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK26LC

SADD26LC ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK26LC RLF AARGB2, F





MOVLW 7


AN617

MOVWF LOOPCOUNT

LOOPS3216D RLF AARGB3,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB3,LSB GOTO SADD26LD

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK26LD

SADD26LD ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK26LD RLF AARGB3, F

DECFSZ LOOPCOUNT, F GOTO LOOPS3216D

BTFSC AARGB3,LSB GOTO SOK26L MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FSOK26L

endm

UDIV3216L macro

; Max Timing: 16+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+8 = 699 clks

; Min Timing: 16+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 663 clks

; PM: 240 DM: 9

CLRF TEMP

RLF AARGB0,W RLF REMB1, F MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F RLF AARGB0, F



AN617

LOOPU3216A RLF AARGB0,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO UADD26LA

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK26LA

UADD26LA ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK26LA RLF AARGB0, F


RLF AARGB1,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO UADD26L8

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK26L8

UADD26L8 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK26L8 RLF AARGB1, F

MOVLW 7


AN617

MOVWF LOOPCOUNT

LOOPU3216B RLF AARGB1,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB1,LSB GOTO UADD26LB

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK26LB

UADD26LB ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK26LB RLF AARGB1, F






AN617


LOOPU3216C RLF AARGB2,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO UADD26LC

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK26LC

UADD26LC ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK26LC RLF AARGB2, F




UADD26L24 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F


AN617



LOOPU3216D RLF AARGB3,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB3,LSB GOTO UADD26LD

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK26LD

UADD26LD ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK26LD RLF AARGB3, F


BTFSC AARGB3,LSB GOTO UOK26L MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FUOK26L

endm

UDIV3115L macro

; Max Timing: 9+6*17+16+16+6*17+16+16+6*17+16+16+6*17+16+8 = 537 clks

; Min Timing: 9+6*16+15+15+6*16+15+15+6*16+15+15+6*16+15+3 = 501 clks

; PM: 157 DM: 9

MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F


AN617

RLF AARGB0, F


LOOPU3115A RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO UADD15LA

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK15LA

UADD15LA ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK15LA RLF AARGB0, F


RLF AARGB1,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO UADD15L8


UADD15L8 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK15L8 RLF AARGB1, F


LOOPU3115B RLF AARGB1,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB1,LSB GOTO UADD15LB

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W


AN617

SUBWF REMB0, F GOTO UOK15LB

UADD15LB ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK15LB RLF AARGB1, F






LOOPU3115C RLF AARGB2,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO UADD15LC

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK15LC

UADD15LC ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK15LC RLF AARGB2, F


RLF AARGB3,W RLF REMB1, F


AN617

RLF REMB0, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO UADD15L24




LOOPU3115D RLF AARGB3,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB3,LSB GOTO UADD15LD

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK15LD

UADD15LD ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK15LD RLF AARGB3, F



endm ;**********************************************************************************************;********************************************************************************************** ; 32/16 Bit Signed Fixed Point Divide 32/16 -> 32.16

; Input: 32 bit fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3


AN617

; 16 bit fixed point divisor in BARGB0, BARGB1


; Output: 32 bit fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 16 bit fixed point remainder in REMB0, REMB1




; PM: 40+157+21+55 = 273 DM: 12

FXD3216S CLRF SIGN CLRF REMB0 ; clear partial remainder CLRF REMB1 MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00







C3216SX MOVF AARGB0,W IORWF BARGB0,W


AN617

MOVWF TEMP BTFSC TEMP,MSB GOTO C3216SX1

C3216S SDIV3216L




COMF REMB1, F COMF REMB0, F INCF REMB1, F BTFSC _Z INCF REMB0, F

RETLW 0x00

C3216SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C3216SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C3216SX2 MOVF AARGB2,W MOVWF REMB0 MOVF AARGB3,W MOVWF REMB1 BCF REMB0,MSB RLF AARGB2,F RLF AARGB1,F RLF AARGB0,F MOVF AARGB0,W MOVWF AARGB2 MOVF AARGB1,W MOVWF AARGB3 CLRF AARGB0 CLRF AARGB1 GOTO C3216SOKC3216SX2 CLRF AARGB3 ; quotient = 1, remainder = 0 INCF AARGB3,F CLRF AARGB2 CLRF AARGB1 CLRF AARGB0 RETLW 0x00


C3216SX4 INCF REMB1,F ; increment remainder and test for


AN617

BTFSC _Z INCF REMB0,F MOVF BARGB1,W ; overflow SUBWF REMB1,W BTFSS _Z GOTO C3216SOK MOVF BARGB0,W ; overflow SUBWF REMB0,W BTFSS _Z GOTO C3216SOK CLRF REMB0 ; if remainder overflow, clear CLRF REMB1 INCF AARGB3,F ; remainder, increment quotient and BTFSC _Z INCF AARGB2,F BTFSC _Z INCF AARGB1,F ; test for overflow exception BTFSC _Z INCF AARGB0,F BTFSS AARGB0,MSB GOTO C3216SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 16 bit unsigned fixed point divisor in BARGB0, BARGB1


; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 16 bit unsigned fixed point remainder in REMB0, REMB1




; PM: 2+240+1 = 243 DM: 9

FXD3216U CLRF REMB0 CLRF REMB1

UDIV3216L

RETLW 0x00


; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 15 bit unsigned fixed point divisor in BARGB0, BARGB1


; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 15 bit unsigned fixed point remainder in REMB0, REMB1



AN617



; PM: 2+157+1 = 160 DM: 9


UDIV3115L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $

; 24/24 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD2424S 581 24 bit/24 bit -> 24.24 signed fixed point divide;; FXD2424U 676 24 bit/24 bit -> 24.24 unsigned fixed point divide;; FXD2323U 531 23 bit/23 bit -> 23.23 unsigned fixed point divide;**********************************************************************************************;**********************************************************************************************


SDIV2424L macro

; Max Timing: 13+6*22+21+21+6*22+21+21+6*22+21+12 = 526 clks

; Min Timing: 13+6*21+20+20+6*21+20+20+6*21+20+3 = 494 clks

; PM: 11+3*51+31+12 = 207 DM: 12

MOVF BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB0, F


LOOPS2424A RLF AARGB0,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO SADD44LA



AN617


SADD44LA ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK44LA RLF AARGB0, F


RLF AARGB1,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO SADD44L8

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK44L8

SADD44L8 ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK44L8 RLF AARGB1, F


LOOPS2424B RLF AARGB1,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO SADD44LB

SUBWF REMB2, F MOVF BARGB1,W


AN617

BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK44LB

SADD44LB ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK44LB RLF AARGB1, F


RLF AARGB2,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO SADD44L16

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK44L16

SADD44L16 ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK44L16 RLF AARGB2, F


LOOPS2424C RLF AARGB2,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB2,LSB GOTO SADD44LC


AN617

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK44LC

SADD44LC ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK44LC RLF AARGB2, F


BTFSC AARGB2,LSB GOTO SOK44L MOVF BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FSOK44L

endm

UDIV2424L macro

; Max Timing: 20+6*28+27+27+6*28+27+27+6*28+27+12 = 671 clks

; Min Timing: 20+6*27+26+26+6*27+26+26+6*27+26+3 = 639 clks

; PM: 18+2*76+40+12 = 222 DM: 13

CLRF TEMP

RLF AARGB0,W RLF REMB2, F MOVF BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F

CLRW


AN617

BTFSS _C MOVLW 1 SUBWF TEMP, F RLF AARGB0, F


LOOPU2424A RLF AARGB0,W RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD44LA

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK44LA

UADD44LA ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK44LA RLF AARGB0, F


RLF AARGB1,W RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD44L8

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W


AN617

BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK44L8

UADD44L8 ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK44L8 RLF AARGB1, F


LOOPU2424B RLF AARGB1,W RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD44LB

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK44LB

UADD44LB ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F


AN617

UOK44LB RLF AARGB1, F


RLF AARGB2,W RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD44L16

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK44L16

UADD44L16 ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK44L16 RLF AARGB2, F


LOOPU2424C RLF AARGB2,W RLF REMB2, F RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB2,W BTFSS AARGB2,LSB GOTO UADD44LC

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F


AN617

CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK44LC

UADD44LC ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK44LC RLF AARGB2, F


BTFSC AARGB2,LSB GOTO UOK44L MOVF BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK44L

endm

UDIV2323L macro

; Max Timing: 13+6*22+21+21+6*22+21+21+6*22+21+12 = 526 clks

; Min Timing: 13+6*21+20+20+6*21+20+20+6*21+20+3 = 494 clks

; PM: 11+3*51+31+12 = 207 DM: 12

MOVF BARGB2,W SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB0, F


LOOPU2323A RLF AARGB0,W


AN617

RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD33LA

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK33LA

UADD33LA ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK33LA RLF AARGB0, F


RLF AARGB1,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB0,LSB GOTO UADD33L8

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK33L8

UADD33L8 ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK33L8 RLF AARGB1, F



AN617

LOOPU2323B RLF AARGB1,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD33LB

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK33LB

UADD33LB ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK33LB RLF AARGB1, F


RLF AARGB2,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB1,LSB GOTO UADD33L16

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK33L16

UADD33L16 ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK33L16 RLF AARGB2, F


AN617


LOOPU2323C RLF AARGB2,W RLF REMB2, F RLF REMB1, F RLF REMB0, F MOVF BARGB2,W BTFSS AARGB2,LSB GOTO UADD33LC

SUBWF REMB2, F MOVF BARGB1,W BTFSS _C INCFSZ BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK33LC

UADD33LC ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK33LC RLF AARGB2, F


BTFSC AARGB2,LSB GOTO UOK33L MOVF BARGB2,W ADDWF REMB2, F MOVF BARGB1,W BTFSC _C INCFSZ BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FUOK33L

endm


; Input: 24 bit fixed point dividend in AARGB0, AARGB1,AARGB2; 24 bit fixed point divisor in BARGB0, BARGB1, BARGB2


; Output: 24 bit fixed point quotient in AARGB0, AARGB1,AARGB2; 24 bit fixed point remainder in REMB0, REMB1, REMB2


AN617




; PM: 40+207+21+53 = 321 DM: 14

FXD2424S CLRF SIGN CLRF REMB0 ; clear partial remainder CLRF REMB1 CLRF REMB2 MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W BTFSC _Z RETLW 0x00








C2424S SDIV2424L


AN617




COMF REMB2, F COMF REMB1, F COMF REMB0, F INCF REMB2, F BTFSC _Z INCF REMB1, F BTFSC _Z INCF REMB0, F

RETLW 0x00

C2424SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C2424SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C2424SX2 MOVF AARGB0,W MOVWF REMB0 ; quotient = 0, remainder = AARG MOVF AARGB1,W MOVWF REMB1 MOVF AARGB2,W MOVWF REMB2 CLRF AARGB0 CLRF AARGB1 CLRF AARGB2 GOTO C2424SOKC2424SX2 CLRF AARGB0 ; quotient = 1, remainder = 0 CLRF AARGB1 CLRF AARGB2 INCF AARGB2,F RETLW 0x00

C2424SX3 COMF AARGB0,F ; numerator = 0x7FFFFF + 1 COMF AARGB1,F COMF AARGB2,F INCF TEMPB3,F GOTO C2424S

C2424SX4 INCF REMB2,F ; increment remainder and test for BTFSC _Z ; overflow INCF REMB1,F BTFSC _Z INCF REMB0,F MOVF BARGB2,W SUBWF REMB2,W BTFSS _Z GOTO C2424SOK MOVF BARGB1,W SUBWF REMB1,W BTFSS _Z GOTO C2424SOK MOVF BARGB0,W


AN617

SUBWF REMB0,W BTFSS _Z GOTO C2424SOK CLRF REMB0 ; if remainder overflow, clear CLRF REMB1 ; remainder, increment quotient and CLRF REMB2 INCF AARGB2,F ; test for overflow exception BTFSC _Z INCF AARGB1,F BTFSC _Z INCF AARGB0,F BTFSS AARGB0,MSB GOTO C2424SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2


; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2; 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2




; PM: 3+222+1 = 226 DM: 13


UDIV2424L

RETLW 0x00


; Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARBB2


; Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2




; PM: 3+207+1 = 211 DM: 12


AN617


UDIV2323L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************

END


AN617


; $Revision: 2.3 $

; 24/16 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD2416S 454 24 bit/16 bit -> 24.16 signed fixed point divide;; FXD2416U 529 24 bit/16 bit -> 24.16 unsigned fixed point divide;; FXD2315U 407 23 bit/15 bit -> 23.15 unsigned fixed point divide

;**********************************************************************************************;**********************************************************************************************


SDIV2416L macro

; Max Timing: 9+6*17+16+16+6*17+16+16+6*17+16+8 = 403 clks

; Min Timing: 9+6*16+15+15+6*16+15+15+6*16+15+3 = 375 clks

; PM: 7+2*40+22+8 = 117 DM: 7



LOOPS2416A RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO SADD46LA


SADD46LA ADDWF REMB1, F MOVF BARGB0,W


AN617

BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK46LA RLF AARGB0, F






LOOPS2416B RLF AARGB1,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB1,LSB GOTO SADD46LB

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK46LB

SADD46LB ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK46LB RLF AARGB1, F




AN617




LOOPS2416C RLF AARGB2,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO SADD46LC

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK46LC

SADD46LC ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F SOK46LC RLF AARGB2, F



endm

UDIV2416L macro

; Max Timing: 16+6*22+21+21+6*22+21+21+6*22+21+8 = 525 clks

; Min Timing: 16+6*21+20+20+6*21+20+20+6*21+20+3 = 497 clks

; PM: 14+31+27+31+27+31+8 = 169 DM: 8

CLRF TEMP

RLF AARGB0,W


AN617

RLF REMB1, F MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F

CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F RLF AARGB0, F


LOOPU2416A RLF AARGB0,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO UADD46LA

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK46LA

UADD46LA ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK46LA RLF AARGB0, F



SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C


AN617

MOVLW 1 SUBWF TEMP, F GOTO UOK46L8



LOOPU2416B RLF AARGB1,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB1,LSB GOTO UADD46LB

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK46LB

UADD46LB ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK46LB RLF AARGB1, F



SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F


AN617

CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK46L16



LOOPU2416C RLF AARGB2,W RLF REMB1, F RLF REMB0, F RLF TEMP, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO UADD46LC

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F CLRW BTFSS _C MOVLW 1 SUBWF TEMP, F GOTO UOK46LC

UADD46LC ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F CLRW BTFSC _C MOVLW 1 ADDWF TEMP, F UOK46LC RLF AARGB2, F


BTFSC AARGB2,LSB GOTO UOK46L MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK46L


AN617

endm

UDIV2315L macro

; Max Timing: 9+6*17+16+16+6*17+16+16+6*17+16+8 = 403 clks

; Min Timing: 9+6*16+15+15+6*16+15+15+6*16+15+3 = 375 clks

; PM: 7+2*40+22+8 = 117 DM: 7



LOOPU2315A RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB0,LSB GOTO UADD35LA

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK35LA

UADD35LA ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK35LA RLF AARGB0, F




UADD35L8 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F


AN617



LOOPU2315B RLF AARGB1,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB1,LSB GOTO UADD35LB

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK35LB

UADD35LB ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK35LB RLF AARGB1, F






LOOPU2315C RLF AARGB2,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W BTFSS AARGB2,LSB GOTO UADD35LC



AN617

SUBWF REMB0, F GOTO UOK35LC

UADD35LC ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F UOK35LC RLF AARGB2, F



endm


; Input: 24 bit fixed point dividend in AARGB0, AARGB1,AARGB2; 16 bit fixed point divisor in BARGB0, BARGB1


; Output: 24 bit fixed point quotient in AARGB0, AARGB1,AARGB2; 16 bit fixed point remainder in REMB0, REMB1




; PM: 36+117+18+48 = 219 DM: 10

FXD2416S CLRF SIGN CLRF REMB0 ; clear partial remainder CLRF REMB1 MOVF AARGB0,W IORWF AARGB1,W IORWF AARGB2,W BTFSC _Z RETLW 0x00

MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMP


AN617

BTFSC TEMP,MSB COMF SIGN,F







C2416S SDIV2416L





RETLW 0x00

C2416SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C2416SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C2416SX2 MOVF AARGB1,W MOVWF REMB0 MOVF AARGB2,W MOVWF REMB1


AN617

BCF REMB0,MSB RLF AARGB1,F RLF AARGB0,F MOVF AARGB0,W MOVWF AARGB2 CLRF AARGB0 CLRF AARGB1 GOTO C2416SOKC2416SX2 CLRF AARGB2 ; quotient = 1, remainder = 0 INCF AARGB2,F CLRF AARGB1 CLRF AARGB0 RETLW 0x00


C2416SX4 INCF REMB1,F ; increment remainder and test for BTFSC _Z INCF REMB0,F MOVF BARGB1,W ; overflow SUBWF REMB1,W BTFSS _Z GOTO C2416SOK MOVF BARGB0,W ; overflow SUBWF REMB0,W BTFSS _Z GOTO C2416SOK CLRF REMB0 ; if remainder overflow, clear CLRF REMB1 INCF AARGB2,F ; remainder, increment quotient and BTFSC _Z INCF AARGB1,F ; test for overflow exception BTFSC _Z INCF AARGB0,F BTFSS AARGB0,MSB GOTO C2416SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2; 16 bit unsigned fixed point divisor in BARGB0, BARGB1


; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2; 16 bit unsigned fixed point remainder in REMB0, REMB1




; PM: 2+169+1 = 172 DM: 8

FXD2416U CLRF REMB0


AN617

CLRF REMB1

UDIV2416L

RETLW 0x00


; Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2; 15 bit unsigned fixed point divisor in BARGB0, BARGB1


; Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2; 15 bit unsigned fixed point remainder in REMB0, REMB1




; PM: 2+117+1 = 120 DM: 7


UDIV2315L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************

END


AN617


; $Revision: 2.4 $

; 16/16 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD1616S 334 16 bit/16 bit -> 16.16 signed fixed point divide;; FXD1616U 373 16 bit/16 bit -> 16.16 unsigned fixed point divide;; FXD1515U 294 15 bit/15 bit -> 15.15 unsigned fixed point divide;; The above timings are based on the looped macros. If space permits,; approximately 65-69 clocks can be saved by using the unrolled macros.;

;**********************************************************************************************;**********************************************************************************************


SDIV1616L macro

; Max Timing: 13+14*18+17+8 = 290 clks

; Min Timing: 13+14*16+15+3 = 255 clks

; PM: 42 DM: 7

RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB1, F RLF AARGB0, F

MOVLW D’15’ MOVWF LOOPCOUNT

LOOPS1616 RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W

BTFSS AARGB1,LSB GOTO SADD66L


AN617

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK66LL

SADD66L ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

SOK66LL RLF AARGB1, F RLF AARGB0, F

DECFSZ LOOPCOUNT, F GOTO LOOPS1616


endm

UDIV1616L macro

; restore = 23 clks, nonrestore = 17 clks

; Max Timing: 2+15*23+22 = 369 clks

; Min Timing: 2+15*17+16 = 273 clks

; PM: 24 DM: 7


LOOPU1616 RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F

BTFSC _C GOTO UOK66LL MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

BCF _C

UOK66LL RLF AARGB1, F


AN617

RLF AARGB0, F

DECFSZ LOOPCOUNT, F GOTO LOOPU1616

endm

UDIV1515L macro

; Max Timing: 13+14*18+17+8 = 290 clks

; Min Timing: 13+14*17+16+3 = 270 clks

; PM: 42 DM: 7

RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F RLF AARGB1, F RLF AARGB0, F


LOOPU1515 RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W

BTFSS AARGB1,LSB GOTO UADD55L

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK55LL

UADD55L ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK55LL RLF AARGB1, F RLF AARGB0, F




AN617

endm

SDIV1616 macro

; Max Timing: 7+10+6*14+14+7*14+8 = 221 clks

; Min Timing: 7+10+6*13+13+7*13+3 = 202 clks

; PM: 7+10+6*18+18+7*18+8 = 277 DM: 6

variable i


RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F RLF AARGB0, F

variable i = 2

while i < 8

RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W

BTFSS AARGB0,LSB GOTO SADD66#v(i)

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK66#v(i)

SADD66#v(i) ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

SOK66#v(i) RLF AARGB0, F

variable i = i + 1

endw

RLF AARGB1,W RLF REMB1, F RLF REMB0, F


AN617

MOVF BARGB1,W

BTFSS AARGB0,LSB GOTO SADD668

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK668

SADD668 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

SOK668 RLF AARGB1, F

variable i = 9

while i < 16



SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO SOK66#v(i)

SADD66#v(i) ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

SOK66#v(i) RLF AARGB1, F

variable i = i + 1

endw

BTFSC AARGB1,LSB GOTO SOK66 MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FSOK66

endm

UDIV1616 macro



AN617

; Max Timing: 16*20 = 320 clks

; Min Timing: 16*14 = 224 clks

; PM: 16*20 = 320 DM: 6

variable i

variable i = 0

while i < 16

RLF AARGB0,W RLF REMB1, F RLF REMB0, F MOVF BARGB1,W SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F

BTFSC _C GOTO UOK66#v(i) MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

BCF _C

UOK66#v(i) RLF AARGB1, F RLF AARGB0, F

variable i = i + 1

endw

endm

UDIV1515 macro

; Max Timing: 7+10+6*14+14+7*14+8 = 221 clks

; Min Timing: 7+10+6*13+13+7*13+3 = 202 clks

; PM: 7+10+6*18+18+7*18+8 = 277 DM: 6

variable i




AN617

ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F RLF AARGB0

variable i = 2

while i < 8


BTFSS AARGB0,LSB GOTO UADD55#v(i)

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK55#v(i)

UADD55#v(i) ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK55#v(i) RLF AARGB0, F

variable i = i + 1

endw


BTFSS AARGB0,LSB GOTO UADD558

SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK558

UADD558 ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK558 RLF AARGB1, F

variable i = 9

while i < 16

RLF AARGB1,W


AN617

RLF REMB1, F RLF REMB0, F MOVF BARGB1,W


SUBWF REMB1, F MOVF BARGB0,W BTFSS _C INCFSZ BARGB0,W SUBWF REMB0, F GOTO UOK55#v(i)

UADD55#v(i) ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, F

UOK55#v(i) RLF AARGB1, F

variable i = i + 1

endw

BTFSC AARGB1,LSB GOTO UOK55 MOVF BARGB1,W ADDWF REMB1, F MOVF BARGB0,W BTFSC _C INCFSZ BARGB0,W ADDWF REMB0, FUOK55

endm


; Input: 16 bit fixed point dividend in AARGB0, AARGB1; 16 bit fixed point divisor in BARGB0, BARGB1


; Output: 16 bit fixed point quotient in AARGB0, AARGB1; 16 bit fixed point remainder in REMB0, REMB1




; PM: 32+42+15+39 = 128 DM: 10


AN617

FXD1616S CLRF SIGN CLRF REMB0 ; clear partial remainder CLRF REMB1 MOVF AARGB0,W IORWF AARGB1,W BTFSC _Z RETLW 0x00








C1616S SDIV1616L





RETLW 0x00

C1616SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C1616SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C1616SX2


AN617

MOVF AARGB0,W MOVWF REMB0 ; quotient = 0, remainder = AARG MOVF AARGB1,W MOVWF REMB1 CLRF AARGB0 CLRF AARGB1 GOTO C1616SOKC1616SX2 CLRF AARGB0 ; quotient = 1, remainder = 0 CLRF AARGB1 INCF AARGB1,F RETLW 0x00

C1616SX3 COMF AARGB0,F ; numerator = 0x7FFF + 1 COMF AARGB1,F INCF TEMPB3,F GOTO C1616S

C1616SX4 INCF REMB1,F ; increment remainder and test for BTFSC _Z ; overflow INCF REMB0,F MOVF BARGB1,W SUBWF REMB1,W BTFSS _Z GOTO C1616SOK MOVF BARGB0,W SUBWF REMB0,W BTFSS _Z GOTO C1616SOK CLRF REMB0 ; if remainder overflow, clear CLRF REMB1 ; remainder, increment quotient and INCF AARGB1,F ; test for overflow exception BTFSC _Z INCF AARGB0,F BTFSS AARGB0,MSB GOTO C1616SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1; 16 bit unsigned fixed point divisor in BARGB0, BARGB1


; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1; 16 bit unsigned fixed point remainder in REMB0, REMB1




; PM: 2+24+1 = 27 DM: 7


UDIV1616L

RETLW 0x00


AN617


; Input: 15 bit unsigned fixed point dividend in AARGB0, AARGB1; 15 bit unsigned fixed point divisor in BARGB0, BARGB1


; Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1; 15 bit unsigned fixed point remainder in REMB0, REMB1




; PM: 2+42+1 = 45 DM: 7


UDIV1515L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617


; $Revision: 2.3 $

; 16/8 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD1608S 203 16 bit/8 bit -> 16.08 signed fixed point divide;; FXD1608U 294 16 bit/8 bit -> 16.08 unsigned fixed point divide;; FXD1607U 174 16 bit/7 bit -> 16.07 unsigned fixed point divide;; FXD1507U 166 15 bit/7 bit -> 15.07 unsigned fixed point divide;; The above timings are based on the looped macros. If space permits,; approximately 41-50 clocks can be saved by using the unrolled macros.;

;**********************************************************************************************;**********************************************************************************************


SDIV1608L macro

; Max Timing: 3+5+2+5*11+10+10+6*11+10+2 = 163 clks

; Min Timing: 3+5+2+5*11+10+10+6*11+10+2 = 163 clks

; PM: 42 DM: 5

MOVF BARGB0,W SUBWF REMB0, F RLF AARGB0, F

RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W ADDWF REMB0, F RLF AARGB0, F


LOOPS1608A RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W

BTFSC AARGB0,LSB SUBWF REMB0, F BTFSS AARGB0,LSB


AN617

ADDWF REMB0, F RLF AARGB0, F


RLF AARGB1,W RLF REMB0, F MOVF BARGB0,W

BTFSC AARGB0,LSB SUBWF REMB0, F BTFSS AARGB0,LSB ADDWF REMB0, F RLF AARGB1, F


LOOPS1608B RLF AARGB1,W RLF REMB0, F MOVF BARGB0,W



BTFSS AARGB1,LSB ADDWF REMB0, F

endm

UDIV1608L macro

; Max Timing: 2+7*12+11+3+7*24+23 = 291 clks

; Min Timing: 2+7*11+10+3+7*17+16 = 227 clks

; PM: 39 DM: 7


LOOPU1608A RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W SUBWF REMB0, F

BTFSC _C GOTO UOK68A ADDWF REMB0, F BCF _CUOK68A RLF AARGB0, F


CLRF TEMP



AN617

LOOPU1608B RLF AARGB1,W RLF REMB0, F RLF TEMP, F MOVF BARGB0,W SUBWF REMB0, F CLRF AARGB5 CLRW BTFSS _C INCFSZ AARGB5,W SUBWF TEMP, F

BTFSC _C GOTO UOK68B MOVF BARGB0,W ADDWF REMB0, F CLRF AARGB5 CLRW BTFSC _C INCFSZ AARGB5,W ADDWF TEMP, F

BCF _CUOK68B RLF AARGB1, F


endm

UDIV1607L macro

; Max Timing: 7+6*11+10+10+6*11+10+2 = 171 clks

; Min Timing: 7+6*11+10+10+6*11+10+2 = 171 clks

; PM: 39 DM: 5

RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W SUBWF REMB0, F RLF AARGB0, F


LOOPU1607A RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W




BTFSC AARGB0,LSB SUBWF REMB0, F


AN617

BTFSS AARGB0,LSB ADDWF REMB0, F RLF AARGB1, F


LOOPU1607B RLF AARGB1,W RLF REMB0, F MOVF BARGB0,W




endm

UDIV1507L macro

; Max Timing: 3+5+2+5*11+10+10+6*11+10+2 = 163 clks

; Min Timing: 3+5+2+5*11+10+10+6*11+10+2 = 163 clks

; PM: 42 DM: 5




LOOPU1507A RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W






AN617



LOOPU1507B RLF AARGB1,W RLF REMB0, F MOVF BARGB0,W




endm

SDIV1608 macro

; Max Timing: 3+5+14*8+2 = 122 clks

; Min Timing: 3+5+14*8+2 = 122 clks

; PM: 122 DM: 4



variable i = 2

while i < 8



variable i = i + 1

endw


BTFSC AARGB0,LSB SUBWF REMB0, F


AN617

BTFSS AARGB0,LSB ADDWF REMB0, F RLF AARGB1, F

variable i = 9

while i < 16



variable i = i + 1

endw


endm

UDIV1608 macro

; restore = 9/21 clks, nonrestore = 8/14 clks

; Max Timing: 8*9+1+8*21 = 241 clks

; Min Timing: 8*8+1+8*14 = 177 clks

; PM: 241 DM: 6

variable i = 0

while i < 8

RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W SUBWF REMB0, F

BTFSC _C GOTO UOK68#v(i) ADDWF REMB0, F BCF _CUOK68#v(i) RLF AARGB0, F

variable i = i + 1

endw

CLRF TEMP

variable i = 8

while i < 16

RLF AARGB1,W RLF REMB0, F RLF TEMP, F MOVF BARGB0,W


AN617

SUBWF REMB0, F CLRF AARGB5 CLRW BTFSS _C INCFSZ AARGB5,W SUBWF TEMP, F

BTFSC _C GOTO UOK68#v(i) MOVF BARGB0,W ADDWF REMB0, F CLRF AARGB5 CLRW BTFSC _C INCFSZ AARGB5,W ADDWF TEMP, F

BCF _CUOK68#v(i) RLF AARGB1, F

variable i = i + 1

endw

endm

UDIV1607 macro

; Max Timing: 5+15*8+2 = 127 clks

; Min Timing: 5+15*8+2 = 127 clks

; PM: 127 DM: 4


variable i = 1

while i < 8



variable i = i + 1

endw


BTFSC AARGB0,LSB SUBWF REMB0, F BTFSS AARGB0,LSB ADDWF REMB0, F


AN617

RLF AARGB1, F

variable i = 9

while i < 16



variable i = i + 1

endw


endm

UDIV1507 macro

; Max Timing: 3+5+14*8+2 = 122 clks

; Min Timing: 3+5+14*8+2 = 122 clks

; PM: 122 DM: 4



variable i = 2

while i < 8



variable i = i + 1

endw


BTFSC AARGB0,LSB


AN617

SUBWF REMB0, F BTFSS AARGB0,LSB ADDWF REMB0, F RLF AARGB1, F

variable i = 9

while i < 16



variable i = i + 1

endw



; Input: 16 bit signed fixed point dividend in AARGB0, AARGB1; 8 bit signed fixed point divisor in BARGB0


; Output: 16 bit signed fixed point quotient in AARGB0, AARGB1; 8 bit signed fixed point remainder in REMB0




; PM: 28+42+12+34 = 116 DM: 8

FXD1608S CLRF SIGN CLRF REMB0 ; clear partial remainder MOVF AARGB0,W IORWF AARGB1,W BTFSC _Z RETLW 0x00

MOVF AARGB0,W XORWF BARGB0,W MOVWF TEMP


AN617

BTFSC TEMP,MSB COMF SIGN,F



COMF BARGB0, F INCF BARGB0, F




C1608S SDIV1608

BTFSC TEMPB3,LSB ; test exception flag GOTO C1608SX4C1608SOK BTFSS SIGN,MSB RETLW 0x00


COMF REMB0, F INCF REMB0, F

RETLW 0x00

C1608SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C1608SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C1608SX2 MOVF AARGB1,W MOVWF REMB0 BCF REMB0,MSB RLF AARGB1,F RLF AARGB0,F MOVF AARGB0,W MOVWF AARGB1 CLRF AARGB0 GOTO C1608SOKC1608SX2 CLRF AARGB1 ; quotient = 1, remainder = 0 INCF AARGB1,F CLRF AARGB0 RETLW 0x00



AN617

C1608SX4 INCF REMB0,F ; increment remainder and test for MOVF BARGB0,W ; overflow SUBWF REMB0,W BTFSS _Z GOTO C1608SOK CLRF REMB0 ; if remainder overflow, clear INCF AARGB1,F ; remainder, increment quotient and BTFSC _Z INCF AARGB0,F ; test for overflow exception BTFSS AARGB0,MSB GOTO C1608SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1; 8 bit unsigned fixed point divisor in BARGB0


; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1; 8 bit unsigned fixed point remainder in REMB0




; PM: 1+39+1 = 41 DM: 7

FXD1608U CLRF REMB0

UDIV1608L

RETLW 0x00








; PM: 1+39+1 = 41 DM: 5

FXD1607U CLRF REMB0

UDIV1607L


AN617

RETLW 0x00








; PM: 1+42+1 = 44 DM: 5

FXD1507U CLRF REMB0

UDIV1507L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************

END


AN617


; $Revision: 2.3 $

; 8/8 PIC16 FIXED POINT DIVIDE ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG in AARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD0808S 109 8 bit/8 bit -> 08.08 signed fixed point divide;; FXD0808U 100 8 bit/8 bit -> 08.08 unsigned fixed point divide;; FXD0807U 88 8 bit/7 bit -> 08.07 unsigned fixed point divide;; FXD0707U 80 7 bit/7 bit -> 07.07 unsigned fixed point divide;; The above timings are based on the looped macros. If space permits,; approximately 19-25 clocks can be saved by using the unrolled macros.;

;**********************************************************************************************;**********************************************************************************************


SDIV0808L macro

; Max Timing: 3+5+2+5*11+10+2 = 77 clks

; Min Timing: 3+5+2+5*11+10+2 = 77 clks

; PM: 22 DM: 4




LOOPS0808A RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W



AN617




endm

UDIV0808L macro

; Max Timing: 2+7*12+11 = 97 clks

; Min Timing: 2+7*11+10 = 89 clks

; PM: 13 DM: 4


LOOPU0808A RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W SUBWF REMB0, F

BTFSC _C GOTO UOK88A ADDWF REMB0, F BCF _CUOK88A RLF AARGB0, F


endm

UDIV0807L macro

; Max Timing: 7+6*11+10+2 = 85 clks

; Min Timing: 7+6*11+10+2 = 85 clks

; PM: 19 DM: 4



LOOPU0807 RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W


DECFSZ LOOPCOUNT, F


AN617

GOTO LOOPU0807


endm

UDIV0707L macro

; Max Timing: 3+5+2+5*11+10+2 = 77 clks

; Min Timing: 3+5+2+5*11+10+2 = 77 clks

; PM: 22 DM: 4




LOOPU0707 RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W




endm

SDIV0808 macro

; Max Timing: 3+5+6*8+2 = 58 clks

; Min Timing: 3+5+6*8+2 = 58 clks

; PM: 58 DM: 3

variable i




AN617

i = 2

while i < 8



i= i + 1

endw


endm

UDIV0808 macro


; Max Timing: 8*9 = 72 clks

; Min Timing: 8*8 = 64 clks

; PM: 72 DM: 3

variable i

i = 0

while i < 8

RLF AARGB0,W RLF REMB0, F MOVF BARGB0,W SUBWF REMB0, F

BTFSC _C GOTO UOK88#v(i) ADDWF REMB0, F BCF _CUOK88#v(i) RLF AARGB0, F

i= i + 1

endw

endm

UDIV0807 macro

; Max Timing: 5+7*8+2 = 63 clks

; Min Timing: 5+7*8+2 = 63 clks

; PM: 63 DM: 3

variable i


AN617


i = 1

while i < 8



i= i + 1

endw


endm

UDIV0707 macro

; Max Timing: 3+5+6*8+2 = 58 clks

; Min Timing: 3+5+6*8+2 = 58 clks

; PM: 58 DM: 3

variable i



i = 2

while i < 8



i= i + 1

endw


AN617



; Input: 8 bit signed fixed point dividend in AARGB0; 8 bit signed fixed point divisor in BARGB0


; Output: 8 bit signed fixed point quotient in AARGB0; 8 bit signed fixed point remainder in REMB0




; PM: 23+22+9+25 = 79 DM: 7

FXD0808S CLRF SIGN CLRF REMB0 ; clear partial remainder MOVF AARGB0,W BTFSC _Z RETLW 0x00

XORWF BARGB0,W MOVWF TEMP BTFSC TEMP,MSB COMF SIGN,F





COMF AARGB0, F INCF AARGB0, F


C0808S SDIV0808L


AN617





RETLW 0x00

C0808SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C0808SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C0808SX2 MOVF AARGB0,W ; quotient = 0, remainder = AARG MOVWF REMB0 CLRF AARGB0 GOTO C0808SOKC0808SX2 CLRF AARGB0 ; quotient = 1, remainder = 0 INCF AARGB0,F RETLW 0x00

C0808SX3 COMF AARGB0,F ; numerator = 0x7F + 1 INCF TEMPB3,F GOTO C0808S

C0808SX4 INCF REMB0,F ; increment remainder and test for MOVF BARGB0,W ; overflow SUBWF REMB0,W BTFSS _Z GOTO C0808SOK CLRF REMB0 ; if remainder overflow, clear INCF AARGB0,F ; remainder, increment quotient and BTFSS AARGB0,MSB ; test for overflow exception GOTO C0808SOK BSF FPFLAGS,NAN RETLW 0xFF


; Input: 8 bit unsigned fixed point dividend in AARGB0; 8 bit unsigned fixed point divisor in BARGB0


; Output: 8 bit unsigned fixed point quotient in AARGB0; 8 bit unsigned fixed point remainder in REMB0




; PM: 1+13+1 = 15 DM: 4


AN617

FXD0808U CLRF REMB0

UDIV0808L

RETLW 0x00








; PM: 1+19+1 = 21 DM: 4

FXD0807U CLRF REMB0

UDIV0807L

RETLW 0x00








; PM: 1+22+1 = 44 DM: 4

FXD0707U CLRF REMB0

UDIV0707L

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

NOTES:


AN617

APPENDIX F: PIC17CXXX MULTIPLY ROUTINES; RCS Header $Id: fxm.a17 2.2 1996/06/11 21:42:11 F.J.Testa Exp $

; $Revision: 2.2 $

; PIC17 FIXED POINT MULTIPLY ROUTINES;; Input: fixed point arguments in AARG and BARG;; Output: product AARG*BARG in AARG;; All timings are worst case cycle counts;; Routine Clocks Function;;; FXM0808S 11 08x08 -> 16 bit signed fixed point multiply;; FXM0808U 6 08x08 -> 16 bit unsigned fixed point multiply;; FXM1608S 21 16x08 -> 24 bit signed fixed point multiply;; FXM1608U 12 16x08 -> 24 bit unsigned fixed point multiply;; FXM1616S 39 16x16 -> 32 bit signed fixed point multiply;; FXM1616U 26 16x16 -> 32 bit unsigned fixed point multiply;; FXM2416S 56 24x16 -> 40 bit signed fixed point multiply;; FXM2416U 40 24x16 -> 40 bit unsigned fixed point multiply;; FXM2424S 81 24x24 -> 48 bit signed fixed point multiply;; FXM2424U 65 24x24 -> 48 bit unsigned fixed point multiply;; FXM3216S 73 32x16 -> 48 bit signed fixed point multiply;; FXM3216U 54 32x16 -> 48 bit unsigned fixed point multiply;; FXM3224S 108 32x24 -> 56 bit signed fixed point multiply;; FXM3224U 90 32x24 -> 56 bit unsigned fixed point multiply;; FXM3232S 145 32x32 -> 64 bit signed fixed point multiply;; FXM3232U 125 32x32 -> 64 bit unsigned fixed point multiply;;**********************************************************************************************;**********************************************************************************************; ; 8x8 Bit Signed Fixed Point Multiply 08 x 08 -> 16;; Input: 8 bit signed fixed point multiplicand in AARGB0; 8 bit signed fixed point multiplier in BARGB0;; Use: CALL FXM0808S;; Output: 16 bit signed fixed point product in AARGB0, AARGB1;; Result: AARG <-- AARG * BARG;



AN617

; Max Timing: 11 clks;; Min Timing: 11 clks;; PM: 10 DM: 3;FXM0808S MOVFP AARGB0,WREG MULWF BARGB0 BTFSC BARGB0,MSB SUBWF PRODH,F MOVFP BARGB0,WREG BTFSC AARGB0,MSB SUBWF PRODH,F MOVPF PRODH,AARGB0 MOVPF PRODL,AARGB1 RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 8x8 Bit Unsigned Fixed Point Multiply 08 x 08 -> 16;; Input: 8 bit unsigned fixed point multiplicand in AARGB0; 8 bit unsigned fixed point multiplier in BARGB0;; Use: CALL FXM0808U;; Output: 16 bit unsigned fixed point product in AARGB0, AARGB1;; Result: AARG <-- AARG * BARG;; Max Timing: 6 clks;; Min Timing: 6 clks;; PM: 5 DM: 3;FXM0808U MOVFP BARGB0,WREG MULWF AARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,AARGB1 RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 16x8 Bit Signed Fixed Point Multiply 16 x 08 -> 24;; Input: 16 bit signed fixed point multiplicand in AARGB0; 8 bit signed fixed point multiplier in BARGB0;; Use: CALL FXM1608S;; Output: 24 bit signed fixed point product in AARGB0, AARGB1;; Result: AARG <-- AARG * BARG;; Max Timing: 21 clks;; Min Timing: 18 clks;; PM: 20 DM: 4;FXM1608S MOVFP BARGB0,WREG MULWF AARGB1 MOVPF AARGB1,TEMP


AN617

MOVPF PRODH,AARGB1 MOVPF PRODL,AARGB2 MULWF AARGB0 BTFSC AARGB0,MSB SUBWF PRODH,F BTFSS BARGB0,MSB GOTO SIGN1608OK MOVFP TEMP,WREG SUBWF AARGB1,F MOVFP AARGB0,WREG SUBWFB PRODH,F

SIGN1608OK CLRF AARGB0,F MOVFP PRODL,WREG ADDWF AARGB1,F MOVFP PRODH,WREG ADDWFC AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 16x8 Bit Unsigned Fixed Point Multiply 16 x 08 -> 24;; Input: 16 bit unsigned fixed point multiplicand in AARGB0; 8 bit unsigned fixed point multiplier in BARGB0;; Use: CALL FXM1608U;; Output: 24 bit unsigned fixed point product in AARGB0, AARGB1, AARGB2;; Result: AARG <-- AARG * BARG;; Max Timing: 12 clks;; Min Timing: 12 clks;; PM: 11 DM: 4;FXM1608U MOVFP BARGB0,WREG MULWF AARGB1 MOVPF PRODH,AARGB1 MOVPF PRODL,AARGB2 MULWF AARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,WREG ADDWF AARGB1,F CLRF WREG,F ADDWFC AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 16x16 Bit Signed Fixed Point Multiply 16 x 16 -> 32;; Input: 16 bit signed fixed point multiplicand in AARGB0, AARGB1; 16 bit signed fixed point multiplier in BARGB0, BARGB1;; Use: CALL FXM1616S;; Output: 32 bit signed fixed point product in AARGB0, AARGB1,; AARGB2, AARGB3;


AN617

; Result: AARG <-- AARG * BARG;; Max Timing: 39 clks;; Min Timing: 31 clks;; PM: 38 DM: 8;FXM1616S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1

MOVFP AARGB1,WREG MULWF BARGB1 MOVPF PRODH,AARGB2 MOVPF PRODL,AARGB3 MOVFP AARGB0,WREG MULWF BARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,AARGB1

MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F CLRF WREG,F ADDWFC AARGB0,F

MOVFP TEMPB1,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F CLRF WREG,F ADDWFC AARGB0,F

BTFSS BARGB0,MSB GOTO TSIGN1616A MOVFP TEMPB1,WREG SUBWF AARGB1,F MOVFP TEMPB0,WREG SUBWFB AARGB0,F

TSIGN1616A BTFSS TEMPB0,MSB RETLW 0x00 MOVFP BARGB1,WREG SUBWF AARGB1,F MOVFP BARGB0,WREG SUBWFB AARGB0,F RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 16x16 Bit Unsigned Fixed Point Multiply 16 x 16 -> 32;; Input: 16 bit unsigned fixed point multiplicand in AARGB0, AARGB1; 16 bit unsigned fixed point multiplier in BARGB0, BARGB1;; Use: CALL FXM1616U;; Output: 32 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3


AN617

;; Result: AARG <-- AARG * BARG;; Max Timing: 26 clks;; Min Timing: 26 clks;; PM: 25 DM: 7;;FXM1616U MOVPF AARGB1,TEMPB1



MOVFP TEMPB1,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F CLRF WREG,F ADDWFC AARGB0,F RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 24x16 Bit Signed Fixed Point Multiply 24 x 16 -> 40;; Input: 24 bit signed fixed point multiplicand in AARGB0, AARGB1, AARGB2; 16 bit signed fixed point multiplier in BARGB0, BARGB1;; Use: CALL FXM2416S;; Output: 40 bit signed fixed point product in AARGB0, AARGB1,; AARGB2, AARGB3, AARGB4;; Result: AARG <-- AARG * BARG;; Max Timing: 56 clks;; Min Timing: 46 clks;; PM: 55 DM: 10;FXM2416S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2


AN617



MOVFP TEMPB2,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F CLRF WREG,F ADDWFC AARGB1,F MOVFP AARGB0,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F MOVFP AARGB0,WREG MULWF BARGB0 CLRF AARGB0,W ADDWFC AARGB0,F MOVPF PRODL,WREG ADDWF AARGB1,F MOVPF PRODH,WREG ADDWFC AARGB0,F

BTFSS BARGB0,MSB GOTO TSIGN2416A MOVFP TEMPB2,WREG SUBWF AARGB2,F MOVFP TEMPB1,WREG SUBWFB AARGB1,F MOVFP TEMPB0,WREG SUBWFB AARGB0,F

TSIGN2416A BTFSS TEMPB0,MSB RETLW 0x00 MOVFP BARGB1,WREG SUBWF AARGB1,F MOVFP BARGB0,WREG SUBWFB AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 24x16 Bit Unsigned Fixed Point Multiply 24 x 16 -> 40;; Input: 24 bit unsigned fixed point multiplicand in AARGB0, AARGB1, AARGB2


AN617

; 16 bit unsigned fixed point multiplier in BARGB0, BARGB1;; Use: CALL FXM2416U;; Output: 40 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4;; Result: AARG <-- AARG * BARG;; Max Timing: 40 clks;; Min Timing: 40 clks;; PM: 39 DM: 8;;FXM2416U MOVPF AARGB2,TEMPB2



MOVFP TEMPB2,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F CLRF WREG,F ADDWFC AARGB1,F MOVFP AARGB0,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F MOVFP AARGB0,WREG MULWF BARGB0 CLRF AARGB0,W ADDWFC AARGB0,F MOVPF PRODL,WREG ADDWF AARGB1,F MOVPF PRODH,WREG ADDWFC AARGB0,F RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 24x24 Bit Signed Fixed Point Multiply 24 x 24 -> 48


AN617

;; Input: 24 bit signed fixed point multiplicand in AARGB0, AARGB1, AARGB2; 24 bit signed fixed point multiplier in BARGB0, BARGB1, BARGB2;; Use: CALL FXM2424S;; Output: 48 bit signed fixed point product in AARGB0, AARGB1,; AARGB2, AARGB3, AARGB4, AARGB5;; Result: AARG <-- AARG * BARG;; Max Timing: 81 clks;; Min Timing: 69 clks;; PM: 80 DM: 12;FXM2424S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2




MOVFP TEMPB2,WREG MULWF BARGB0 MOVPF PRODL,WREG


AN617

ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F CLRF AARGB0,W ADDWFC AARGB1,F ADDWFC AARGB0,F


MOVFP TEMPB0,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB1,F MOVPF PRODH,WREG ADDWFC AARGB0,F

BTFSS BARGB0,MSB GOTO TSIGN2424A MOVFP TEMPB2,WREG SUBWF AARGB2,F MOVFP TEMPB1,WREG SUBWFB AARGB1,F MOVFP TEMPB0,WREG SUBWFB AARGB0,F

TSIGN2424A BTFSS TEMPB0,MSB RETLW 0x00 MOVFP BARGB2,WREG SUBWF AARGB2,F MOVFP BARGB1,WREG SUBWFB AARGB1,F MOVFP BARGB0,WREG SUBWFB AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 24x24 Bit Unsigned Fixed Point Multiply 24 x 24 -> 48;; Input: 24 bit unsigned fixed point multiplicand in AARGB0, AARGB1, AARGB2; 24 bit unsigned fixed point multiplier in BARGB0, BARGB1, BARGB2;; Use: CALL FXM2424U;; Output: 48 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5;; Result: AARG <-- AARG * BARG;; Max Timing: 65 clks;; Min Timing: 65 clks;; PM: 64 DM: 12;;FXM2424U MOVPF AARGB0,TEMPB0


AN617

MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2




MOVFP TEMPB2,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F CLRF AARGB0,W ADDWFC AARGB1,F ADDWFC AARGB0,F


MOVFP TEMPB0,WREG MULWF BARGB0


AN617

MOVPF PRODL,WREG ADDWF AARGB1,F MOVPF PRODH,WREG ADDWFC AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32x16 Bit Signed Fixed Point Multiply 32 x 16 -> 48;; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3; 16 bit signed fixed point multiplier in BARGB0, BARGB1;; Use: CALL FXM3216S;; Output: 48 bit signed fixed point product in AARGB0, AARGB1,; AARGB2, AARGB3, AARGB4, AARGB5;; Result: AARG <-- AARG * BARG;; Max Timing: 73 clks;; Min Timing: 61 clks;; PM: 72 DM: 12;FXM3216S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3



MOVFP TEMPB3,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F CLRF WREG,F ADDWFC AARGB2,F MOVFP AARGB1,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG


AN617

ADDWFC AARGB2,F MOVFP AARGB1,WREG MULWF BARGB0 CLRF AARGB1,W ADDWFC AARGB1,F MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F

MOVFP AARGB0,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB2,F MOVPF PRODH,WREG ADDWFC AARGB1,F MOVFP AARGB0,WREG MULWF BARGB0 CLRF AARGB0,W ADDWFC AARGB0,F MOVPF PRODL,WREG ADDWF AARGB1,F MOVPF PRODH,WREG ADDWFC AARGB0,F

BTFSS BARGB0,MSB GOTO TSIGN3216A MOVFP TEMPB3,WREG SUBWF AARGB3,F MOVFP TEMPB2,WREG SUBWFB AARGB2,F MOVFP TEMPB1,WREG SUBWFB AARGB1,F MOVFP TEMPB0,WREG SUBWFB AARGB0,F

TSIGN3216A BTFSS TEMPB0,MSB RETLW 0x00 MOVFP BARGB1,WREG SUBWF AARGB1,F MOVFP BARGB0,WREG SUBWFB AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32x16 Bit Unsigned Fixed Point Multiply 32 x 16 -> 48;; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3; 16 bit unsigned fixed point multiplier in BARGB0, BARGB1;; Use: CALL FXM3216U;; Output: 48 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5;; Result: AARG <-- AARG * BARG;; Max Timing: 54 clks;; Min Timing: 54 clks;; PM: 53 DM: 9


AN617

;;FXM3216U MOVPF AARGB3,TEMPB3





RETLW 0x00

;**********************************************************************************************;**********************************************************************************************;


AN617

; 32x24 Bit Signed Fixed Point Multiply 32 x 24 -> 56;; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3; 24 bit signed fixed point multiplier in BARGB0, BARGB1, BARGB2;; Use: CALL FXM3224S;; Output: 56 bit signed fixed point product in AARGB0, AARGB1,; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6;; Result: AARG <-- AARG * BARG;; Max Timing: 108 clks;; Min Timing: 94 clks;; PM: 107 DM: 15;FXM3224S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3

MOVFP AARGB3,WREG MULWF BARGB2 MOVPF PRODH,AARGB5 MOVPF PRODL,SIGN MOVFP AARGB2,WREG MULWF BARGB1 MOVPF PRODH,AARGB3 MOVPF PRODL,AARGB4


MOVF TEMPB3,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB5,F MOVPF PRODH,WREG ADDWFC AARGB4,F CLRF WREG,F ADDWFC AARGB3,F MOVFP AARGB1,WREG MULWF BARGB2 MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F MOVFP AARGB1,WREG MULWF BARGB1 CLRF AARGB2,W ADDWFC AARGB2,F MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F


AN617





MOVFP TEMPB0,WREG MULWF BARGB2 MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F CLRF WREG,F ADDWFC AARGB1,F ADDWFC AARGB0,F

MOVFP SIGN,AARGB6


TSIGN3224A BTFSS TEMPB0,MSB RETLW 0x00


AN617

MOVFP BARGB2,WREG SUBWF AARGB2,F MOVFP BARGB1,WREG SUBWFB AARGB1,F MOVFP BARGB0,WREG SUBWFB AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32x24 Bit Unsigned Fixed Point Multiply 32 x 24 -> 56;; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3; 24 bit unsigned fixed point multiplier in BARGB0, BARGB1, BARGB2;; Use: CALL FXM3224U;; Output: 56 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6;; Result: AARG <-- AARG * BARG;; Max Timing: 90 clks;; Min Timing: 90 clks;; PM: 89 DM: 15;;FXM3224U MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3

MOVFP AARGB3,WREG MULWF BARGB2 MOVPF PRODH,AARGB5 MOVPF PRODL,SIGN MOVFP AARGB2,WREG MULWF BARGB1 MOVPF PRODH,AARGB3 MOVPF PRODL,AARGB4


MOVFP TEMPB3,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB5,F MOVPF PRODH,WREG ADDWFC AARGB4,F CLRF WREG,F ADDWFC AARGB3,F MOVFP AARGB1,WREG MULWF BARGB2


AN617

MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F MOVFP AARGB1,WREG MULWF BARGB1 CLRF AARGB2,W ADDWFC AARGB2,F MOVPF PRODL,WREG ADDWF AARGB3,F MOVPF PRODH,WREG ADDWFC AARGB2,F






MOVFP SIGN,AARGB6


AN617

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32x32 Bit Signed Fixed Point Multiply 32 x 32 -> 64;; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3; 32 bit signed fixed point multiplier in BARGB0, BARGB1,; BARGB2, BARGB3;; Use: CALL FXM3232S;; Output: 64 bit signed fixed point product in AARGB0, AARGB1,; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7;; Result: AARG <-- AARG * BARG;; Max Timing: 145 clks;; Min Timing: 129 clks;; PM: 144 DM: 18;FXM3232S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3

MOVFP AARGB3,WREG MULWF BARGB3 MOVPF PRODL,TBLPTRL MOVPF PRODH,TBLPTRH MOVFP AARGB2,WREG MULWF BARGB2 MOVPF PRODL,AARGB5 MOVPF PRODH,AARGB4

MULWF BARGB3 MOVPF PRODL,WREG ADDWF TBLPTRH,F MOVPF PRODH,WREG ADDWFC AARGB5,F CLRF WREG,F ADDWFC AARGB4,F

MOVFP TEMPB3,WREG MULWF BARGB2 MOVPF PRODL,WREG ADDWF TBLPTRH,F MOVPF PRODH,WREG ADDWFC AARGB5,F CLRF WREG,F ADDWFC AARGB4,F MOVFP AARGB1,WREG MULWF BARGB3 MOVPF PRODL,WREG ADDWF AARGB5,F MOVPF PRODH,WREG ADDWFC AARGB4,F MOVFP AARGB1,WREG MULWF BARGB2 CLRF AARGB3,W


AN617

ADDWFC AARGB3,F MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F






MOVFP TEMPB0,WREG MULWF BARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,WREG ADDWF AARGB1,F CLRF WREG,F ADDWFC AARGB0,F

MOVFP TEMPB3,WREG


AN617

MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F CLRF WREG,F ADDWFC AARGB2,F ADDWFC AARGB1,F ADDWFC AARGB0,F



MOVFP TBLPTRL,AARGB7 MOVFP TBLPTRH,AARGB6


TSIGN3232A BTFSS TEMPB0,MSB RETLW 0x00 MOVFP BARGB3,WREG SUBWF AARGB3,F MOVFP BARGB2,WREG SUBWFB AARGB2,F MOVFP BARGB1,WREG SUBWFB AARGB1,F MOVFP BARGB0,WREG SUBWFB AARGB0,F

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32x32 Bit Unsigned Fixed Point Multiply 32 x 32 -> 64;; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1,; AARGB2, AARGB3; 32 bit unsigned fixed point multiplier in BARGB0, BARGB1,; BARGB2, BARGB3


AN617

;; Use: CALL FXM3232U;; Output: 64 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7;; Result: AARG <-- AARG * BARG;; Max Timing: 125 clks;; Min Timing: 125 clks;; PM: 124 DM: 18;;FXM3232U MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3

MOVFP AARGB3,WREG MULWF BARGB3 MOVPF PRODL,TBLPTRL MOVPF PRODH,TBLPTRH MOVFP AARGB2,WREG MULWF BARGB2 MOVPF PRODL,AARGB5 MOVPF PRODH,AARGB4

MULWF BARGB3 MOVPF PRODL,WREG ADDWF TBLPTRH,F MOVPF PRODH,WREG ADDWFC AARGB5,F CLRF WREG,F ADDWFC AARGB4,F

MOVFP TEMPB3,WREG MULWF BARGB2 MOVPF PRODL,WREG ADDWF TBLPTRH,F MOVPF PRODH,WREG ADDWFC AARGB5,F CLRF WREG,F ADDWFC AARGB4,F MOVFP AARGB1,WREG MULWF BARGB3 MOVPF PRODL,WREG ADDWF AARGB5,F MOVPF PRODH,WREG ADDWFC AARGB4,F MOVFP AARGB1,WREG MULWF BARGB2 CLRF AARGB3,W ADDWFC AARGB3,F MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F

MOVFP TEMPB3,WREG MULWF BARGB1 MOVPF PRODL,WREG ADDWF AARGB5,F


AN617

MOVPF PRODH,WREG ADDWFC AARGB4,F CLRF AARGB2,W ADDWFC AARGB3,F ADDWFC AARGB2,F





MOVFP TEMPB0,WREG MULWF BARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,WREG ADDWF AARGB1,F CLRF WREG,F ADDWFC AARGB0,F

MOVFP TEMPB3,WREG MULWF BARGB0 MOVPF PRODL,WREG ADDWF AARGB4,F MOVPF PRODH,WREG ADDWFC AARGB3,F CLRF WREG,F ADDWFC AARGB2,F ADDWFC AARGB1,F ADDWFC AARGB0,F


AN617



MOVFP TBLPTRL,AARGB7 MOVFP TBLPTRH,AARGB6

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

NOTES:


AN617

APPENDIX G:PIC17CXXX DIVIDE ROUTINESTable of Contents for Appendix GG.1 PIC17CXXX Fixed Point Divide Routines A.................................................................................................. 261G.2 PIC17CXXX Fixed Point Divide Routines B.................................................................................................. 306G.3 PIC17CXXX Fixed Point Divide Routines C ................................................................................................. 347

G.1 PIC17CXXX Fixed Point Divide Routines A

; RCS Header $Id: fxda.a17 2.4 1997/03/22 03:11:13 F.J.Testa Exp $

; $Revision: 2.4 $

; PIC17 FIXED POINT DIVIDE ROUTINES A;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;;; FXD3232S 630 32 bit/32 bit -> 32.32 signed fixed point divide;; FXD3232U 683 32 bit/32 bit -> 32.32 unsigned fixed point divide;; FXD3231U 588 32 bit/31 bit -> 32.31 unsigned fixed point divide;; FXD3131U 579 31 bit/31 bit -> 31.31 unsigned fixed point divide;;; FXD3224S 529 32 bit/24 bit -> 32.24 signed fixed point divide;; FXD3224U 584 32 bit/24 bit -> 32.24 unsigned fixed point divide;; FXD3223U 489 32 bit/23 bit -> 32.23 unsigned fixed point divide;; FXD3123U 481 31 bit/23 bit -> 31.23 unsigned fixed point divide;

;**********************************************************************************************;**********************************************************************************************;; 32/32 Bit Division Macros;SDIV3232 macro;; Max Timing: 9+14+30*18+10 = 573 clks;; Min Timing: 9+14+30*17+3 = 536 clks;; PM: 9+14+30*24+10 = 753 DM: 12; variable i

MOVFP BARGB3,WREG



AN617

SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F RLCF AARGB0, F

variable i = D’2’

while i < D’8’

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB GOTO SADD22#v(i) SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK22#v(i)

SADD22#v(i) ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

SOK22#v(i) RLCF AARGB0, F

variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB


AN617

GOTO SADD228 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK228

SADD228 ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

SOK228 RLCF AARGB1, F


while i < D’16’




variable i = i + 1

endw

RLCF AARGB2,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB1,LSB GOTO SADD2216 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F


AN617

MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK2216




while i < D’24’




variable i = i + 1

endw

RLCF AARGB3,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB2,LSB GOTO SADD2224 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG


AN617

SUBWFB REMB0, F GOTO SOK2224




while i < D’32’




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO SOK22 MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FSOK22

endm

UDIV3232 macro;; restore = 25/30 clks, nonrestore = 17/20 clks


AN617

;; Max Timing: 16*25+1+16*30 = 881 clks;; Min Timing: 16*17+1+16*20 = 593 clks;; PM: 16*25+1+16*30 = 881 DM: 13; variable i


while i < D’8’

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK22#v(i) MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C

UOK22#v(i) RLCF AARGB0, F

variable i = i + 1

endw


while i < D’16’

RLCF AARGB1,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK22#v(i) MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG


AN617

ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C


variable i = i + 1

endw

CLRF TEMP, F


while i < D’24’

RLCF AARGB2,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB3,WREG SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG SUBWFB TEMP, F BTFSC _C GOTO UOK22#v(i) MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C


variable i = i + 1

endw


while i < D’32’

RLCF AARGB3,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB3,WREG


AN617

SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F BTFSC _C GOTO UOK22#v(i) MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C


variable i = i + 1

endw

endm

NDIV3232 macro

; Max Timing: 16+31*21+10 = 677 clks;; Min Timing: 16+31*20+3 = 639 clks;; PM: 16+31*29+10 = 925 DM: 13; variable i

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F


AN617

RLCF REMB0, F RLCF TEMP, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB GOTO NADD22#v(i) SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK22#v(i)

NADD22#v(i) ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK22#v(i) RLCF AARGB0, F

variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB GOTO NADD228 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK228

NADD228 ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK228 RLCF AARGB1, F



AN617

while i < D’16’

RLCF AARGB1,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB3,WREG BTFSS AARGB1,LSB GOTO NADD22#v(i) SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK22#v(i)


variable i = i + 1

endw


NADD2216 ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F


AN617

ADDWFC TEMP, F NOK2216 RLCF AARGB2, F


while i < D’24’



variable i = i + 1

endw


NADD2224 ADDWF REMB3, F MOVFP BARGB2,WREG


AN617

ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK2224 RLCF AARGB3, F


while i < D’32’



variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO NOK22 MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

NOK22 endm

UDIV3231 macro


AN617

;; Max Timing: 14+31*18+10 = 582 clks;; Min Timing: 14+31*17+3 = 544 clks;; PM: 14+31*24+10 = 768 DM: 12; variable i

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB GOTO UADD21#v(i) SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK21#v(i)

UADD21#v(i) ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB


AN617

GOTO UADD218 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK218

UADD218 ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

UOK218 RLCF AARGB1, F


while i < D’16’




variable i = i + 1

endw

RLCF AARGB2,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB1,LSB GOTO UADD2116 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F


AN617

MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK2116




while i < D’24’




variable i = i + 1

endw

RLCF AARGB3,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB2,LSB GOTO UADD2124 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG


AN617

SUBWFB REMB0, F GOTO UOK2124




while i < D’32’




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO UOK21 MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FUOK21

endm

UDIV3131 macro;; Max Timing: 9+14+30*18+10 = 573 clks


AN617

;; Min Timing: 9+14+30*17+3 = 536 clks;; PM: 9+14+30*24+10 = 753 DM: 12; variable i

MOVFP BARGB3,WREG SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F

RLCF AARGB0,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F RLCF AARGB0, F


while i < D’8’




variable i = i + 1

endw


AN617

RLCF AARGB1,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB0,LSB GOTO UADD118 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK118




while i < D’16’




variable i = i + 1

endw

RLCF AARGB2,W RLCF REMB3, F RLCF REMB2, F


AN617

RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG BTFSS AARGB1,LSB GOTO UADD1116 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK1116




while i < D’24’




variable i = i + 1

endw

RLCF AARGB3,W RLCF REMB3, F RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB3,WREG


AN617

BTFSS AARGB2,LSB GOTO UADD1124 SUBWF REMB3, F MOVFP BARGB2,WREG SUBWFB REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK1124




while i < D’32’




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO UOK11 MOVFP BARGB3,WREG ADDWF REMB3, F MOVFP BARGB2,WREG ADDWFC REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


AN617

UOK11

endm


MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO SADD24#v(i) SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK24#v(i)

SADD24#v(i) ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F



AN617

variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO SADD248 SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK248

SADD248 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F



while i < D’16’




variable i = i + 1

endw

RLCF AARGB2,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB1,LSB GOTO SADD2416 SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F


AN617

MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK2416




while i < D’24’




variable i = i + 1

endw






AN617

while i < D’32’




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO SOK24 MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FSOK24

endm

UDIV3224 macro;; restore = 20/25 clks, nonrestore = 14/17 clks;; Max Timing: 16*20+1+16*25 = 721 clks;; Min Timing: 16*14+1+16*17 = 497 clks;; PM: 16*20+1+16*25 = 721 DM: 11; variable i


while i < D’8’

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F


AN617

MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK24#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C


variable i = i + 1

endw


while i < D’16’

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK24#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C


variable i = i + 1

endw

CLRF TEMP, F


while i < D’24’

RLCF AARGB2,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F


AN617

SUBWFB TEMP, F BTFSC _C GOTO UOK24#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C


variable i = i + 1

endw


while i < D’32’

RLCF AARGB3,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F BTFSC _C GOTO UOK24#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C


variable i = i + 1

endw

endm

NDIV3224 macro;; Max Timing: 13+31*18+8 = 579 clks;; Min Timing: 13+31*17+3 = 543 clks;; PM: 13+31*24+8 = 765 DM: 11; variable i


AN617

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO NADD24#v(i) SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK24#v(i)

NADD24#v(i) ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK24#v(i) RLCF AARGB0, F

variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO NADD248 SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK248


AN617

NADD248 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK248 RLCF AARGB1, F


while i < D’16’



variable i = i + 1

endw


NADD2416 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG


AN617

ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK2416 RLCF AARGB2, F


while i < D’24’



variable i = i + 1

endw


NADD2424 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F


AN617

NOK2424 RLCF AARGB3, F


while i < D’32’



variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO NOK24 MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

NOK24 endm

UDIV3223 macro;; Max Timing: 11+31*15+8 = 484 clks;; Min Timing: 11+31*14+3 = 448 clks;; PM: 11+31*19+8 = 608 DM: 10; variable i

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F


AN617

MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO UADD23#v(i) SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK23#v(i)

UADD23#v(i) ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO UADD238 SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK238

UADD238 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F



while i < D’16’

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F


AN617

MOVFP BARGB2,WREG BTFSS AARGB1,LSB GOTO UADD23#v(i) SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK23#v(i)



variable i = i + 1

endw





while i < D’24’


UADD23#v(i) ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F


AN617

MOVFP BARGB0,WREG ADDWFC REMB0, F


variable i = i + 1

endw





while i < D’32’




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO UOK23 MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG


AN617

ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FUOK23

endm

UDIV3123 macro;; Max Timing: 7+11+30*15+8 = 476 clks;; Min Timing: 7+11+30*14+3 = 441 clks;; PM: 7+11+30*19+8 = 596 DM: 10; variable i




while i < D’8’




variable i = i + 1


AN617

endw





while i < D’16’




variable i = i + 1

endw

RLCF AARGB2,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB1,LSB GOTO UADD1316 SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F


AN617

GOTO UOK1316




while i < D’24’




variable i = i + 1

endw





while i < D’32’


AN617




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO UOK13 MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FUOK13

endm

;**********************************************************************************************;**********************************************************************************************;; 32/32 Bit Signed Fixed Point Divide 32/32 -> 32.32;; Input: 32 bit signed fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3;; Use: CALL FXD3232S;; Output: 32 bit signed fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit fixed point remainder in REMB0, REMB1, REMB2, REMB3;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 27+573+5 = 605 clks A > 0, B > 0; 34+573+23 = 630 clks A > 0, B < 0; 34+573+23 = 630 clks A < 0, B > 0; 41+573+5 = 619 clks A < 0, B < 0; 12 clks A = 0;; Min Timing: 27+536+5 = 568 clks A > 0, B > 0; 34+536+23 = 593 clks A > 0, B < 0; 31+536+23 = 593 clks A < 0, B > 0; 41+536+5 = 582 clks A < 0, B < 0;


AN617

; PM: 41+753+22+54 = 870 DM: 14;FXD3232S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F CLRF REMB2,F CLRF REMB3,F MOVPF AARGB0,WREG IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00

MOVPF AARGB0,WREG XORWF BARGB0,W BTFSC WREG,MSB COMF SIGN,F

CLRF TEMPB3,W ; clear exception flag


COMF BARGB3, F COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB3, F ADDWFC BARGB2, F ADDWFC BARGB1, F ADDWFC BARGB0, F


COMF AARGB3, F COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F INCF AARGB3, F ADDWFC AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F

C3232SX MOVPF AARGB0,WREG IORWF BARGB0,W BTFSC WREG,MSB GOTO C3232SX1

C3232S SDIV3232



COMF AARGB3, F COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB3, F ADDWFC AARGB2, F ADDWFC AARGB1, F


AN617

ADDWFC AARGB0, F

COMF REMB3, F COMF REMB2, F COMF REMB1, F COMF REMB0, F INCF REMB3, F ADDWFC REMB2, F ADDWFC REMB1, F ADDWFC REMB0, F

RETLW 0x00

C3232SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C3232SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C3232SX2 MOVPF AARGB0,REMB0 ; quotient = 0, remainder = AARG MOVPF AARGB1,REMB1 MOVPF AARGB2,REMB2 MOVPF AARGB3,REMB3 CLRF AARGB0,F CLRF AARGB1,F CLRF AARGB2,F CLRF AARGB3,F GOTO C3232SOKC3232SX2 CLRF AARGB0,F ; quotient = 1, remainder = 0 CLRF AARGB1,F CLRF AARGB2,F CLRF AARGB3,F INCF AARGB3,F RETLW 0x00


C3232SX4 INCF REMB3,F ; increment remainder and test for CLRF WREG,F ; overflow ADDWFC REMB2,F ADDWFC REMB1,F ADDWFC REMB0,F MOVFP BARGB3,WREG CPFSEQ REMB3 GOTO C3232SOK MOVFP BARGB2,WREG CPFSEQ REMB2 GOTO C3232SOK MOVFP BARGB1,WREG CPFSEQ REMB1 GOTO C3232SOK MOVFP BARGB0,WREG CPFSEQ REMB0 GOTO C3232SOK CLRF REMB0,F ; if remainder overflow, clear CLRF REMB1,F ; remainder, increment quotient and CLRF REMB2,F CLRF REMB3,W INCF AARGB3,F ; test for overflow exception ADDWFC AARGB2,F ADDWFC AARGB1,F ADDWFC AARGB0,F BTFSS AARGB0,MSB


AN617

GOTO C3232SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 32/32 Bit Unsigned Fixed Point Divide 32/32 -> 32.32;; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 32 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3;; Use: CALL FXD3232U;; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1AARGB2,AARGB3; 32 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 4+677+2 = 683 clks;; Min Timing: 4+639+2 = 645 clks;; PM: 4+925+1 = 930 DM: 13;FXD3232U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F CLRF REMB3, F

NDIV3232

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32/31 Bit Unsigned Fixed Point Divide 32/31 -> 32.31;; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 31 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3;; Use: CALL FXD3231U;; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 31 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 4+582+2 = 588 clks;; Min Timing: 4+544+2 = 550 clks;; PM: 4+768+1 = 773 DM: 12;FXD3231U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F CLRF REMB3, F

UDIV3231

RETLW 0x00


AN617

;**********************************************************************************************;**********************************************************************************************;; 31/31 Bit Unsigned Fixed Point Divide 31/31 -> 31.31;; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 31 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3;; Use: CALL FXD3131U;; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 31 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 4+573+2 = 579 clks;; Min Timing: 4+536+2 = 542 clks;; PM: 4+753+1 = 758 DM: 12;FXD3131U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F CLRF REMB3, F

UDIV3131

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************;; 32/24 Bit Signed Fixed Point Divide 32/24 -> 32.24;; Input: 32 bit signed fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD3224S;; Output: 32 bit signed fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 24 bit fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 25+476+5 = 506 clks A > 0, B > 0; 30+476+21 = 527 clks A > 0, B < 0; 32+476+21 = 529 clks A < 0, B > 0; 37+476+5 = 518 clks A < 0, B < 0; 11 clks A = 0;; Min Timing: 25+441+3 = 469 clks A > 0, B > 0; 30+441+19 = 490 clks A > 0, B < 0; 32+441+19 = 492 clks A < 0, B > 0; 37+441+3 = 481 clks A < 0, B < 0;; PM: 37+596+20+51 = 704 DM: 12;FXD3224S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F CLRF REMB2,F MOVPF AARGB0,WREG IORWF AARGB1,W IORWF AARGB2,W


AN617

IORWF AARGB3,W BTFSC _Z RETLW 0x00




COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB2, F ADDWFC BARGB1, F ADDWFC BARGB0, F




C3224S SDIV3224



COMF AARGB3, F COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB3, F ADDWFC AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F

COMF REMB2, F COMF REMB1, F COMF REMB0, F INCF REMB2, F ADDWFC REMB1, F ADDWFC REMB0, F

RETLW 0x00


AN617

C3224SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C3224SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C3224SX2 MOVPF AARGB1,REMB0 MOVPF AARGB2,REMB1 MOVPF AARGB3,REMB2 BCF REMB0,MSB RLCF AARGB1,F RLCF AARGB0,F MOVFP AARGB0,AARGB3 CLRF AARGB0,F CLRF AARGB1,F CLRF AARGB2,F GOTO C3224SOKC3224SX2 CLRF AARGB3,F ; quotient = 1, remainder = 0 INCF AARGB3,F CLRF AARGB2,F CLRF AARGB1,F CLRF AARGB0,F RETLW 0x00


C3224SX4 INCF REMB2,F ; increment remainder and test for CLRF WREG,F ADDWFC REMB1,F ADDWFC REMB0,F MOVFP BARGB2,WREG ; overflow CPFSEQ REMB2 GOTO C3224SOK MOVFP BARGB1,WREG CPFSEQ REMB1 GOTO C3224SOK MOVFP BARGB0,WREG CPFSEQ REMB0 GOTO C3224SOK CLRF REMB0,F ; if remainder overflow, clear CLRF REMB1,F CLRF REMB2,W INCF AARGB3,F ; remainder, increment quotient and ADDWFC AARGB2,F ADDWFC AARGB1,F ; test for overflow exception ADDWFC AARGB0,F BTFSS AARGB0,MSB GOTO C3224SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 32/24 Bit Unsigned Fixed Point Divide 32/24 -> 32.24;; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2, AARGB3; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD3224U;; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2, AARGB3


AN617

; 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 3+579+2 = 584 clks;; Min Timing: 3+543+2 = 548 clks;; PM: 3+765+1 = 769 DM: 11;FXD3224U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F

NDIV3224

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************;; 32/23 Bit Unsigned Fixed Point Divide 32/23 -> 32.23;; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2, AARGB3; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD3223U;; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2, AARGB3; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 3+484+2 = 489 clks;; Min Timing: 3+448+2 = 453 clks;; PM: 3+608+1 = 612 DM: 10;FXD3223U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F

UDIV3223

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************;; 31/23 Bit Unsigned Fixed Point Divide 31/23 -> 31.23;; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2, AARGB3; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD3123U;; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2, AARGB3; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 3+476+2 = 481 clks;; Min Timing: 3+441+2 = 446 clks


AN617

;; PM: 3+596+1 = 600 DM: 10;FXD3123U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F

UDIV3123

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

G.2 PIC17CXXX Fixed Point Divide Routines B

; RCS Header $Id: fxdb.a17 2.4 1997/03/22 03:11:13 F.J.Testa Exp $

; $Revision: 2.4 $

; PIC17 FIXED POINT DIVIDE ROUTINES B;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD2416S 328 24 bit/16 bit -> 24.16 signed fixed point divide;; FXD2416U 365 24 bit/16 bit -> 24.16 unsigned fixed point divide;; FXD2415U 294 24 bit/15 bit -> 24.15 unsigned fixed point divide;; FXD2315U 287 23 bit/15 bit -> 23.15 unsigned fixed point divide;;; FXD1616S 227 16 bit/16 bit -> 16.16 signed fixed point divide;; FXD1616U 244 16 bit/16 bit -> 16.16 unsigned fixed point divide;; FXD1615U 197 16 bit/15 bit -> 16.15 unsigned fixed point divide;; FXD1515U 191 15 bit/15 bit -> 15.15 unsigned fixed point divide;;; FXD1608S 159 16 bit/08 bit -> 16.08 signed fixed point divide;; FXD1608U 196 16 bit/08 bit -> 16.08 unsigned fixed point divide;; FXD1607U 130 16 bit/07 bit -> 16.07 unsigned fixed point divide;; FXD1507U 125 15 bit/07 bit -> 15.07 unsigned fixed point divide;;; FXD0808S 88 08 bit/08 bit -> 08.08 signed fixed point divide;; FXD0808U 75 08 bit/08 bit -> 08.08 unsigned fixed point divide;; FXD0807U 66 08 bit/07 bit -> 08.07 unsigned fixed point divide;; FXD0707U 61 07 bit/07 bit -> 07.07 unsigned fixed point divide;;**********************************************************************************************;**********************************************************************************************;; 24/16 Bit Division Macros;SDIV2416 macro;; Max Timing: 5+8+22*12+6 = 283 clks;; Min Timing: 5+8+22*11+3 = 258 clks


AN617

;; PM: 5+8+22*14+6 = 327 DM: 8; variable i

MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F

RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO SADD46#v(i) SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK46#v(i)

SADD46#v(i) ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO SADD468 SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK468

SADD468 ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F



while i < D’16’


AN617




variable i = i + 1

endw





while i < D’24’




variable i = i + 1

endw

BTFSC AARGB2,LSB GOTO SOK46


AN617

MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FSOK46

endm



while i < D’8’

RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK46#v(i) MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C


variable i = i + 1

endw


while i < D’16’




AN617

variable i = i + 1

endw

CLRF TEMP, F


while i < D’24’

RLCF AARGB2,W RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F BTFSC _C GOTO UOK46#v(i) MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C


variable i = i + 1

endw

endm


RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W


AN617

RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO NADD46#v(i) SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK46#v(i)

NADD46#v(i) ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK46#v(i) RLCF AARGB0, F

variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO NADD468 SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK468

NADD468 ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK468 RLCF AARGB1, F


while i < D’16’

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB1,WREG BTFSS AARGB1,LSB GOTO NADD46#v(i) SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK46#v(i)

NADD46#v(i) ADDWF REMB1, F


AN617

MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK46#v(i) RLCF AARGB1, F

variable i = i + 1

endw




while i < D’24’



variable i = i + 1

endw

BTFSC AARGB2,LSB GOTO NOK46 MOVFP BARGB1,WREG


AN617

ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

NOK46 endm


RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO UADD45#v(i) SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK45#v(i)



variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO UADD458 SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK458

UADD458 ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


AN617



while i < D’16’




variable i = i + 1

endw





while i < D’24’





AN617

variable i = i + 1

endw

BTFSC AARGB2,LSB GOTO UOK45 MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FUOK45

endm





while i < D’8’




variable i = i + 1

endw


AN617





while i < D’16’




variable i = i + 1

endw





while i < D’24’

RLCF AARGB2,W RLCF REMB1, F


AN617

RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB2,LSB GOTO UADD35#v(i) SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK35#v(i)



variable i = i + 1

endw


endm





while i < D’8’



AN617

RLCF REMB0, F MOVFP BARGB1,WREG


SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK66#v(i)

SADD66#v(i) ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F SOK66#v(i) RLCF AARGB0, F

variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG

BTFSS AARGB0,LSB GOTO SADD668

SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK668

SADD668 ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F SOK668 RLCF AARGB1, F


while i < D’16’



SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK66#v(i)

SADD66#v(i) ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F SOK66#v(i) RLCF AARGB1, F

variable i = i + 1

endw


AN617

BTFSC AARGB1,LSB GOTO SOK66 MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FSOK66

endm

UDIV1616 macro;; restore = 15 clks, nonrestore = 11 clks;; Max Timing: 8*15+8*15 = 240 clks;; Min Timing: 8*11+8*11 = 176 clks;; PM: 8*15+8*15 = 240 DM: 6; variable i


while i < D’8’

RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F

BTFSC _C GOTO UOK66#v(i) MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _CUOK66#v(i) RLCF AARGB0, F

variable i = i + 1

endw


while i < D’16’

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F

BTFSC _C GOTO UOK66#v(i) MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


AN617

BCF _CUOK66#v(i) RLCF AARGB1, F

variable i = i + 1

endw

endm


RLCF AARGB0,W RLCF REMB1, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’



variable i = i + 1

endw

RLCF AARGB1,W RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO NADD668


AN617

SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK668



while i < D’16’



variable i = i + 1

endw

BTFSC AARGB1,LSB GOTO NOK66 MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

NOK66 endm


RLCF AARGB0,W


AN617

RLCF REMB1, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F


while i < D’8’



SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK65#v(i)

UADD65#v(i) ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F UOK65#v(i) RLCF AARGB0, F

variable i = i + 1

endw



SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK658

UADD658 ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F UOK658 RLCF AARGB1, F


while i < D’16’



SUBWF REMB1, F


AN617

MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK65#v(i)


variable i = i + 1

endw


endm





while i < D’8’





AN617


variable i = i + 1

endw



SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK558

UADD558 ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F UOK558 RLCF AARGB1, F


while i < D’16’





variable i = i + 1

endw



AN617

endm

;_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ;; Extra 16 Bit Divide Macros; DIV1616 macro;; Timing: restore = 16 clks, nonrestore = 13 clks 16*16 = 256 clks; variable i


while i < D’16’

RLCF AARGB1, F RLCF AARGB0, F RLCF REMB1, F RLCF REMB0, F

MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F

BTFSS _C GOTO RS1616_#v( i )

BSF AARGB1,LSB GOTO OK1616_#v( i )

RS1616_#v( i ) MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF AARGB1,LSB

OK1616_#v(i)

variable i = i + 1

endw

endm

DIVMAC macro;; Timing: restore = 19 clks, nonrestore = 14 clks 16*19 = 304 clks; variable i


while i < D’16’

RLCF AARGB1, F RLCF AARGB0, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB0,WREG SUBWF REMB0,W BTFSS _Z GOTO notz#v( i ) MOVFP BARGB1,WREG SUBWF REMB1,W


AN617

notz#v( i ) BTFSS _C GOTO nosub#v( i )

MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BSF AARGB1,LSB GOTO ok#v(i)

nosub#v(i) BCF AARGB1,LSB

ok#v(i)

variable i = i + 1

endw

endm


MOVFP BARGB0,WREG SUBWF REMB0, F RLCF AARGB0, F

RLCF AARGB0,W RLCF REMB0, F MOVFP BARGB0,WREG ADDWF REMB0, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB0, F MOVFP BARGB0,WREG

BTFSC AARGB0,LSB SUBWF REMB0, F BTFSS AARGB0,LSB ADDWF REMB0, F RLCF AARGB0, F

variable i = i + 1

endw

RLCF AARGB1,W


AN617

RLCF REMB0, F MOVFP BARGB0,WREG



while i < D’16’



variable i = i + 1

endw


endm

UDIV1608 macro;; restore = 9/15 clks, nonrestore = 8/11 clks;; Max Timing: 8*9+1+8*15 = 193 clks max;; Min Timing: 8*8+1+8*11 = 153 clks min;; PM: 8*9+1+8*15 = 193 DM: 4; variable i


while i < D’8’

RLCF AARGB0,W RLCF REMB0, F MOVFP BARGB0,WREG SUBWF REMB0, F

BTFSC _C GOTO UOK68#v(i) ADDWF REMB0, F BCF _CUOK68#v(i) RLCF AARGB0, F

variable i = i + 1

endw

CLRF TEMP, F



AN617

while i < D’16’

RLCF AARGB1,W RLCF REMB0, F RLCF TEMP, F MOVFP BARGB0,WREG SUBWF REMB0, F CLRF WREG, F SUBWFB TEMP, F

BTFSC _C GOTO UOK68#v(i) MOVFP BARGB0,WREG ADDWF REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _CUOK68#v(i) RLCF AARGB1, F

variable i = i + 1

endw

endm


RLCF AARGB0,W RLCF REMB0, F MOVFP BARGB0,WREG SUBWF REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’

RLCF AARGB0,W RLCF REMB0, F RLCF TEMP, F MOVFP BARGB0,WREG

BTFSS AARGB0,LSB GOTO NADD68#v(i) SUBWF REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK68#v(i)

NADD68#v(i) ADDWF REMB0, F CLRF WREG, F ADDWFC TEMP, F

NOK68#v(i) RLCF AARGB0, F


AN617

variable i = i + 1

endw


BTFSS AARGB0,LSB GOTO NADD688 SUBWF REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK688

NADD688 ADDWF REMB0, F CLRF WREG, F ADDWFC TEMP, F

NOK688 RLCF AARGB1, F


while i < D’16’


BTFSS AARGB1,LSB GOTO NADD68#v(i) SUBWF REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK68#v(i)

NADD68#v(i) ADDWF REMB0, F CLRF WREG, F ADDWFC TEMP, F

NOK68#v(i) RLCF AARGB1, F

variable i = i + 1

endw

BTFSS AARGB1,LSB MOVFP BARGB0,WREG ADDWF REMB0, F

endm



AN617

RLCF AARGB0,W RLCF REMB0, F MOVFP BARGB0,WREG SUBWF REMB0, F RLCF AARGB0, F


while i < D’8’



variable i = i + 1

endw




while i < D’16’



variable i = i + 1

endw


endm



AN617




while i < D’8’



variable i = i + 1

endw




while i < D’16’



variable i = i + 1

endw


endm

;**********************************************************************************************


AN617

;**********************************************************************************************;; 08/08 Bit Division Macros;SDIV0808 macro;; Max Timing: 3+5+6*8+2 = 58 clks;; Min Timing: 3+5+6*8+2 = 58 clks;; PM: 3+5+6*8+2 = 58 DM: 3; variable i




while i < D’8’



variable i = i + 1

endw


endm

UDIV0808 macro;; restore = 9 clks, nonrestore = 8 clks;; Max Timing: 8*9 = 72 clks max;; Min Timing: 8*8 = 64 clks min;; PM: 8*9 = 72 DM: 3; variable i


while i < D’8’



AN617

MOVFP BARGB0,WREG SUBWF REMB0, F

BTFSC _C GOTO UOK88#v(i) ADDWF REMB0, F BCF _CUOK88#v(i) RLCF AARGB0, F

variable i = i + 1

endw

endm


RLCF AARGB0,W RLCF REMB0, F MOVFP BARGB0,WREG SUBWF REMB0, F RLCF AARGB0, F


while i < D’8’



variable i = i + 1

endw


endm



AN617




while i < D’8’



variable i = i + 1

endw


endm

;**********************************************************************************************;**********************************************************************************************;; 24/16 Bit Signed Fixed Point Divide 24/16 -> 24.16;; Input: 24 bit fixed point dividend in AARGB0, AARGB1, AARGB2; 16 bit fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD2416S;; Output: 24 bit fixed point quotient in AARGB0, AARGB1, AARGB2; 16 bit fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 23+283+5 = 311 clks A > 0, B > 0; 26+283+17 = 326 clks A > 0, B < 0; 28+283+17 = 328 clks A < 0, B > 0; 31+283+5 = 319 clks A < 0, B < 0; 9 clks A = 0;; Min Timing: 23+258+5 = 286 clks A > 0, B > 0; 26+258+17 = 301 clks A > 0, B < 0; 28+258+17 = 303 clks A < 0, B > 0; 31+258+5 = 294 clks A < 0, B < 0;; PM: 30+327+16+41 = 414 DM: 9;FXD2416S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F MOVPF AARGB0,WREG IORWF AARGB1,W


AN617

IORWF AARGB2,W BTFSC _Z RETLW 0x00



BTFSS BARGB0,MSB ; if MSB set go & negate BARG GOTO CA2416S

COMF BARGB1, F COMF BARGB0, F INCF BARGB1, F ADDWFC BARGB0, F

CA2416S BTFSS AARGB0,MSB ; if MSB set go & negate AARGa GOTO C2416SX

COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F INCF AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F


C2416S SDIV2416


C2416SOK BTFSS SIGN,MSB ; negate RETLW 0x00

COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F

COMF REMB1, F COMF REMB0, F INCF REMB1, F ADDWFC REMB0, F

RETLW 0x00

C2416SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C2416SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C2416SX2 MOVPF AARGB1,REMB0 MOVPF AARGB2,REMB1 BCF REMB0,MSB RLCF AARGB1,F RLCF AARGB0,F


AN617

MOVFP AARGB0,AARGB2 CLRF AARGB0,F CLRF AARGB1,F GOTO C2416SOKC2416SX2 CLRF AARGB2,F ; quotient = 1, remainder = 0 INCF AARGB2,F CLRF AARGB1,F CLRF AARGB0,F RETLW 0x00


C2416SX4 INCF REMB1,F ; increment remainder and test for CLRF WREG,F ADDWFC REMB0,F MOVFP BARGB1,WREG ; overflow CPFSEQ REMB1 GOTO C2416SOK MOVFP BARGB0,WREG ; overflow CPFSEQ REMB0 GOTO C2416SOK CLRF REMB0,W ; if remainder overflow, clear CLRF REMB1,W INCF AARGB2,F ; remainder, increment quotient and ADDWFC AARGB1,F ; test for overflow exception ADDWFC AARGB0,F BTFSS AARGB0,MSB GOTO C2416SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 24/16 Bit Unsigned Fixed Point Divide 24/16 -> 24.16;; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2; 16 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD2416U;; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2; 16 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+361+2 = 365 clks;; Min Timing: 2+335+2 = 339 clks;; PM: 2+450+1 = 453 DM: 8;FXD2416U CLRF REMB0, F CLRF REMB1, F

NDIV2416

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

;; 24/15 Bit Unsigned Fixed Point Divide 24/15 -> 24.15;; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2; 15 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD2415U;; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2; 15 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+290+2 = 294 clks;; Min Timing: 2+264+2 = 268 clks;; PM: 2+336+1 = 339 DM: 8;FXD2415U CLRF REMB0, F CLRF REMB1, F

UDIV2415

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 23/15 Bit Unsigned Fixed Point Divide 23/15 -> 23.15;; Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2; 15 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD2315U;; Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2; 15 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+283+2 = 287 clks;; Min Timing: 2+258+2 = 262 clks;; PM: 2+327+1 = 330 DM: 8;FXD2315U CLRF REMB0, F CLRF REMB1, F

UDIV2315

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************;; 16/16 Bit Signed Fixed Point Divide 16/16 -> 16.16;; Input: 16 bit fixed point dividend in AARGB0, AARGB1; 16 bit fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD1616S;; Output: 16 bit fixed point quotient in AARGB0, AARGB1; 16 bit fixed point remainder in REMB0, REMB1


AN617

;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 22+187+5 = 214 clks A > 0, B > 0; 25+187+15 = 227 clks A > 0, B < 0; 25+187+15 = 227 clks A < 0, B > 0; 28+187+5 = 220 clks A < 0, B < 0; 8 clks A = 0;; Min Timing: 22+173+5 = 200 clks A > 0, B > 0; 25+173+15 = 213 clks A > 0, B < 0; 25+173+15 = 213 clks A < 0, B > 0; 28+173+5 = 206 clks A < 0, B < 0;; PM: 27+215+14+34 = 290 DM: 8;FXD1616S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F MOVPF AARGB0,WREG IORWF AARGB1,W BTFSC _Z RETLW 0x00






COMF AARGB1, F COMF AARGB0, F INCF AARGB1, F ADDWFC AARGB0, F


C1616S SDIV1616



COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB1, F ADDWFC AARGB0, F


AN617


RETLW 0x00

C1616SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C1616SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C1616SX2 MOVPF AARGB0,REMB0 ; quotient = 0, remainder = AARG MOVPF AARGB1,REMB1 CLRF AARGB0,F CLRF AARGB1,F GOTO C1616SOKC1616SX2 CLRF AARGB0,F ; quotient = 1, remainder = 0 CLRF AARGB1,F INCF AARGB1,F RETLW 0x00


C1616SX4 INCF REMB1,F ; increment remainder and test for CLRF WREG,F ; overflow ADDWFC REMB0,F MOVFP BARGB1,WREG CPFSEQ REMB1 GOTO C1616SOK MOVFP BARGB0,WREG CPFSEQ REMB0 GOTO C1616SOK CLRF REMB0,F ; if remainder overflow, clear CLRF REMB1,W ; remainder, increment quotient and INCF AARGB1,F ; test for overflow exception ADDWFC AARGB0,F BTFSS AARGB0,MSB GOTO C1616SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 16/16 Bit Unsigned Fixed Point Divide 16/16 -> 16.16;; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1; 16 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD1616U;; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1; 16 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+240+2 = 244 clks;; Min Timing: 2+176+2 = 180 clks;


AN617

; PM: 2+240+1 = 243 DM: 6;FXD1616U CLRF REMB0, F CLRF REMB1, F

UDIV1616

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 16/15 Bit Unsigned Fixed Point Divide 16/15 -> 16.15;; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1; 15 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD1615U;; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1; 15 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+193+2 = 197 clks;; Min Timing: 2+178+2 = 182 clks;; PM: 2+213+1 = 216 DM: 6;FXD1615U CLRF REMB0, F CLRF REMB1, F

UDIV1615

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************;; 15/15 Bit Unsigned Fixed Point Divide 15/15 -> 15.15;; Input: 15 bit unsigned fixed point dividend in AARGB0, AARGB1; 15 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD1515U;; Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1; 15 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+187+2 = 191 clks;; Min Timing: 2+173+2 = 177 clks;; PM: 2+215+1 = 218 DM: 6;FXD1515U CLRF REMB0, F CLRF REMB1, F

UDIV1515

RETLW 0x00

;**********************************************************************************************


AN617

;**********************************************************************************************;; 16/8 Bit Signed Fixed Point Divide 16/08 -> 16.08;; Input: 16 bit fixed point dividend in AARGB0, AARGB1; 8 bit fixed point divisor in BARGB0;; Use: CALL FXD1608S;; Output: 16 bit fixed point quotient in AARGB0, AARGB1; 8 bit fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 21+122+5 = 148 clks A > 0, B > 0; 22+122+13 = 157 clks A > 0, B < 0; 24+122+13 = 159 clks A < 0, B > 0; 25+122+5 = 152 clks A < 0, B < 0; 7 clks A = 0;; Min Timing: 21+122+5 = 148 clks A > 0, B > 0; 22+122+13 = 157 clks A > 0, B < 0; 24+122+13 = 159 clks A < 0, B > 0; 25+122+5 = 152 clks A < 0, B < 0;; PM: 25+122+12+30 = 189 DM: 6;FXD1608S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder MOVPF AARGB0,WREG IORWF AARGB1,W BTFSC _Z RETLW 0x00






COMF AARGB1, F COMF AARGB0, F INCF AARGB1, F ADDWFC AARGB0, F


C1608S SDIV1608


C1608SOK BTFSS SIGN,MSB ; negate


AN617

RETLW 0x00

COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB1, F ADDWFC AARGB0, F


RETLW 0x00

C1608SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C1608SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C1608SX2 MOVPF AARGB1,REMB0 BCF REMB0,MSB RLCF AARGB1,F RLCF AARGB0,F MOVFP AARGB0,AARGB1 CLRF AARGB0,F GOTO C1608SOKC1608SX2 CLRF AARGB1,F ; quotient = 1, remainder = 0 INCF AARGB1,F CLRF AARGB0,F RETLW 0x00


C1608SX4 INCF REMB0,F ; increment remainder and test for MOVFP BARGB0,WREG ; overflow CPFSEQ REMB0 GOTO C1608SOK CLRF REMB0,W ; if remainder overflow, clear INCF AARGB1,F ; remainder, increment quotient and ADDWFC AARGB0,F ; test for overflow exception BTFSS AARGB0,MSB GOTO C1608SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 16/8 Bit Unsigned Fixed Point Divide 16/08 -> 16.08;; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1; 8 bit unsigned fixed point divisor in BARGB0;; Use: CALL FXD1608U;; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1; 8 bit unsigned fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 1+193+2 = 196 clks;; Min Timing: 1+153+2 = 156 clks;


AN617

; PM: 1+193+1 = 195 DM: 4;FXD1608U CLRF REMB0, F

UDIV1608

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 16/7 Bit Unsigned Fixed Point Divide 16/07 -> 16.07;; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1; 7 bit unsigned fixed point divisor in BARGB0;; Use: CALL FXD1607U;; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1; 7 bit unsigned fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 1+127+2 = 130 clks;; Min Timing: 1+127+2 = 130 clks;; PM: 1+127+1 = 129 DM: 4;FXD1607U CLRF REMB0, F

UDIV1607

RETLW 0x00

;**********************************************************************************************;********************************************************************************************** ; 15/7 Bit Unsigned Fixed Point Divide 15/07 -> 15.07;; Input: 15 bit unsigned fixed point dividend in AARGB0, AARGB1; 7 bit unsigned fixed point divisor in BARGB0;; Use: CALL FXD1507U;; Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1; 7 bit unsigned fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 1+122+2 = 125 clks;; Min Timing: 1+122+2 = 125 clks;; PM: 1+122+1 = 124 DM: 4;FXD1507U CLRF REMB0, F

UDIV1507

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 8/8 Bit Signed Fixed Point Divide 08/08 -> 08.08;


AN617

; Input: 8 bit fixed point dividend in AARGB0; 8 bit fixed point divisor in BARGB0;; Use: CALL FXD0808S;; Output: 8 bit fixed point quotient in AARGB0; 8 bit fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 19+58+5 = 82 clks A > 0, B > 0; 20+58+10 = 88 clks A > 0, B < 0; 20+58+10 = 88 clks A < 0, B > 0; 21+58+5 = 84 clks A < 0, B < 0; 6 clks A = 0;; Min Timing: 19+58+5 = 82 clks A > 0, B > 0; 20+58+10 = 88 clks A > 0, B < 0; 20+58+10 = 88 clks A < 0, B > 0; 21+58+5 = 84 clks A < 0, B < 0;; PM: 20+58+9+23 = 110 DM: 5;FXD0808S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder MOVPF AARGB0,WREG BTFSC _Z RETLW 0x00

XORWF BARGB0,W BTFSC WREG,MSB COMF SIGN,F


BTFSS BARGB0,MSB GOTO CA0808S


CA0808S BTFSS AARGB0,MSB GOTO C0808SX



C0808S SDIV0808






AN617

RETLW 0x00

C0808SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C0808SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C0808SX2 MOVPF AARGB0,REMB0 ; quotient = 0, remainder = AARG CLRF AARGB0,F GOTO C0808SOKC0808SX2 CLRF AARGB0,F ; quotient = 1, remainder = 0 INCF AARGB0,F RETLW 0x00

C0808SX3 COMF AARGB0,F ; numerator = 0x7F + 1 INCF TEMPB3,F GOTO C0808S

C0808SX4 INCF REMB0,F ; increment remainder and test for MOVFP BARGB0,WREG ; overflow CPFSEQ REMB0 GOTO C0808SOK CLRF REMB0,F ; if remainder overflow, clear INCF AARGB0,F ; remainder, increment quotient and BTFSS AARGB0,MSB ; test for overflow exception GOTO C0808SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************; ; 8/8 Bit Unsigned Fixed Point Divide 08/08 -> 08.08;; Input: 8 bit unsigned fixed point dividend in AARGB0; 8 bit unsigned fixed point divisor in BARGB0;; Use: CALL FXD0808U;; Output: 8 bit unsigned fixed point quotient in AARGB0; 8 bit unsigned fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 1+72+2 = 75 clks;; Min Timing: 1+64+2 = 67 clks;; PM: 1+72+1 = 74 DM: 3;FXD0808U CLRF REMB0, F

UDIV0808

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 8/7 Bit Unsigned Fixed Point Divide 08/07 -> 08.07;; Input: 8 bit unsigned fixed point dividend in AARGB0; 7 bit unsigned fixed point divisor in BARGB0;


AN617

; Use: CALL FXD0807U;; Output: 8 bit unsigned fixed point quotient in AARGB0; 7 bit unsigned fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 1+63+2 = 66 clks;; Min Timing: 1+63+2 = 66 clks;; PM: 1+63+1 = 65 DM: 3;FXD0807U CLRF REMB0, F

UDIV0807

RETLW 0x00

;**********************************************************************************************;********************************************************************************************** ; 7/7 Bit Unsigned Fixed Point Divide 07/07 -> 07.07;; Input: 7 bit unsigned fixed point dividend in AARGB0; 7 bit unsigned fixed point divisor in BARGB0;; Use: CALL FXD0707U;; Output: 7 bit unsigned fixed point quotient in AARGB0; 7 bit unsigned fixed point remainder in REMB0;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 1+58+2 = 61 clks;; Min Timing: 1+58+2 = 61 clks;; PM: 1+58+1 = 60 DM: 3;FXD0707U CLRF REMB0, F

UDIV0707

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************


AN617

G.3 PIC17CXXX Fixed Point Divide Routines C

; RCS Header $Id: fxdc.a17 2.4 1997/03/22 03:11:13 F.J.Testa Exp $

; $Revision: 2.4 $

; PIC17 FIXED POINT DIVIDE ROUTINES C;; Input: fixed point arguments in AARG and BARG;; Output: quotient AARG/BARG followed by remainder in REM;; All timings are worst case cycle counts;; It is useful to note that the additional unsigned routines requiring a non-power of two; argument can be called in a signed divide application where it is known that the; respective argument is nonnegative, thereby offering some improvement in; performance.;; Routine Clocks Function;; FXD3216S 429 32 bit/16 bit -> 32.16 signed fixed point divide;; FXD3216U 485 32 bit/16 bit -> 32.16 unsigned fixed point divide;; FXD3215U 390 32 bit/15 bit -> 32.15 unsigned fixed point divide;; FXD3115U 383 31 bit/15 bit -> 31.15 unsigned fixed point divide;;; FXD2424S 404 24 bit/24 bit -> 24.24 signed fixed point divide;; FXD2424U 440 24 bit/24 bit -> 24.24 unsigned fixed point divide;; FXD2423U 369 24 bit/23 bit -> 24.23 unsigned fixed point divide;; FXD2323U 361 23 bit/23 bit -> 23.23 unsigned fixed point divide;



RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG ADDWF REMB1, F


AN617

MOVFP BARGB0,WREG ADDWFC REMB0, F RLCF AARGB0, F


while i < D’8’




variable i = i + 1

endw





while i < D’16’





AN617

variable i = i + 1

endw





while i < D’24’




variable i = i + 1

endw






AN617

while i < D’32’




variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO SOK26 MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, FSOK26

endm



while i < D’8’




AN617

variable i = i + 1

endw


while i < D’16’



variable i = i + 1

endw

CLRF TEMP, F


while i < D’24’



variable i = i + 1

endw


while i < D’32’


AN617



variable i = i + 1

endw

endm


RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’



AN617


variable i = i + 1

endw




while i < D’16’



variable i = i + 1

endw

RLCF AARGB2,W


AN617

RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB1,WREG BTFSS AARGB1,LSB GOTO NADD2616 SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F GOTO NOK2616



while i < D’24’



variable i = i + 1

endw


NADD2624 ADDWF REMB1, F


AN617

MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK2624 RLCF AARGB3, F


while i < D’32’



variable i = i + 1

endw

BTFSC AARGB3,LSB GOTO NOK26 MOVFP BARGB1,WREG ADDWF REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

NOK26 endm


RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F


AN617


while i < D’8’




variable i = i + 1

endw





while i < D’16’




variable i = i + 1

endw


AN617





while i < D’24’




variable i = i + 1

endw





while i < D’32’

RLCF AARGB3,W


AN617

RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB3,LSB GOTO UADD25#v(i) SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK25#v(i)



variable i = i + 1

endw


endm





while i < D’8’

RLCF AARGB0,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB0,LSB GOTO UADD15#v(i)


AN617




variable i = i + 1

endw





while i < D’16’




variable i = i + 1

endw

RLCF AARGB2,W RLCF REMB1, F RLCF REMB0, F MOVFP BARGB1,WREG BTFSS AARGB1,LSB GOTO UADD1516 SUBWF REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F


AN617

GOTO UOK1516




while i < D’24’




variable i = i + 1

endw





while i < D’32’



AN617



variable i = i + 1

endw


endm





while i < D’8’

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO SADD44#v(i)


AN617

SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO SOK44#v(i)



variable i = i + 1

endw





while i < D’16’





AN617

variable i = i + 1

endw





while i < D’24’




variable i = i + 1

endw

BTFSC AARGB2,LSB GOTO SOK44 MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


AN617

SOK44

endm


variable i = 0

while i < 8

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK44#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C


variable i = i + 1

endw


while i < D’16’

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F BTFSC _C GOTO UOK44#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG


AN617

ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F BCF _C


variable i = i + 1

endw

CLRF TEMP, F


while i < D’24’

RLCF AARGB2,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F RLCF TEMP, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF WREG, F SUBWFB TEMP, F BTFSC _C GOTO UOK44#v(i) MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C


variable i = i + 1

endw

endm


RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG


AN617

SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F CLRF TEMP,W SUBWFB TEMP, F RLCF AARGB0, F


while i < D’8’



variable i = i + 1

endw


NADD448 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F


AN617

CLRF WREG, F ADDWFC TEMP, F NOK448 RLCF AARGB1, F


while i < D’16’



variable i = i + 1

endw


NADD4416 ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F CLRF WREG, F ADDWFC TEMP, F NOK4416 RLCF AARGB2, F


AN617


while i < D’24’



variable i = i + 1

endw

BTFSC AARGB2,LSB GOTO NOK44 MOVFP BARGB2,WREG ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG ADDWFC REMB0, F

NOK44 endm


RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG SUBWF REMB2, F MOVFP BARGB1,WREG


AN617

SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F RLCF AARGB0, F


while i < D’8’




variable i = i + 1

endw





while i < D’16’

RLCF AARGB1,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG


AN617

BTFSS AARGB1,LSB GOTO UADD43#v(i) SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG SUBWFB REMB0, F GOTO UOK43#v(i)



variable i = i + 1

endw





while i < D’24’


UADD43#v(i) ADDWF REMB2, F MOVFP BARGB1,WREG ADDWFC REMB1, F MOVFP BARGB0,WREG


AN617

ADDWFC REMB0, F


variable i = i + 1

endw


endm





while i < D’8’

RLCF AARGB0,W RLCF REMB2, F RLCF REMB1, F RLCF REMB0, F MOVFP BARGB2,WREG BTFSS AARGB0,LSB GOTO UADD33#v(i) SUBWF REMB2, F MOVFP BARGB1,WREG SUBWFB REMB1, F MOVFP BARGB0,WREG


AN617

SUBWFB REMB0, F GOTO UOK33#v(i)



variable i = i + 1

endw





while i < D’16’




variable i = i + 1

endw


AN617





while i < D’24’




variable i = i + 1

endw



AN617

endm

;**********************************************************************************************;**********************************************************************************************; ; 32/16 Bit Signed Fixed Point Divide 32/16 -> 32.16;; Input: 32 bit signed fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 16 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD3216S;; Output: 32 bit signed fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3; 16 bit fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 24+379+5 = 408 clks A > 0, B > 0; 27+379+19 = 425 clks A > 0, B < 0; 31+379+19 = 429 clks A < 0, B > 0; 34+379+5 = 418 clks A < 0, B < 0; 10 clks A = 0;; Min Timing: 24+349+5 = 378 clks A > 0, B > 0; 27+349+19 = 395 clks A > 0, B < 0; 31+349+19 = 399 clks A < 0, B > 0; 34+349+5 = 388 clks A < 0, B < 0;; PM: 34+439+18+46 = 537 DM: 10;FXD3216S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F MOVPF AARGB0,WREG IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00








AN617


C3216S SDIV3216



COMF AARGB3, F COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB3, F ADDWFC AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F


RETLW 0x00

C3216SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C3216SX3 BTFSC AARGB0,MSB ; test AARG exception GOTO C3216SX2 MOVPF AARGB2,REMB0 MOVPF AARGB3,REMB1 BCF REMB0,MSB RLCF AARGB2,F RLCF AARGB1,F RLCF AARGB0,F MOVFP AARGB0,AARGB2 MOVFP AARGB1,AARGB3 CLRF AARGB0,F CLRF AARGB1,F GOTO C3216SOKC3216SX2 CLRF AARGB3,F ; quotient = 1, remainder = 0 INCF AARGB3,F CLRF AARGB2,F CLRF AARGB1,F CLRF AARGB0,F RETLW 0x00


C3216SX4 INCF REMB1,F ; increment remainder and test for CLRF WREG,F ADDWFC REMB0,F MOVFP BARGB1,WREG ; overflow CPFSEQ REMB1


AN617

GOTO C3216SOK MOVFP BARGB0,WREG ; overflow CPFSEQ REMB0 GOTO C3216SOK CLRF REMB0,W ; if remainder overflow, clear CLRF REMB1,W INCF AARGB3,F ; remainder, increment quotient and ADDWFC AARGB2,F ADDWFC AARGB1,F ; test for overflow exception ADDWFC AARGB0,F BTFSS AARGB0,MSB GOTO C3216SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 32/16 Bit Unsigned Fixed Point Divide 32/16 -> 32.16;; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 16 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD3216U;; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1AARGB2,AARGB3; 16 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+481+2 = 485 clks;; Min Timing: 2+450+2 = 459 clks;; PM: 2+605+1 = 608 DM: 9;FXD3216U CLRF REMB0, F CLRF REMB1, F

NDIV3216

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 32/15 Bit Unsigned Fixed Point Divide 32/15 -> 32.15;; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 15 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD3215U;; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1; 15 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+386+2 = 390 clks;; Min Timing: 2+355+2 = 359 clks;; PM: 2+448+1 = 451 DM: 8;


AN617

FXD3215U CLRF REMB0, F CLRF REMB1, F

UDIV3215

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 31/15 Bit Unsigned Fixed Point Divide 31/15 -> 31.15;; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3; 15 bit unsigned fixed point divisor in BARGB0, BARGB1;; Use: CALL FXD3115U;; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1; 15 bit unsigned fixed point remainder in REMB0, REMB1;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 2+379+2 = 383 clks;; Min Timing: 2+349+2 = 353 clks;; PM: 2+439+1 = 442 DM: 8;FXD3115U CLRF REMB0, F CLRF REMB1, F

UDIV3115

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 24/24 Bit Signed Fixed Point Divide 24/24 -> 24.24;; Input: 24 bit signed fixed point dividend in AARGB0, AARGB1, AARGB2; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD2424S;; Output: 24 bit signed fixed point quotient in AARGB0, AARGB1, AARGB2; 24 bit fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 24+356+5 = 385 clks A > 0, B > 0; 29+356+19 = 404 clks A > 0, B < 0; 29+356+19 = 404 clks A < 0, B > 0; 34+356+5 = 395 clks A < 0, B < 0; 10 clks A = 0;; Min Timing: 24+329+5 = 358 clks A > 0, B > 0; 29+329+19 = 377 clks A > 0, B < 0; 29+329+19 = 377 clks A < 0, B > 0; 34+329+5 = 368 clks A < 0, B < 0;; PM: 34+444+18+44 = 540 DM: 11;FXD2424S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F


AN617

CLRF REMB2,F MOVPF AARGB0,WREG IORWF AARGB1,W IORWF AARGB2,W BTFSC _Z RETLW 0x00




COMF BARGB2, F COMF BARGB1, F COMF BARGB0, F INCF BARGB2, F ADDWFC BARGB1, F ADDWFC BARGB0, F


COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F INCF AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F


C2424S SDIV2424



COMF AARGB2, F COMF AARGB1, F COMF AARGB0, F CLRF WREG, F INCF AARGB2, F ADDWFC AARGB1, F ADDWFC AARGB0, F

COMF REMB2, F COMF REMB1, F COMF REMB0, F INCF REMB2, F ADDWFC REMB1, F ADDWFC REMB0, F

RETLW 0x00

C2424SX1 BTFSS BARGB0,MSB ; test BARG exception GOTO C2424SX3


AN617

BTFSC AARGB0,MSB ; test AARG exception GOTO C2424SX2 MOVPF AARGB0,REMB0 ; quotient = 0, remainder = AARG MOVPF AARGB1,REMB1 MOVPF AARGB2,REMB2 CLRF AARGB0,F CLRF AARGB1,F CLRF AARGB2,F GOTO C2424SOKC2424SX2 CLRF AARGB0,F ; quotient = 1, remainder = 0 CLRF AARGB1,F CLRF AARGB2,F INCF AARGB2,F RETLW 0x00


C2424SX4 INCF REMB2,F ; increment remainder and test for CLRF WREG,F ; overflow ADDWFC REMB1,F ADDWFC REMB0,F MOVFP BARGB2,WREG CPFSEQ REMB2 GOTO C2424SOK MOVFP BARGB1,WREG CPFSEQ REMB1 GOTO C2424SOK MOVFP BARGB0,WREG CPFSEQ REMB0 GOTO C2424SOK CLRF REMB0,F ; if remainder overflow, clear CLRF REMB1,F ; remainder, increment quotient and CLRF REMB2,W INCF AARGB2,F ; test for overflow exception ADDWFC AARGB1,F ADDWFC AARGB0,F BTFSS AARGB0,MSB GOTO C2424SOK BSF FPFLAGS,NAN RETLW 0xFF

;**********************************************************************************************;**********************************************************************************************;; 24/24 Bit Unsigned Fixed Point Divide 24/24 -> 24.24;; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD2424U;; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2; 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 3+435+2 = 440 clks;; Min Timing: 3+407+2 = 412 clks;


AN617

; PM: 3+573+1 = 577 DM: 10;FXD2424U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F

NDIV2424

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 24/23 Bit Unsigned Fixed Point Divide 24/23 -> 24.23;; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD2423U;; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 3+364+2 = 369 clks;; Min Timing: 3+336+2 = 341 clks;; PM: 3+456+1 = 460 DM: 9;FXD2423U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F

UDIV2423

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************; ; 23/23 Bit Unsigned Fixed Point Divide 23/23 -> 23.23;; Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2;; Use: CALL FXD2323U;; Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2;; Result: AARG, REM <-- AARG / BARG;; Max Timing: 3+356+2 = 361 clks;; Min Timing: 3+329+2 = 334 clks;; PM: 3+444+1 = 448 DM: 9;FXD2323U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F

UDIV2323


AN617

RETLW 0x00

;**********************************************************************************************;**********************************************************************************************



Information contained in this publication regarding deviceapplications and the like is intended through suggestion onlyand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.No representation or warranty is given and no liability isassumed by Microchip Technology Incorporated with respectto the accuracy or use of such information, or infringement ofpatents or other intellectual property rights arising from suchuse or otherwise. Use of Microchip’s products as critical com-ponents in life support systems is not authorized except withexpress written approval by Microchip. No licenses are con-veyed, implicitly or otherwise, under any intellectual propertyrights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,PICSTART, PRO MATE, SEEVAL and The Embedded ControlSolutions Company are registered trademarks of Microchip Tech-nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,In-Circuit Serial Programming, ICSP, ICEPIC, microPort,Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Modeand Total Endurance are trademarks of Microchip TechnologyIncorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service markof Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of theirrespective companies.

© 2002, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

• The PICmicro family meets the specifications contained in the Microchip Data Sheet.• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.


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