floyd05 jssc vol40no1 pp156-167 sigebipolartransceivercircuitsoperatingat60ghz

8/8/2019 Floyd05 JSSC Vol40no1 Pp156-167 SiGeBipolarTransceiverCircuitsOperatingAt60Ghz

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FLOYD et al.: SiGe BIPOLAR TRANSCEIVER CIRCUITS OPERATING AT 60 GHz 157

than , a high impedance or RF choke for a length equal to

, and capacitive for lengths between and . Like-

wise, open-circuited stubs are capacitive for lengths less than

and inductive for lengths between and . Since

our t-lines are implemented solely in the back-end-of-the-line,

silicon dioxide rather than the silicon substrate appears in the

t-line stack-up. Accordingly, is 600 m at 60 GHz;thus, RF chokes can easily be integrated, as can the stubs.

Matching networks are implemented in a number of our cir-

cuits using single-stub shunt tuning [28]. This network consists

of a series t-line followed by a stub connected in parallel, and

can be found in the LNA and PA schematics. An advantage

of the single-stub tuner is that it does not require prohibitively

small series capacitors (e.g., 10s of fF), since the network is

realized solely with t-lines. Operation of the tuner is best de-

scribed through an example of matching a given admittance,

to 50 . The series line first transforms to ,i.e., rotating along a constant VSWR circle on the Smith chart.

The shunt stub thengeneratesan admittanceof which adds

directly to i.e., moving along the 0.02 conductancecircle to the center of the Smith chart, resulting in a matched

condition.

Models for the microstrip transmission lines were included

in the design kit [29]. We further verified these models up to110 GHz using electromagnetic (EM) simulations and subse-

quent measurements. Note that bends and junctions were ig-

nored in our simulations, since earlier measurements showed

small discontinuities from these structures [29]. In most places,

the microstrip was implemented using top-level metal (AM)

with either metal-1 (M1) or metal-2 ground planes. The AM

layer is much thicker than the 0.34- m skin depth at 60 GHz.

Side ground shields were used in a number of places to min-imize coupling to adjacent structures. This resulted in a max-

imum characteristic impedance of 65 for the minimum line

width of 4 m. Finally, the quality factor of a short-cir-

cuited stub can be shown to be [28], which equals at

60 GHz for the AM-over-M1 microstrip ( mm and

Np/mm, where dB).

B. Simulation Methodology

The circuits were designed using a standard Cadence-based

methodology, with SpectreRF as the simulator for the LNA,

VCO, and mixer, and ADS as the simulator for the PA. In ad-

dition, EM simulations (method-of-moments using IE3D fromZeland Software) were used to simulate more complicated pas-

sive structures such as coplanar waveguide tapers or 90 hybrids

(e.g., a branch-line coupler), as well as to verify the t-line model

and to estimate via inductance.

At MMW frequencies, the difference between a device and a

parasitic can be small; therefore, accurate parasitic extraction is

crucial. For these designs, most of the circuit was covered with

a ground plane, allowing many interconnects to be accounted

for using the design-kits t-line models. Parasitic capacitance

was then extracted on local (i.e., nondistributed) nodes. Parasitic

via inductance was included wherever practical. An initial value

of 7 pH was included for the AM-to-M1 via stack; however,

subsequent measurements show that the via inductance is closerto pH.

C. Measurement Setups

All measurements were made on-chip through wafer-

probing. Standard measurement setups were employed for

network analysis, spectrum analysis, and power measure-

ments using a 65- or 110-GHz vector network analyzer, a

40-GHz spectrum analyzer with external WR-15 harmonic

mixer (5075 GHz), and a power meter with a 1.85-mm,65-GHz power sensor. Custom measurement setups were

constructed to measure noise figure (NF) and intercept points,

and to implement V-band baluns. The NF setup consists of

a WR-15 noise source with isolator, the device-under-test

with probes/cables/adaptors, an external 5964 GHz down-

converter, an LO signal generator for the downconverter, and

the noise-figure measurement system. Mixer double-sideband

NF measurements were obviously made without the external

downconverter. The external downconverter consists of an

LNA, mixer, and active frequency quadrupler, and has 5-dB

NF, 20-dB gain, and -dB image rejection. To generate

two tones for an IM3 or IM2 measurement, a 65-GHz signal

generator was used to produce one tone, while the other tone

was produced using a 20-GHz generator and a frequency

quadrupler. The tones were combined with a WR-15 directional

coupler, and then adjusted with an attenuator. Finally, 60-GHz

baluns were built using magic-Ts [28], WR-15 variable phase

shifters, and WR-15 to 1.85-mm adaptors. A simple routine

was developed to calibrate the baluns such that 180 phase shift

was obtained at the probe tips.

III. MILLIMETER-WAVE CIRCUITS

A. 60-GHz System Overview and Proof of Concept

The planned 60-GHz transceiver architecture consists of adirect-conversion receiver (RX) and a variable-IF heterodyne

transmitter (TX). Fig. 1 shows a simplified block diagram of the

components in the transceiver which have currently been im-

plemented. Direct conversion was selected for the RX to avoid

the need for integrating an image-reject filter, though a super-

heterodyne RX is also being investigated [30]. The large signal

bandwidth envisioned for high rate 60-GHz data transmissions

enables a highpass filter to be used to filter away any LO-RF

leakage effects in the direct-conversion RX. Although this

dc-blockfilter can affect the switching time between TX, RX,

and standby operating modes in the transceiver, the cutoff fre-

quency can be relatively high with wideband modulation whichminimizes the duration of the settling transient. For the TX,

direct-conversion seems ill-advised due to carrier feedthrough

in the mixer at 60 GHz, which most likely would need to be

addressed using a nulling approach to maintain desired carrier

suppression. To avoid the need for an LO-feedthrough compen-

sation based upconversion design, a two-stage superheterodyne

transmitter design is used. A variable-IF concept was chosen to

allow the use of a single TX-VCO operating at two-sevenths

the RF frequency. This results in an IF of RF/7. The two LO

frequencies for the TX are then generated by tripling or halving

the TX-VCO.

To investigate the feasibility of 60-GHz links, breadboard

versions of a superheterodyne TX and superheterodyne RXwere constructed using commercially available components


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158 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005

Fig. 1. Block diagram of four 60-GHz transceiver componentsLNA, direct downconverter, PA, and 20-GHz VCO. Dashed boxes show boundaries of each chip.

Fig. 2. Simplified schematic of 60-GHz low-noise amplifier.

[31]. The demonstrators have about 8-dB NF and 10-dBm

output power at the RX and TX antennas, respectively. Using

direct-sequence spread-spectrum based QPSK modulation,

a 200-Mb/s link was demonstrated over two meters using

omni-directional antennas even after totally blocking the

line-of-sight. In [31], a 900-Mb/s link was demonstrated with

the same breadboard system using 20-dBi horn antennas.

B. Low-Noise Amplifier

A two-stage single-ended LNA was implemented as shown

in Fig. 2. The first stage common-base amplifier was chosen for

its simple input matching, its higher gain compared to an induc-

tively degenerated common-emitter amplifier (due to the lack of

degeneration), and its high reverse isolation which decouples the

input and inter-stage matching networks. The second stage con-

sists of a common-emitter cascode amplifier with emitter degen-

eration. Each stage provides dB of gain whenbiased at 3 mAand V. Single-stub tuners are used for the input,

inter-stage, and output matching networks, with stub lengths of

m and series t-line lengths of m

for the output and inter-stage networks. MIM ac coupling capac-

itors operating beyond self-resonance are used between

the two stages and at the output. At 60 GHz, the silicon sub-

strate exhibits low impedance; thus, care was taken in circuit

design and layout to ensure adequate reverse isolation and sta-

bility. Metal-1 ground shields are used throughout the amplifier,

and substrate ties are included wherever possible. Also, metal-2

planes are used together with many MIM bypass capaci-

tors to realize a low-impedance supply. A die photograph of the

LNA is shown in Fig. 3. The die size is 0.9 0.6 mm . Dia-

mond-shaped pads are used at the input and output to reduce

the parasitic capacitance of the pad.

The measured S-parameters for the LNA are shown in Fig. 4,

together with the simulated results. The LNA is uncondition-

ally stable over 30110 GHz. At 61.5 GHz, the gain is 14.7 dBand the reverse isolation is 40 dB, when biased at 6 mA from


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Fig. 3. Die photograph of 60-GHz low-noise amplifier. Die size is 0.9 2 0.6 mm .

Fig. 4. Measured and simulated S-parameters of the LNA forV = 1 : 8

V,I = 6

mA.

a 1.8-V supply. The input return loss is 6 dB, while the output

return loss is 17 dB. Model-to-hardware correlation is excellent

for , and . The miss in , though, was unexpected,

particularly given that the output match was right on target. An

alternate version of the LNA which had 50- coplanar wave-

guide (CPW) tapers at the input and output [27] showed

and better than 12 dB, as expected. These CPW tapers

absorb pad parasitics, providing a 50- impedance directly at

the microstrip ports of the LNA. Since the CPW-LNA input

match was on target, we know that the input matching network

and transistor have been correctly modeled. This then leaves

the bondpad as the source of mismatch. Simulations reveal that

when the bondpad capacitance is significantly reduced, simu-lated and measured agree very well, while the other three

S-parameters still agree. This is shown in Fig. 4 by the curve

labeled sim. w/o pad in the plot. Work is ongoing to char-

acterize the bondpad using on-chip TRL (Thru-Reflect-Line)

calibration structures.

Fig. 5 shows the measured and simulated NF of the LNA (with

pads) at 6 mA and 1.8 V. No on-chip loss has been de-embedded

from this result. Note that a better-calibrated WR-15 noise

source over that used in [27] resulted in less ripple across

the band, but slightly higher NF values. The measured NF is

4.5 dB at 61.5 GHz, while the simulated NF is 4.6 dB. The

taper-LNA also has a NF of 4.5 dB when the insertion loss of

the tapers is de-embedded. The simulated minimum NF of the

LNA is 4.2 dB, while the of a single transistor is 3.1 dB.From simulation, the input common-base device contributes


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Fig. 5. Measured and simulated noise figure (NF) of the LNA for V = 1 : 8V,

I = 6

mA.

80% of the added noise (split nearly equally between collectorshot noise and thermal noise from base resistance), while the

second-stage cascode contributes 10%. The remaining 10%

comes from other assorted sources.

Biasing of the two stages in the LNA is independent and

adjustable. By changing the second-stage current, adjustable

gain is obtained while NF remains relatively constant. Specif-

ically, with the first-stage current held constant at 3 mA and

the second-stage current adjusted between 0.5 and 5 mA, mea-

surements show that the gain varies by 10 dB while the NF re-

mains below 5.5 dB and remains below 9 dB. The gain

and NF of the LNA were measured across multiple dies and

over temperature. Die-to-die gain and NF variations of dBand dB, respectively, were observed for 23 LNA sam-

ples. Fig. 6 shows the measured gain, NF, and current of the

taper-LNA over a 5 C95 C temperature range. With a con-

stant voltage applied to the current mirror, the resultant bias

currents increase faster than proportional-to-absolute-tempera-

ture (PTAT). The measured gain varies a total 1.5 dB while NF

varies 1 dB. Finally, Fig. 7 shows the measured 1-dB compres-

sion point and IIP3 (at 100-MHz tone spacing) of the

LNA, revealing a 20-dBm and 8.5-dBm IIP3 for

both LNA versions when biased at 6 mA and 1.8 V. Simulations

predict a 22-dBm iCP and 12-dBm IIP3.

C. Downconverter

The architecture of the direct-conversion downconverter is

shown in Fig. 1. Direct conversion is often used at microwave

frequencies because it facilitates high integration, eliminating

image-reject and IF filters [32]. However, one of the issues in a

direct-conversion receiver is leakage of the local oscillator (LO)

signal into the RF signal path, which results in dc offsets at the

mixer output. LO leakage becomes a greater issue at 60 GHz

because of coupling through the silicon substrate. In the present

design, coupling was controlled by covering most of the sub-

strate with a ground plane on the first metal level (M1), placing

substrate contacts every 5 m.

Referring to Fig. 1, LNA2 has 12 dB of gain and serves asan active balun, providing a differential RF signal to the two

Fig. 6. Measured gain, NF, and current of the taper-LNA versus temperature.

Fig. 7. Two-tone IP3 measurement of the LNA.

double-balanced Gilbert-cell mixers, which have 4 dB of gain.

The mixers are driven with quadrature LO signals from a dif-

ferential branch-line directional coupler. A pilot signal comes

on-chip at a third of the desired LO frequency, and a frequency

tripler generates the final LO signal to drive the branch-line cou-

pler. This architecture minimizes LO-RF coupling through the

probes and pads, and the inclusion of the frequency tripler will

ultimately allow the frequency synthesizer to run at one-third ofthe LO frequency.

LNA2 consists of a cascoded differential pair with inductive

load and degeneration, as shown in Fig. 8. The four inductors are

realized with ac short-circuited stubs, realizing an effective load

inductance of 80 pH and degeneration of 60 pH. Inductive de-

generation creates a 50- real part to the input impedance, and

the input match is completed by series inductor . is made

from a straight segment of top-metal (AM) over the substrate,

and losses are reduced by cross-hatching the substrate under

with oxide-filled trenches. LNA2 draws 8 mA from 2.7 V.

The mixers are conventional resistively degenerated double-

balanced Gilbert cells, as shown in Fig. 9. Each mixer and asso-

ciated LO buffer together draw 12 mA. Double emitter followersare used to provide a low-impedance LO signal to the mixer


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Fig. 9. Simplified schematic of 60-GHz double-balanced Gilbert-cell.

Fig. 8. Simplified schematic of LNA2 used in downconverter.

switches and to isolate the load capacitance of the switches from

the branch-line coupler. The mixer load resistors are 300 , so

the mixers are followed by unity-gain buffers to provide 100-

differential baseband signals to drive off-chip. The baseband

3-dB bandwidth is 1.5 GHz. The buffers, which draw 26 mA

each, are for test only, since an analog baseband is planned tobe integrated with the downconverter.

The frequency tripler block in Fig. 10 consists of two stages:

the actual tripler, and an LO amplifier following the tripler and

preceding the branch-line coupler. A 0-dBm, 20-GHz differen-

tial LO pilot signal is applied to the tripler (a cascoded differen-

tial amplifier with a tuned load), which produces third-harmonic

distortion. The LO amplifier has high input-impedance emitter

followers so that isolated, high-Q (510) tuned loads are pro-

duced at the collectors of . This provides gain for the third

harmonic around 60 GHz while attenuating the 20-GHz funda-

mental. The LO amplifier also has a tuned load to further am-

plify the third harmonic and reject the fundamental; it supplies

2 dBm (simulated) with the fundamental dB down. Com-ponents - and - match the input impedance of the

tripler to 100- differential at 20 GHz. The tripler alone draws

4 mA and LO amplifier 16 mA.

Fig. 11 is a die photograph of the direct downconverter, which

has a die size of 1.9 1.6 mm . The branch-line coupler, folded

into the shape of a peanut to reduce its size, is located in the

center. The measured gain and NF of the downconverter are

shown in Fig. 12. All measurements of conversion gain, NF,

, and linearity refer to the unbalanced 50- input of LNA2.

Measured cable and probe losses in the test setup have been

de-embedded from the measurements, but no on-chip losses

(such as those due to the pads) have been de-embedded. Data

was taken from a wafer on which transistors had a peakof 290 GHz, whereas simulations were done with models that

correspond to an of 240 GHz. Therefore, measured per-

formance is sometimes better than simulated performance. At

60 GHz, gain is 18.6 dB and NF is 13.3 dB, while simulated

gain is 17.1 dB and NF is 14.9 dB. Some samples, such as chip

F6 in Fig. 12, show a dip in conversion gain at 64 GHz, which

we believe is due to interaction between the LO amplifier and

branch-line coupler. Measured is 17 dBm, with a cor-

responding IIP3 of 7 dBm and IIP2 in the range of 9 to 20

dBm, depending on the sample. Average IIP2 for 4 samples

was 13 dBm. IIP3 and IIP2 were measured with a 19-GHz

LO-pilot signal applied to the frequency tripler and RF input

tones at 57.1 and 57.12 GHz. is 12 dB or better from 57

to 65 GHz.

Fig. 13 shows LO leakage measured at LNA2s input with a

spectrum analyzer; it varies little from chip-to-chip. The leakage

generally rises with frequency and reaches 50 dBm at 60 GHz,

implying approximately 50 dB of isolation. Mixer offset volt-

ages are another measure of LO-RF isolation. Measured I and

Q offsets on eight chips have an average offset-voltage magni-

tude of 56 mV (49 mV for I-channel, 64 mV for Q-channel), in-

cluding 2 chips with offsets mV. The remaining six chips

had an average offset of 21 mV. These offsets are 100 times

higher than we measured on an earlier 2.1-GHz design [ 32],

but still indicate that direct conversion is practical for a 60-GHzWPAN, given 650-mV mixer output swing and ac coupling.


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Fig. 10. Simplified schematic of frequency tripler block.

Fig. 11. Die photo of the direct downconverter. Die size is 1.92

1.65 mm .

AC coupling at the mixer outputs can prevent the offsets from

unbalancing subsequent stages and will have little impact on

a wideband WPAN baseband signal. The offsets do consume

some of the mixers dynamic range and decrease IIP2, but lin-

earity requirements for a 60-GHz WPAN are minimal, due to a

lack of adjacent-channel interference.

Fig. 14 shows the variation in gain and NF over tempera-

ture with bias currents held PTAT by adjusting an off-chip bias

supply. The gain is held fairly constant up to 60 C, but then

falls off rapidly. Simulations reveal that the LO amplifier which

drives the branch-line coupler has reduced output above 60 C,

and the mixer conversion gain drops with the reduced LO drive.

Fig. 14 also shows measured NF rising from 12.5 to 16.5 dB as

temperature increases from 5 to 80 C.

Figs. 15 and 16 reveal the performance of the branch-line cou-

pler. Ideally, the I and Q channels would have the same gain and

be exactly 90 out of phase. But the outputs of the branch-line

coupler vary in amplitude and phase over the frequency range,

and thus the I and Q channel mixer outputs also vary. Fig. 15shows that the coupler produces LO outputs of roughly equal

Fig. 12. Measured conversion gain and NF for the direct downconverter.

Fig. 13. Measured local oscillator leakage to LNA2 RF input versusfrequency.

amplitude from 54 to 62 GHz, and the simulations match the

measurements quite closely. Fig. 16 shows that the simulated

phase difference between I and Q channels is within of90 from 44 to 66 GHz, but the measured results show a phase


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Fig. 14. Measured and simulation conversion gain and NF of downconverterversus temperature with PTAT bias.

difference of 87 to 105 from 57 to 64 GHz. These results in-dicate that our simulation model for the coupler is not as accu-

rate as we would like. However, our system-level simulations

indicate that even without improvement, the measured quadra-

ture accuracy is still adequate for a 60-GHz WPAN, since it has

a small impact on the bit-error rate of the demodulated signal.

Smulders [25] discusses some of the modulation schemes that

might be used in a 60-GHz WPAN.

D. Power Amplifier

The PA is a two-stage class-AB balanced amplifier, designed

to directly feed a differential antenna, eliminating any need

for an on-chip balun. The balanced amplifier is implementedwith two unbalanced amplifiers in parallel. Each unbalanced

amplifier, shown in Fig. 17, consists of two common-emitter

amplifiers, with input, inter-stage, and output matching net-

works. Single open-circuited stub tuning networks are used at

the input and output, while the inter-stage match uses a MIM

capacitor instead of a stub. Quarter-wavelength RF chokes

supply to each stage. Each of the four power transistors

has a separate temperature-compensated bias circuit [33], which

is located nearby for good thermal matching. Two major prob-

lems associated with the design of on-chip power amplifiers in

an advanced SiGe bipolar technology are the low breakdown

voltages and the high loss of the on-chip impedance transfor-mation. In order to operate the transistor at higher voltages,

each bias circuit provides to the power transistors

base terminal. Thus, the NPN is limited by operation

rather than , where is slightly above 4 V for

equal to 300 . Fig. 18 shows a die photograph of the

PA, which has a size of 2.1 0.8 mm . Clearly visible left

and right are the two identical unbalanced amplifiers.

The PA was biased at 150 mA from a 2.5-V supply. Fig. 19

shows the measured transducer power gain and output power

versus input power for the balanced amplifier. At 61.5 GHz,

the gain and are 10.8 dB and 11.2 dBm, respectively.

The saturated output power level is 16.2 dBmmeasured for

an unbalanced amplifier to which 3 dB is added. The max-imum power-added efficiency (PAE) is 4.3%. Fig. 20 shows

Fig. 15. Measured I-channel to Q-channel gain balance versus frequency.

Fig. 16. Measured I-channel to Q-channel phase difference versus frequency.

the measured gain and output power versus tempera-

ture, with constant-current biasing. Across 5 C135 C, the gain

and each drop around 4 dB, yet the amplifier still delivers

9-dBm output power at 100 C. Input and output return losses

at 61.5 GHz are 6.2 and 8.9 dB, respectively, with respect to a

100- differential impedance.

E. Voltage-Controlled Oscillators

VCOs have been implemented at both 20 GHz, for usewith the frequency tripler, and at 60 GHz, for use as a fun-

damental-frequency oscillator. A fully differential Colpitts

topology is used at both frequencies. Fig. 21 shows a schematic

of the 60-GHz VCO. The hallmark capacitive divider of the

Colpitts architecture is formed by the base-to-emitter capaci-

tance of and the coupling capacitor between both sides

of the VCO. Microstrip transmission lines are used to form a

resonant circuit, connecting the bases to a current mirror and

realizing an inductance of 40 pH. Frequency tuning is provided

by junction varactors located in the base. No explicit output

buffers are includedthe output is obtained directly from the

collector, which has a microstrip load. The 20-GHz VCO is

identical in architecture except that a slab inductor is used inplace of the base microstrip, a spiral inductor is used in place


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Fig. 17. Simplified schematic of unbalanced amplifier used for power amplifier.

Fig. 18. Die photograph of the PA. Die size is 2.12

0.8 mm .

Fig. 19. Measured transducer power gain andoutputpowerat 61.5 GHzversus

input power for the balanced PA.

of the collector microstrip, and a MIM capacitor is added

between the base and emitter. Note that an output buffer would

be required to drive an off-chip load, and the buffer would

likely degrade the phase noise [17]. The buffer is required

since unmatched external loads cause the two halves of the

VCO to oscillate at slightly different frequencies, resulting in a

discontinuous and hysteretic tuning response.

The 60-GHz VCO consumes 8 mA from 3 V. The 60-GHz

VCO was designed to operate between 60 and 63 GHz, usinga parasitic via inductance value of 7 pH. Measurements show

Fig. 20. Measured gain and output power ( P ) of the PA versustemperature.

the tuning range to instead be 65.8 to 67.9 GHz (3.1%), for

from 0 to 3 V. This is consistent with a via inductance

value of 4 pH, which gives a 64.3 to 67.7 GHz simulated tuning

range. The differential output power, measured with a power

meter, is 8 dBm across the band. The measured phase noise

at the tuning range edges is 98 dBc/Hz at 1-MHz offset for

50- loads. This improves to 104 to 102 dBc/Hz (shown in

Fig. 22) in the middle of the tuning range. The correspondingfigure of merit for the VCO [34] is between 181 and 187 dB.


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Fig. 21. Simplified schematic of the 60-GHz VCO.

Fig. 22. Output spectrum of 60-GHz VCO, showing phase noise at 1-MHzoffset.

The 20-GHz VCO can be tuned from 21.2 to 22.4 GHz

(4.5%), and the differential output power is 5.5 dBm. Powerconsumption is 9 mA from 3 V. Phase noise at 1-MHz offset is

between 109 and 116 dBc/Hz. Note that this measurement

helps to verify the 67-GHz phase noise measurements, since

adjusting for frequency, we should see at least a or

9.5-dB improvement. More than this improvement is seen

since varactor Q should be three times larger at 22 GHz than at

67 GHz.

IV. SUMMARY AND CONCLUSIONS

This paper has described key RF front-end components

in silicon for a 60-GHz transceiver, including an LNA, a di-

rect-downconverter, a PA, and VCOs. The performance of thesecircuits is summarized in Table I. Excellent model-to-hardware

correlation has been achieved for each circuit. At 61.5 GHz, the

LNA achieves 4.5-dB NF, 14.7-dB gain, and 10.8-mW power

dissipation, and is the first known demonstration of a silicon

LNA at V-band. In comparison, III-V LNAs have typically

achieved NFs in the 2 to 4 dB range, gains greater than or equal

to 20 dB, and power dissipations between 20 and 160 mW

[1][5]. Our silicon V-band LNA achieves similar NF to GaAs

at lower power consumption. The III-V LNAs, though, do

achieve higher compression points than this SiGe LNA.

At 61.5 GHz, the downconverter achieves 16-dB gain,

14.8-dB NF, and 150-mW power dissipation. Once again, this

is the first known demonstration of active mixers in siliconat V-band. In comparison, III-V mixers are often passive or

diode-based [35], requiring LO-drive levels of 10 to 20 dBm

and thereby consuming a large amount of power in the LO

amplifiers (e.g., 1 W in [3]). Thus, the silicon downconverter

described here represents a very low power consumption.

Also, the downconverter block contains 80 transistors and 43

inductors or transmission lines, which is a very high level of

integration at this frequency.

The PA provides a 10.8-dB gain, a 11.2-dBm 1-dB com-

pression point, and a maximum PAE of 4.3%. The saturated

output power is 16 dBm. This is the second known demon-

stration of a silicon PA at these frequencies, where Li [21]has demonstrated a 14-dBm silicon amplifier at 77 GHz with

% efficiency. In comparison, III-V PAs for V-band deliver

2330 dBm of power with 815 dB of gain and 20%40% of

power-added efficiency [6][9]. Finally, 60- and 20-GHz VCOs

have been demonstrated with very low phase noise, albeit with

narrow tuning ranges. The 60-GHz VCO achieves an excellent

phase noise at 1-MHz offset between 98 and 104 dBc/Hz,

which is comparable to the performance achieved in [17].

Based on these results, a fully integrated transceiver with

less than 6-dB NF and greater than 11-dBm output power

should be possible. Specifically, cascading the LNA and down-

converter mathematically results in a receiver front-end with a

5.8-dB NF, 31-dBgain, 22-dBm IIP3, and 32-dBm .The utility of such hardware has already been demonstrated in


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TABLE ISUMMARY OF MEASURED PERFORMANCE OF LNA, DOWNCONVERTER , PA, AND VCO

Section III-A and in [31], where discrete III-V based 60-GHz

radios with 8-dB NF and 10-dBm output power (both an-

tenna-referred) were used to implement a 200-Mb/s omnidi-

rectional link and a 900-Mb/s directional link in our lab. This

hardware, then, is the first step toward the implementation

of a fully integrated 60-GHz transceiver in SiGe technology.

Clearly, it is in the integration level where silicon can trulystand out over III-V implementations. SiGes high level of in-

tegration and potentially low power consumption of the MMW

downconverter/upconverter could open the door to new MMW

applications and market opportunities, including high data-rate

wireless personal-area networks.

ACKNOWLEDGMENT

The authors thank IBMs SiGe Technology group for

chip fabrication. Additionally, the authors thank D. Beisser,

D. Goren, D. Friedman, M. Soyuer, and M. Oprysko of IBM

Research, and Y. Tretiakov, and G. Freeman of IBM Micro-electronics for their contributions.

REFERENCES

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Brian A. Floyd (S98M01) received the B.S. (withhighest honors), M.Eng., and Ph.D. degrees in elec-trical and computer engineering from the Universityof Florida, Gainesville, in 1996, 1998, and 2001,

respectively. While at the University of Florida,he held the Intersil/SRC Graduate Fellowship and

the Pittman Fellowship. His doctoral research onwireless interconnects was a Phase One winner anda Phase Two first runnerup in the 2000 SRC CopperDesign Contest.

In 2001,he joinedIBM and ispresently a ResearchStaff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY,

engaged in millimeter-wave, RF, and high-speed wired integrated circuit design.

ScottK. Reynolds received the B.S.E.E. degreefrom

the University of Michigan in 1983, the M.S.E.E. de-gree from Stanford University in 1984, and the Ph.D.degree in electrical engineering, also from Stanford

in 1987.He joined IBM in 1988 and is presently a Re-

search Staff Member at the IBM T. J. WatsonResearch Center in Yorktown Heights, New York.His job responsibilities have involved analog andmixed-signal circuit design for high speed commu-nication systems, including optical, wired, and RF

wireless systems, and disk drive channels. Currently, he is engaged primarilyin development of RFICs for high data rate wireless communication links.

Ullrich R. Pfeiffer received the diploma degree inphysicsand thePh.D. degreein physicsfrom theUni-versity of Heidelberg, Germany, in 1996 and 1999,respectively.

In 1997, he worked as a Research Fellow at theRutherford Appleton Laboratory, Oxfordshire, U.K.,where he developed high-speed multi-chip modules.In 2000, his research was based on high-integrated

real-time electronics for a particle physics exper-iment at the European Organization for NuclearResearch (CERN), Switzerland. He joined IBM

in 2001 and is presently a Research Staff Member at the IBM T. J. WatsonResearch Center. His research involves RF circuit design, high-power amplifierdesign at 60 GHz and 77 GHz, high-frequency modeling and packaging for60-GHz and 3G cellular systems.

Thomas Zwick (M00) received the Dipl.-Ing.(M.S.E.E.) and the Dr.-Ing. (Ph.D.E.E.) degreesfrom the Universitt Karlsruhe (TH), Germany in1994 and 1999, respectively.

From 1994 to 2001 he was a Research Assis-tant at the Institut fr Hchstfrequenztechnik und

Elektronik (IHE) at the Universitt Karlsruhe (TH),Germany. Since February 2001, he has been withthe IBM T. J. Watson Research Center, YorktownHeights, NY. His research topics include wavepropagation, stochastic channel modeling, channel

measurement techniques, material measurements, microwave techniques,wireless communication system design and millimeter wave antenna design.He participated as an expert in the European COST231 Evolution of Land

Mobile Radio (Including Personal) Communications and COST259 Wireless

Flexible Personalized Communications. For the Carl Cranz Series for ScientificEducation, he served as a lecturer for Wave Propagation.

Dr. Zwick received the Best Paper Award from the International Symposiumon Spread Spectrum Technology and Applications (ISSSTA) 1998.

Troy Beukema received the B.S.E.E. and M.S.E.E. degrees from MichiganTechnological University in 1984 and 1988, respectively.

From 1984 to 1988, he was an R&D Engineer with Hewlett-Packard in thearea of communications test equipment. He joined Motorola in 1989 and con-tributed to development of digital cellular wireless systems with a focus on dig-ital signal processing algorithm design and implementation. In 1996, he joinedIBM, where he is presentlya research staff memberinvolved in communicationssystem research. His research interests include communication link system de-

sign and simulation, with an emphasis on signal processing algorithms for wire-less and high-speed wireline channels.

Brian Gaucher performed his undergraduate workat the Univesity of Massachusetts and graduate work

at Northeastern University.From 1982 to 1983, he worked at Alpha Industries

R&D Laboratory designing microwave GaAsFET

amplifiers, switches detectors limiters, filters, andsupercomponents. In 1984, he joined GTE Commu-

nication Systems Division, working in the area ofresearch and development of secure spread spectrumcommunication and radar systems for the military,

across the 900 MHz to 60 GHz frequency bands. In1993, he joined IBM and is presently a Research Staff Member at the IBMT. J. Watson Research Center, Yorktown Heights, NY, where he manages acommunication system design and characterization group. His present researchinterests include 60 GHz Gb/s wireless communication design and biomedicalapplications of wireless technology. His group has helped more than fiveproducts come to market.

Dr. Gaucher is an IBM master inventor and holds two outstanding technicalachievement awards and one corporate award.

floyd05 jssc vol40no1 pp156-167 sigebipolartransceivercircuitsoperatingat60ghz

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