fm receiver
TRANSCRIPT
CHAPTER 1: INTRODUCTION TO THE PROJECT
The FM (Frequency Modulation) is one of very famous wireless communication
method.Carrier frequency is modulated according to the strength of analog signal such
as Voice. In this design project, we are going to design the all digital FM receiver
circuit assuming the Frequency Modulated signal is converted to series of numerical
values (digital signal) via Analog to Digital Conversion (ADC) circuit.The core of the
target design will be digital phase locked loop circuit, which generates sinusoidal wave
synchronizing to the input FM wave. The requirements of the design is to write HDL
(VHDL) and to synthesize digital circuits using Synopsys design analyzer.
.
` Figure 1 System Diagram
Figure1 shows the Frequency modulation and demodulation system. Signal generator
(SigGen) generates the transmitting signal. In the figure 1, although only 1 or -1 are
assumed for SigGen output, other value such as 0.5 is also acceptable. VCO represents
Voltage Controlled Oscillator, which generates sinusoidal wave frequency-modulated
by the SigGen output. ADC is Analog to Digital Converter, which converts the analog
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FM signal to descrete digitaized signals. When the output of SigGen is -1, the VCO
output frequency is relatively low, and when the SigGen output is 1, the VCO output
frequency is relatively high. In our design target, we assume the ADC output bit width
is 8 bit. Then 28=256 different values can be expressed at the output of ADC. The FM
Receiver gets the 8 bit signal every clock cycle and outputs the demodulated output.
Phase Locked Loop (PLL)
The figure 2 shows the serially connnected PLL cirucit and Low Pass Filter circuit.
This simple circuit configuration realizes the our target FM Receiver circuit.
Figure 2 PLL and LPF
NCO is similar oscillator as VCO. although VCO is analog circuit, NCO is digital
circuit.The output sinusoidal frequency is controlled by digital input value. The the
oscillator iscalled as Numerical Controlled Oscillator (NCO). As shown in figure 1,
since the PLLincludes the feedback loop, NCO outputs the same frequency.
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Figure 3 NCO
In our target system, let's assume that system clock frequency is 16MHz =
16,000,000MHz and center NCO operating frequency is 1MHz = 1,000,000MHz.
Then as shown in the figure 3, there are 16 sampling points in 1 cycle of 1MHz
sinusoidal wave.
The NCO generates exactly 1 cycle of sinusoidal wave when input value = 0. Then the
offset value is 1/16. Every clock cycle, the D flipflop accumulates the offset value.
Then, in 16 cycles, accumulated value will increase by 1.0. The accumulator output is
multiplied by 2pai, then cosine value is extracted from the cos ROM. When the input
value is more than 0, the accumulation speed gets higher. Then in less than 16 cycles,
the accumulator increases by 1.0. This corresponds to higher frequency than 1.0MHz
is generated. Vice versa, when the input value is less than 0, lower frequency than
1.0MHz is generated. Consequently, the NCO operating frequency will be controlled
by the input value with center frequency of 1.0MHz.
Here, the system clock frequency and the sampling frequency are 16MHz =
16,000,000Hz. FM modulation is +- 10KHz at center of 1MHz=1,000,000Hz. The
modulation is just +-10% of the 1MHz carrier frequency, then it is difficult to identify
the FM modulation in the figure 5 simulation waveform. In the simulation, we have
assumed the sampling frequency = 16MHz. However, you can scale the sampling
frequency as you wish. Be sure not to forget to scale the carrier frequency. The first
row shows the sending data is repeating 1 and -1. The second row show the FM
modulated waveform according to the sending data. The third row is NCO output and
the fourth row is Phase comparator, that is, multiplier output. The fifth row and the
sixth row are the accumulator output and the demodulated output. In this view, all
sampled signal, which are discrete, are connected in line. At the initial simulation
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phase, the demodulated output overshoots since the phase synchronization is in
convergence phase.
BLOCK DIAGRAM OF SYSTEM:
Figure 4 System Diagram
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CHAPTER 2 : INTRODUCTION TO VHDL
2.1 DESIGN APPROACH
Digital design methodologies can be broadly classified into two approaches
1. Top down approach
2. Bottom up approach
TOP DOWN APPROACH
In this design flow, the top level system is first modelled for functionality and
performance using a high level behavioural description. Each major component is then
modelled at the behavioural level and the design is simulated again for functionality
and performance each major component is modelled at he gate level and the design is
simulated again for timing, functionality and performance.
SOME MAJOR ADVANTAGES OF THIS APPROACH ARE
1. System analysis is done at the beginning of the design cycle. Therefore, quality
& performance trade off decision can be made at the earliest stage.
2. Strong connection between system level engineering and implementation level
engineering.
3. As this approach enables a number of engineers to work on different parts of
the design at the same time, it facilitates concurrent engineering
4. Typically, fewer design iteration are required. Hence time to market is reduced.
5. Increasingly large design becomes easy to handle.
TWO MAJOR DISADVANTAGES OF THIS APPROACH ARE
1. There is a learning curve involved because it is not as traditional as bottom up
design
2. Requires software and hardware capable of performing mixed level simulation.
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BOTTOM UP APPROACH
In this approach the lowest level component or the design are first modelled at gate
level. Form these, the intermediate level component are formed ant than the complete
design modelled and tested. In such a design procedure, design timings, performance
and testability is analyzed at the last step. This design methodology closely follows the
step involved in bread boarding a system using hardware only and hence this has been
the traditional method used by designers.
ADVANTAGES
1. Many designers already have the software required to design the way
2. Designers are traditionally trained to work this way
3. Less time is needed to implement the individual pieces of the circuit
DISADVANTAGES
1. Typically, there is a poor functional view of the entire system
2. More time is needed to implement the entire system, because the individual
pieces have to be tested first. In other words, designing several stages in
parallel is more difficult with this approach.
2.2 WHY USE A HARDWARE DESCRIPTION LANGUAGE
As the complexity of the system increase, it becomes difficult to design directly on
hardware. This is the most basic reason, which has lead to the increasing use of
HDLs, exploring different design options is easier & cheaper , as only the HDL
description is to be changed which is much easier than reconfiguring the prototype.
Finally HDLs are more economical in his sense than design based on as HDL takes
much less time & cost as compared to hardware prototyping. Today a very important
feature of any successful product is the time taken by the product from the workbench
to the market. Using a HDL helps in significant reduction of this time.
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1981
1987
1985
1993
Publication of revised VHD
L standard
Publication of first VHD
L standard
VHDL
VHDL is a programming language that has been designed and optimized for
describing the behavior of digital systems. VHDL stands for VHSIC Hardware
Description Language, and VHSIC, in turn, stands for Very High Speed Integrated
Circuit, It was developed by the Institute of Electrical and Electronics Engineers
(IEEE) as Standard VHDL-1076. It VHDL was developed in the early 1980s as a
spin-off of a high-speed integrated circuit research project funded by the U.S.
Department of Defense.
2.3 HISTORY OF VHDL
Fig. 3.1 shows the history of evolution of VHDL which can be stated as-
1981 Initiated by US DOD to address hardware life-cycle crisis
1983-85 Development of baseline language by Intermetrics, IBM and TI
1986 - All rights transferred to IEEE
1987 Publication of IEEE Standard
1994 Revised standard (named VHDL 1076-1993)
FIG 5. HISTORY OF VHDL
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ARCHITECTURE(Functionality)
ENTITY(Interface description)
CONFIGURATION(Connection betweenEntity and architecture)
PACKAGEDECLARATION
PACKAGE BODY(Often used functions, constants, components…)
2.4 ORGANIZATION OF VHDL DESIGN
A VHDL program consists of one or more “Design Units”. A Design unit is a
smallest compliable piece of code. A statement must be enclosed inside a design unit
to get compiled. Fig. shows all the design units used to organize a VHDL program.
Fig6: Organization of a VHDL model
There are five types of design units namely entity, architecture, configuration,
package declaration and package body. One can have a meaningful program with
entity and architecture units only. The other units are used for additional information.
A) Entity
Each component or subsystem that we want to design is identified by its entity name.
The entity unit defines the component’s name and its port signals. The syntax of
entity declaration is:
Entity ENTITY_NAME is
Port (SIGNAL_NAME: mode DATA_TYPE, …more signals);
End ENTITY_NAME;
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PORT MODES:
An in port can be read but not updated within the module, carrying information into
the module. (An in port cannot appear on the left hand side of a signal assignment.)
An out port can be updated but not read within the module, carrying information out of
the module. (An out port cannot appear on the right hand side of a signal assignment.)
A buffer port likewise carries information out of a module, but can be both updated
and read within the module.
An inout port is bidirectional and can be both read and updated, with multiple update
sources possible.
Example
Entity ANDGATE is
Port (in1, in2: in BIT; output: out BIT);
End ANDGATE;
B) Architecture
Architecture defines one particular implementation of a design unit, at some desired
level of abstraction. An architecture body describes the internal view of an entity. It
describes the functionality or the structure of the entity.
Syntax:
Architecture arch_name of entity_name is
... Declarations...
Begin
... Concurrent statements...
End
Declarations include data types, constants, signals, files, components, attributes,
subprograms, and other information to be used in the implementation description.
Concurrent statements describe a design unit at one or more levels of modelling
abstraction, including dataflow, structure, and/or behaviour.
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BEHAVIOURAL DESCRIPTIONS
The highest level of abstraction supported in VHDL is called the behavioural level of
abstraction. When creating a behavioural description of a circuit, we will describe our
circuit in terms of its operation over time. The concept of time is the critical distinction
between behavioural descriptions of circuits and lower-level descriptions (specifically
descriptions created at the dataflow level of abstraction).
PROCESS STATEMENT
Behavioural descriptions are supported with the process statement. The process
statement can appear in the body of an architecture declaration just as the signal
assignment statement does. The contents of the process statement can include
sequential statements like those found in software programming languages. These
statements are used to compute the outputs of the process from its inputs. Sequential
statements are often more powerful, but sometimes have no direct correspondence to a
hardware implementation. The process statement can also contain signal assignments
in order to specify the outputs of the process. A group of processes will be executed
concurrently since the process is a concurrent statement, it usually contains sequential
statements. We can also group a block of concurrent statements together and specify
when they are to be executed.
DATA FLOW DESCRIPTION
In the dataflow level of abstraction, we describe our circuit in terms of how data
moves through the system. At the heart of most digital systems today are registers, so
in the dataflow level of abstraction we describe how information is passed between
registers in the circuit. The dataflow level of abstraction is often called register transfer
logic, or RTL. This level of abstraction is an intermediate level that allows the
drudgery of combinational logic to be simplified while the more important parts of the
circuit, the registers, are more completely specified.
There are some drawbacks to using a dataflow method of design in VHDL. First, there
are no built-in registers in VHDL; the language was designed to be general-purpose,
and the emphasis was placed by VHDL’s designers on its behavioural aspects. If we
are going to write VHDL at the dataflow level of abstraction, we must first create
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behavioural descriptions of the register elements we will be using in our design. These
elements must be provided in the form of components (using VHDL’s hierarchy
features) or in the form of subprograms (functions or procedures).
STRUCTURAL DESCRIPTION
The third level of abstraction, structure, is used to describe a circuit in terms of its
components. Structure can be used to create a very low-level description of a circuit
(such as a transistor-level description) or a very high-level description (such as a block
diagram).
In a gate-level description of a circuit, for example, components such as basic logic
gates and flip-flops might be connected in some logical structure to create the circuit.
This is what is often called a netlist. For a higher-level circuit—one in which the
components being connected are larger functional blocks—structure might simply be
used to segment the design description into manageable parts.
Structure-level VHDL features, such as components and configurations, are very
useful for managing complexity. The use of components can dramatically improve
your ability to re-use elements of your designs, and they can make it possible to work
using a top-down design approach.
There can be any number of architecture units for a single entity unit. All the
architecture names referring to a single entity must be distinct. Usually the architecture
name denotes its description style.
C) Configuration
The component declaration in a structural description only defines a socket where
some component will be plugged in. If there exits a component by the same name in
the design library, then it is automatically chosen to be plugged in.
D) Package declaration
The Package and Package body units are used for declaring a set of useful type
declarations, functions and procedures. Other programs can easily use the package
contents with the “use” statement.
E) Package body
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The package declaration gives only the prototype declarations of the functions. The
implementation is provided in the Package body.
The entity, configuration and package declarations are called “Primary design units”
because they can be compiled independently. Architecture and Package bodies are
called “Secondary design units” as they can be compiled only with reference to a
primary design unit.
2.5 LIBRARIES
A set of utility packages can be put inside a library. Library is basically a subdirectory
in the host environment. The primary library for standard VHDL design is the IEEE
library. Within the IEEE Design Automation Standards Committee (DASC), various
committees have developed libraries, packages and extensions to standard VHDL.
Some of these are listed below:
IEEE Std 1076 Standard VHDL Language
IEEE Std 1076.1 Standard VHDL Analog and Mixed-Signal Extensions
(VHDL-AMS)
IEEE Std 1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions –
Packages for Multiple Energy Domain Support
IEEE Std 1076.4 Standard VITAL ASIC (Application Specific Integrated
Circuit) Modelling Specification (VITAL)
IEEE Std 1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis
(SIWG)
IEEE Std 1076.2 IEEE Standard VHDL Mathematical Packages (math)
IEEE Std 1076.3 Standard VHDL Synthesis Packages (vhdlsynth)
IEEE Std 1164 Standard Multivalue Logic System for VHDL Model
Interoperability (Std_logic_1164)
STD_LOGIC LIBRARIES
There are a number of std_logic libraries available in the IEEE library and these are:
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std_logic_1164
std_logic_arith
std_logic_unsigned
std_logic_signed
std_logic_entities
std_logic_components
std_logic_misc
std_logic_textio
The std_logic_1164 package is particularly important for most digital design,
especially for Field Programmable Gate Array (FPGA), because it defines the standard
logic types used by ALL the commercially available simulation and synthesis software
tools, and is included as a standard library. It incorporates not only the definition of the
standard logic types, but also conversion functions (to and from the standard logic
types).
STD_LOGIC TYPE DEFINITION
As it is such an important type, the std_logic type is described in this section. The type
has the following definition:
‘U’: uninitialized; this signal hasn’t been set yet
‘X’: unknown; impossible to determine this value/result
‘0’: logic 0
‘1’: logic 1
‘Z’: High Impedance
‘W’: Weak signal, can’t tell if it should be 0 or 1
‘L’: Weak signal that should probably go to 0
‘H’: Weak signal that should probably go to 1
‘-’: Don’t care
Example:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
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The key word ALL causes all definitions in the STD_LOGIC_1164 package to be
used. The entity name or the function name must be unique within a library. It is
possible to have the same name repeated in different libraries. The compiler searches
for the names in various libraries in a user defined search order. The “work” library is
always the first in the search order. The first match in the search sequence is
accepted.
General:
All VHDL statements end with a semicolon. New line may be freely introduced to
break long statements. Note that the “entity” statement ends with the “end” statement
and therefore, the semicolon is put after “end”.
The language is not case sensitive. So entity, ENTITY and ENtity have same
meaning. Indentation should be used to clearly identify various statement blocks.
However, it is not mandatory.
A pair of dashes denotes the beginning of comment. All matter on the line after “--”is
ignored.
2.6 BASIC VARIABLE TYPES AND OPERATORS
Constants
When a value needs to be static throughout a simulation, the type of element to use is a
constant. This is often used to initialize parameters or to set fixed register values for
comparison. A constant can be declared for any defined type in VHDL with examples
as follows:
constant a : integer := 1;
constant b : real := 0.123;
constant c : std_logic := ‘0’;
Signals
Signals are the link between processes and sequential elements within the processes.
They are effectively ‘wires’ in the design and connect all the design elements together.
When simulating signals, the simulator will in turn look at updating the signal values
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and also checking the sensitivity lists in processes to see whether any changes have
occurred that will mean that processes become active.
Signals can be assigned immediately or with a time delay, so that an event is
scheduled for sometime in the future (after the specified delay). It is also important to
recognize that signals are not the same as a set of sequential program code (such as in
C), but are effectively concurrent signals that will not be able to be considered stable
until the next time the process is activated. Examples of signal declaration and
assignment are shown below:
signal sig1 : integer := 0;
signal sig2 : integer := 1;
sig1 <= sig2;
sig1 <= sig2 after 10 ns;
VARIABLES
While signals are the external connections between processes, variables are the
internal values within a process. They are only used in a sequential manner, unlike the
concurrent nature of signals within and between processes. Variables are used within
processes and are declared and used as follows:
variable var1 : integer := 0;
variable var2 : integer := 1;
var1 := var2;
There is no concept of a delay in the variable assignment – if we need to schedule an
event, it is necessary to use a signal.
BOOLEAN OPERATORS
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VHDL has a set of standard Boolean operators built in, which are self-explanatory.
The list of operators are and, or, nand, not, nor, xor. These operators can be applied to
BIT, BOOLEAN or logic types with examples as follows:
out1 <= in1 and in2;
out2 <= in3 or in4;
out5 <= not in5;
2.7 BASIC DATA TYPES
Basic types
VHDL has the following standard types defined as built in data types:
BIT
BOOLEAN
BIT_VECTOR
INTEGER
REAL
Data type: BIT
The BIT data type is the simple logic type built into VHDL. The type can have two
legal values ‘0’ or ‘1’. The elements defined as of type BIT can have the standard
VHDL built in logic functions applied to them. Examples of signal and variable
declarations of
type BIT follow:
signal ina : bit;
variable inb : bit := ‘0’;
ina <= inb and inc;
ind <= ‘1’ after 10 ns;
DATA TYPE : BOOLEAN
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The Boolean data type is primarily used for decision-making, so the test value for ‘if’
statements is a Boolean type. The elements defined as of type Boolean can have the
standard VHDL built in logic functions applied to them. Examples of signal and
variable declarations of type Boolean follow:
signal test1 : Boolean;
variable test2 : Boolean := FALSE;
DATA TYPE : INTEGER
The basic numeric type in VHDL is the integer and is defined as an integer in the
range -2147483647 to + 2147483647. There are obviously implications for synthesis
in the definition of integers in any VHDL model, particularly the effective number of
bits, and so it is quite common to use a specified range of integer to constrain the
values of the signals or variables to within physical bounds.
Examples of integer usage follow:
signal int1 : integer;
variable int2 : integer := 124;
There are two subtypes (new types based on the fundamental type) derived from the
integer type which are integer in nature, but simply define a different range of values.
Integer subtypes: natural
The natural subtype is used to define all integers greater than and equal to zero. They
are actually defined with respect to the high value of the integer range as follows:
natural values : 0 to integer’high
Integer subtypes: positive
The positive subtype is used to define all integers greater than and equal to one. They
are actually defined with respect to the high value of the integer range as follows:
positive values : 1 to integer’high
DATA TYPE : CHARACTER
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In addition to the numeric types inherent in VHDL, there are also the complete sets of
ASCII characters available for designers. There is no automatic conversion between
characters and a numeric value per se; however, there is an implied ordering of the
characters defined in the VHDL standard (IEEE Std 1076-1993). The characters can
be defined as individual characters or arrays of characters to create strings. The best
way to consider characters is an enumerated type.
DATA TYPE : REAL
Floating point numbers are used in VHDL to define real numbers and the predefined
floating point type in VHDL is called real. This defines a floating point number in the
range -1.0e38 to +10e38. This is an important issue for many FPGA designs, as most
commercial synthesis products do not support real numbers – precisely because they
are floating point. In practice, it is necessary to use integer or fixed point numbers
which can be directly and simply synthesized into hardware. An example of defining
real signals or variables is shown below:
signal realno : real;
variable realno : real := 123.456;
DATA TYPE : TIME
Time values are defined using the special time type. These not only include the time
value, but also the unit – separated by a space. The basic range of the time type value
is between -2147483647 and +2147483647, and the basic unit of time is defined as the
femto-second (fs). Each subsequent time unit is derived from this basic unit of the fs
as shown below:
ps = 1000 fs;
ns = 1000 ps;
µs = 1000 ns;
ms = 1000 µs;
min = 60 sec;
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hr = 60 min;
Examples of time definitions are shown below:
delay : time := 10 ns;
wait for 20 us;
y <= x after 10 ms;
z <= y after delay;
2.8 VHDL SIMULATION WITH MODEL SIM
ModelSim VHDL supports the IEEE 1076-1987 and 1076-1993 VHDL, the 1164-
1993 Standard Multivalue Logic System for VHDL Interoperability, and the 1076.2-
1996 Standard VHDL Mathematical Packages standards. Any design developed with
ModelSim will be compatible with any other VHDL system that is compliant with
either IEEE Standard 1076-1987 or 1076-1993.
Fig. 3.3 shows the simulation flow for VHDL. For simulations of VHDL descriptions
the code has to be compiled into a binary format which is understood by the simulator.
Therefore a VHDL compiler is available within ModelSim. The Compiler also checks
the syntax and searches for the used libraries. After compilation the binary data for
simulation is stored in the specified library. After definition of the signals to be traced
and shown the simulator is started.
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ModelSimComplier
Design.vhd Testbench.vhd
Library Design Library TB
Library DesignLibrary IEEEModelSimSimulator
Waves.wlfScript.do
ModelSimWave
Procedure load hierarchy select signal start simulation
FIG 7: SIMULATION FLOW
The simulator creates a wave form file which includes the simulation results. If no
wave form file is specified, the file ’vsim.wlf’ is created or overwritten in the current
directory. This file represents the source for analysis of simulation results. The
graphical user interface for ModelSim automatically reads this file after a simulation
has finished.
ModelSim compiles one or more VHDL design units with a single invocation of vcom
(CR-266), the VHDL compiler. The design units are compiled in the order that they
appear on the command line. For VHDL, the order of compilation is important we
must compile any entities or configurations before an architecture that references
them.
2.9 FPGA
FPGA is the abbreviation of Field Programmable Gate Array. An FPGA is an IC chip
that allows designers to “download” their digital circuit into the IC chip and allows the
IC chip to function as described by the downloaded digital circuit. A designer can
design many different digital circuits and program these digital circuits into the FPGA.
Among the many FPGAs that are available in the market are Altera, Xilinx, Actel and
Atmel. FPGAs are programmable and allow for ease of configuration of digital
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circuits. The FPGAs were the next step from CPLD. Instead of a fixed array of gates,
the FPGA uses the concept of a Complex Logic Block (CLB). This is configurable and
allows not only routing on the device, but also each logic block can be configured
optimally. The CLB has a Look-Up Table (LUT) that can be configured to give a
specific type of logic function when programmed.
Once a design has been downloaded into an FPGA, the design must be tested for its
functionality and features on the FPGA. As such, it is common for designers to use an
FPGA development board. These boards consist of an FPGA and several other
peripheral ICs, push buttons, an LCD display, an LED display, connectors to off-board
function generators, and oscilloscopes, allowing for system level testing of the FPGA.
FPGA DESIGN TECHNIQUES
When we design using VHDL, these functions need to be mapped onto the low-level
logic blocks on an FPGA. In order to do this, we need to carry out three specific
functions:
1. Mapping: Logic functions mapped onto CLBs.
2. Placement: CLBs placed on FPGA.
3. Routing: Routed connections between CLBs.
2.10 SYSTHESIS
After verifying the simulation results of the design, the next step is to synthesize the
design. Synthesis is the process of converting and mapping the RTL VHDL code into
logic gates based on a standard cell library.
The process of synthesis requires three separate inputs:
1. Standard cell library
2. Design constraints
3. RTL design code
Synthesis can be categorized into pre-layout synthesis and post-layout synthesis. Pre-
layout synthesis is synthesis on the RTL code using estimation on interconnects
between gates. Pre-layout synthesis uses wire load models which are statistical models
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of estimation on interconnects. Post-layout synthesis is an incremental synthesis
process that is performed after layout. Interconnects between gates are accurately
extracted after layout and back annotated for post-layout synthesis.
STANDARD CELL LIBRARY
A standard cell library is a library that consists of many different types of logic gates
(and, or, not, nand, nor, xor, flip-flop, latch, and-nor, or-nand, and many others) with
different types of sizing. A standard cell library normally consists of the following:
basic logic gates, complex logic gates, Registers, Latches. The standard cell library is
an important requirement during synthesis, as the RTL code is mapped to the logic
gates of the standard cell library.
DESIGN CONSTRAINTS
During the process of synthesis, the synthesis tool reads in the RTL code and maps it
into logic gates based on the standard cell library. Apart from requiring an RTL code
and standard cell library, the process of synthesis also requires design constraints.
Design constraints specify requirements of the synthesized circuit, for example:
1. What is the clock frequency?
2. Should synthesis focus on synthesizing a circuit for performance or should it
synthesize for area optimization?
3. What is the allowed fan-out for the logic gates?
DESIGN FLOW FOR SYNTHESIS
Synthesis is the key stage between high-level design and the physical place and route
which is the final product of the design flow. There are several different types of
synthesis ranging from behavioural, to RTL and finally physical synthesis. RTL
Synthesis is what most designers call synthesis, and is the mechanism whereby a direct
translation of structural and register level VHDL can be synthesized to individual
gates targeted at a specific FPGA platform. Physical synthesis is the last stage in a
synthesis design flow and is where the individual gates are placed (using a ‘floor
plan’) and routed on the specific FPGA platform. The basic HDL design flow is
shown in Fig.
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Specification
Place and Route
Synthesis
HDL Entry
Bread board
Timing Simulation
Netlist Simulation
RTL Simulation
Errors?
VHDL Model
Synthesis
EDIF Netlist
Place & Route
Bit File
RTL Simulation
Timing Information
Timing Simulation
Structural VHDL
Test bench
FIG 8 : HDL DESIGN FLOW
RTL DESIGN FLOW
RTL VHDL is the input to most standard synthesis software tools. Fig. 3.5 shows all
the processes for RTL design flow.
FIG 9: RTL DESIGN FLOW
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The VHDL must be written in a form that contains Registers, State Machines (FSM)
and combinational logic functions. The synthesis software translates these blocks and
functions into gates and library cells from the FPGA library.
The Design process starts from RTL VHDL:
Simulation (RTL) – is needed to develop a test bench (VHDL).
Synthesis (RTL) – targeted at a standard FPGA platform.
Timing simulation (Structural) – simulate to check timing.
Place and route using standard tools (e.g. Xilinx Design Manager).
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CHAPTER 3 : PROJECT SIMULATION
3.1 RTL SCHEMATIC DIAGRAM
FIG 10: RTL SCHEMATIC
FIG 11 : RTL SCHEMATIC II
3.2 WAVEFORMS
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FIG 12: WAVEFORM
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3.3 DESIGN SUMMARY
TABLE 1 : DESIGN SUMMARY
3.4 SYNTHESIS REPORT
HDL SYNTHESIS REPORT
Macro Statistics
# ROMs : 1
257x8-bit ROM : 1
# Adders/Subtractors : 27
12-bit adder : 1
12-bit subtractor : 1
16-bit adder : 23
18-bit adder : 1
27
8-bit adder : 1
# Accumulators : 1
18-bit up accumulator : 1
# Registers : 394
Flip-Flops : 394
# Comparators : 5
10-bit comparator greatequal : 2
10-bit comparator less : 3
# Multiplexers : 7
16-bit 4-to-1 multiplexer : 7
FINAL REPORT:
Final Results:-
RTL Top Level Output File Name : circuit.ngr
Top Level Output File Name : circuit
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 22
28
Cell Usage :
# BELS : 1487
# GND : 1
# LUT1 : 7
# LUT2 : 53
# LUT2_D : 10
# LUT2_L : 268
# LUT3 : 39
# LUT3_D : 16
# LUT3_L : 63
# LUT4 : 198
# LUT4_D : 19
# LUT4_L : 143
# MUXCY : 306
# MUXF5 : 58
# MUXF6 : 4
# MUXF7 : 1
# VCC : 1
# XORCY : 300
# FlipFlops/Latches : 412
# FDC : 412
# Clock Buffers : 1
# BUFGP : 1
29
# IO Buffers : 21
# IBUF : 9
# OBUF : 12
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 541 out of 960 56%
Number of Slice Flip Flops: 412 out of 1920 21%
Number of 4 input LUTs: 816 out of 1920 42%
Number of bonded IOBs: 22 out of 66 33%
Number of GCLKs: 1 out of 24 4%
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 11.661ns (Maximum Frequency: 85.757MHz)
30
Minimum input arrival time before clock: 2.055ns
Maximum output required time after clock: 4.105ns
31
CHAPTER 4 : CONCLUSION
This project DIGITAL FM RECEIVER In VHDL has been a sincere effort. It makes
use of one of the most emerging and technologically advanced fields of electronics.
VHDL appears to be the most successful and outstanding hardware description tools.
And this project has been a success as it makes an appropriate use of it in designing a
complete in itself prototype. The software used for simulation also turned out to be
befitting. Last but not least, the scope of the project can be enhanced by extending it
from design using VHDL to implement on FPGA.
32
REFERENCES
J. Bhaskar, A VHDL Primer.
http://bw-www.ie.u-ryukyu.ac.jp/~wada/design05/spec_e.html
www.google.com
33
APPENDIX A
XILINX ISE 8.1i synthesis software to synthesize optimizes and fit designs to CPLD
at FPGA devices. The XILINX ISE 8.1i software consists of.
1. VHDL synthesis software for use with several PLDs, CPLDs, FPGA.
2. Place and Route software for use with FPGA editor
3. A static time analyzer for use in the place and rout tool. It also includes the
Core generator, Floor plan, Constraints editor, Impact, PACE etc.
A.1 Starting with the ISE Software
Start ISE from the Start menu by selecting Start→ Programs → Xilinx (Integrated
Software Environment) ISE8.1i → Project Navigator.
Creating a New Project
A project in ISE is a collection of all files necessary to create and download a design
to the selected device. To create a new project
1. Select File → New Project.
2. In the New Project Wizard dialog box, type the desired location in the Project
Location field, or browse to the directory under which you want to create your new
project directory using the browse button next to the Project Location field.
3. Enter “clk_fpga” in the Project Name field.
4. Use the pull-down arrow to select Schematic from the Top-Level Module Type
field. Click in the field to access the pull-down list.
5. Click Next
6. In the New Project Wizard Device and Design Flow dialog box, use the pull-down
arrow to select the Value for each Property Name. Click in the field to access the pull
down list.
34
Change the values as follows:
Device Family: Spartan 3E
Device: XC3S500E
Package: fg320
Speed Grade: -4Q
Synthesis Tool: XST (VHDL)
Simulator: ModelSim
Generated Simulation Language: VHDL
7. Click Next.
Next, create a VHDL module for a square. To create a square module.
8. Click New Source in the New Project Wizard Create a New Source Dialog box to
add one new source to your project.
9. In the New Source dialog box, select VHDL Module as the source type.
10. Type in the file name ‘square’.
11. Verify that the “Add to Project” checkbox is selected.
12. Click Next.
13. Click next in the Define VHDL Source dialog box.
14. Click Finish to complete the new source file template
15. Click next in the New Project Wizard Create a New Source dialog box.
16. Click next in the New Project Wizard Add Existing Sources dialog box
17. Click Finish in the New Project Wizard Summary dialog box.
ISE creates and displays the new project in the Sources in Project window, and opens
the .vhd file in ISE Text Editor.
35
FIG 13: NEW PROJECT IN ISE
Checking the Syntax of the Square Module
When the source files are complete, and then check the syntax of the design to find
errors.
1. Verify that Synthesis/Implementation is selected from the drop-down list in the
source window.
2. Select the square design source in the Sources window to display the related
processes in the Processes window.
3. Click the “+” next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process.
5. Close the HDL file.
Implement Design and Verify Constraints
Implementing the Design
1. Select the square source file in the Sources window.
2. Open the Design Summary by double-clicking the View Design Summary
process in the Processes tab.
3. Double-click the Implement Design process in the Processes tab.
36
4. Notice that after Implementation is complete, the Implementation processes
have a green check mark next to them indicating that they completed
successfully without Errors or Warnings.
5. Locate the Performance Summary table near the bottom of the Design
Summary.
6. Click the All Constraints Met link in the Timing Constraints field to view the
Timing Constraints report. Verify that the design meets the specified timing
requirements.
FIG 14: POST IMPLEMENTATION DESIGN SUMMARY
37
APPENDIX B
SIMULATING WITH MODELSIM
We are now ready to run our simulation with ModelSim. Simulating the square design
verifies the logic and timing of the design. We will run a behavioral simulation (also
referred to as a functional simulation).
Behavioral Model found in the ModelSim Simulator hierarchy.
ModelSim is launched. For first-time users of ModelSim, a dialog box appears in
which we:
a) Check the Do not show this dialog again option
b) After opening of ModelSim main window also open signal, structure and wave
default window and specifying the input condition (clock & bit value 0 or 1) in signal
window and then goes to wave default window.
Fig 15: ModelSim wave, structure and signals window
38
Click Run ModelSim.
Our simulation results are displayed in the ModelSim wave window. We may be
required to maximize the ModelSim wave window from the task bar.
c) In the Wave window, click View → Zoom → Zoom Full or click the Zoom Full
icon in the toolbar for seeing the output waveform for particular input.
d) Exit ModelSim by closing the main ModelSim window.
39
APPENDIX C
CODING:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY circuit IS
-- Declarations
PORT(
clk : IN std_logic;
reset : IN std_logic;
fmin : IN std_logic_vector(7 downto 0);
dmout : OUT std_logic_vector (11 DOWNTO 0)
);
END circuit ;
ARCHITECTURE behavior OF circuit IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL d1 : signed(11 DOWNTO 0);
SIGNAL d2 : signed(11 DOWNTO 0);
40
SIGNAL dout : signed(7 DOWNTO 0);
SIGNAL output : signed(7 DOWNTO 0);
-- Component Declarations
COMPONENT multiplier
PORT (
clk : IN std_logic ;
reset : IN std_logic ;
input1 : IN std_logic_vector (7 DOWNTO 0);
input2 : IN signed (7 DOWNTO 0);
output : OUT signed (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT fir
PORT (
clock : IN std_logic ;
reset : IN std_logic ;
data_in : IN signed (11 DOWNTO 0);
data_out : OUT std_logic_vector (11 DOWNTO 0)
);
END COMPONENT;
COMPONENT loop_filter
PORT (
41
clk : IN std_logic ;
reset : IN std_logic ;
c : IN signed (7 DOWNTO 0);
d1 : OUT signed (11 DOWNTO 0);
d2 : OUT signed (11 DOWNTO 0)
);
END COMPONENT;
COMPONENT nco
PORT (
clk : IN std_logic ;
reset : IN std_logic ;
din : IN signed (11 DOWNTO 0);
dout : OUT signed (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Instance port mappings.
I1 : multiplier
PORT MAP (
clk => clk,
reset => reset,
input1 => fmin,
input2 => dout,
output => output
);
42
I4 : fir
PORT MAP (
clock => clk,
reset => reset,
data_in => d1,
data_out => dmout
);
I3 : loop_filter
PORT MAP (
clk => clk,
reset => reset,
c => output,
d1 => d1,
d2 => d2
);
I2 : nco
PORT MAP (
clk => clk,
reset => reset,
din => d2,
dout => dout
);
END behavior;
43
ENTITY multiplier IS
-- Declarations
port (CLK : in std_logic;
RESET : in std_logic;
input1 : in std_logic_vector(7 downto 0);
input2 : in signed(7 downto 0);
output : out signed(7 downto 0)
);
END multiplier ;
ARCHITECTURE behavior OF multiplier IS
signal out_temp : signed(15 downto 0);
signal input1_buf : signed(15 downto 0);
signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0);
begin
process(CLK, RESET)
begin
if (RESET='1') then
out_temp <= (others => '0');
output <= (others => '0');
input1_buf <= (others => '0');
part0 <= (others => '0');
44
part1 <= (others => '0');
part2 <= (others => '0');
part3 <= (others => '0');
part4 <= (others => '0');
part5 <= (others => '0');
part6 <= (others => '0');
part7 <= (others => '0');
elsif rising_edge(CLK) then
input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1);
if (input2(0)='1') then
part0 <= -(input1_buf);
else
part0 <= (others => '0');
end if;
if (input2(1)='1') then
if (input2(0)='1') then
part1 <= (others => '0');
else
part1 <= -(input1_buf);
end if;
else
if (input2(0)='1') then
part1 <= input1_buf;
else
part1 <= (others => '0');
end if;
45
end if;
if (input2(2)='1') then
if (input2(1)='1') then
part2 <= (others => '0');
else
part2 <= -(input1_buf);
end if;
else
if (input2(1)='1') then
part2 <= input1_buf;
else
part2 <= (others => '0');
end if;
end if;
if (input2(3)='1') then
if (input2(2)='1') then
part3 <= (others => '0');
else
part3 <= -(input1_buf);
end if;
else
if (input2(2)='1') then
part3 <= input1_buf;
else
part3 <= (others => '0');
end if;
end if;
46
if (input2(4)='1') then
if (input2(3)='1') then
part4 <= (others => '0');
else
part4 <= -(input1_buf);
end if;
else
if (input2(3)='1') then
part4 <= input1_buf;
else
part4 <= (others => '0');
end if;
end if;
if (input2(5)='1') then
if (input2(4)='1') then
part5 <= (others => '0');
else
part5 <= -(input1_buf);
end if;
else
if (input2(4)='1') then
part5 <= input1_buf;
else
part5 <= (others => '0');
end if;
end if;
if (input2(6)='1') then
47
if (input2(5)='1') then
part6 <= (others => '0');
else
part6 <= -(input1_buf);
end if;
else
if (input2(5)='1') then
part6 <= input1_buf;
else
part6 <= (others => '0');
end if;
end if;
if (input2(7)='1') then
if (input2(6)='1') then
part7 <= (others => '0');
else
part7 <= -(input1_buf);
end if;
else
if (input2(6)='1') then
part7 <= input1_buf;
else
part7 <= (others => '0');
end if;
end if;
out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000");
48
output <= out_temp(15 downto 8);
end if;
end process;
END behavior;
entity FIR is
port(
clock : in std_logic;
reset : in std_logic;
data_in: in signed(11 downto 0);
data_out : out std_logic_vector(11 downto 0)
);
end FIR;
architecture behavior of FIR is
signal d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15 : signed(15 downto 0);
signal sum : signed(15 downto 0);
begin
process(clock,reset)
begin
if (reset = '1') then
d0 <= (others => '0');
49
d1 <= (others => '0');
d2 <= (others => '0');
d3 <= (others => '0');
d4 <= (others => '0');
d5 <= (others => '0');
d6 <= (others => '0');
d7 <= (others => '0');
d8 <= (others => '0');
d9 <= (others => '0');
d10 <= (others => '0');
d11 <= (others => '0');
d12 <= (others => '0');
d13 <= (others => '0');
d14 <= (others => '0');
d15 <= (others => '0');
sum <= (others => '0');
data_out <= (others => '0');
ELSIF rising_edge(clock) THEN
d0 <= data_in(11)&data_in(11)&data_in(11)&data_in(11)&data_in;
d1 <= d0;
d2 <= d1;
d3 <= d2;
d4 <= d3;
d5 <= d4;
d6 <= d5;
d7 <= d6;
d8 <= d7;
50
d9 <= d8;
d10 <= d9;
d11 <= d10;
d12 <= d11;
d13 <= d12;
d14 <= d13;
d15 <= d14;
sum <= (d0+d1+d2+d3+d4+d5+d6+d7+d8+d9+d10+d11+d12+d13+d14+d15) srl 4;
data_out <= std_logic_vector(sum(11 downto 0));
end if;
end process;
end behavior;
ENTITY loop_filter IS
-- Declarations
port ( CLK : in std_logic;
RESET : in std_logic;
C : in signed(7 downto 0);
D1 : out signed(11 downto 0);
D2 : out signed(11 downto 0)
);
END loop_filter ;
51
ARCHITECTURE behavior OF loop_filter IS
signal E : signed(11 downto 0);
signal dtemp : signed(11 downto 0);
begin
process(CLK, RESET)
begin
if (RESET='1') then
D1 <= (others => '0');
D2 <= (others => '0');
E <= (others => '0');
dtemp <= (others => '0');
elsif rising_edge(CLK) then
dtemp <= (C(7)&C(7)&C(7)&C&'0') + dtemp - E;
E <= dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11 downto 4);
D1 <= dtemp;
D2 <= dtemp(11 downto 4)&"0000";
end if;
end process;
END behavior;
52
ENTITY nco IS
-- Declarations
port ( clk : in std_logic;
reset : in std_logic;
din : in signed(11 downto 0);
dout : out signed(7 downto 0)
);
END nco ;
-- hds interface_end
ARCHITECTURE behavior OF nco IS
type vectype is array (0 to 256) of signed(7 downto 0);
-- ROM cosrom
constant cosrom : vectype := (
0 => "01111111",
1 => "01111111",
2 => "01111111",
3 => "01111111",
4 => "01111111",
5 => "01111111",
6 => "01111111",
7 => "01111111",
8 => "01111111",
9 => "01111111",
10 => "01111111",
11 => "01111111",
53
12 => "01111111",
13 => "01111111",
14 => "01111111",
15 => "01111111",
16 => "01111111",
17 => "01111111",
18 => "01111111",
19 => "01111111",
20 => "01111111",
21 => "01111111",
22 => "01111111",
23 => "01111111",
24 => "01111111",
25 => "01111110",
26 => "01111110",
27 => "01111110",
28 => "01111110",
29 => "01111110",
30 => "01111110",
31 => "01111110",
32 => "01111110",
33 => "01111101",
34 => "01111101",
35 => "01111101",
36 => "01111101",
37 => "01111101",
38 => "01111101",
54
39 => "01111100",
40 => "01111100",
41 => "01111100",
42 => "01111100",
43 => "01111100",
44 => "01111011",
45 => "01111011",
46 => "01111011",
47 => "01111011",
48 => "01111010",
49 => "01111010",
50 => "01111010",
51 => "01111010",
52 => "01111010",
53 => "01111001",
54 => "01111001",
55 => "01111001",
56 => "01111001",
57 => "01111000",
58 => "01111000",
59 => "01111000",
60 => "01110111",
61 => "01110111",
62 => "01110111",
63 => "01110111",
64 => "01110110",
65 => "01110110",
55
66 => "01110110",
67 => "01110101",
68 => "01110101",
69 => "01110101",
70 => "01110100",
71 => "01110100",
72 => "01110100",
73 => "01110011",
74 => "01110011",
75 => "01110011",
76 => "01110010",
77 => "01110010",
78 => "01110010",
79 => "01110001",
80 => "01110001",
81 => "01110001",
82 => "01110000",
83 => "01110000",
84 => "01101111",
85 => "01101111",
86 => "01101111",
87 => "01101110",
88 => "01101110",
89 => "01101101",
90 => "01101101",
91 => "01101101",
92 => "01101100",
56
93 => "01101100",
94 => "01101011",
95 => "01101011",
96 => "01101010",
97 => "01101010",
98 => "01101010",
99 => "01101001",
100 => "01101001",
101 => "01101000",
102 => "01101000",
103 => "01100111",
104 => "01100111",
105 => "01100110",
106 => "01100110",
107 => "01100101",
108 => "01100101",
109 => "01100100",
110 => "01100100",
111 => "01100011",
112 => "01100011",
113 => "01100010",
114 => "01100010",
115 => "01100001",
116 => "01100001",
117 => "01100000",
118 => "01100000",
119 => "01011111",
57
120 => "01011111",
121 => "01011110",
122 => "01011110",
123 => "01011101",
124 => "01011101",
125 => "01011100",
126 => "01011100",
127 => "01011011",
128 => "01011011",
129 => "01011010",
130 => "01011001",
131 => "01011001",
132 => "01011000",
133 => "01011000",
134 => "01010111",
135 => "01010111",
136 => "01010110",
137 => "01010101",
138 => "01010101",
139 => "01010100",
140 => "01010100",
141 => "01010011",
142 => "01010010",
143 => "01010010",
144 => "01010001",
145 => "01010001",
146 => "01010000",
58
147 => "01001111",
148 => "01001111",
149 => "01001110",
150 => "01001110",
151 => "01001101",
152 => "01001100",
153 => "01001100",
154 => "01001011",
155 => "01001010",
156 => "01001010",
157 => "01001001",
158 => "01001000",
159 => "01001000",
160 => "01000111",
161 => "01000111",
162 => "01000110",
163 => "01000101",
164 => "01000101",
165 => "01000100",
166 => "01000011",
167 => "01000011",
168 => "01000010",
169 => "01000001",
170 => "01000001",
171 => "01000000",
172 => "00111111",
173 => "00111110",
59
174 => "00111110",
175 => "00111101",
176 => "00111100",
177 => "00111100",
178 => "00111011",
179 => "00111010",
180 => "00111010",
181 => "00111001",
182 => "00111000",
183 => "00111000",
184 => "00110111",
185 => "00110110",
186 => "00110101",
187 => "00110101",
188 => "00110100",
189 => "00110011",
190 => "00110011",
191 => "00110010",
192 => "00110001",
193 => "00110000",
194 => "00110000",
195 => "00101111",
196 => "00101110",
197 => "00101101",
198 => "00101101",
199 => "00101100",
200 => "00101011",
60
201 => "00101010",
202 => "00101010",
203 => "00101001",
204 => "00101000",
205 => "00100111",
206 => "00100111",
207 => "00100110",
208 => "00100101",
209 => "00100100",
210 => "00100100",
211 => "00100011",
212 => "00100010",
213 => "00100001",
214 => "00100001",
215 => "00100000",
216 => "00011111",
217 => "00011110",
218 => "00011110",
219 => "00011101",
220 => "00011100",
221 => "00011011",
222 => "00011011",
223 => "00011010",
224 => "00011001",
225 => "00011000",
226 => "00011000",
227 => "00010111",
61
228 => "00010110",
229 => "00010101",
230 => "00010100",
231 => "00010100",
232 => "00010011",
233 => "00010010",
234 => "00010001",
235 => "00010001",
236 => "00010000",
237 => "00001111",
238 => "00001110",
239 => "00001101",
240 => "00001101",
241 => "00001100",
242 => "00001011",
243 => "00001010",
244 => "00001010",
245 => "00001001",
246 => "00001000",
247 => "00000111",
248 => "00000110",
249 => "00000110",
250 => "00000101",
251 => "00000100",
252 => "00000011",
253 => "00000010",
254 => "00000010",
62
255 => "00000001",
256 => "00000000");
signal dtemp : unsigned(17 downto 0);
signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";
begin
process(CLK, RESET)
begin
if (RESET='1') then
dout <= (others => '0');
din_buf <= (others => '0');
dtemp <= (others => '0');
dtemp1 <= 0;
elsif rising_edge(CLK) then
din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto 8));
if (dtemp1 >= 0) and (dtemp1 < 257) then
dout <= cosrom(dtemp1);
elsif (dtemp1 >= 257) and (dtemp1 < 513) then
dout <= -cosrom(512-dtemp1);
elsif (dtemp1 >= 513) and (dtemp1 < 769) then
dout <= -cosrom(dtemp1-512);
63
else
dout <= cosrom(1024-dtemp1);
end if;
end if;
end process;
END behavior;
64