fmx2r3 technical description
TRANSCRIPT
Information
Flexible Multiplexer FMX2R3.2
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f Important Notice on Product SafetyElevated voltages are inevitably present at specific points in this electrical equipment. Some of the parts may also have elevated operating temperatures.
Non-observance of these conditions and the safety instructions can result in personal injury or in prop-erty damage.
Therefore, only trained and qualified personnel may install and maintain the system.
The system complies with the standard EN 60950-1 / IEC 60950-1. All equipment connected has to comply with the applicable safety standards.
The same text in German:
Wichtiger Hinweis zur Produktsicherheit
In elektrischen Anlagen stehen zwangsläufig bestimmte Teile der Geräte unter Spannung. Einige Teile können auch eine hohe Betriebstemperatur aufweisen.
Eine Nichtbeachtung dieser Situation und der Warnungshinweise kann zu Körperverletzungen und Sachschäden führen.
Deshalb wird vorausgesetzt, dass nur geschultes und qualifiziertes Personal die Anlagen installiert und wartet.
Das System entspricht den Anforderungen der EN 60950-1 / IEC 60950-1. Angeschlossene Geräte müssen die zutreffenden Sicherheitsbestimmungen erfüllen.
Trademarks:
All designations used in this document can be trademarks, the use of which by third parties for their own purposes could violate the rights of their owners.
Copyright (C) Siemens AG 2005-2007.
Issued by the Communications GroupHofmannstraße 51D-81359 München
Technical modifications possible.Technical specifications and features are binding only insofar as they are specifically and expressly agreed upon in a written contract.
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Reason for Update
Details:
Chapter/Section Reason for Update
5.7 Management connections in the MXS19C
Issue HistoryIssue Date of issue Reason for Update
2 03/2006
3 05/2006
5 03/2007
6 05/2007 see above
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This document consists of a total of 386 pages. All pages are issue 6.
Contents
1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.1 Structure of the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.2 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.3 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.4 Protection Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.4.1 Protection Against Excessive High Contact Voltages . . . . . . . . . . . . . . . . . 211.4.2 Protection Against Escaping Laser Light . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.4.3 Protection Against Fire in Racks or Housings . . . . . . . . . . . . . . . . . . . . . . . 221.4.4 Components Subject to Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . 221.4.5 Handling Modules (General) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.4.6 Handling Optical Fiber Connectors and Cables . . . . . . . . . . . . . . . . . . . . . . 231.4.7 Protection against Foreign Voltages in the System . . . . . . . . . . . . . . . . . . . 231.4.8 Virus Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241.5 CE Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241.6 Waste of Electrical and Electronic Equipment (WEEE) . . . . . . . . . . . . . . . . 24
2 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.2 System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.2.2 Central Unit CUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2.3 Bus Extension Card BEC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2.4 Units for Operation and Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2.5 Line Cards for Analog Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.2.6 Line Cards for ISDN Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.2.7 Line Cards for Digital Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.3 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.4 Internal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.1 SNUS Subrack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.1.1 Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.1.2 Ethernet Applications of the LT2ME1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.1.3 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.1.4 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.1.5 QD2 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.1.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.1.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.1.8 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.1.9 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.1.10 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633.2 FMX2S Subrack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.2.1 Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.2.2 Ethernet Applikations of LT2ME1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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3.2.3 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.2.4 QD2 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.2.5 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.2.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693.2.7 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.2.8 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823.2.9 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913.3 MXS19C Subrack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923.3.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923.3.2 Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943.3.3 E1 Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953.3.4 Line Termination Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953.3.5 Ethernet Applikations of the LT2ME1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963.3.6 Cables and Filters for Electromagnetic Compatibility . . . . . . . . . . . . . . . . . 973.3.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973.3.8 QD2 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983.3.9 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003.3.10 Alarming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013.3.11 Power Supply and Dissipation in the Shelf . . . . . . . . . . . . . . . . . . . . . . . . 1013.3.12 Front Panels for Data Interfaces of the CPF2. . . . . . . . . . . . . . . . . . . . . . 1023.3.13 Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033.3.14 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043.3.15 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163.4 ONU 30 FTTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173.4.1 Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173.4.2 Shelf AMXMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193.4.3 Supervision Unit MSUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.4.4 Fan and Alarm Module FAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.4.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283.4.6 Management Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.4.7 Front Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.4.8 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323.5 ONU 20 FTTO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353.5.1 Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353.5.2 Configuration and Equipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373.5.3 Hardware Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383.5.4 Terminal Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413.5.5 Clock Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513.5.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513.5.7 Operating Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523.5.8 Local Operation of the ONU 20 FTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523.5.9 Control and Supervision Unit COSU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533.5.10 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573.6 CUD Central Unit Drop/Insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603.6.2 Monitoring and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613.6.3 Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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3.6.4 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673.6.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693.7 Bus Extension Unit BEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723.7.2 Monitoring and Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723.7.3 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733.7.4 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743.7.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753.8 SUB102 Subscriber Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763.8.2 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773.8.3 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783.9 SLX102 and SLX102E Subscriber Converters . . . . . . . . . . . . . . . . . . . . . 1813.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813.9.2 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823.9.3 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833.10 SLB62 Subscriber Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853.10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853.10.2 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863.10.3 Monitoring and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863.10.4 Connector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873.10.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.11 UAC68 Universal Analog Line Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903.11.2 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923.11.3 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923.11.4 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953.12 SEM106C E&M Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973.12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973.12.2 Monitoring and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983.12.3 Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983.12.4 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993.12.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003.13 SEM108HC E&M Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023.13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023.13.2 Monitoring and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033.13.3 Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033.13.4 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043.13.5 Signal Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053.13.6 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053.14 Analog Leased Line LLA102/104C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2073.14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2073.14.2 Supervision and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2073.14.3 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2083.14.4 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093.15 ISDN I8S0P Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113.15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
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3.15.2 Time Slot Allocation and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123.15.3 Supervision and Alarm Signaling and Diagnostics . . . . . . . . . . . . . . . . . . 2133.15.4 Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2143.15.5 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153.15.6 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163.16 IUL82C and IUL84C ISDN Line Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183.16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183.16.2 Time Slot Allocation and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2193.16.3 Supervision and Alarm Signaling and Diagnostics . . . . . . . . . . . . . . . . . . 2193.16.4 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2203.16.5 Technical Data IUL82C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213.16.6 Technical Data IUL84C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233.17 I4UK2NTP/I4UK4NTP ISDN Line Cards. . . . . . . . . . . . . . . . . . . . . . . . . . 2253.17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253.17.2 Time Slot Assignment and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253.17.3 Connector Assignment of I4UK2NTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273.17.4 Connector Assignment of the I4UK4NTP . . . . . . . . . . . . . . . . . . . . . . . . . 2293.17.5 Technical Data I4UK2NTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303.17.6 Technical Data I4UK4NTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313.18 DSC104C Digital Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333.18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333.18.2 Point-to-Multipoint Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333.18.3 Conference Modes of the Central Unit Drop/Insert, CUD . . . . . . . . . . . . . 2343.18.4 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2343.18.5 Supervision and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2343.18.6 Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2353.18.7 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2363.18.8 Supervision and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2373.18.9 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2383.19 DSC6-n× 64C Digital Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2393.19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2393.19.2 Codirectional Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2393.19.3 Centralized Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403.19.4 Contradirectional Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403.19.5 Point-to-Multipoint Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403.19.6 Conference Modes of the Central Unit Drop/Insert, CUD . . . . . . . . . . . . . 2403.19.7 Test Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403.19.8 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413.19.9 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423.20 CM64/2 Channel Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2443.20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2443.20.2 2-Mbit/s Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453.20.3 Sa Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453.20.4 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453.20.5 Supervision and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463.20.6 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2473.20.7 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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3.20.8 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503.21 CPF2 Digital Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523.21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523.21.2 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2533.21.3 Sub Bitrate Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2533.21.4 Point-to-Multipoint Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2543.21.5 Channel Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2543.21.6 Supervision and Diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2553.21.7 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2573.21.8 Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2583.21.9 Overview CIM Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633.21.10 CIM-X.21 Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2643.21.11 CIM-V.24 Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2733.21.12 CIM-V.35 Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2833.21.13 CIM-V.36 Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2943.21.14 Ethernet Module CIM-nx64E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3043.21.15 Technical Data CPF2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3093.22 Supervision Unit, SUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3173.22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3173.22.2 Control and Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3193.22.3 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3193.22.4 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3213.22.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3233.23 Supervision Unit, OSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3253.23.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3253.23.2 Supervision and Alarm Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3273.23.3 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3283.23.4 Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3303.23.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3323.24 SISA Concentrator SISAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3343.24.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3343.24.2 Control and Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3363.24.3 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3373.24.4 Terminal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3393.24.5 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3444.1 Operating Modes of the Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3444.1.1 Drop Insert Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3444.1.2 Terminal Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3464.1.3 Terminal Multiplexer with 1+1 Protection Switching. . . . . . . . . . . . . . . . . . 3464.1.4 Ethernet Connection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3484.2 End-to-End Protection for Subrates and n × 64 kbit/s . . . . . . . . . . . . . . . . 3504.3 Timed Tasks for Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3524.4 Signaling of the ISDN Line Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3534.4.1 Dial-up Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3534.4.2 Leased Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3534.5 Clock Generation and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
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5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565.1 Network Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565.2 SISA Communication Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3575.3 Access to Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3585.4 DCN Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3605.5 Management in an SDH Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3615.5.1 SDH Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3615.5.2 Access via the ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3635.5.3 DCN Decoupling via ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3645.5.4 Node in an SDH Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3695.6 Management in a Line Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3705.6.1 Access of the Network Management System . . . . . . . . . . . . . . . . . . . . . . 3705.6.2 DCN Decoupling via ECC in a Line Network . . . . . . . . . . . . . . . . . . . . . . 3715.6.3 DCN Decoupling in the FMX2S in the Line Network. . . . . . . . . . . . . . . . . 3715.7 DCN Structures with MXS19C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3725.7.1 ECC Channel (64 kbit/s or 9.6 kbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3725.7.2 Overhead Channel (9.6 kbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3735.8 Software Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3775.8.1 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3775.8.2 Data Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3775.9 Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
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IllustrationsFig. 2.1 FMX2R3.2 Corporate Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Fig. 2.2 Ethernet Switching via an FMX2R3.2 Network . . . . . . . . . . . . . . . . . . . . 27
Fig. 2.3 Access via FMX2R3.2 Network to V5.1/V5.2 Exchange. . . . . . . . . . . . . 27
Fig. 2.4 Connecting the Network Termination Units to the Multiplexer . . . . . . . . 28
Fig. 2.5 Overview Circuit Diagram of Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . 31
Fig. 2.6 Subscriber Access to Digital Exchange . . . . . . . . . . . . . . . . . . . . . . . . . 32
Fig. 2.7 Subscriber Access to Analog Exchange . . . . . . . . . . . . . . . . . . . . . . . . . 32
Fig. 2.8 LLA102/104C in Leased Lines with 2-Wire Interface . . . . . . . . . . . . . . . 33
Fig. 2.9 LLA102/104C in Leased Lines with 4-Wire Interface . . . . . . . . . . . . . . . 33
Fig. 2.10 I8S0P Dial-up Connection with CAS Signaling . . . . . . . . . . . . . . . . . . . . 34
Fig. 2.11 I8S0P Dial-up Connection Using FA Signaling . . . . . . . . . . . . . . . . . . . . 34
Fig. 2.12 I8S0P Leased-line Connections Using FA Signaling . . . . . . . . . . . . . . . 35
Fig. 2.13 I8S0P Leased-line Connections for Stand-alone Operation . . . . . . . . . . 35
Fig. 2.14 Dial-up Connection of the IUL82C or IUL84C with CAS Signalingin Repeater Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fig. 2.15 Dial-up Connection of the IUL84C with FA Signaling . . . . . . . . . . . . . . . 36
Fig. 2.16 Leased-Line Connections of the IUL84C with FA-Signaling . . . . . . . . . . 37
Fig. 2.17 Leased-Line Connections of the IUL82C in Stand-alone Mode . . . . . . . 37
Fig. 2.18 Leased-Line Connection of the IUL84C in Stand-alone Mode . . . . . . . . 37
Fig. 2.19 CPF2 Front Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig. 3.1 Use of FMX2R3.2 Multiplexer in an SNU Shelf (Example) . . . . . . . . . . . 43
Fig. 3.2 Shelf SNUS (without Front Panel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Fig. 3.3 SNUS Equipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Fig. 3.4 LT2ME1 on Slots 207, 208 and 209, Two Ethernet Modules . . . . . . . . . 47
Fig. 3.5 SNUS Internal 2-Mbit/s Connections, Subrack fitted with SMX1/4c . . . . 47
Fig. 3.6 SNUS Internal Wiring of PCI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fig. 3.7 SNUS Internal 34-Mbit/s and STM-1 Connections . . . . . . . . . . . . . . . . . 48
Fig. 3.8 SNUS Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fig. 3.9 SNUS QD2 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig. 3.10 SNUS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig. 3.11 SNUS Front View without Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Fig. 3.12 SNUS Connector Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Fig. 3.13 Shelf FMX2S (without Front Panel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Fig. 3.14 FMX2S Equipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Fig. 3.15 LT2ME1 on Slot 216, One Ethernet Module . . . . . . . . . . . . . . . . . . . . . . 67
Fig. 3.16 FMX2S Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Fig. 3.17 FMX2S QD2 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Fig. 3.18 FMX2S Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Fig. 3.19 FMX2S Front View without Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . 70
Fig. 3.20 Shelf MXS19C with Front Cover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Fig. 3.21 MXS19C Front View without Front Cover, Unequipped . . . . . . . . . . . . . 93
Fig. 3.22 MXS19C Rear View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Fig. 3.23 MXS19C Equipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Fig. 3.24 External Interfaces of the Line Termination Units . . . . . . . . . . . . . . . . . 95
Fig. 3.25 LT2ME1 Each With One Ethernet Module. . . . . . . . . . . . . . . . . . . . . . . 96
Fig. 3.26 LT2ME1 on Slots 202 and 203, Two Ethernet Modules . . . . . . . . . . . . 96
Fig. 3.27 MXS19C Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Fig. 3.28 MXS19C QD2 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Fig. 3.29 QD2 Bus Switch-over. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Fig. 3.30 Connecting Cable S42023-A799-S18 . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig. 3.31 MXS19C Backplane, Shelf from Inside . . . . . . . . . . . . . . . . . . . . . . . . 103
Fig. 3.32 Structure of ONU 30 FTTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Fig. 3.33 Front View of ONU 30 FTTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Fig. 3.34 ONU 30 FTTB Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig. 3.35 Equipping of the AMXMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Fig. 3.36 Control Elements of the MSUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Fig. 3.37 MSUE Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Fig. 3.38 SV 65 W 12 V/48 V, Front View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Fig. 3.39 Switching from 230 V to 115 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Fig. 3.40 Management Access to the ONU 30 FTTB . . . . . . . . . . . . . . . . . . . . . 131
Fig. 3.41 Use of FMX2R3.2 Multiplexer in an ONU 20 FTTO (Example) . . . . . . 135
Fig. 3.42 Front View of the ONU 20 FTTO (with and without Front Plate) . . . . . 135
Fig. 3.43 Structure of ONU 20 FTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Fig. 3.44 ONU 20 FTTO with Power Supply and Backup Battery. . . . . . . . . . . . 136
Fig. 3.45 Configuration of the 2-Mbit/s Interfaces of ONU 20 FTTO. . . . . . . . . . 137
Fig. 3.46 ONU 20 Equipping and Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Fig. 3.47 Rear Side of the ONU 20 FTTO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Fig. 3.48 Switches and Connectors in the ONU 20 FTTO . . . . . . . . . . . . . . . . . 139
Fig. 3.49 Connecting Cable S42022-A768-S56 . . . . . . . . . . . . . . . . . . . . . . . . . 147
Fig. 3.50 Battery Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Fig. 3.51 Supervision Unit COSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Fig. 3.52 Controls of the CUD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Fig. 3.53 Connector Assignment of the CUD . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Fig. 3.54 Controls of the BEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Fig. 3.55 Connector Assignment BEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fig. 3.56 Connector Assignment of SUB102 . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Fig. 3.57 Connector Assignment of the SLX102/E . . . . . . . . . . . . . . . . . . . . . . 182
Fig. 3.58 Controls of the SLB62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Fig. 3.59 Connector Assignment of the SLB62. . . . . . . . . . . . . . . . . . . . . . . . . . 187
Fig. 3.60 Internal Sin Interface Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Fig. 3.61 Internal Interface Circuit of S2in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Fig. 3.62 Connector Assignment of the SEM106C . . . . . . . . . . . . . . . . . . . . . . . 199
Fig. 3.63 Internal Interface Circuit of S2in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Fig. 3.64 Connector Assignment SEM108HC. . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Fig. 3.65 Connector Assignment of LLA102/104C . . . . . . . . . . . . . . . . . . . . . . . 208
Fig. 3.66 Loops on the I8S0P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Fig. 3.67 Control Elements of the I8S0P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
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Fig. 3.68 Connector Assignment of I8S0P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Fig. 3.69 Connector Assignment of IUL82C and IUL84C . . . . . . . . . . . . . . . . . . 220
Fig. 3.70 Connector Assignment of I4UK2NTP . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Fig. 3.71 Connector Assignment of the I4UK4NTP . . . . . . . . . . . . . . . . . . . . . . . 229
Fig. 3.72 Controls of the DSC104C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Fig. 3.73 Connector Assignment of the DSC104C . . . . . . . . . . . . . . . . . . . . . . . 236
Fig. 3.74 Connector Assignment of DSC6-nx64C . . . . . . . . . . . . . . . . . . . . . . . 241
Fig. 3.75 Controls of the CM64/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Fig. 3.76 Connector Assignment of the Jacks 20, 21 and 22 . . . . . . . . . . . . . . . 248
Fig. 3.77 Connector Assignment of the CM64/2 . . . . . . . . . . . . . . . . . . . . . . . . . 249
Fig. 3.78 Controls of the CPF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Fig. 3.79 Controls of the X.21 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Fig. 3.80 Controls of the V.24 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Fig. 3.81 Controls of the V.35 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Fig. 3.82 Controls of the V.36 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Fig. 3.83 Functional Diagram of CIM-nx64E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Fig. 3.84 Controls Ethernet Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Fig. 3.85 Ethernet Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Fig. 3.86 Operation and Monitoring via the SUE’s QD2-Interface . . . . . . . . . . . . 317
Fig. 3.87 Controls of the SUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Fig. 3.88 Connector 11 of the SUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Fig. 3.89 Connector 10 of the SUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Fig. 3.90 Operation of the System Modules with OSU (Example) . . . . . . . . . . . . 325
Fig. 3.91 Application of QD2 Master Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Fig. 3.92 Controls of the OSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Fig. 3.93 Connector of the OSU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Fig. 3.94 Controls of the SISAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Fig. 3.95 Contact Assignment of the F Connector . . . . . . . . . . . . . . . . . . . . . . . . 338
Fig. 3.96 Terminal Assignment of the SISAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Fig. 4.1 Connecting a 2-Mbit/s Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Fig. 4.2 Tapping off and Inserting 64-kbit/s Signals. . . . . . . . . . . . . . . . . . . . . . 344
Fig. 4.3 Digital Conference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Fig. 4.4 Point (Port E1A)-to-Multipoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Fig. 4.5 Point (Port E1B)-to-Multipoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Fig. 4.6 Point (Time Slot)-to-Multipoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Fig. 4.7 Broadcasting with E1A as Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Fig. 4.8 Broadcasting with E1B as Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Fig. 4.9 Broadcasting with Time Slot as Point . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Fig. 4.10 Terminal Multiplexer TMX30(1+1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Fig. 4.11 Ethernet Traffic in Different Time Slot Groups . . . . . . . . . . . . . . . . . . . 348
Fig. 4.12 Ethernet Traffic of 2 Time Slot Groups . . . . . . . . . . . . . . . . . . . . . . . . . 349
Fig. 4.13 Ethernet Traffic in Star Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Fig. 4.14 End-to-end Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Fig. 4.15 Actions for Channel Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
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Fig. 4.16 CAS Signaling on ISDN Dial-up Lines . . . . . . . . . . . . . . . . . . . . . . . . . 353
Fig. 4.17 FA Signaling on ISDN Dial-up Lines . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Fig. 4.18 Stand-alone Operation with D Channel Signaling . . . . . . . . . . . . . . . . 353
Fig. 4.19 FA Signaling in ISDN Leased Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Fig. 4.20 Clock Control in Linear Network (T3 Available at both End Points). . . 354
Fig. 5.1 Network Management of FMX2R3.2 (Example) . . . . . . . . . . . . . . . . . 356
Fig. 5.2 SISA Structure of FMX2R3.2 Network. . . . . . . . . . . . . . . . . . . . . . . . . 357
Fig. 5.3 Example of a FMX2R3 Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Fig. 5.4 Operation of System Modules in Standalone Operation of SNUS (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Fig. 5.5 DCN Transport via Overhead in an SDH Ring with One Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Fig. 5.6 DCN Transport via Overhead in an SDH Ring with Two Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Fig. 5.7 DCN Access via ECC in an SDH Ringwith One Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Fig. 5.8 DCN Access via ECC in an SDH Ring with Redundant Transmission Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Fig. 5.9 DCN Access via ECC in an SDH Ringwith Two Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Fig. 5.10 DCN Decoupling via ECC in an SDH Ring . . . . . . . . . . . . . . . . . . . . . 365
Fig. 5.11 DCN Decoupling via ECC in an SDH Ringwith Two Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Fig. 5.12 DCN Decoupling via ECC in an SDH Ringwith Redundant Transmission Path . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Fig. 5.13 DCN Decoupling via ECC in an SDH Ringwith Branch to Line Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Fig. 5.14 DCN Decoupling via ECC in an SDH Ring with Branch to Line Networks, Two Management Systems . . . . . . . . . . . . 368
Fig. 5.15 DCN Decoupling via ECC in an SDH Ring at the Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Fig. 5.16 DCN Access via ECC in a Line Networkwith DCN Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Fig. 5.17 DCN Access via ECC in a Line Network with Two Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Fig. 5.18 DCN Decoupling via ECC in a Line Networkor Star Network with Two Management Systems . . . . . . . . . . . . . . . . 371
Fig. 5.19 ECC Channel (64 kbit/s or 9.6 kbit/s). . . . . . . . . . . . . . . . . . . . . . . . . . 372
Fig. 5.20 ECC in the Central Station. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Fig. 5.21 ECC in the Line Network and in the Remote Station. . . . . . . . . . . . . . 373
Fig. 5.22 Overhead Channel (9.6 kbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Fig. 5.23 Overhead Channel in the Central Station with LTO. . . . . . . . . . . . . . . 374
Fig. 5.24 Overhead Channel in the Line Network with LTO . . . . . . . . . . . . . . . . 374
Fig. 5.25 Overhead Channel in the Remote Station with LTO . . . . . . . . . . . . . . 375
Fig. 5.26 Overhead Channel in the Central Station with LT2ME1 . . . . . . . . . . . 375
Fig. 5.27 Overhead Channel in the Line Network with LT2ME1. . . . . . . . . . . . . 376
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Fig. 5.28 Overhead Channel in the Remote Station with LT2ME1 . . . . . . . . . . . 376
Fig. 5.29 Software Download. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
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TablesTab. 1.1 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Tab. 2.1 Interface Modules for Use on the CPF2. . . . . . . . . . . . . . . . . . . . . . . . . 38
Tab. 2.2 CPF2 Front Panel Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Tab. 3.1 SNUS FMX2R3.2 and LTx Equipping, and Assignment of Connectors in the Terminal Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Tab. 3.2 SNUS CMXC Equipping, and Assignment of Connectors in the Terminal Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Tab. 3.3 SNUS SMX1/4c Equipping, and Assignment of Connectors in the Terminal Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Tab. 3.4 SNUS DIL Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Tab. 3.5 SNUS Units and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Tab. 3.6 SNUS Connectors X141 and X142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Tab. 3.7 SNUS 15-Contact Jacks X101, X102 and X121 . . . . . . . . . . . . . . . . . . 54
Tab. 3.8 SNUS 9-Contact Jacks X120, X143 and X144 . . . . . . . . . . . . . . . . . . . 55
Tab. 3.9 SNUS Connectors X122, X131, X138, X112 and X132. . . . . . . . . . . . . 56
Tab. 3.10 SNUS Connectors X103 to X108, X123 to X128, X103, X123, X107, X108 and X111. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Tab. 3.11 SNUS Connectors X109, X110, X 113, X114, X129, X130, X133, X134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Tab. 3.12 SNUS Connectors X115 to X117, X135 to X137. . . . . . . . . . . . . . . . . . 59
Tab. 3.13 SNUS Connectors X103 to X108, X123 to X128 (Part 1) . . . . . . . . . . . 60
Tab. 3.14 SNUS Connectors X103 to X108, X123 to X128 (Part 2) . . . . . . . . . . . 61
Tab. 3.15 SNUS Connectors X103 to X108, X123 to X128 (Part 3) . . . . . . . . . . . 62
Tab. 3.16 FMX2S Equipping, and Assignment of Connectors in the Terminal Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Tab. 3.17 FMX2S Overview of the Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Tab. 3.18 FMX2S Address Settings for the Units . . . . . . . . . . . . . . . . . . . . . . . . . 71
Tab. 3.19 FMX2S LC Connectors (General) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Tab. 3.20 FMX2S Connectors X105 to X110, X113 to X118,X123 to X128 and X131 to X136 (Part 1) . . . . . . . . . . . . . . . . . . . . . . . 83
Tab. 3.21 FMX2S Connectors X105 to X110, X113 to X118X123 to X128 und X131 to X136 (Part 2) . . . . . . . . . . . . . . . . . . . . . . . 84
Tab. 3.22 FMX2S Connectors X105 to X110, X113 to X118X123 to X128 und X131 to X136 (Part 3) . . . . . . . . . . . . . . . . . . . . . . . 85
Tab. 3.23 FMX2S Connectors X101 to X104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Tab. 3.24 FMX2S Connectors X119 to X121 and X138 . . . . . . . . . . . . . . . . . . . . 87
Tab. 3.25 FMX2S Connectors X139 and X140 . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Tab. 3.26 FMX2S Connectors X111, X112, X129 and X130. . . . . . . . . . . . . . . . . 89
Tab. 3.27 FMX2S Connector X137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Tab. 3.28 FMX2S Connectors X141 and X142 . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Tab. 3.29 MXS19C Equipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Tab. 3.30 Cables and Filters for EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Tab. 3.31 MXS19C Plug-in Units and Addresses . . . . . . . . . . . . . . . . . . . . . . . . 100
Tab. 3.32 MXS19C Connector Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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Tab. 3.33 MXS19C Connector X101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Tab. 3.34 MXS19C Connector X103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Tab. 3.35 MXS19C Connectors X104 to X109, X112 to X117 (General) . . . . . . . 108
Tab. 3.36 MXS19C Connectors X104 to X109, X112 to X117, Part 1 . . . . . . . . . 109
Tab. 3.37 MXS19C Connectors X104 to X109, X112 to X117, Part 2 . . . . . . . . . 110
Tab. 3.38 MXS19C, Connectors X104 to X109, X112 to X117, Part 3 . . . . . . . . . 111
Tab. 3.39 MXS19C Signalzuordnung der LT2ME1-Module . . . . . . . . . . . . . . . . . 112
Tab. 3.40 MXS19C Connectors X110 and X111 . . . . . . . . . . . . . . . . . . . . . . . . . 112
Tab. 3.41 MXS19C Connector X118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Tab. 3.42 MXS19C Connector X120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Tab. 3.43 AMXMS Equipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Tab. 3.44 Visual Signalizing of the MSUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Tab. 3.45 ONU 30 FTTB External Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Tab. 3.46 FAM Connector X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Tab. 3.47 LED Displays on SV 65 W 12 V/48 V . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Tab. 3.48 Equipping the ONU 20 FTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Tab. 3.49 DIL Switch Setting in the Central Terminal Panel . . . . . . . . . . . . . . . . . 140
Tab. 3.50 Central Terminal Panels on the ONU 20 FTTO . . . . . . . . . . . . . . . . . . 141
Tab. 3.51 Terminal Panels of Line Cards in ONU 20 FTTO . . . . . . . . . . . . . . . . . 141
Tab. 3.52 Optical Signalling of the COSU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Tab. 3.53 Setting the DIL Switch S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Tab. 3.54 Table of Alarms of the CUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Tab. 3.55 Optical Signaling of the CUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Tab. 3.56 Setting the Controls of the CUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Tab. 3.57 Address Switch Settings on the CUD . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Tab. 3.58 SLX102/E Plug-in Unit Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Tab. 3.59 Table of Alarms of the SLB62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Tab. 3.60 System Connector of the UAC68 (Internal Interface) . . . . . . . . . . . . . . 192
Tab. 3.61 Exchange Connector of the UAC68 (External Interface) . . . . . . . . . . . 193
Tab. 3.62 Table of Alarms for the SEM106C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Tab. 3.63 Table of Alarms for the SEM108HC . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Tab. 3.64 Controls on the I8S0P (S0-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Tab. 3.65 Restricted Time Slot Occupancy of the I4UK2NTP at 128 kbit/s . . . . . 226
Tab. 3.66 Restricted Time Slot Occupancy of the I4UK4NTP at 128 kbit/s . . . . . 226
Tab. 3.67 Table of Alarms for the DSC104C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Tab. 3.68 Table of Alarms of the CM64/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Tab. 3.69 Controls of the CM64/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Tab. 3.70 Interface Modules for Use on the CPF2 . . . . . . . . . . . . . . . . . . . . . . . . 252
Tab. 3.71 Assignment of the LEDs to the Ports of the Unit. . . . . . . . . . . . . . . . . . 255
Tab. 3.72 LED Control when the Alarm Occurs . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Tab. 3.73 Connector Assignment X15 of the CPF2 . . . . . . . . . . . . . . . . . . . . . . . 258
Tab. 3.74 Terminal Assignment X16 (General) of the CPF2 . . . . . . . . . . . . . . . . 259
Tab. 3.75 Connector Assignment X16 (for X.21-Modules) of the CPF2 . . . . . . . . 260
Tab. 3.76 CPF2 Connector X16 (with CIM-nx64E Modules) . . . . . . . . . . . . . . . . 261
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Tab. 3.77 Relationship between Number of Bits and Transmission Speed. . . . . 264
Tab. 3.78 Signal States at the X.21 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Tab. 3.79 Alarm Table CPF2 with X.21 Module. . . . . . . . . . . . . . . . . . . . . . . . . . 268
Tab. 3.80 Interface Signals X.21 at the Module Connector . . . . . . . . . . . . . . . . . 272
Tab. 3.81 Terminal Assignment of the X.21 Module Connector . . . . . . . . . . . . . 273
Tab. 3.82 Signal States at the V interface, Part 1(not for V.110 protocol operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Tab. 3.83 Signal States at the V Interface, Part 2 (V.110 protocol operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Tab. 3.84 Alarm Table CPF2 with V.24 Module. . . . . . . . . . . . . . . . . . . . . . . . . . 278
Tab. 3.85 V.24 Interface Signals at the Module Connector . . . . . . . . . . . . . . . . . 282
Tab. 3.86 Terminal Assignment of the V.24 Module Connector . . . . . . . . . . . . . 283
Tab. 3.87 Signal States at the V Interface, Part 1 (not for V.110 protocol operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Tab. 3.88 Signal States at the V Interface, Part 2 ( V.110 protocol operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Tab. 3.89 Alarm Table CPF2 with V.35 Module. . . . . . . . . . . . . . . . . . . . . . . . . . 289
Tab. 3.90 V.35 Interface Signals at the Module Connector . . . . . . . . . . . . . . . . . 290
Tab. 3.91 Terminal Assignment of the V.35 Module Connector . . . . . . . . . . . . . 291
Tab. 3.92 Signal States at the V Interface, Part 1 (not for V.110 protocol operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Tab. 3.93 Signal States at the V Interface, Part 2 (V.110 protocol operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Tab. 3.94 Alarm Table CPF2 with V.36 Module. . . . . . . . . . . . . . . . . . . . . . . . . . 299
Tab. 3.95 V.36 Interface Signals at the Module Connector . . . . . . . . . . . . . . . . . 302
Tab. 3.96 Terminal Assignment of the V.36 Module Connector . . . . . . . . . . . . . 303
Tab. 3.97 CIM-nx64E Module Connector X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Tab. 3.98 CIM-nx64E Module Connector X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Tab. 3.99 Visual Signals Output by the SUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Tab. 3.100 LED Displays of OSU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Tab. 3.101 As-delivered State of the Interfaces of the OSU . . . . . . . . . . . . . . . . . 328
Tab. 3.102 DIL Switch on the OSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Tab. 3.103 DIL Switch on the OSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Tab. 3.104 SISAK Transmission Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Tab. 3.105 SISAK Input and Output Stages for the Data Channels and Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Tab. 3.106 Interfaces and Bit Rates at the SISAK’s Slave Ports . . . . . . . . . . . . . . 335
Tab. 3.107 Interfaces and Bit Rates at the SISAK’s Master Port. . . . . . . . . . . . . . 336
Tab. 3.108 Settings by Control Elements of the SISAK. . . . . . . . . . . . . . . . . . . . . 337
Tab. 3.109 Optical Signalling of the SISAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Tab. 4.1 Priorities of Alarm Criteria for Protection Switching . . . . . . . . . . . . . . . 347
Tab. 4.2 Functions with Channel Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Tab. 5.1 DCN Channels for Remote Operation of the FMX2R3.2 . . . . . . . . . . . 360
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1 General InformationThis manual, an overview about the components and their interworking in networks withthe multiplexer FMX2R3.2 is given. Functions, commissioning, operation and mainte-nance of FMX2R3.2 are described in detail. The operation is done via the graphical userinterface of the AccessIntegrator domain manager version 8.2 (ACI DM V8.2) or higherversions. For the ACI DM V8.2, there is a separate documentation available (see Sec-tion 1.3).
1.1 Structure of the ManualThe manual consists of the following Registers:• Information• Installation• Commissioning• Operation• Maintenance.
Information The register Information (UMN:TED) gives a general overview about applications andthe structure of the FMX2R3.2 and its components. Shelves, ONUs (Optical NetworkUnits) and plug-in units of FMX2R3.2 are described in detail, including technical data,controls and connector assignment. At the end of the document there is a completeproduct overview of all components, which can be plugged in the shelves or ONUs ofthe FMX2R3.2.
Installation The FMX2R3.2 shelves are offered stand alone. They can be mounted in ETSI- or 19’’-racks or shelters. The ONUs are compact devices, which can be mounted at the wall.The necessary information for that are contained in the register Installation (UMN:IMN).
Commissioning The register Commissioning (UMN:ITMN) describes all the procedures and measure-ments for activating the installed system, including step-by-step instructions to commis-sion the FMX2R3.2.
Operation FMX2R3.2 is operated via the graphical user interface of the ACI Domain Manager ver-sion 8.3 or higher, which is described in separat manuals, see Section 1.3. The registerOperation (UMN:OMN) offers a guide line to use the operating procedures for configur-ing the system and for creating connections.
Maintenance The procedures which expedite the re-establishment of normal operating state after amalfunction has occurred in the FMX2R3.2 can be find out via the operating system by“Branch to Maintenance”. The register Maintenance (UMN:MMN) gives an overview ofthe possible malfunctions and contains a guideline for using of the “Branch to Mainte-nance”.
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1.2 Typographical ConventionsIn all sections of this manual, the following conventions are applied:
1.3 Additional DocumentationIn addition, following documentation are used:• User Manual AccessIntegrator Domain Manager: UMN ACI DM TDM version V8.3,
SIEMENS Kit No. A50010-T3-A819• Depending on plugged components:
– Crossconnect Multiplexer CMXC: UMN CMXCSIEMENS Ordering No. A50010-A3-C800-*-7619
– 2-Mbit/s Line Terminating unit: UMN LE2 (FastLink)SIEMENS Ordering No. A50010-A3-K600-*-7619
– Synchronous Multiplexer SMX1/4c: UMN SMX1/4c (FastLink)SIEMENS Ordering No. A50010-A3-K19-*-7619
– Infrastructure: UMN Infrastructure (FastLink)SIEMENS Ordering No. A50010-A3-K419-*-7619
• Project (planning) documentation.
Style of Representation Meaning
Courier Inputs and outputs
Example: Enter LOCAL as the server name
Command not found
Italics Variables
Example: name can be up to eight letters long.
“Italics” Variables fin procedures and title bas
Example: “General NE Parameter. <Network Element#...>:CUC#...”
Boldface Special emphasis
Example: This name may not be deleted
“Quotation marks” Labels on the user interface (e.g. windows, menu items, buttons)
Example: Activate the “OK” button
Make a selection in the “File” menu.
<Courier> Key combinations
Example: <CTRL> <ALT>+<ESC>
→ Successive menu items
Example: “File” → “Close”
iAdditional items of information
!Warnings at critical points in the activity sequence
Tab. 1.1 Typographical Conventions
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1.4 Protection MeasuresThis Section contains a summary of the most important requirements with regard to pro-tection of people and equipment. It does not claim to be complete. The installation in-structions listed are shown in detail in the relevant Installation Manuals.
All assembly, installation, operation and repair work may only be undertaken by properlytrained and qualified personnel.In the event of any injury (e.g. burns and acid burns) being sustained, seek medical helpimmediately.
1.4.1 Protection Against Excessive High Contact VoltagesWhen handling the power supply or working on it, observe the safety measures de-scribed in the specifications of the European Norm EN 50110, part 1 and part 2 (Oper-ation of electrical Systems) and the valid national country specific standards.
Special warning labels on the shelves point to the dangers which can result from highcontact voltages when they are not grounded.
1.4.2 Protection Against Escaping Laser LightWhen working on optical modules, note the regulations covering radiation safety on la-ser light units (EN 60825).
Modules equipped with laser light units carry the laser symbol.The following points should be noted here:For operation in closed systems the laser light units comply with Laser class 1, and suchunits can be identified by a stick on label as well as by a warning label.
Laser symbol
Warning label
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To guard against any possible hazards, all optical transmitters are equipped with an au-tomatic laser shutdown circuit. This trips if an input signal is missing at the relevant op-tical receiver, e.g. if the connection is interrupted.
This preventive measure should also be followed to avoid any damage to health by mak-ing sure that escaping laser light is not directed towards the eye.
When breaking laser connections, the following procedure should be followed, despitethe presence of the laser shutdown circuit:• Pull out the plug-in unit about 5 cm• Disconnect optical fiber• Pull out unit completely.
1.4.3 Protection Against Fire in Racks or HousingsIf FMX2R3.2 shelves are used in housing, the shelves must be performed the conditionsfor a fire protection housing according to Din EN 60950.
To comply with fire protection standards as defined in Din EN 60950, a protective plate(C42165-A320-C285) must be fitted into the floor of ETS and 19-inch standard racks.The rack must also meet the requirements of a fire-resistant housing as defined inDin EN 60950.
1.4.4 Components Subject to Electrostatic Discharge
When packing or unpacking, touching pulling or plugging plug-in units bearing the ESDsymbol, it is essential to wear a grounding bracelet, which should be grounded to a shel-ter or rack when working on it. This ensures that the units are not subject to electrostaticdischarge.
Under no circumstances should the printed conductors or components of modules betouched. Take hold of modules by the edge only.
Once they have been removed, modules must be placed in the conductive plasticsleeves intended for them, and kept or dispatched in the special boxes or transport cas-es bearing the ESD symbol.
In order to avoid further damage to defective modules, they should be treated with thesame degree of care as new ones.
Modules which are accommodated in a closed and intact housing are protected anyway.
European standard EN50082-1 provides information on the proper handling of compo-nents which are subject to electrostatic discharge.
!Note, the laser safety shutdown must be always activated.
ESD symbol
!Slide-in units bearing this symbol are equipped with components subject to electrostatic discharge, that is to say the relevant safety provisions must be adhered to.
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1.4.5 Handling Modules (General)When working with modules (slide-in units, power supply modules, subracks) the follow-ing points should be noted:• Existing ventilation equipment must not be changed. The sufficient air circulation
must not be obstructed.
• When changing power supply modules you must switch off the fuse at the ac power connection. Damaged power connection cables for ac power operated systems are to be replaced by special leads supplied by the manufacturer.
• All slide-in units except for power supply modules can be removed or inserted with the power still applied. To remove and insert the units you should use the two levers fitted to the front of the unit. A type label is fixed to one of the two levers providing information on the hardware and software version of the unit.
• When inserting and removing subracks and when transporting them, take their weight into consideration.
• Cables may never be disconnected by pulling on the cable. Disconnection/connec-tion may only be undertaken by pushing in/pulling out the connector involved.
1.4.6 Handling Optical Fiber Connectors and CablesOptical connectors are precision-made components and must be handled accordingly.To ensure faultless functioning, the following points must be observed:• The minimum bending radius for optical fibers is 30 mm!• Mechanical damage to the surfaces of optical connectors impairs transmission qual-
ity by higher attenuation.– For this reason, do not expose the connectors to impact and tensile load.– Always fit optical fiber connectors with protective caps to guard them against me-
chanical damage and contamination. The protective dust caps should only be re-moved immediately prior to installation.
– Once the protective dust caps have been removed, you must check the surfaces of the optical fiber connectors to ensure that they are clean, and clean them if nec-essary.For cleaning, the C42334-A380-A926 optical fiber cleaning tool or a clean, lint-free cellulose cloth or a chamois leather is suitable. Isopropyl alcohol can be used as cleaning fluid.
1.4.7 Protection against Foreign Voltages in the SystemTwo-level foreign voltage protection for the outdoor user lines is provided within the en-tire system (shelf or ONU and subscriber ports on the slide-in units).
For outdoor user lines, 420-V gas tube arresters are recommended. These can be in-stalled in the MDF (Main Distribution Frame) of the ONU 30 FTTB or in an external MDFon the LSAs.
!Beware of rotating parts.
!Sufficient protection against foreign voltages for outdoor subscriber lines are only given when appropriate protection elements are used.
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With the ONU 20 FTTO, the protection elements are implemented on the terminal panelof the line card, if the line card provides outdoor ports, see technical data of the con-cerned line card (see Section 3).
1.4.8 Virus Protection
Even when exchanging data via network or external data carries (e.g. floppy disks) thereis a possibility of infecting your system with a virus. The occurrence of a virus in yoursystem may lead to a loss of data and breakdown of functionality.
You have to do the following task:• You have to check every data carrier (used data carriers as well as new ones) for
virus before reading data from it.• You must ensure that a current valid virus scanning program is always available. This
program has to be supplied with regular updates by a certified software.• It is recommended to make period checks against viruses in your OS.• At the LCT it is recommended to integrate the virus scanning program into the start-
up sequence.
1.5 CE Declaration of ConformityThe CE conformity of the product will be given if the construction and cabling is under-taken in accordance with the manual and the documents listed there in, e.g. mountinginstructions, cable lists. Where necessary account should be taken of project-specificdocuments.
Deviations from the specifications or unstipulated changes during construction, e.g. theuse of cable types with lower screening values can lead to violation of the CE require-ments. In such case the conformity declaration is invalidated and the responsibility pass-es to those who have caused the deviations.
1.6 Waste of Electrical and Electronic Equipment (WEEE)
!To prevent a virus infection you may not use any software other than that which is re-leased for Operating System (TMN-OS based on Basis AccessIntegrator), Local Craft Terminal (LCT) and transmission system.
!The operator is responsible for protecting against viruses, and for carrying out repair procedures when the system is infected.
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All electrical and electronic products should be disposed of separately from themunicipal waste stream via designated collection facilities appointed by the governmentor the local authorities.
The correct disposal and separate collection of your old appliance will help preventpotential negative consequences for the environment and human health. It is aprecondition for reuse and recycling of used electrical and electronic equipment.
For more detailed information about disposal of your old appliance, please contact yourSIEMENS partner.
The statements quoted above are only fully valid for equipment which is installed in thecountries of the European Union and is covered by the directive 2002/96/EC.
Countries outside the European Union may have other regulations regarding the dispos-al of electrical and electronic equipment.
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2 System Description
2.1 ApplicationThe flexible multiplexer FMX2R3.2 is a PCM30 system for building and extending flexi-ble networks, and is suitable for linear, cascade and ring structures. It is intended mainlyfor use in corporate networks, but can also be used for subscriber-side termination of aV5.1/V5.2 access network.
Companies and administrations like railway operators and utilities operate corporatenetworks along oil or gas pipelines, railway tracks and radio links, which are used formonitoring and maintenance purposes. Due to the ongoing worldwide success of theEthernet technology more and more control engineering components have been intro-duced with an Ethernet interface. FMX2R3.2 offers the possibility to use data interfacesbased on Ethernet technology.
The FMX2R3.2 operates as terminal or drop/insert multiplexer for the following services:• POTS, POTS with local battery• ISDN-BA (S0, Uk0 with line code 4B3T or 2B1Q), also semipermanent• Analog 2/4- wire transmission as leased lines or with E&M signaling• V.24/V.35/V.36/RS530 and X.21 data transmission with subrates up to
30/31 × 64 kbit/s, G.703 with 30/31 × 64 kbit/s• Data transmission with up to 30/31 × 64 kbit/s via Ethernet 10/100Base-T.
The features and properties of the multiplexer correspond to ITU-T RecommendationG.797. In the transmission network direction, it implements up to two 2-Mbit/s interfacesaccording to ITU-T G.703/9. The signaling codes are transmitted using CAS (ChannelAssociated Signaling). As a special signaling variant, FA signaling is also available.
Essential tasks of the multiplexer are:• Multiplexing functions for speech and data signals.• Provision of appropriate subscriber interfaces• Control of subscriber interfaces with CAS or FA signaling.
The CAS code frame corresponds to ITU-T Recommendation G.704/5.1.3.
Fig. 2.1 displays an example for an FMX2R3.2 corporate network:
Fig. 2.1 FMX2R3.2 Corporate Network
FMX2R3.2
FMX2R3.2
Subs.
2 Mbit/sG.703
CAS, FA, LL
FMX2R3.2
Subs.
2 Mbit/sG.703
FMX2R3.2
Subs.
FMX2R3.2
FMX2R3.2
Subs.
Subs.
PBX ComputerCenter
FMX2R3.2Subs.
FMX2R3.2Subs.FMX2R3.2
Subs.
STM-1/STM-4
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Fig. 2.2 shows the typical application scenario, if FMX2R3.2 is used for monitoring andcontrolling along an oil pipeline. The FMX2R3.2 elements along the pipeline provideEthernet interfaces for data transport between Ethernet based sensors, valves or similarand the maintenance centre.
The Ethernet interfaces always work in mirror mode. The Ethernet traffic from the sen-sors is mapped into n x 64 kbit/s timeslots of an E1 link and transported to the nextFMX2R3.2 station. The Ethernet interfaces of all sensors of the same FMX2R3.2 stationand additionally all FMX2R3.2 stations along the pipeline operate together with their dis-tant terminal in the centre as distributed L2 Ethernet switch. This is necessary becausemapping of Ethernet traffic of each single sensor to its own dedicated 64-kbit/s timeslotwould limit the maximum possible amount of Ethernet controlled devices to 31 for anE1 link. Furthermore Ethernet broadcast traffic encapsulated in the TDM link betweenFMX2R3.2 network elements is reduced to a minimum.
Fig. 2.2 Ethernet Switching via an FMX2R3.2 Network
For connection to the public switching network the channel-associated signaling is con-verted in V5.1/V5.2 protocols in conjunction with system module CMXII from FastLink,see Fig. 2.3.
Fig. 2.3 Access via FMX2R3.2 Network to V5.1/V5.2 Exchange
1
4
sensor 1 to 4
Exch
2 Mbit/sG.703
2 Mbit/sG.703
2 Mbit/sG.703
2 Mbit/s, G.703
FMX2R3.2
FMX2R3.2FMX2R3.2FMX2R3.2
sensor 1 to 4 sensor 1 to 4
e. g. oil pipeline
Eth 10/100bT
Eth 10/100bT
Eth 10/100bT Eth 10/100bT
1
4 FMX2R3.2
Eth 10/100bT
2 Mbit/sG.703
2 Mbit/s, G.703
FMX2R3.2
Eth 10bT
Maintenance
of the oil
ET
HE
TH
ET
HETH ETH ETH
FMX2R3.2
ET
H
FMX2R3.2
ET
H
Center
pipeline
1
60
e.g. STM-1
STM-4 opticalor
Subs. Subs.
CMXII
2 Mbit/sG.703
2 Mbit/sG.703
Subs.
2 Mbit/sG.703
2 Mbit/s, G.703 2 Mbit/s, G.703V5.1/V5.2CAS
2 Mbit/sG.703
FastLinkFMX2R3.2
FMX2R3.2FMX2R3.2FMX2R3.2
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Multiplexer FMX2R3.2 can be accommodated as follows:• up to 2 x in FMX2S (Flexible Multiplexer Shelf)• up to 2 x in MXS19C (Multiplexer Shelf 19’’)• in SNUS (Service Network Unit Shelf) in combination with the cross-connect multi-
plexer CMXC and the FastLink system module SMX1/4c• in ONU 30 FTTB or• in ONU 20 FTTO.
ONU 30 FTTB and ONU 20 FTTO each connect a multiplexer to the transmission net-work by means of a line termination unit (LTx). It is possible to cascade several ONUsor to operate two ONUs in a point-to-point connection for fixed analog or digital connec-tions.
Network termination units which are connected to the multiplexer enable one or two datainterfaces to access the subscriber directly. Network termination units for the basic ac-cess connect remote ISDN subscribers via Uk0 (4B3T or 2B1Q) to the multiplexer.
Fig. 2.4 Connecting the Network Termination Units to the Multiplexer
The multiplexer supports the following network termination units:• Network termination unit NTU for interfaces in accordance with G.703 (64 kbit/s),
V.24 (Subbit rates, 64 kbit/s), V.35, V.36, X.21 (subbit rates, 1 or 2 × 64 kbit/s), linked to the FMX2R3.2 via Uk0/2B1Q
• Network termination unit for basic access NTBA via Uk0 (4B3T/2B1Q).
Operating modes of FMX2R3.2
The FMX2R3.2 multiplexer supports the following applications:• Operating modes, chosen from
– TMX2 × 30 terminal multiplexer, which contains two complete multiplexers– DIMX drop-insert multiplexer, with which individual channels of a signal which is
connected between the two 2-Mbit/s ports of the multiplexer can be tapped off and inserted
– TMX30(1+1) terminal multiplexer with 1+1 standby operation, which switches a 2-Mbit/s link to another on a fault
The transmission capacity of the multiplexer in the TMX2× 30 and DIMX operating modes is 60 channels each with 64 kbit/s, and in TMX30(1+1) operating mode it is 30 channels. The assignment of timeslots to the two 2-Mbit/s ports is independent of the channel plug-in unit positions in the multiplexer. If no signaling is transmitted, up to 31 or 62 channels each with 64 kbit/s are available.
• Port-to-port connections for V.24, V.35, V.36, RS530 or X.21 interfaces• End-to-end protection on n × 64-kbit/s level for analog 2-wire/4-wire interfaces (with
or without E&M) and for V.24, V.35, V.36, RS530, X.21 interfaces
FMX2R3.2
8
1
NTU
UK0 (2B1Q)
n × 64 kbit/s (n ≤ 2)X.21,V.24V.35,V.36/RS530
Subratesup to n × 64 kbit/s
G.703 64 kbit/s
NTBA
UK0 (2B1Q)
n × 64 kbit/s (n ≤ 2)S0
NTBA
UK0 (4B3T))
n × 64 kbit/s (n ≤ 2)8
1
S0
IUL82C
IUL84C
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• Broadcasting for POTS with local battery, analog 2-wire/4-wire leased lines and all digital interfaces
• Ethernet switch – Ethernet over TDM mirror– 2 Ethernet modules on a CPF2 possible– 4 Ethernet ports 10/100Base-T according to IEEE802.3 and 802.3x and
1 or 2 TDM uplinks ports per Ethernet module– TDM multiplexer as two times terminal or drop and insert mode– Data rate at TDM: 1 up to 31 time slots per E1 port– automatic MDI/MDIX crossover (for automatic switch, hub or PC detection)
• Digital conference and point-to-multipoint operation• Voice channel in common frequency radio networks
This application is realized using system modules FMX2R3.2 (with CUD and UAC68) and CMXC, see also user manual UMN CMXC.1+1 protection switching of n × 64-kbit/s and 2-Mbit/s signals is not supported in this case.
• IWU submodules of the CPF2 convert digital subscribers, which are connected at a given customer network with X.50/X.51 data structures, into one of the system-inter-nal data structures V.110/X.30 or I.4601).
• Timer jobs for one or two complete channels over a maximum of two timeslotsWith end-to-end protection, a timer job can be set up for each subscriber port.
• Software-controlled configuration, operation and operation monitoringSuitable interfaces are present for connecting a local operating PC and for connect-ing to a TMN. Connected network termination units can be operated and monitored via the multiplexer.
1) Special documentation is available for the IWU sub modules (Prod. No. A50010-A3-H102-*-7619).
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2.2 System Structure
2.2.1 OverviewThe multiplexer includes the following units, see Fig. 2.5:• A central unit drop/insert CUD• Up to 6 line cards LC, of the following types:
– SUB102 subscriber converter, a/b wire, subscriber side– SLX102 or SLX102E subscriber converter, a/b wire, switching side– SLB62 subscriber converter for local battery, a/b wire– UAC68 universal analog line card, 2/4-wire leased lines or with E&M– SEM106C 2-wire E&M converter1) – SEM108HC 4-wire E&M converter1)
– LLA102/104C line card for analog 2-wire/4-wire leased lines– I8S0P ISDN line card, S0 interface– IUL82C ISDN line card, Uk0 interface 2B1Q– I4UK2NTP ISDN line card, Uk0 interface 2B1Q, switching side– IUL84C ISDN line card, Uk0 interface 4B3T – I4UK4NTP ISDN line card, Uk0 interface 4B3T, switching side– DSC104C digital signal channel, 64 kbit/s, codirectional, G.703 interfaces– DSC6-n× 64C digital signal channel, n × 64 kbit/s, G.703 interfaces– CPF2 digital signal channel with a maximum of
- 4 interface modules forsubrates up to 31 × 64 kbit/s, V.24/V35/V36/RS530 or X.21 interfaces,or protocol conversion X.50/X.51 to X.30/V.110/I.460
- 2 Ethernet modules, each Ethernet module with4 Ethernet 10/100Base-T interfaces
– CM64/2 (digital signal card, 2 Mbit/s channel multiplexer, G.703)• Optionally a bus extension card BEC, if up to 12 line cards are connected to the
CUD2).
The multiplexer is operated and monitored via the QD2 slave interface (QD2-S) of thecentral card, which is connected to a supervision unit.
1) only in MXS19C shelf and ONU 20 FTTO
2) only possible in the shelves FMX2S and MXS19C
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Fig. 2.5 Overview Circuit Diagram of Multiplexer
2.2.2 Central Unit CUDThe CUD forms the interface between the line cards of the multiplexer and the PCM sig-nals at E1 ports E1A and E1B. In a synchronous network it operates as a Terminal Mul-tiplexer or as a drop/insert multiplexer.
2.2.3 Bus Extension Card BECThe BEC is used when more than 6 LCs are used:• for full utilization of the 2-Mbit/s signal,
since a few LCs have a limited number of interfaces,• for a comprehensive range of different subscriber interfaces.
A CUD can operate 6 LCs without a BEC, with a BEC it can operate 12 LCs. The numberof time slots of the 2-Mbit/s signal is not increased by a BEC. The BEC connects thesystem bus to a further 6 LC slots and supplies these LCs with the necessary voltages.
2.2.4 Units for Operation and SupervisionThe operation and supervision units include:• Supervision unit SUE (-B1) in shelves SNUS, FMX2S and MXS19C• Supervision unit MSUE in the ONU 30 FTTB• Supervision unit COSU in the ONU 20 FTTO• Supervision unit OSU for synchronous or asynchronous transmission of control in-
formation for remote equipment• SISA concentrator SISAK for asynchronous transmission of control information to
remote equipment (can only be installed in shelf MXS19C).
F2/D2 subscriber interfaces
System bus
Network interfaces
ISDN Uk0, 4B3T
CUD
ZA(A), ZA(B)
SUE
F
QD2-S
Tin/out
E1A (G.703)
QD2-S
LC1)
7
LC1)
12
QD2 bus
Sa5 to Sa8
QD2-MAlarms
E1B (G.703)
BEC1)
LC1
LC6
ECC
n × 64 kbit/s, V.35
≤ 64 kbit/s, V.36
≤ 64 kbit/s, V.35
≤ 19.2 kbit/s, V.24
n × 64 kbit/s, X.21
≤ 64 kbit/s, X.21
n × 64 kbit/s, V.36
2 Mbit/s, G.703
n × 64 kbit/s, G.703
VF, a/b, 2w/4w
ISDN S0
VF, E&M, 2w/4w
VF, a/b, 2w LB
ISDN Uk0, 2B1Q
1) optional10/100Base-T
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For a DCN (Data Communication Network) these units implement a virtual concentrator(SISA-V) in each case. They possess QD2 slave and QD2 master interfaces for incor-porating the FMX2R3.2 into a SISA communication network. For local operation an F-in-terface is available at the supervision units. The SUE can also signal external alarms(e.g. door contact, fan failure) to the operating system (OS).
2.2.5 Line Cards for Analog Services
2.2.5.1 Converter SUB102 The SUB102 subscriber converter provides 10 a/b interfaces and can be used for thefollowing applications:• Connection of conventional analog subscriber telephones or extension telephones
to digital exchange• Together with the SLX102/E for connection of conventional analog subscriber tele-
phones or extension telephones to analog exchange or to an analog subscriber ac-cess of digital exchange.
Fig. 2.6 Subscriber Access to Digital Exchange
Fig. 2.7 Subscriber Access to Analog Exchange
2.2.5.2 Converters SLX102 and SLX102EThe SLX102 or SLX102E provides 10 a/b interfaces and, in conjunction with theSUB102, the SLX102/E connects conventional analog subscriber telephones or exten-sion telephones to analog exchange or to an analog subscriber access of digital ex-change, see Fig. 2.7. The grounding key function is transmitted for use in PABXs.
FMX2R3.2
TE SUB102
F2 2 Mbit/sCAS
EXCH
FMX2R3.2
TE SUB102
F2
FMX2R3.2
SLX102E
F2 2 Mbit/s
EXCH
CAS
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2.2.5.3 Converter SLB62The SLB62 (2-wire LB) line card connects up to 6 analog subscriber terminals with a lo-cal battery power supply to the transmission network.
2.2.5.4 Universal Analog Unit UAC68Universal analog line card UAC68 for 6 channels is used to provide either analog 2-wireor 4-wire interfaces with signaling (E&M operation) or without signaling (analog leasedlines).
2.2.5.5 E & M Converter SEM106CThe SEM106C line card is used for connection of 10 VF signals in 2-wire operation toexchange or transmission equipment which operates with E&M signaling.
2.2.5.6 E & M Converter SEM108HCThe SEM108HC line card is used in the multiplexer for connection of 10 VF signals in4-wire operation to exchange or transmission equipment which operates with E&M sig-naling.
2.2.5.7 Analog Leased Lines LLA102/104CThe analog leased line LLA102/104C with 10 channels is used to provide up to 10 ana-log leased lines within a digital transmission link for service-neutral transparent point-to-point transmission of information.
The channels can be operated with 2- or 4-wire interfaces.
Fig. 2.8 LLA102/104C in Leased Lines with 2-Wire Interface
Fig. 2.9 LLA102/104C in Leased Lines with 4-Wire Interface
FMX2R3.2
TE
F2
FMX2R3.2
F2 2 Mbit/s
TE
LLA102/104C
LLA102/104C
FMX2R3.2
TE
F2
FMX2R3.2
F2 2 Mbit/s
TE
LLA102/104C
LLA102/104C
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2.2.6 Line Cards for ISDN Services
2.2.6.1 ISDN Line Card I8S0PThe I8S0P unit enables an ISDN basic access to be established for remote subscriberterminal equipment or PBXs with S0 port:• With dial-up connections between exchange and remote subscriber terminal equip-
ment or private branch exchanges with CAS (FMX2R3.2 specific, for lengthening from S0 to UK0) or FA signaling, Fig. 2.10 and Fig. 2.11.
• With leased lines between subscriber terminal equipment or private branch ex-changes with FA signaling, Fig. 2.12.
• With leased lines in stand-alone mode, Fig. 2.13.
The I8S0P contains 8 independent S0 interfaces according to ITU-T I.430 that are usedin NT mode or in TE mode.
Dial-up connections with CAS signaling
Fig. 2.10 I8S0P Dial-up Connection with CAS Signaling
Dial-up connections with FA signaling
Fig. 2.11 I8S0P Dial-up Connection Using FA Signaling
S0 2 Mbit/sLE
Uk0TE/
NT mode
I4UK2NTPPBXNT mode
I8S0P
2 Mbit/s Uk0
LT mode
IUL84C NTBA
e.g. multiplexerwith DSC6-nx64C
NT mode
I8S0PS0TE/PBX
S0 PBX
LENT mode
I4UK4NTP
FA
Uk0
2 Mbit/s
2 Mbit/sI8S0P
TE mode(NT mode)
LT mode
IUL84C2 Mbit/sUK0
NTBA
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Leased-line connections using FA signaling
Fig. 2.12 I8S0P Leased-line Connections Using FA Signaling
Leased-line connections for stand-alone operation multiplexer
Fig. 2.13 I8S0P Leased-line Connections for Stand-alone Operation
2.2.6.2 ISDN Line Cards IUL82C and IUL84CThe IUL82C and IUL84C line cards with 8 Uk0 interfaces are employed within digitaltransmission links between subscribers and switching equipment on the subscriber sidewhen ISDN network termination units are to be connected to the multiplexer.
The IUL82C line card is used for 2B1Q code, while the IUL84C line card implements the4B3T code.
This allows the following applications:• Dial-up connections between exchange and subscriber terminal equipment with
CAS signaling (FMX2R3.2 specific, in repeater mode) or with FA signaling (IUL84C only),
• Leased-line connections in stand-alone mode.
NT mode
S0
NT mode
LT mode
IUL84C
FA e.g multiplexer2 Mbit/s
2 Mbit/s
2 Mbit/s
2 Mbit/sS0
Uk0
with DSC6-nx64C
I8S0P I8S0P
NT mode
I8S0PS0
NT-Mode
I8S0P
LT-Mode
IUL82C/
e.g multiplexer2 Mbit/s
2 Mbit/s
2 Mbit/s
2 Mbit/s S0
Uk0
with DSC6-nx64CTE mode
S0
e.g. multiplexer2 Mbit/s
with DSC6-nx64CIUL84C
2 Mbit/sI8S0P
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The Uk0 ISDN interface conforms to standard TS 102 080. Data transmission is alsopossible in the format 128 kbit/s via the B1- and B2-channels of an ISDN line. The fram-ing integrity of the 128-kbit/s connection is ensured. Connected NTBAs are fed per portwith up to 1.1 W power as consumed at the NTBA.
Dial-up connections with CAS signaling
Together with unit I8S0P, the IUL82C or IUL84C operates in an dial-up connection withCAS signaling for lengthening from S0 to UK0, see Fig. 2.10. Additionally, the IUL82C,or IUL84C can be used as shown in Fig. 2.14:
Fig. 2.14 Dial-up Connection of the IUL82C or IUL84C with CAS Signalingin Repeater Mode
Dial-up connections with FA signaling
Together with unit I8S0P, the IUL84C implements an dial-up connection withFA signaling by Fig. 2.11. Additionally, the IUL84C can be used as shown in Fig. 2.15:
Fig. 2.15 Dial-up Connection of the IUL84C with FA Signaling
Leased-line connections with FA signaling
Together with unit I8S0P, the IUL84C implements an ISDN leased-line connection withFA signaling between Uk0 and S0, see Fig. 2.12 In addition to the leased-line connec-tions shown in Fig. 2.12 the IUL84C can be used as shown in Fig. 2.16:
2 Mbit/sLE
Uk0NTBA
NT-Mode
I4UK2NTP
LT-Mode
Uk0TE
IUL82C/IUL84C
2 Mbit/sLE
Uk0NTBA
NT modeLT mode
IUL84CUk0
TE
FA e.g. multiplexer2 Mbit/s with DSC6-nx64C
FAe.g. multiplexer
2 Mbit/s
with DSC6-nx64C
I4UK4NTP
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Fig. 2.16 Leased-Line Connections of the IUL84C with FA-Signaling
Leased-line connections in stand-alone mode
In conjunction with card I8S0P the IUL82C or IUL84C implements in stand-alone modethe conversion from S0 to Uk0 in an ISDN connection, see Fig. 2.13. In addition to thepermanent connection shown in Fig. 2.13, the following applications can be implement-ed:
Fig. 2.17 Leased-Line Connections of the IUL82C in Stand-alone Mode
Fig. 2.18 Leased-Line Connection of the IUL84C in Stand-alone Mode
2.2.6.3 ISDN Line Cards I4UK2NTP and I4UK4NTPISDN line cards I4UK2NTP and I4UK4NTP with 4 Uk0 interfaces provide the interfacebetween multiplexer and ISDN switching equipment on the switching side. The datafrom the I4UK2NTP is transmitted using the 2B1Q code and the data from theI4UK4NTP is transmitted using the 4B3T code.
Dial-up connections with CAS signalling
Together with card I8S0P the I4UK2NTP implements in CAS dial-up connections con-version from Uk0 to S0, see Fig. 2.10.
With card IUL82C on the subscriber side, unit I4UK2NTP (exchange side) operates inthe transmit-receive multiplexer, see Fig. 2.14.
FAe.g. multiplexer2 Mbit/s
with DSC6-nx64C
2 Mbit/s
LT mode
IUL84C
NT mode
FA e.g. multiplexer2 Mbit/s
2 Mbit/s
with DSC6-nx64C
Uk0 Uk0I4UK4NTP
LT mode
IUL82C
LT mode
IUL82C2 Mbit/sUk0NTU
NTBADTEUk0 NTU
NTBA DTE
V.24/X.21/V.35/V.36/
S0
V.24/X.21/V.35/V.36/
S0
LT mode
IUL84C
LT mode
IUL84C2 Mbit/sUk0
NTBADTEUk0
NTBA DTES0S0
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Dial-up connections with FA signaling
Together with unit I8S0P, the I4UK4NTP implements in FA dial-up connections conver-sion of Uk0 to S0, see Fig. 2.11.
With the IUL84C (as a subscriber-side unit) the I4UK4NTP operates in the back-to-backmultiplexer as a Uk0 extension, see Fig. 2.15.
2.2.7 Line Cards for Digital Services
2.2.7.1 Digital Signal Unit DSC104CThe DSC104C (Digital Signal Channel) line card will be employed for the transmissionof digital signals at a bit rate of 64 kbit/s. The unit incorporates 10 codirectional interfac-es which conform to ITU-T Recommendation G.703. If a signal is being transmitted, sig-naling bits a, b, c, d are given the fixed values 1 1 0 1.
2.2.7.2 Digital Signal Unit DSC6-nx64CDigital Signal Channel DSC6-nx64C provides 6 interfaces in accordance with ITU-TRecommendation G.703 and will be used for transmission of digital signals with bit ratesof n × 64 kbit/s (n = 1 to 30/31).
There is the option of operating the 6 interfaces codirectionally (n = 1 to 8) or with cen-tralized clock (n = 1). Two of the interfaces can also be switched over to contradirection-al mode (n = 1 to 30/31).
If a signal is being transmitted, signaling bits a, b, c, d are given the fixed values 1 1 0 1.
2.2.7.3 Digital Signal Unit CM64/2The CM64/2 line card is used for network branch to the 2-Mbit/s level. The CM64/2 com-bines any number of time slots and the associated signaling information (CAS) of the E1ports (2 Mbit/s) of a multiplexer with a 2-Mbit/s signal.
2.2.7.4 Digital Signal Unit CPF2The CPF2 is a universal digital signal channel unit for providing various local data inter-faces (V.24, V.35, V.36, X.21), for connecting to X.50 or X.51 data networks as well asfor data transmission via Ethernet.
The following interface modules are available:
Module Interfaces Operating mode Bit rates
CIM-V.24 V.24 synchronous
asynchronous
0.6 to 64 kbit/s and 128 kbit/s
0.3 to 38.4 kbit/s and 115.2 kbit/s
CIM-V.35 V.35 synchronous
asynchronous
0.6 to 56 kbit/s, n × 64 kbit/s (n ≤ 30 with CAS/
31 without CAS)
0.3 to 38.4 kbit/s and 115.2 kbit/sCIM-V.36 V.35/RS530
CIM-X.21 X.21
CIM-nx64E 10/100Base-T n × 64 kbit/s (n ≤ 30 with CAS/31 without CAS)
Tab. 2.1 Interface Modules for Use on the CPF2
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There are 4 interfaces on the channel unit which will be implemented with four plug-inchannel interface modules (CIM-V24, CIM-V35, CIM-V36 or CIM-X.21). The function,electrical interface and speed of the 4 ports can be configured individually and indepen-dently of each other.
Up to 2 Ethernet interface modules CIM-nx64E can be equipped per CPF2. EachCIM-nx64E module provides 4 Ethernet ports.
Beside the unlimited use of CIM-nx64E module in combination with all other CPF2-mod-ules (CIM-V.24/-V.35/-V.36/-X.21) is possible via separate traffic. The number of linecards CPF2 is only limited by the shelf or ONU equipment rules.
2.2.7.5 Front Panel Connectors for the CPF2Different front panel connectors are intended to simplify matters wiring of the CPF2 datainterfaces with external data terminals, see also installation manual (UMN:IMN).The interfaces of the CPF2 are connected with the front panel connectors via specialadapter cables.
Fig. 2.19 CPF2 Front Panel Connectors
Front panel connectors Ordering number
V.24 S42023-A862-S12
X.21 S42023-A862-S13
V.35 with Sub-D connection S42023-A862-S14
V.36 S42023-A862-S15
RS 530 S42023-A862-S25
V.35 S42023-A862-S26
Ethernet 10/100Base-T S42023-A862-S16
Tab. 2.2 CPF2 Front Panel Connectors
V.24RS530X.21V.36V.35V.35
3
4
1
2
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2.3 External Interfaces
E1 Interfaces
The E1 interfaces are on the CUD central unit drop/insert and conform to ITU-T Recom-mendation G.703. Each E1 interface has a transmission rate of 2 Mbit/s. By setting aswitch, the interface can be terminated as desired with 120 Ω or 75 Ω.
F2/D2 Subscriber Interfaces
The F2/D2 subscriber interfaces are provided by the line cards. They are used to con-nect analog, digital and ISDN subscribers. The number of subscriber interfaces for eachLC card type is different. For detailed information on the line cards, see Sections 2.2.5to 2.2.7.
10/100 Base-T Ethernet Interfaces
The 10/100Base-T interfaces are provided from the Ethernet module on the line cardCPF2. They are used to connect monitoring equipment with 10/100 Base-T interfaces,which data are transmitted via the time slot structure of a 2-Mbit/s signal. 4 Ethernet in-terfaces are available per Ethernet module, 2 modules can be equipped pre CPF2.
T3 Interface
The T3 interface is implemented by the central unit and conforms to ITU-T G.703/13. Anexternal 2048-kHz clock is fed in via the T3in interface. The interface can be set to highor low resistance by a switch. The 2048-kHz clock, which is derived from the appropriateclock source, is output at the T3out interface, see Section 4.5.
QD2 Interface
The QD2 interface of the multiplexer is on the central unit and conforms to EIA RS485.It is in the form of a slave interface (QD2-S), and implements access to the FMX2R3.2network element and to remote network termination units, see also Section 2.10.
ZA(A) and ZA(B) Interface
The interface signals an alarm in the direction of the central service observation equip-ment.
The ZA(A) interface is in the form of a normally closed contact. At the normally closedcontact ZA(A), either A alarm (urgent) or S alarm (service) is output, and for both casesfailure of the operating voltage. The ZA(B) interface is in the form of a normally opencontact. It is used to signal B alarm (non-urgent).
Interface of ECC
Via the ECC interface of the CUD, a control signal can be derived from any timeslot ofone of the E1 ports and inserted in the opposite direction. This timeslot can then no long-er be used for information transmission. The ECC interface conforms to ITU-T Recom-mendation V.11.
iAt the 64 kbit/s bit rate, no transparent data transmission is possible. The data signal must be transmitted using HDLC frames.
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Sa Bit Interfaces
The Sa bit interfaces are designed according to the interface conditions of EIA RS485.Four Sa bit interfaces, Sa5 to Sa8, are available on the CUD.
One symmetrical signal line for the sending direction and one for the receiving directioncan be connected for each Sa bit. The transmission speed is 0.6 kbit/s (signal distortionabout 15 %) to 1.2 kbit/s (signal distortion about 30 %).
The following options for the data paths are available for all Sa bits on the CUD unit:• Source for E1Aout: low-level / high-level / Sa*in / E1Bin / Sa*in ANDed with
E1Bin,• Source for E1Bout: low-level / high-level / Sa*in / E1Ain /Sa*in ANDed with E1Ain,• Source for Sa*out: low-level / high-level / high-resistance / E1Ain / E1Bin / E1Ain
ANDed with E1Bin.
2.4 Internal Interfaces
System Bus
The system bus is subdivided into the PCM highway and the LC bus. The line cards alsoreceive their power supply via the system bus.
PCM Highway
The PCM highway forms the interface between the central unit and the various linecards for serial transmission of data channels and PCM-coded speech signals.
The sending and receiving signals of the PCM interface are synchronized by the sameclock, but can be in any phase position in relation to each other as far as the frame clockis concerned. Both signal flow directions keep their own frame synchronization pulse.
LC bus
The LC bus is an 8-bit computer bus for transmission of control and signaling data be-tween the central unit and the LCs.
The interface works on the master-slave principle, i.e. the central unit is the master andthe LCs are the slaves. Irrespective of the division in the subrack, up to 12 line cards canbe operated every 4 ms with one CUD central unit drop/insert.
!If the option of frame synchronization of the CUD is used, the Sa bits are not available as a transmission channel. They are permanently set to “1” in the sent signal. The Sa bit interfaces are switched to high-resistance.
LC
LC
PCM highway
.
.
.
4 Mbit/s
SYNCclock
(PCM)
CUD
SUE
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2.5 Power SupplyThe multiplexer is supplied with an input voltage of −48 V/−60 V.
Power supply modules on the central unit convert the −48 V/ −60 V input voltage into thenecessary operating voltages, +5 V and −5 V, to supply the modules on the unit andLCs. The −48 V/ −60 V input voltage is protected by a 1 A replaceable fusible cartridgeon the unit.
Additionally, the power supply of the central unit switches the UKZU voltage (−48 V/ −60 V) to the LCs, protected by a 2 A replaceable fusible cartridge.
CUD
SUELC
LC
LC bus
.
.
.
AD0 to AD7
4 × CTRL
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3 Components
3.1 SNUS SubrackThe SNUS is a subrack in 19“ design, using adapters it is adapted to the fitting condi-tions for the ETSI housing and racks with a minimum depth of 300 mm.
The SNUS allows the building and extending of flexible networks, because it combinesseveral system modules in a single shelf:• FMX2R3.2 multiplexer with up to 6 line cards• CMXC cross connect• STM-1/STM-4 SDH feeder• 2-Mbit/s line termination unit, with one of the following transmission capabilities
– 2 × 2 Mbit/s on one glass fiber– HDB3 coded (UK2) on 2-core local loops, 2 interfaces per line termination unit– SHDSL (2-wire/4-wire), 2 interfaces per line termination unit.Special modules for line termination unit with Ethernet 10/100Base-T interface can be used to transmit Ethernet data over TDM via one of the following feeder interfaces (2 Mbit/s or STM-1/STM-4 optical, SHDSL, Uk2 or STM-1 electrical).
Fig. 3.1 Use of FMX2R3.2 Multiplexer in an SNU Shelf (Example)
The subrack can accept units in double Eurocard format, and has a backplane board toconnect the internal and external interfaces.
The SNUS is equipped with a terminal panel which provides all external interfaces viathe corresponding sub-D connectors. The optical interfaces of the corresponding unitsare directly accessible on the units themselves. For mechanical routing of the optical fi-bers the SNUS is equipped with FO clips.
FMX2R3.2
CMXC
2 × LTx
LTx8
16 x
2 Mbit/s
STM-1
STM-4 optical
2 x 2 Mbit/s 1
G.703POTS
ISDN (UK0/S0)data (G.703/V.24/
opt., UK2
opt./electrical
leased lineor feeder
26 x
1 ... 26SHDSL
V.35/V.36/Eth.RS530/X.21)
2-wire/4-wire LL/E&M2 Mbit/sG.703
2 Mbit/sG.703
SMX1/4c
Subscribers
(2-wire/4-wire)
4 x 2 Mbit/s opt., UK2
leased lineor feeder
SHDSL, Eth.(2-wire/4-wire)
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Fig. 3.2 Shelf SNUS (without Front Panel)
For the CPF2 data interfaces, different front panels are available, which can be pluggedinto an external Main Distribution Field (MDF 180 or MDF 210), see UMN:IMN. For ca-bling the connectors in the shelf terminal panel to the front panels, the adapter cableS42023-A862-S11 has to be used.
3.1.1 FittingThe SNUS has 18 slots, only a maximum of 16 of these can be used at the same time.
Fig. 3.3 SNUS Equipping
2
SU
E
3 4 5 6 7 8 9 10 11 12 13 1714 16
LCT
1
CU
D
LC 1
LC 2
LC 3
LC 4
LC 5
LC 6
PU
16
CU
C
CU
C
PU
16
TU
AD
M1e
/o/A
DM
4
PS
D
LTx
11)
LTx
21)
LTx
32)
1) LT2ME1/LTO, only one port of the LT2ME1 can be used2) LT2ME1/LTO, two ports of the LT2ME1 can be used
1815
OT
SU
2M
alternatively fitting
!For the two slots 207 and 208, before the units are inserted the associated DIL switches must be checked, see Tab. 3.4 and Fig. 3.11.
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FMX2R3.2 and LTx
Plug-in unit1) Plug-in place Filter7)
201 202 203 204 205 206 207 208 209 218
Sub D in terminal panel at 2wire LC (a, b)
or LTx
C1 D1 E1 F1 G1
G1
H1
H1 L1 V42256
-Z82-M1
V42256
-Z82-M2Sub D in terminal panel at 4wire LC (c, d) C2 D2 E2 F2 G2 H2
SUE ×
CUD ×
UAC68 × × × × × × ×
SUB102 × × × × × × ×
SLB62 × × × × × × ×
LLA102/104C × × × × × ×
I8S0P × × × × × ×
I4UK2NTP × × × × × × ×
IUL82C × × × × × × ×
IUL84C × × × × × × ×
I4UK4NTP × × × × × × ×
CM64/2 × × × × × ×
SLX102/E × × × × × × ×
DSC104C × × × × × ×
DSC6-nx64C × × × × × ×
CPF22) × × × × × × × 3)
LT2ME14) × 5) × 5) × 6)
LTO × × ×
OTSU2M ×
1) Pay attention to switch positions according at different equipping variants!
2) Modules for CPF2 that can be plugged: - CIM V.24, - CIM X.21, - CIM V.35, - CIM V.36, CIM-nx64E
3) No filter is used with CIM-nx64E module
4) Modules for LT2ME1: - Uk2mp, - SDSLmp, - SDSLop, - SDSL4op optionally with T4 module, - G703sh, -Ethernet
5) On these slots, only one interface for copper transmission lines of each LT2ME1 is wired to the Sub D in terminal panel
(means only one module - Uk2mp, - SDSLmp, - SDSLop, - SDSL4op, - G703sh)
6) This slot can be used for LT2ME1 with 2 Ethernet modules.
7) Filter types according to LC types and to Sub D in terminal panel that must be plugged and screwed on
Tab. 3.1 SNUS FMX2R3.2 and LTx Equipping, and Assignment of Connectors in the Terminal Panel
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CMXC
Feeder SMX1/4c
Interfaces/
Plug-in unit
Plug-in places
210 211 212 213
Port unit 1: G.703; 1 to 4/5 to 8 J1/J2
Port unit 1: G.703: 9 to 12/13 to 16 K1/K2
Port unit 2: G.703; 1 to 4/5 to 8 N1/N2
Port unit 2: G.703: 9 to 12/13 to 16 P1/P2
PCI/PCIS M1 M2
ECC L2 L2
PU16(1) ×
CUC(1) ×
CUC(2) ×
PU16(2) ×
Tab. 3.2 SNUS CMXC Equipping, and Assignment of Connectors in the Terminal Panel
Interfaces/
Plug-in unit
Plug-in places
214 216 218
(+) (-) 48V (3W3) V1, X1
V.11 interface T2
2-Mbit/s interface Q1, Q2, R1, R2, S1 S2
STM-1/STM-4 interface V2, V3, W2, W3
E3 interface U2, U3
ADM1o L-1.1 ×
ADM1o S-1.1 ×
ADM4o L-4.1 ×
ADM4o S-4.1 ×
ADM1E ×
TC21E1 ×
TC21E1R ×
TC1E3 ×
PSD ×
Tab. 3.3 SNUS SMX1/4c Equipping, and Assignment of Connectors in the Terminal Panel
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3.1.2 Ethernet Applications of the LT2ME1When all three LTx slots are used for Ethernet applications, two LT2ME1, each with twoSDSL modules, have to be plugged-in slots 207 (LTx1) and 208 (LTx2). The thirdLT2ME1 with two Ethernet modules have to be inserted in slot 209 (LTx3).
Fig. 3.4 LT2ME1 on Slots 207, 208 and 209, Two Ethernet Modules
Additionally, an Ethernet adapter must be used (see Fig. 3.85). Ports 2 and 3 of theEthernet adapter are used. The G.703 interfaces are connected via the Digital Distribu-tion Frame (DDF).
3.1.3 Internal Connections
2-Mbit/s Connections
The internal wiring of the 2-Mbit/s connections is shown in Fig. 3.5.
Fig. 3.5 SNUS Internal 2-Mbit/s Connections, Subrack fitted with SMX1/4c
Module 1SDSL
LT2ME1
SHDSL
Module 1SDSL
LT2ME1
SHDSL
DDF
Module 1Ethernet
Module 2Ethernet
LT2ME1
100bT (port 2) 100bT (port 3)
207 208 209
G.703 G.703 G.703 G.703
CUD LTx PU16123456789
10111213141516
PU16123456789
10111213141516
LTxLTx TU123456789
101112131415161718192021
ADM1123456789
101112131415161718192021
4 ×
E1I
/O
4 ×
E1I
/O
4 ×
E1I
/O
4 ×
IE1/
O
4 ×
E1I
/O
4 ×
E1I
/O
4 ×
E1I
/O
4 ×
E1I
/O
5 ×
E1I
/O
4 ×
E1I
/O
4 ×
E1I
/O
4 ×
E1I
/O
4 ×
E1I
/O
5 ×
E1I
/OConnectors intermination panel
ADM41 2 3
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PCI Connections
Of the 12 PCI interfaces of a CUC, the first 4 are fed to the left-hand PU16 (slot 10) asPCI (from the active CUC, slot 11) and as PCIS (from the redundant CUC, slot 12).
Fig. 3.6 SNUS Internal Wiring of PCI Interfaces
Interfaces 5 to 8 are wired analogously as active and redundant interfaces to the right-hand PU16 (slot 13). The changeover signals for these internal interfaces (CCUR fromthe active CUC, CCURS from the redundant CUC) are in asymmetrical form.
34-Mbit/s and STM-1 Connections
The internal 34-Mbit/s and STM-1 connections are shown in Fig. 3.7.
Fig. 3.7 SNUS Internal 34-Mbit/s and STM-1 Connections
3.1.4 Clock Synchronization
Fig. 3.8 SNUS Clock Distribution
clocksynchr.
CUC123456789
101112
CUC123456789101112
PU1612341234
PU1612341234
CCUR
CCURS
PCI
PCIS STSB
PCIS
PCIS
PCIPCI
PCI
1 2
TU ADM1e
STM1in1
STM1out1
STM1in2
STM1out2
E3in1
E3out1
CUD LTx LTx LTx CUC CUC ADM1
T4
T3
T3in_1 (input)
T3in_2 (input)
T4out_1
T4out_2
ADM41 2 3 1 2
T3in_1 (output)
T3in_2 (output)
Connectors in termination panel
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Synchronous signals can be fed externally via connectors in the termination panel, andreach the ADM1/ADM4 as T3in 2 on CUD, LTx2 and CUC units and as T3in 1. The sub-rack loops the T3in lines for onward connection to other subracks.
For synchronization purposes, T3out signals can be extracted from the CUCs (T3out 1)or CUD (T3out 2).
3.1.5 QD2 AccessThe internal wiring for operation and monitoring is shown in Fig. 3.9.
The TMN access for the subrack is the QD2 slave connector in the termination panel.This leads to the QD2 slave port 1 of the SUE and to a changeover unit, which switchesthe internal QD2 bus to either the QD2 master port of the SUE (in standalone operationof the subrack) or parallel to the QD2 slave port 1 of the SUE (SNU operation).
The T terminals of the QD2 slave interface 1 of the SUE are also accessible in the QD2slave connector.
Fig. 3.9 SNUS QD2 Access
The following internal DCN channels can be used:• ECC channel of CUD, 4 × ECC channels of CUC 1/CUC 2
The ECC terminations of the two CUC positions are connected in parallel. Two of the four ECC interfaces are designed with clock transfer.
• Overhead channel of LTx on slot 3• V.11 channel of ADM1/ADM4.
The QD2 slave port 2 of the SUE is in the QD2-M connector. Via this port, the DCN chan-nel OH64 of the line termination unit LTx3 can be connected using an appropriately as-signed connector.
SUECUD LTx LTx LTx LTx ADM1 PSDLTx
QD
2-S
QD
2-M
EC
C
V.1
1QD2 bus
QD2 bus
4 ×
EC
C
4 ×
V.1
1
1 ×
EC
C
QD
2-S
2
QD
2-S
1 (T
)
QD
2-M
OH64
SPI
S1 S2M
ADM4OTSU2M
Connectors in termination panel
F IF(for LCT)
1 2 3 1 2
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3.1.6 AddressingAll units in this subrack, except SUE and CUD, are assigned slot addresses. For the ad-dresses which are assigned to the slots, see Section 3.1.8.
The SISA address of the SUE is set using the DIL switch in the termination panel. Theaddress of the CUD is set using the DIL switch in the backplane.
For line termination units in line card slots, some address bits are given by the coding ofthe line cards. This makes it necessary to change address bits to adapt the addressing,as it is defined in Tab. 3.5. The change is done using DIL switches in the backplane,see Section 3.1.8.
3.1.7 Power SupplyThe −48 V input voltages are fed via two separate 3W3 plugs in the termination panel.The positive poles of both voltages are connected to each other and to the backplane,via a common filter and protection device, as the operating ground GND. The negativepoles of both voltages are filtered separately, and supply the units in the subrack asMUP1 and MUP2. They are fed separately to the SUE, PSD, and PU16 and connectedto the units with reserve. For CUD, OTSU2M and the line termination units, reserve di-odes are arranged on the backplane. The CUC units are each connected to one of thetwo voltages.
The line cards receive the required secondary voltages +5 V and −5 V from the CUD. The PSD supplies the SMX1/4c with the secondary voltages +5 V and −5 V.
Without forced ventilation and with homogeneous distribution of heat sources in the sub-rack, about 105 W of power dissipation (1.25 W per 5.08 mm of basic grid) are permitted.
Fig. 3.10 SNUS Power Supply
OT
SU
2M
CU
D
LTx
1
LTx
2
LTx
3
CU
C 1
CU
C 2
PS
DMUP 2
SU
E
PU
16
PU
16
MUP 1
48 V
+48 V
+
Connectors in termination panel
EMCprotection
EMCprotection
EMCprotection
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3.1.8 Switch Settings
DIL switch settings according equipping
Fig. 3.11 SNUS Front View without Front Panel
The equipping options are contained in Section 3.1.1.
The following points must be taken into account:
Before slots 207 and 208 are equipped, the DIL switches on the backplane must be setaccordingly to determine whether an LC of the FMX2R3.2 or an LTx module is to beequipped. DIL switches S111, S112, S113 and also S105, S106 and S107 must be setfor slot 207 and S114, S115, S116 and also S108 and S109 for slot 208 according tothe following table.
101
address
BA DC FE HG KJ ML PN RQ TS VU XW YX1V1A1 B1 C1 D1 E1 E1 G1 H1 J1 K1 L1 M1 N1 P1 Q1 R1 S1
116onoff
QD
2-S
lave
QD
2-M
aste
r
Tln
Tln
Tln
G.7
03
Tln
Tln
Tln
G.7
03 HD
SL(
LT3)
PC
I
G.7
03
G.7
03
G.7
03
G.7
03
G.7
03
(+)(
-)48
V
6A
(+)(
-)48
V
6AY2X2U2
E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 Q2 R2 S2 T2
LC1
LC2
LC3
LC4
LC5
LC6
LTx2
LTx1
1 . .
4
9 . .
12
1 . .
4
9 . .
12
17. .
21
1 . .
4
9 . .
12
W2V2
D2C2B2
PBA2
Port Unit 1 CMXC Port Unit 2 Trib Unit SMX
A3
Tln
Tln
Tln
Tln
Tln
Tln
G.7
03
G.7
03
5 . .
8
13. .
16
EC
C
PC
IS
G.7
03
G.7
03
5 . .
8
13. .
16
G.7
03
G.7
03
5 . .
8
13. .
16
G.7
0317
. .21
V.1
1
U3 V3 W3 X3Y3
SMX DSMXTrib.Unit T
3T
3
xt. c
onta
cts
ZA
201 202 204 205 206 207 208 209 210 211 212 213 214 215 216 217 SNUS
201202
204 205 206 207 208 209 210 211 212 213214
215216
217
S103 S104
S10
2
S111 S112 S114 S115
S113 S116
S108
S109
S105
S106
S107
S101
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Addresses
The SISA addresses of all units in this subrack are assigned to the backplane as follows:
Slot Equipping with LC of the FMX2R3.2 Equipping with the LTx module
207 - S111 to S113, all slider switches of
the DIL switches on “OFF”
- S105 to S116, all slider switches of
the DIL switches on “ON”
- S107, all slider switches of the DIL
switch on “OFF”
- S111 to S113, all slider switches of the
DIL switches on “ON”
- S105 to S116, all slider switches of the
DIL switches on “OFF”
- S107, all switches of the DIL switch on “ON”
208 - S114 to S116, all slider switches of
the DIL switches on “OFF”
- S108, all slider switches of the
DIL switch on “ON”
- S109, all switches of the DIL switch
on “OFF”
- S114 to S116, all switches of the DIL
switches on “ON”
- S108, all switches of the DIL switch
on “OFF”
- S109, all switches of the DIL switch on “ON”
Tab. 3.4 SNUS DIL Switch Settings
Unit In slot QD2 address Slot address (connected and fixed)
SUE 201 Is set using DIL switch
S101 in the terminal panel
of the SNUS, see Fig. 3.12
and Fig. 3.11.
5Bit = 1 to 30
5 bit = 3
(K0...K4 shelf model)
CUD 202 Is set using DIL switch
S102 on the backplane of
the SNUS, see Fig. 3.11.
5Bit; here only 1 to 8 usable
SEL_0 = GND
SEL_1 = GND
Line cards 1-6 203 to 208 4 bit = 1 to 6
LTx11) 2) 207 Fixed (5 bit) = 7
LTx21) 2) 208 Fixed (5 bit) = 8
LTx32) 209 Fixed (5 bit) = 9
PU16(1) 210 5 bit = 10
CUC(1) 211 Fixed (5 bit) = 13 5 bit = 11
CUC(2) 212 Fixed (5 bit) = 13 5 bit = 12
PU16(2) 213 5 bit = 13
ADM (SMX) 216 Fixed (5 bit) = 16
Trib.Unit 214
PSD 218 5 bit = 18
OTSU_2M 218 Fixed (5 bit) = 18
1) LTO, LTCOH, LT2ME1
2) If an LTx unit instead of a line card is equipped in slots 207 or 208, the slot must be configured
accordingly (with DIL switches S106 and S107 for slot 207 or with DIL switch S109 for slot 208).
Switches S105 and S108 must always be switched, see Fig. 3.11.)
Tab. 3.5 SNUS Units and Addressing
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DIL Switch S101 for SUE address
DIL Switch S102 for CUD address
TMN connection of the SNUS
3.1.9 Connector Assignment
Fig. 3.12 SNUS Connector Assignment
1
ON = LOW = log 0Example: Switch 1 on OFF corresponds to 20 = 1Switch 5 on OFF corresponds to 24 = 16Corresponds to address 17 for the SUE
ON (0)
OFF (1)
20 21 22 23 24
5
ON (0) OFF (1)
24
23
22
21
20
ON = LOW = log 0Example: Switch 2 on OFF corresponds to 21 = 2Corresponds to address 2 for the CUD
5
4
3
2
1
ON
S104
4321
ON
S103
4321
Delivery state: all slides at S103 are switched to “OFF” (to bottom) and at S104 all slides are switched to “ON” (to top), it means supervision of the SNUS by SUE (stand alone, without COMPS2 and without OSU)
48 V
48 V
QD
2-S
Ala
rm
PB
-+
-+
A
1) DIL switch S101 for setting the SISA address of the SUE
2) LTx1/2/3 line terminating units
C
QD
2-M
B D E F G H
I/O 1
-4
J
I/O 9
-12
K
HD
SL-
LT3
L
PC
I
M
I/O 1
-4
N
I/O 9
-12
P
I/O 1
-4
Q
I/O 9
-12
R
I/O 1
7-21
S
I/O 5
-8
I/O 1
3-16
EC
C-C
UC
PC
IS
I/O 5
-8
I/O 1
3-16
I/O 5
-8
I/O 1
3-16
I/O 1
7-21
ZA
T3a
nT
3out
V.1
1
Add.1)
E3in
X153
X151
E3out
X154
X152
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 218217
X121 X122
X123 X125 X127 X129 X131 X133 X135 X137
X124 X126 X128 X130 X132 X134 X136
X138
Exchange conn.
LC slots 2Mbit/s 2Mbit/s 2Mbit/sX120
X104 X106 X108 X110 X112 X114 X116
X103 X105 X107 X109 X111 X113 X115 X117 X141 X142X101
X102
X143
X144
Slot desig-
nations:
S101
T
HD
SL-
LT1
HD
SL-
LT2
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The possible equipping variants are shown in Tab. 3.1 to Tab. 3.3.
Power Supply Connectors X141 and X142
Coaxial Jack X151
X151: E3in1 X152: E3out1 interface 34 Mbit/s from Tributary Unit
X153:STM-1in1 X154:STM-1out1 electrical STM-1 interface of the ADM, east
X155:STM-1in2 X156:STM-1out2 electrical STM-1 interface of the ADM, west
QD2 (X101 and X102) and Alarm Inputs (X121)
Signal Abbreviations
Pin X141 X142
1
2 -48V (MUP1) -48V (MUP2)
3 +48V (GND) +48V (GND)
Tab. 3.6 SNUS Connectors X141 and X142
Pin X101
QD2 slave
X102
QD2 master
X121
Alarm inputs
1 GND_S GND_S GND_S
2 QD2S1out_a QD2Min_a A1P
3 QD2T1out_a A3P
4 QD2S1in_a QD2Mout_a A5P
5 QD2T1in_a A7P
6
7 DAT
8 GND GND GND
9 QD2S1out_b QD2Min_b A2P
10 QD2T1out_b A4P
11 QD2S1in_b QD2Mout_b A6P
12 QD2T1in_b A8P
13
14 NRST
15 CLK AM
Tab. 3.7 SNUS 15-Contact Jacks X101, X102 and X121
GND Operation groundGND-S Shielded groundQD2Sin_a1, b1QD2Sout_a1, b1
Slave 1 from the SUE
QD2Sin_a2, b2QD2Sout_a2, b2
Slave 2 from the SUE
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T3-Interfaces X143 and X144
Signal Abbreviations
Qin_a/b, Qout_a/b Master from the SUEQD2Tin_a, bQD2Tout_a, b
T-connections of slave1 from the SUE
DAT, CLK, NRST SPI connections to the OSU for temperature monitoringA1P...A8P Alarm inputs of the SUEAM Negative operating voltage for alarm contactsO64in_a/b, O64out_a/b
Overhead 64 kbit/s from LTx, plug-in place 209
Pin X143
Connector T3out
X144
Connector T3in
1 GND_S GND_S
2 T4out1_a T3in1_a (input)
3 T3in1_a (output)
4 T4out2_a T3in2_a (input)
5 T3in 2_a (output)
6 T4out1_b T3in1_b (input)
7 T3in1_b (output)
8 T4out2_b T3in2_b (input)
9 T3in2_b (output)
Tab. 3.8 SNUS 9-Contact Jacks X120, X143 and X144
GND Operation groundGND-S Shielded groundT4out_a1,_b1 T4 output from the CUC plug-in placesT4out_a2,_b2 T4 output from the CUDT3in1_a, b (input) T3in1 input to the CUD-, LTx- and CUC plug-in placesT3in1_a, b (output) T3in1 output for forwardingT3in2_a, b (input) T3in2 input to the ADMT3in2_a, b (output) T3in2 output for forwarding
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ZA-Contacts (X122), ECC of CUC/CUD (X131), V.11 of ADM (X138)
Signal Abbreviations
Pin X122
ZA-contacts
X131
ECC of the CUCs
X138
V.11 of the ADM
1 GND_S GND_S GND_S
2 Ein_a1 V11ETXD_a1
3 ZAA2 Eout_a1 V11ETXD_b1
4 ZAA3 ET_a1 V11ERXD_a1
5 ZAA4 Ein_a2 V11ERXD_b1
6 ZAA5 Eout_a2 V11ETXD_a2
7 ZAA6 ET_a2 V11ETXD_b2
8 ZAA7 Ein_a3 V11ERXD_a2
9 ZAA8 Eout_a3 V11ERXD_b2
10 ZAA9 Ein_a4 V11ETXC_a
11 Eout_a4 V11ETXC_b
12 EinCUD_a V11ERXC_a
13 GND EoutCUD_a V11ERXC_b
14 ZAB1 Ein_b1 V11WTXD_a1
15 ZAB2 Eout_b1 V11WTXD_b1
16 ZAB3 ET_b1 V11WRXD_a1
17 ZAB4 Ein_b2 V11WRXD_b1
18 ZAB5 Eout_b2 V11WTXD_a2
19 ZAB6 ET_b2 V11WTXD_b2
20 ZAB7 Ein_b3 V11WRXD_a2
21 ZAB8 Eout_b3 V11WRXD_b2
22 ZAB9 Ein_b4 V11WTXC_a
23 Eout_b4 V11WTXC_b
24 EinCUD_b V11WRXC_a
25 GND EoutCUD_b V11WRXC_b
Tab. 3.9 SNUS Connectors X122, X131, X138, X112 and X132
GND Operation groundGND-S Shielded groundZAA Central alarming, urgentZAB Central alarming, non-urgentIndex 1 from SUEIndex 2 from CUDIndex 3...5 from LTxIndex 6, 7 from CUCsIndex 8 from PSDIndex 9 from OTSU2MEin/out_a/b1 to a/b4 ECC1 to ECC4 of both CUCs
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Line cards (X103 to X108 and X123 to X128) and LTx (X107, X108 and X111)
ET_a/b1 and ET_a/b2 Clock signals of ECC1 and ECC2Ein/outCUD_a/b ECC of the CUDV11E V.11 interface eastV11W V.11 interface westTXD TransmitRXD ReceiveTXC Transmit clockRXC Receive clock
Line cards LTx1 to LTx3 Modules of the LT2ME1
Pin X103 to X108 X123 to X128 X107, X108, X111 Sign. G703 Uk2 SDSL T42) Eth.1)
1 GND GND GND_S H1a1 F1in_a1 F1in_a1 SHDSL_a1 T4out_a Rx_a_1
2 LC(y)A1_A1 LC(y)C1_A13 H1b2 (F1in_b2)1) H1b1 F1in_b1 F1in_b1 SHDSL_b1 T4out_b Rx_b_1
3 LC(y)A3_A2 LC(y)C3_A14 H2a1 F1out_a1 F1out_a1 SHDSL_c12) Tx_a_1
4 LC(y)A7_A3 LC(y)C9_A15 H2b2 {F1out_b2}1) H2b1 F1out_b1 F1out_b1 SHDSL_d12) Tx_b_1
5 LC(y)A11_A4 LC(y)C13_A16 H1a2 F1in_a2 F1in_a2 SHDSL_a2 T4out_a Rx_a_2
6 LC(y)A13_A5 LC(y)C17_A17 H1b2 F1in_b2 F1in_b2 SHDSL_b2 T4out_b Rx_b_2
7 LC(y)A19_A6 LC(y)C19_A18 H2b1 {F1out_b1} H2a2 F1out_a2 F1out_a2 SHDSL_c22) Tx_a_2
8 LC(y)A23_A7 LC(y)C23_A19 H2b2 F1out_b2 F1out_b2 SHDSL_d22) Tx_b_2
9 LC(y)A25_A8 LC(y)C25_A20 2) only with SDSL4op
10 LC(y)A29_A9 LC(y)C29_A21
11 LC(y)A31_A10 LC(y)C31_A22
12 LC(y)A15_A11 LC(y)C7_A23
13 LC(y)A17_A12 LC(y)C15_A24
14 LC(y)A2_B1 LC(y)C2_B13 H1a2 (F1in_a2)1)
15 LC(y)A4_B2 LC(y)C4_B14
16 LC(y)A8_B3 LC(y)C10_B15 H2a2 {F1out_a2}1)
17 LC(y)A12_B4 LC(y)C14_B16
18 LC(y)A14_B5 LC(y)C18_B17
19 LC(y)A20_B6 LC(y)C20_B18 H2a1 {F1out_a1}
20 LC(y)A24_B7 LC(y)C24_B19
21 LC(y)A26_B8 LC(y)C26_B20
22 LC(y)A30_B9 LC(y)C30_B21
23 LC(y)A32_B10 LC(y)C32_B22
24 LC(y)A16_B11 LC(y)C8_B23 H1a1 {F1in_a1}
25 LC(y)A18_B12 LC(y)C16_B24 H1b1 (F1in_b1)
1) The interface exists only at X111
Tab. 3.10 SNUS Connectors X103 to X108, X123 to X128, X103, X123, X107, X108 and X111
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Signal Abbreviations
Interfaces 2 Mbit/s G.703 (PU16/1: X109, X129, X110, X130 and PU16/2: X113, X133, X114, X134)
GND Operation groundGND-S Shielded ground(y) y = 1...6 e.g. LC2C1_3
For LC1...LC6 Signal from pin C1 of the line card 2A-wire from wire pair 3
H1a1, H1b1 1. interface of the LT2ME1, 1.wire pair (with 4-w. incoming)H2a1, H2b1 1. interface of the LT2ME1, 2.wire pair (with 4-w. outgoing)H1a2, H1b2 2. interface of the LT2ME1, 1.wire pair (with 4-w. incoming)H2a2, H2b2 2. interface of the LT2ME1, 2.wire pair (with 4-w. outgoing)T4out_a, b Clock output from the T4 moduleRx_a_1/2, b_1/2 Ethernet data receive direction, 1. or 2. interfaceTx_a_1/2, b_1/2 Ethernet data transmit direction, 1. or 2. interface
Interfaces 2 Mbit/s G.703
Pin X109/X113 X129/X133 X110/X114 X130/X134
1 GND_S GND_S GND_S GND_S
2 E1out1_a E1out5_a E1out9_a E1out13_a
3 E1in1_a E1in5_a E1in9_a E1in13_a
4 E1out2_a E1out6_a E1out10_a E1out14_a
5 E1in2_a E1in6_a E1in10_a E1in14_a
6 E1out3_a E1out7_a E1out11_a E1out15_a
7 E1in3_a E1in7_a E1in11_a E1in15_a
8 E1out4_a E1out8_a E1out12_a E1out16_a
9 E1in4_a E1in8_a E1in12_a E1in16_a
10
11
14 E1out1_b E1out5_b E1out9_b E1out13_b
15 E1in1_b E1in5_b E1in9_b E1in13_b
16 E1out2_b E1out6_b E1out10_b E1out14_b
17 E1in2_b E1in6_b E1in10_b E1in14_b
18 E1out3_b E1out7_b E1out11_b E1out15_b
19 E1in3_b E1in7_b E1in11_b E1in15_b
20 E1out4_b E1out8_b E1out12_b E1out16_b
21 E1in4_b E1in8_b E1in12_b E1in16_b
24
25
Tab. 3.11 SNUS Connectors X109, X110, X 113, X114, X129, X130, X133, X134
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Port 5 to 8 of the PU16/1 in slot 210 (connector X129) are internal connected to the first2-Mbit/s interface of the CUD and of the 3 LTx. Port 9 to 12 (connector X110) and port13 to 16 (connector X130) are internal connected with the ADM.
Port 5 to 8 of the PU16/2 in slot 213 (connector X133) are internal connected to the sec-ond 2-Mbit/s interface of the CUD and of the 3 LTx. Port 9 to 12 (connector X114) andport 13 to 16 (connector X134) are internal connected with the ADM.
Signal Abbreviations
Interfaces 2 Mbit/s G.703 (TU: X115, X116, X117, X135, X136 and ADM: X137)
GND Operation groundGND-S Shielded groundE1outy_a and b (y = 1 to 16) a and b wire output 2 Mbit/s G.703 from port yE1iny_a and b (y = 1 to 16) a and b wire input 2 Mbit/s G.703 from port y
Interfaces 2 Mbit/s G.703
Pin X115 X135 X116 X136 X117 X137
1 GND_S GND_S GND_S GND_S GND_S GND_S
2 E1out22_a E1out26_a E1out30_a E1out34_a E1out38_a E1out17_a
3 E1in22_a E1in26_a E1in30_a E1in34_a E1in38_a E1in17_a
4 E1out23_a E1out27_a E1out31_a E1out35_a E1out39_a E1out18_a
5 E1in23_a E1in27_a E1in31_a E1in35_a E1in39_a E1in18_a
6 E1out24_a E1out28_a E1out32_a E1out36_a E1out40_a E1out19_a
7 E1in24_a E1in28_a E1in32_a E1in36_a E1in40_a E1in19_a
8 E1out25_a E1out29_a E1out33_a E1out37_a E1out41_a E1out20_a
9 E1in25_a E1in29_a E1in33_a E1in37_a E1in41_a E1in20_a
10 E1out42_a E1out21_a
11 E1in42_a E1in21_a
12
13
14 E1out22_b E1out26_b E1out30_b E1out34_b E1out38_b E1out17_b
15 E1in22_b E1in26_b E1in30_b E1in34_b E1in38_b E1in17_b
16 E1out23_b E1out27_b E1out31_b E1out35_b E1out39_b E1out18_b
17 E1in23_b E1in27_b E1in31_b E1in35_b E1in39_b E1in18_b
18 E1out24_b E1out28_b E1out32_b E1out36_b E1out40_b E1out19_b
19 E1in24_b E1in28_b E1in32_b E1in36_b E1in40_b E1in19_b
20 E1out25_b E1out29_b E1out33_b E1out37_b E1out41_b E1out20_b
21 E1in25_b E1in29_b E1in33_b E1in37_b E1in41_b E1in20_b
22 E1out42_b E1out21_b
23 E1in42_b E1in21_b
Tab. 3.12 SNUS Connectors X115 to X117, X135 to X137
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Signal Abbreviations
D-Sub connectors X103 to X108 and X123 to X128 depending on the line card
GND Operation groundGND-S Shielded groundE1outy_a and b (y = 22 to 42) a and b wire output 2 Mbit/s G.703 from port 1 to 21
of the TUE1iny_a and b (y = 22 to 42) a and b wire input 2 Mbit/s G.703 from port 1 to 21
of the TUE1outy_a and b (y = 17 to 21) a and b wire output 2 Mbit/s G.703 from port y of ADME1iny_a and b (y = 17 to 21) a and bwire input 2 Mbit/s G.703 from port y of ADM
CPF2 UAC68 SUB102, SLX102/E SLB62
Pin X103 to X108 X123 to X128 X103 to X108 X123 to X128 X103 to X108 X103 to X108
1 GND GND GND GND GND GND
2 SN0_in_a SN2_in_a F2in_a1 F2in_a4 SB_a1 SB_a1
3 SN0_CNTL_a SN2_CNTL_a F2out_a1 F2out_a4 SB_a2
4 SN0_out_a SN2_out_a F2in_a2 F2in_a5 SB_a3 SB_a2
5 SN0_XCLK_a SN2_XCLK_a F2out_a2 F2out_a5 SB_a4 SB_a3
6 SN0_IND_a SN2_IND_a F2in_a3 F2in_a6 SB_a5
7 SN0_SCLK_a SN2_SCLK_a F2out_a3 F2out_a6 SB_a6 SB_a4
8 SN1_out_a SN3_out_a S2in_a1 S2in_a4 SB_a7
9 SN1_in_a SN3_in_a S2out_a1 S2out_a4 SB_a8 SB_a5
10 SN1_CNTL_a SN3_CNTL_a S2in_a2 S2in_a5 SB_a9
11 SN1_XCLK_a SN3_XCLK_a S2out_a2 S2out_a5 SB_a10 SB_a6
12 SN1_IND_a SN3_IND_a S2in_a3 S2in_a6
13 SN1_SCLK_a SN3_SCLK_a S2out_a3 S2out_a6
14 SN0_in_b SN2_in_b F2in_b1 F2in_b4 SB_b1 SB_b1
15 SN0_CNTL_b SN2_CNTL_b F2out_b1 F2out_b4 SB_b2
16 SN0_out_b SN2_out_b F2in_b2 F2in_b5 SB_b3 SB_b2
17 SN0_XCLK_b SN2_XCLK_b F2out_b2 F2out_b5 SB_b4 SB_b3
18 SN0_IND_b SN2_IND_b F2in_b3 F2in_b6 SB_b5
19 SN0_SCLK_b SN2_SCLK_b F2out_b3 F2out_b6 SB_b6 SB_b4
20 SN1_out_b SN3_out_b S2in_b1 S2in_b4 SB_b7
21 SN1_in_b SN3_in_b S2out_b1 S2out_b4 SB_b8 SB_b5
22 SN1_CNTL_b SN3_CNTL_b S2in_b2 S2in_b5 SB_b9
23 SN1_XCLK_b SN3_XCLK_b S2out_b2 S2out_b5 SB_b10 SB_b6
24 SN1_IND_b SN3_IND_b S2in_b3 S2in_b6
25 SN1_SCLK_b SN3_SCLK_b S2out_b3 S2out_b6
Tab. 3.13 SNUS Connectors X103 to X108, X123 to X128 (Part 1)
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I8S0P I4UK2NTP, I4UK4NTP IUL82C, IUL84C
Pin X103 to X108 X123 to X128 X103 to X108 X103 to X108
1 GND GND GND GND
2 S0a1 S0a5 Uk0_a1 D2a1
3 S0c1 S0c5 D2a2
4 S0a2 S0a6 Uk0_a2 D2a3
5 S0c2 S0c6 D2a4
6 S0a3 S0a7 D2a5
7 S0c3 S0c7 Uk0_a3 D2a6
8 S0a4 S0a8 D2a7
9 S0c4 S0c8 D2a8
10
11 Uk0_a4
12
13
14 S0b1 S0b5 Uk0_b1 D2b1
15 S0d1 S0d5 D2b2
16 S0b2 S0b6 Uk0_b2 D2b3
17 S0d2 S0d6 D2b4
18 S0b3 S0b7 D2b5
19 S0d3 S0d7 Uk0_b3 D2b6
20 S0b4 S0b8 D2b7
21 S0d4 S0d8 D2b8
22
23 Uk0_b4
24
25
Tab. 3.14 SNUS Connectors X103 to X108, X123 to X128 (Part 2)
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CM64/2 DSC104C DSC6-nx64C
Pin X103 to X108 X123 to X128 X103 to X108 X123 to X128 X103 to X108 X123 to X128
1 GND GND GND GND GND GND
2 D2out_a1 D2in_a1 D2out_a1 D2in_a1
3 D2out_a2 D2in_a2 D2out_a2 D2in_a2
4 D2out_a3 D2in_a3 D2out_a3 D2in_a3
5 D2out_a4 D2in_a4 D2out_a4 D2in_a4
6 D2out_a5 D2in_a5 D2out_a5 D2in_a5
7 D2out_a6 D2in_a6 D2out_a6 D2in_a6
8 D2out_a7 D2in_a7 T21_a1 Tin_a
9 D2out_a8 D2in_a8 T22_a1
10 D2out_a9 D2in_a9 T21_a2
11 D2out_a10 D2in_a10 T22_a2
12
13
14 F2in_a F2in_b D2out_b1 D2in_b1 D2out_b1 D2in_b1
15 F2out_a F2out_b D2out_b2 D2in_b2 D2out_b2 D2in_b2
16 Yout1_b D2out_b3 D2in_b3 D2out_b3 D2in_b3
17 Yout2_a Yout2_b D2out_b4 D2in_b4 D2out_b4 D2in_b4
18 Yout3_a Yout3_b D2out_b5 D2in_b5 D2out_b5 D2in_b5
19 Yout4_a Yout4_b D2out_b6 D2in_b6 D2out_b6 D2in_b6
20 Yin1_a Yin1_b D2out_b7 D2in_b7 T21_b1 Tin_b
21 Yin2_a Yin2_b D2out_b8 D2in_b8 T22_b1
22 Yin3_a Yin3_b D2out_b9 D2in_b9 T21_b2
23 Yin4_a Yin4_b D2out_b10 D2in_b10 T22_b2
24
25
Tab. 3.15 SNUS Connectors X103 to X108, X123 to X128 (Part 3)
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3.1.10 Technical Data
3.1.10.1 Environmental Conditions
3.1.10.2 Foreign Voltage Protection
3.1.10.3 Power Supply
Operation acc. to ETSI EN 300 019-1-3 V2.1.2 (04/2003), class 3.1 (+5 ° C to +40 ° C)
Transport acc. to ETSI EN 300 019-1-2 V2.1.4 (04/2003)class 2.3 (−40 ° C bis +70 ° C)
Storage acc. to ETSI EN 300 019-1-1 V2.1.4 (04/2003)class 1.3E (−45 ° C bis +45 ° C)
Product safety acc. to EN 60950-1:2001 (1st edition)EMV compatibility acc. to ETSI EN 300 386 V1.3.2 (05/2003) and
DTAG 1TR9 (Ed. 09.2001 Rev. 06/2002)
Protection against external voltages on the outdoor subscriber lines (OTC applications) is implemented in 2 stages within the entire system. For further information see Section 1.4.7 and UMN:IMN.
Classification for external voltage protection acc. to EN 300 386 V1.3.2 (05/2003) ITC applications according ITU-T K.20 (07/2003), basic1) levelOTC applications according ITU-T K.45 (07/2003), basic1) level
Compliance with the earth conditions according ITU-TIndoor applications (inside subscriber building) K.31 (03/1993)ITC applications (inside telecommunication building) K.27 (05/1996)Outdoor applications (remote electronic sites) K.35 (05/1996)
Units, which are not meet the requirements above, contain specific information about the foreign power protection, see technical data of the line cards.
Rated input voltage −48 V /−60 VPermissible voltage range −36 V to −72 V
1) On enquiry, some line cards can also be used according enhanced level.
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3.2 FMX2S SubrackThe FMX2S is a subrack in 19“ construction, using adapters it is adapted to the fittingconditions for the ETSI housing and racks with a minimum depth of 300 mm.
Shelf FMX2S serves to accommodate the units of:• One multiplexer with up to 12 line cards or
two multiplexers with up to 6 line cards each.• Up to 6 x 2-Mbit/s line terminating units LTx, with one of the following transmission
capabilities– 2 × 2 Mbit/s on one glass fiber– HDB3 coded (UK2) on 2-core local loops, 2 interfaces per line termination unit– SHDSL (2-wire/4-wire), 2 interfaces per line termination unit.Special modules for line termination unit with Ethernet 10/100Base-T interface can be used to transmit Ethernet data over TDM via one of the following feeder interfaces (2 Mbit/s or STM-1/STM-4 optical, SHDSL, Uk2 or STM-1 electrical).
Special modules for line termination unit with Ethernet 10/100Base-T interface can beused to transmit Ethernet data over TDM via optional feeder interface (2 Mbit/s optical,SHDSL or Uk2 electrical).
Fig. 3.13 Shelf FMX2S (without Front Panel)
The subrack can accept units in double Eurocard format, and has a backplane board toconnect the internal and external interfaces.
The FMX2S is equipped with a terminal panel which provides all external interfaces viathe corresponding sub-D connectors. The optical interfaces of the corresponding unitswhich are directly accessible on the units themselves. For mechanical routing of the op-tical fibers the FMX2S is equipped with FO clips.
For the CPF2 data interfaces, different front panels are available, which can be pluggedinto an external Main Distribution Field (MDF 180 or MDF 210), see UMN:IMN. For ca-bling the connectors in the shelf terminal panel to the front panels, the adapter cableS42023-A862-S11 has to be used.
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3.2.1 FittingThe FMX2S has 18 slots, which are fitted in the following way:
Fig. 3.14 FMX2S Equipping
2 3 4 5 6 7 8 9 10 11 12 13 1714 161
1) LT2ME1/LTO, only one port of the LT2ME1 can be used
3) optionally, if more than 6 LCs are to be connected to the CUD (slot 2)
1815
alternatively fitting
CU
D
LC 1
LC 2
LC 3
LC 4
LC 5
LC 6
CU
D
LC 1
LC 2
LC 3
LC 4
LC 5
LC 6LC
TS
UE LT
x 11)
LTx
21)
LTx
31)
LTx
42)
LTx
52)
LTx
62)
BE
C3)
2) LT2ME1/LTO, two ports of the LT2ME1 can be used
!For slots 8, 14 and 15, into which both channel cards and line termination units can be inserted, before the units are inserted the associated DIL switches must be checked, see Section 3.2.7.
Plug-in unit1) Plug-in place Fil-
ter5)
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
V42
256-
Z82
-M1
V42
256-
Z82
-M2LC/LTx
LC
1-1
LC
2-1
LC
3-1
LC
4-1
LC
5-1
LC
6-1
LTx1
LC
1-2
LC
2-2
LC
3-2
LC
4-2
LC
5-2
LTx2
LC
6-2
LTx3
LTx4
LTx5
LTx6
Sub-D 2-wire (a, b)
or LTx
E1 E1 G1 H1 J1 K1 N1 P1 Q1 R1 S1 T1
M1 M1
Sub-D 4-wire (c, d)
or LTx
E2 F2 G2 H2 J2 K2
L2
N2 P2 Q2 R2 S2
L2
T2
M2 M2
SUE ×
CUD × ×
BEC ×
UAC68 × × × × × × × × × × × × ×
SUB102 × × × × × × × × × × × × ×
SLB62 × × × × × × × × × × × × ×
LLA102/104C × × × × × × × × × × × × ×
I8S0P × × × × × × × × × × × ×
I4UK2NTP × × × × × × × × × × × × ×
Tab. 3.16 FMX2S Equipping, and Assignment of Connectors in the Terminal Panel
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IUL82C × × × × × × × × × × × × ×
IUL84C × × × × × × × × × × × × ×
I4UK4NTP × × × × × × × × × × × × ×
CM 64/2 × × × × × × × × × × × ×
SLX102/E × × × × × × × × × × × × ×
DSC104C × × × × × × × × × × × ×
DSC6nx64C × × × × × × × × × × × ×
CPF24) × × × × × × × × × × × × ×
LT2ME1 × 2) × 2) × 2) × 3) × ×
LTO × × × × × ×
1) Pay attention to switch positions at equipping variants! 4) Up to 4 modules for CPF2: -CIM V.24, CIM X.21, CIM V.35, CIM V.36,
2) On these slots, only one module for copper transmission up to 2 modules CIM-nx64E
lines can be equipped:- Uk2mp, - G703sh, -SDSLmp, 5) Filter types according to LC types that must be plugged and
SDSLop, -SDSL4op, -T4 module can be plugged screwed on to Sub D in terminal panel
optionally on plug-in places 216 to 218
3) This slot can be plugged with an LT2ME1 with
one Ethernet module and one SDSL module
Plug-in unit1) Plug-in place Fil-
ter5)
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
V42
256-
Z82
-M1
V42
256-
Z82
-M2LC/LTx
LC
1-1
LC
2-1
LC
3-1
LC
4-1
LC
5-1
LC
6-1
LTx1
LC
1-2
LC
2-2
LC
3-2
LC
4-2
LC
5-2
LTx2
LC
6-2
LTx3
LTx4
LTx5
LTx6
Sub-D 2-wire (a, b)
or LTx
E1 E1 G1 H1 J1 K1 N1 P1 Q1 R1 S1 T1
M1 M1
Sub-D 4-wire (c, d)
or LTx
E2 F2 G2 H2 J2 K2
L2
N2 P2 Q2 R2 S2
L2
T2
M2 M2
Tab. 3.16 FMX2S Equipping, and Assignment of Connectors in the Terminal Panel (Cont.)
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3.2.2 Ethernet Applikations of LT2ME1Slot 216 (LTx4) can be used for Ethernet applications. The LT2ME1 must be equippedwith an Ethernet module (module slot 1) and an SDSL module (module slot 2). AnEthernet adapter (see Fig. 3.85) must be used for this application. Port 2 of the Ethernetadapter provides the 10/100Base-T interface. The G.703 interfaces are connected viathe Digital Distribution Frame (DDF). The cabling allows also to plug-in two LT2ME1 inslot 217 (LTx5) and slot 218 (LTx6), each with two SDSL modules for feeding the2-Mbit/s ports of the CUD.
Fig. 3.15 LT2ME1 on Slot 216, One Ethernet Module
3.2.3 Clock SynchronizationA 2.048 MHz clock can be fed to T3in1 and T3in2 via a D-sub plug in the terminationpanel. The T3in1 clock supplies the line termination units and a level converter on thebackplane. A loop T3in2 supplies the two CUDs with the 2.048 MHz clock and passesthe clock on to external facilities.
Fig. 3.16 FMX2S Clock Distribution
At another D-sub connector in the termination panel, T4out can be extracted from thetwo CUDs, and T4out from LTx 5 and 6.
On plug-in places LTx4, LTx5 and LTx6, the LT2ME1 can receive the clock via the levelconverter as CMOS signal T3CM. For that, the DIL switch S3 must be set accordingly,see user manual UMN:LE2.
Module 1Ethernet
Module 2SDSL
LT2ME1
100bT (port 2) SHDSL
DDF
216
G.703 G.703
Levelconverter
Connectors in termination panel
CUD 2 LTx 4 LTx 5 LTx 6LTx 1 LTx 2 LTx 3CUD 1
T4
T3
T3in_1
T3in_2 (input)
T4o
ut_1
T4o
ut_2
T4o
ut_6
T4o
ut_5
120
Ω
T3in_3 (output)
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3.2.4 QD2 AccessThe internal wiring for operation and monitoring is shown in Fig. 3.17.
Fig. 3.17 FMX2S QD2 Access
The TMN access for the subrack is the QD2 slave plug in the termination panel. Thisleads to the QD2 slave port 1 of the SUE.
The internal QD2 bus can be connected via switches either to the QD2 master port ofthe SUE (in standalone operation of the subrack) or to QD2 access, e.g. from COMPS2within an ONU or SNU. In standalone operation, the QD2 bus connects the QD2 slaveinterfaces of the FMX2R3.2 to the QD2 master interface of the SUE supervision unit.
The QD2 slave port 2 is in the QD2-M connector. Via this port, one of the internal controlchannels can be connected using an appropriately assigned connector.
The following internal control channels can be used:• ECC channels of CUDs
– ECC 2 of CUD 1 (slot 2)– ECC 3 of CUD 2 (slot 9)
• OH64 overhead channels of LTx 4 (slot 16) and LTx 6 (slot 18).
3.2.5 AddressingAll units in this subrack, except SUE and CUD, are assigned slot addresses. For the ad-dresses which are assigned to the slots, see Section 3.2.7. The SISA address of theSUE is set using the DIL switch in the termination panel. The addresses of the CUDsare set using the DIL switch in the backplane.
For line termination units in line card slots, some address bits are given by the coding ofthe line cards. This makes it necessary to change address bits to adapt the addressing,if line termination units are installed in these slots. The change is done using DIL switch-es for fitting LCs or LTx, see Section 3.2.7.
SUECUD LTx CUD LTx LTx LTx LTxLTx
QD
2-S
QD
2-M
EC
C
V.1
1
QD2 bus
QD2 bus
QD
2-S
2
QD
2-S
1 (T
)
QD
2-M
OH
64 4
S1 S2M
EC
C 2
EC
C 3
OH
64 6
Connectors in termination panel
F IF(for LCT)
1 1 2 2 3 4 5 6
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3.2.6 Power SupplyThe −48 V input voltages are fed via two separate 3W3 plugs in the termination panel.The positive poles of both voltages are connected to each other and to the backplane,via a common filter and protection device, as the operating ground GND. The negativepoles of both voltages are filtered separately, and supply the units in the subrack asMUP1 and MUP2.
Whereas the SUE can be fed via its own reserve diodes from both voltages, the inputvoltages for the CUD and the line termination units are applied to the two voltages MUP1and MUP2 via reserve diodes on the backplane. The line cards receive the required sec-ondary voltages +5 V and –5 V from the CUD or BEC.
Without forced ventilation and with homogeneous distribution of heat sources in the sub-rack, about 105 W of power dissipation (1.25 W per 5.08 mm of basic grid) are permitted.
Fig. 3.18 FMX2S Power Supply
LTx 4 LTx 5 LTx 6CUD LTx 1 LTx 2 LTx 3
MUP 2
SUE
MUP 1
48 V
+48 V
+
CUD
Connectors in termination panel
EMCprotection
EMCprotection
EMCprotection
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3.2.7 Switch Settings
Fig. 3.19 FMX2S Front View without Front Panel
System 1
‹W
System 2LE
ECC
S100
QD2-S1+T-Port
ext.
48V/60V15po
l
15po
l
9pol
X102X101 X103
15po
l
X136X119
X141
48V/60V
X142
X21
8X
318
18
LT6
X21
7X
317
17
LT5
X21
6X
316
16
LT4
X21
5X
315
15
LC6-2LT3
X21
3X
313
13
LC4-2
X20
8X
308
8
LC6-1LT1
X20
1X
301
SUE
3W3
3W3
9pol
X120 X137
OHLT3LT5
ZA
25po
l
9pol
X138
HDSLLT1-3
X139
25po
l
X140
25po
l
HDSLLT4-6
a-row LC 1 to 6 system 1
X118
25po
l
25po
l
25po
l
25po
l
25po
l
25po
l
X123 X124
25po
l
25po
l
25po
l
25po
l
25po
l
25po
l
25po
l
25po
l
25po
l
X125 X126 X128
25po
l
25po
l
25po
l
25po
l
X130 X131 X132
25po
l
X129
25po
l
25po
l
25po
l
25po
l
25po
l
25po
l
X133 X134 X135
c-row LC 1 to 6 system 1
a-row LC 1 to 6 system 2
c-row LC 1 to 6 system 2
T3ab
X10415
pol
PB
9pol
X121
X105 X106 X107 X108 X109 X112 X113 X114X111 X115 X116 X117
T3an25
pol
25po
l
X127
X110
E1LT3,4
E1LT1,2
E1LT5,6
E1CUD
SUE addresses
X21
0
X20
3X
303
LC1-1
16 8 4 2 1
QD2-S2QD2-Mo
X31
414
LC5-2LT2
X21
4
X20
2X
302
CUD
X20
4X
304
4
LC2-1
X20
5X
305
5
LC3-1
X20
6X
306
6
LC4-1
X20
7X
307
7
LC5-1
S20
8_1
4pol
X21
2X
312
12
LC3-2
X21
1X
311
11
LC2-2
X31
0
LC1-2
X20
9X
309
9
CUD-2BEC
ON
ON ON
ON
ON
ON ONON
ONON
ON
LTLCLTLC
LTLC
ON ONON
LTLCLTLC
Al. 1-3
4pol
S20
8_3
S20
8_4
8pol
S20
8_2
2pol
S30
94p
ol
S30
8_1
2pol
S30
8_2
2pol
ON
S30
18p
ol
S30
24p
ol
X40
3
X41
0
S21
5_2
2pol
S21
5_4
8pol
S21
5_3
4pol
S21
5_1
4pol
S21
4_2
2pol
S21
4_4
8pol
S21
4_3
4pol
S21
4_1
4pol
S31
52p
olS
314_
22p
olS
314_
12p
ol
ON
ON
S21
82p
ol
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Switch Adaptation to the Equipment in the FMX2
Backplane Addressing of the Units
All units in this subrack are assigned addresses via the backplane:
Switch What is switched Contacts Position, see also
Fig. 3.19
S100 ADR SUE: I4, I3, I2, I1, I0 5-pin In the terminal panel
S301 QD2S-in-out-a-b (ONU/standalone) 8-pin Between X201 and X301
S302 ADR CUD1: A4_1 = GND, A3_1, A2_1, A1_1, A0_1 4-pin Between X202 and X302
S208_1 LC6*/LTx1*/QD2M 4-pin To the right of X208,above
S208_2 LC6*/LTx1*/T3in 2-pin To the right of X208,below
S208_3 LC6*/LTx1*/SHDSL 4-pin To the right of X208,center
S208_4 LC6*/LTx1*/2 MBit/s 8-pin To the right of X208,center
S308_1 ADR1A0 2-pin To the right of X307
S308_2 (PB2/LTK1) PB2LTK11 2-pin To the right of X307
S309 ADR CUD2: A4_2 = GND, A3_2, A2_2, A1_2, A0_2 4-pin Between X308 and X309
S214_1 LC5*/LTx2*/QD2M 4-pin To the right of X214,above
S214_2 LC5*/LTx2*/T3in 2-pin To the right of X214,below
S214_3 LC5*/LTx2*/SHDSL 4-pin To the right of X214,center
S214_4 LC5*/LTx2*/2 MBit/s 8-pin To the right of X214,center
S314_1 ADR0A4 2-pin To the right of X314,below
S314_2 (PB2/LTK1) PB2LTK12 2-pin To the right of X314,center
S215_1 LC6*/LTx3*/QD2M 4-pin To the right of X215,above
S215_2 LC6*/LTx3*/T3in 2-pin To the right of X215,below
S215_3 LC6*/LTx3*/SHDSL 4-pin To the right of X215,center
S215_4 LC6*/LTx3*/2 MBit/s 8-pin To the right of X215,center
S315 (PB2/LTK1) PB2LTK13 2-pin To the right of X314,above
S218 T3ina/b_1, 120 Ohm termination 2-pin To the right of X218
Tab. 3.17 FMX2S Overview of the Switches
Address
setting
Unit model
SUE CUD1 CUD2 LT
Address type Variable Variable Variable Fix,
slot address
Address width 5 Bit 5 bit
(MSB on GND
5 Bit
(MSB on GND
Address type QD2 (SISA)
address
Unit address Unit address Unit address
Tab. 3.18 FMX2S Address Settings for the Units
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Switching Over Addresses for Slots 208, 214 and 215
Slot 208
The following applies to slot 208 (also see Fig. 3.19):• Address switch S308_1 for LTx operation set to 'ON' (right)• Address switch S308_1 for LC operation set to 'OFF' (left)
Slot 214
The following applies to slot 214 (also see Fig. 3.19):• Address switch S314_1 for LTx operation set to 'ON' (right)• Address switch S314_1 for LC operation set to 'OFF' (left)
Slot 215• No address switching is necessary for slot 215.
S301: FMX2S Operating Mode
Address switch S100
in the terminal panel
S302
in the terminal panel
S309
in the terminal panel
None
As-delivered
condition
0-0-1-0-0 (stand-alone)
0-0-0-1-0
(stand-alone)
0-1-0-0-1
-
Address
setting
Unit model
SUE CUD1 CUD2 LT
Tab. 3.18 FMX2S Address Settings for the Units
iImportant advice for LTx addresses.Since line cards and LTXs can be inserted into slots 208, 214 and 215, addresses must also be switched here manually, in order to ensure the correct address detection.
12
11
10
9
5
6
7
8
QD2Mout_a1
QD2Mout_b1
QD2Min_a1
QD2Min_b1
16
15
14
13
1
2
3
4
QD2Sin_a
QD2Sin_b
QD2Sout_a
QD2Sout_b
QD2Sin_a1
QD2Sin_b1
QD2Sout_a1
QD2Sout_b1
S301ON
161
152
Standalone
143
134
125
116
107
98
As-delivered condition: Standalone
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S100: SUE Address
S302: CUD Address Switch in the 1st System
S309: Switch for the CUD Address in the 2nd System
S308_1: Address Adaptation for LC/LTx Equipping in Slot 208
109
12
I4I3
S100
GND
87
34
I2I1
65I0
ON10
1
9
2
Value
8
3
7
4
6
5
16 8 4 2 1
Example: Address = 4
As-delivered condition: Address 4
87
12
A3_1A2_1
S302
GND
65
34
A1_1A0_1
Address A4_1 (16)is on GND!
Closed = 'ON'
ON
81
72
63
54
Example: Address = 2
Value
8
4
2
1
As-delivered condition: Address 2
87
12
A3_1A2_1
S309
GND
65
34
A1_1A0_1
Address A4_2 (16)is on GND!
Closed = 'ON'
ON
81
72
63
54
Value
8
4
2
1
As-delivered condition: Address 9Example: Address = 9
ADR1A0
GND
S308_1
41
32
ON
41
32
ON
41
32
LTx1 LC
As-delivered condition: LC
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S308_2: Switching Internal Signals for LTx Shelf in Slot 208
S314_1: Address Adaptation for LC /LTx Equipping in Slot 214
S314_2: Switching Internal Signals if LTx is Used in Slot 214
S315: Switching Internal Signals if LTx is used in Slot 215
(Warning! Switches turned!)
As-delivered condition: LC
S308_2
23
14
LTx1 LC
ON
4 1
3 2
ON
4 1
3 2PB2 X108 B10
PB2LTK11
Switching for LC 6-1 (PB2) or LTx1 (LTK1) in slot 8
ADR0A4
GNDAs-delivered condition: LC
S314_1
41
32
ON
41
32
ON
41
32
LTx1 LC
(Warning! Switches rotated!)
Switching for addresses for LC 5-2 or LTx2 in slot 14
(Warning! Switches rotated!)
S314_2
23
14
LTx1 LC
ON
4 1
3 2
ON
4 1
3 2PB2 X114 B10
PB2LTK12
As-delivered condition: LC Switch-over LC 5-2 (PB2) or LTx2 (LTK1) in slot 14
iWarning!The switch is used to switch over internal signals. If an LTx is used in slot 215, it must always be open!
(Warning! Switch rotated!)
S315
23
14
LTx1 LC
ON
4 1
3 2
ON
4 1
3 2PB2 X115 B10
PB2LTK13
As-delivered condition: LC Switch over LC 6-2 (PB2) or LTx3 (LTK1) in slot 15
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S218: T3in Terminator with 120 Ohm
S208_1: Adapting to LC /LTx Equipping in Slot 208
S214_1: Adapting to LC /LTx Equipping in Slot 214
41T3ina_1 T3inb_1
S218
120 Ohm termination closed = ON
121 Ohm
32
ON
41
32
120 OhmAs-delivered condition: Open
iWarning!If LTxs are used in slots 208, 214 and 215 (slots for LTx 1, LTx 2 and LTx 3), no lines may be connected to the 25-pin X110, X117 and X118 sub-D-connectors and likewise to X128, X135 and X136.
Separation of sub-D LC and QD2 bus;
If LC is used (open)
If LTx is used, closed = 'ON'
S208_1
LC208A2_1BQD2Min_a1QD2Min_b1QD2Mout_a1QD2Mout_b1
LC208C2_13BLC208A4_2BLC208C4_14B ON
81
72
ON
81
72
LC LTx
63
54
63
54
4321
5678
As-delivered condition: LC
iWarning!If LTxs are used in slots 208, 214 and 215 (slots for LTx 1, LTx 2 and LTx 3), no lines may be connected to the 25-pin X110, X117 and X118 sub-D-connectors and likewise to X128, X135 and X136.
Separation of sub-D LC and QD2Bus;
if LC is used (open)if LTx is used, closed = 'ON'
S214_1
LC214A2_1BQD2Min_a1QD2Min_b1QD2Mout_a1QD2Mout_b1
LC214C2_13BLC214A4_2BLC214C4_14B
ON
81
72
ON
81
72
LC LTx
63
54
63
54
4321
5678
As-delivered condition: LC
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S215_1: Adapting to LC /LTx Equipping in Slot 215
S208_2: Adapting to LC/LTx Equipping in Slot 208 (T3 clock feed)
S214_2: Adapting to LC /LTx Equipping in Slot 214 (T3 clock feed)
S215_2: Adapting to LC /LTx Equipping in Slot 215 (T3 clock feed)
iWarning!If LTxs are used in slots 208, 214 and 215 (slots for LTx 1, LTx 2 and LTx 3), no lines may be connected to the 25-pin X110, X117 and X118 sub-D-connectors and likewise to X128, X135 and X136.
Separation sub-D LC and QD2 bus;
If LC is used (open)
If LTx is used, closed = 'ON'
S215_1
LC215A2_1BQD2Min_a1QD2Min_b1QD2Mout_a1QD2Mout_b1
LC215C2_13BLC215A4_2BLC215C4_14B
ON
81
72
ON
81
72
LC LTx
63
54
63
54
4321
5678
As-delivered condition: LC
S208_243
12
LC208C30_21B T3ina_1T3inb_1LC208C32_22B
LC: OpenLTx1: Closed = 'ON'
Separation of sub-D LC and T3inA/B_1 if LTx is used
ON
41
32
ON
41
32
LC LTxAs-delivered condition: LC
S214_2
43
12
LC214C30_21B T3ina_1T3inb_1LC214C32_22B
L: Open
LTx1: Closed = 'ON'
Separation of sub-D LC and T3inA/B_1 if LTx is used
ON
41
32
ON
41
32
LC LTx
As-delivered condition: LC
S215_243
12
LC215C30_21B T3ina_1T3outb_1LC215C32_22B
LC: OpenLTx1: Closed = 'ON'
Separation of sub-D LC and T3inA/B_1 if LTx is used
ON
41
32
ON
41
32
LC LTx
As-delivered condition: LC
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S208_3: Adapting to LC /LTx Equipping in Slot 208
iWarning!If slot 208 is equipped with the LC card, the switch must be open to exclude any mutual faults in the X139 (SHDSL) and X110 (LC 6, system 1) sub-D-connectors.
Switch separates lines from slot 208 to the X139 sub-D-connector
If LC is used (open)
If LTx is used, closed = 'ON'
S208_3
LC208A16_11B H1_a1_208ON
81
72
ON
81
72
LC LTx
63
54
63
54
LC208A18_12BLC208A20_6BH2_b_208
(F1out_b_208)
H1_b1_208H2_a1_208H2_b1_208
4321
5678
As-delivered condition: LC
(LTx1, LTx2, LTx3) f¸r SHDSL. (If equipped with LC
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Overview of Switches S208_3, S214_3 and S215_3
LC 6 system 1(a contacts)
X110
Sub-D-connector
LC 5 System 2(a contacts)
a
SHDSL
X139
25 pin
25 pin
25 pin
X117
LTx1
LTx3
LTx2
10
231122
6
19 7
18
2
15 3
14
H1_a1_208
H2_b1_208H2_a1_208H1_b1_208
H1_a1_214
H2_b1_214H2_a1_214H1_b1_214
H1_a1_215
H2_b1_215H2_a1_215H1_b1_215
8
567
1
432
S208_3
8
567
1
432
S215_3
8
567
1
432
S214_3
LC 6 system 2 (a contacts)
a
25 pin
X118
X136 25 pinLC 6 system 2(c contacts)not shown
24
19
2516A
20B18A
16B
LC208A16_11B
LC208A18_12B
20A
26B22A
24B
LC208A20_6B
H2_b_208 (F1out_b_208)
X208
External connector slot 8
Slot 8 LC 6 system 1 or LTx1
16A
20B18A
16B
LC214A16_11B
LC214A18_12B
20A
26B22A
24B
LC214A20_6B
H2b2_14 (F1out_b_214)
X214
Connector 14 LC 5 system 2
16A
20B18A
16B
LC215A16_11B
LC215A18_12B
20A
26B22A
24B
LC215A20_6B
H2b2_15 (F1out_B_215)
X215
Slot 15 LC 6 system 2
24
19
25
24
19
25
If LC is used, switch setting is open.If LTx is used, switch setting is closed = 'ON'.
IF LTx is used, (X110 and X128) and/or (X117 and X135) and/or
A clean separation at X139 is achieved by the switches if there is mixed LC and LTx
External connector slot 14
External connector slot 15
H1a1_1
H2b1_1H2a1_1H1b1_1
H1a1_2
H2b1_2H2a1_2H1b1_2
H1a1_3
H2b1_3H2a1_3H1b1_3
o LTx2or
or LTx3
(X118 and X136) cable must be removed!
equipping.
X135 25 pinLC 5 system 2(c contacts)not shown
X128 25 pinLC 6 system 1(c contacts)not shown
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S214_3: Adapting to LC /LTx Equipping in Slot 214
S215_3: Adapting to LC/LTx Equipping in Slot 215
S208_4: Adapting to LC/LTx Equipping in Slot 208
iWarning!If slot 214 is equipped with the LC card, the switch must be open to exclude mutual faults at the X139 (SHDSL) and X117 (LC 5, system 2) sub-D-connectors.
Separates lines from slot 214 to sub-D-connector X139
If LC is used (open)
If LTx is used, closed = 'ON'
S214_3
LC214A16_11B H1_a1_214
ON
81
72
ON
81
72
LC LTx
63
54
63
54
LC214A18_12BLC214A20_6BH2_b_214
(F1out_b_214)
H1_b1_214H2_a1_214H2_b1_214
4321
5678
As-delivered condition: LC (LTx1, LTx2, LTx3) for SHDSL. (If equipped with LC)
iWarning!If slot 215 is equipped with the LC card, the switch must be open to exclude mutual faults at the X139 (SHDSL) and X118 (LC 5, system 2) sub-D-connectors.
If LC is used (open)
If LTx is used, closed = 'ON'
S215_3
LC215A16_11B H1_a1_208 ON
81
72
ON
81
72
LC LTx
63
54
63
54
LC215A18_12BLC215A20_6BH2_b_215
(F1out_b_215)
H1_b1_208H2_a1_208H2_b1_208
4321
5678
As-delivered condition: LC
Separates lines from slot 215 to the X139 sub-D-connector(LTx1, LTx2, LTx3) for SHDSL. (If equipped with LC)
If LC is used (open)
If LTx is used, closed = ‘ON’
S208_4
LC208A24_7B E1inB1_a2
4321
13141516
ON
161
152
LC LTx
143
134
LC208A26_8BLC208A30_9BLC208A32_10B
E1inA1_b2E1inB1_a1E1inA1_b1
125
116
107
98
ON
161
152
143
134
125
116
107
98
8765
9101112
LC208C24_19BLC208C26_20BE1out1_a1E1out1_b1
E1outB1_a2E1outA1_b2E1outB1_a1E1outA1_b1
} in2
} in1
} out2
} out1
in / out from LTx1
Separates lines from slot 208 to sub-D-connector X129
As-delivered condition: LC
(LTx1, LTx2) for 2 MBit/s (E1). (If equipped with LC)
iWarning!IF slot 208 is equipped with LC, the switch must be open to exclude mutual faults at the X129 (2 Mbit/s E1), X110 and X128 sub-D-connectors (both LC 6, system 1).
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Overview of the S208_4 and S214_4 Switches
LC 6 system 1 (a contacts)
X110
Sub-D-connector
E1(2 Mbit/s)
X129
25 pin
25 pin
LTx1
LTx2
3
164
15
214
E1inA1_a1
E1outB1_b2E1outB1_a2E1inA1_b1
E1outA1_a1E1outA1_b1
14
111213
3
654
S208_4
109
78
20
in
24A
26A
LC208A24_7B
LC208A26_8B
30A
32A
LC208A30_9B
LC208A32_10B
X208
External connector slot 8
Slot 8 LC 6 system 1 or LTx1
If LC is used, switch setting is open.If LTx is used, switch setting is closed = 'ON'.
If LTx is used, (X110 and X128)and/or (X117 and X135) cable must be removed!
A clean separation at X129 is achieved by the switches if
22
21
23
LC 6 system 1 (c contacts)
X128
25 pin
20
out
24C
26C
LC208C24_19B
LC208C26_20B
30C
32C
LC208C30_21B
LC208C32_22B22
21
23
28A
28B/28C
E1out1_a1
E1out1_b15
17E1inB1_a2E1inB1_b2
1615
12 }in2
}in1
} out2
} out1
20
719
8
219
E1outB2_b2
E1inA2_a1E1inA2_b1E1outB2_a2
E1inB2_b2E1inB2_a2
14
111213
3
654
109
78
186
E1outA2_b1E1outA2_a1
1615
12 } out1
} out2
}in1
}in2
S214_4 LC 5 System 2 (a contacts)
X117
25 pin.
20
in22
21
23
LC 5 system 2 (c contacts)
X135
25 pin
20
out22
21
23
24A
26A
LC214A24_7B
LC214A26_8B
30A
32A
LC214A30_9B
LC214A32_10B
X214
Slot 14 LC 5 system 2 or LTx2
24C
26C
LC214C24_19B
LC214C26_20B
30C
32C
LC214C30_21B
LC214C32_22B
28A
28B/28C
E1out2_a1
E1out2_b1
External connector slot 14
there is mixed LC and LTx equipping.
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S214_4: Adapting to LC /LTx Equipping in Slot 214
S215_4: Adapting to LC /LTx Equipping in Slot 215
iWarning!If slot 214 is equipped with LC, the switch must be open to exclude faults to the X129 (2 Mbit/s E1), X117 and X135 sub-D-connectors (both LC 5, system 2).
If LC is used (open)
If LTx is used, closed = 'ON'
S214_4
LC214A24_7B
E1outA2_b1
4321
13141516
ON
161
152
LC LTx
143
134
LC214A26_8BLC214A30_9BLC214A32_10B
E1outA2_a1E1outB2_b2E1outB2_a2
125
116
107
98
ON
161
152
143
134
125
116
107
98
87
65
910
1112
LC214C24_19BLC214C26_20BE1out2_a1E1out2_b1
E1inA2_b1E1inA2_a1E1inB2_b2E1inB2_a2
} in2
} in1
} out2
} out1
in / out from LTx2
As-delivered condition: LC
(LTx1, LTx2) for 2 Mbit/s (E1). (If equipped with LC)Separates lines from slot 214 to sub-D-connector X129
iWarning!IF slot 215 is equipped with the LTx card, the switch must be open to exclude mutual faults to the X130 (SHDSL), X118 and X136 (LC 6, system 2) sub-D-connectors.
If LC is used (open)If LTx is used, closed = 'ON'
S215_4
LC215A24_7B E1inB3_a2
4321
13141516
ON
161
152
LC LTx
143
134
LC215A26_8BLC215A30_9BLC215A32_10B
E1inB3_b2E1inA3_a1E1inA3_b1
125
116
107
98
ON
161
152
143
134
125
116
107
98
8765
9101112
LC215C24_19BLC215C26_20BE1out3_a1E1out3_b1
E1outB3_a2E1outB3_b2E1outA3_a1E1outA3_b1
} in2
} in1
} out2
} out1
in / out from LTx3
As-delivered condition: LC
Separates lines from slot 214 to sub-D-connector X129(LTx3, LTx4) for 2 Mbit/s (E1). (If equipped with LC)
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3.2.8 Connector Assignment
LC-Connectors (General)
Pin X105 to X110 and X113 to X118 X123 to X128 and X131 to X136
1 GND GND
2 LC(Y)A1-1A LC(Y)C1_13A
3 LC(Y)A3-2A LC(Y)C3_14A
4 LC(Y)A7-3A LC(Y)C9_15A
5 LC(Y)A11-4A LC(Y)C13_16A
6 LC(Y)A13-5A LC(Y)C17_17A
7 LC(Y)A19-6A LC(Y)C19_18A
8 LC(Y)A23-7A LC(Y)C23_19A
9 LC(Y)A25-8A LC(Y)C25_20A
10 LC(Y)A29-9A LC(Y)C29_21A
11 LC(Y)A31-10A LC(Y)C31_22A
12 LC(Y)A15-11A LC(Y)C7_23A
13 LC(Y)A17-12A LC(Y)C15_24A
14 LC(Y)A2-1B LC(Y)C2_13B
15 LC(Y)A4-2B LC(Y)C4_14B
16 LC(Y)A8-3B LC(Y)C10_15B
17 LC(Y)A12-4B LC(Y)C14_16B
18 LC(Y)A14-5B LC(Y)C18_17B
20 LC(Y)A20-6B LC(Y)C24_19B
21 LC(Y)A24-7B LC(Y)C26_20B
22 LC(Y)A26-8B LC(Y)C30_21B
23 LC(Y)A30-9B LC(Y)C32_22B
24 LC(Y)A32-10B LC(Y)C8_23B
25 LC(Y)A16-11B LC(Y)C16_24B
(Y) must be replaced by the respective number of connector!
LC1to LC6 correspond to the LC plug-in places 1 to 6
Tab. 3.19 FMX2S LC Connectors (General)
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LC Connectors (X105 to X110, X113 to X118, X123 to X128 and X131 to X136)
Pin SLX102/E SUB102 SLB62 UAC68 CM64/2
X105 to X110
X113 to X118
X105 to X110
X113 to X118
X105 to X110
X113 to X118
X105 to X110
X113 to X118
X123 to X128
X131 to X136
X105 to X110
X113 to X118
X123 to X128
X131 to X136
1 GND GND GND GND GND GND GND
2 SB_a1 SB_a1 SB_a1 F2in_a1 F2in_a4
3 SB_a2 SB_a2 F2out_a1 F2out_a4
4 SB_a3 SB_a3 SB_a2 F2in_a2 F2in_a5
5 SB_a4 SB_a4 SB_a3 F2out_a2 F2out_a5
6 SB_a5 SB_a5 F2in_a3 F2in_a6
7 SB_a6 SB_a6 SB_a4 F2out_a3 F2out_a6
8 SB_a7 SB_a7 S2in_a1 S2in_a4
9 SB_a8 SB_a8 SB_a5 S2out_a1 S2out_a4
10 SB_a9 SB_a9 S2in_a2 S2in_a5
11 SB_a10 SB_a10 SB_a6 S2out_a2 S2out_a5
12 S2in_a3 S2in_a6
13 S2out_a3 S2out_a6
14 SB_b1 SB_b1 SB_b1 F2in_a1 F2in_b4 F2in_a F2in_b
15 SB_b2 SB_b2 F2out_b1 F2out_b4 F2out_a F2out_b
16 SB_b3 SB_b3 SB_b2 F2in_b2 F2in_b5 Yout_b1
17 SB_b4 SB_b4 SB_b3 F2out_b2 F2out_b5 Yout_a2 Yout_b2
18 SB_b5 SB_b5 F2in_b3 F2in_b6 Yout_a3 Yout_b3
19 SB_b6 SB_b6 SB_b4 F2out_b3 F2out_b6 Yout_a4 Yout_b4
20 SB_b7 SB_b7 S2in_b1 S2in_b4 Yin_a1 Yin_b1
21 SB_b8 SB_b8 SB_b5 S2out_b1 S2out_b4 Yin_a2 Yin_b2
22 SB_b9 SB_b9 S2in_b2 S2in_b5 Yin_a3 Yin_b3
23 SB_b10 SB_b10 SB_b6 S2out_b2 S2out_b5 Yin_a4 Yin_b4
24 S2in_b3 S2in_b6
25 S2out_b3 S2out_b6
Attention! Yout1_a from CM64/2 is not laid to the Sub-D-jack!
Tab. 3.20 FMX2S Connectors X105 to X110, X113 to X118,X123 to X128 and X131 to X136 (Part 1)
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Pin IUL82C, IUL84C I4UK4NTP, 4UK2NTP I8S0P
X105 to X110
X113 to X118
X105 to X110
X113 to X118
X105 to X110
X113 to X118
X123 to X128
X131 to X136
1 GND GND GND GND
2 D2a1 UK0a1 S0a1 S0a5
3 D2a2 S0c1 S0c5
4 D2a3 UK0a2 S0a2 S0a6
5 D2a4 S0c2 S0c6
6 D2a5 S0a3 S0a7
7 D2a6 UK0a3 S0c3 S0c7
8 D2a7 S0a4 S0a8
9 D2a8 S0c4 S0c8
10
11 UK0a4
12
13
14 D2b1 UK0b1 S0b1 S0b5
15 D2b2 S0d1 S0d5
16 D2b3 UK0b2 S0b2 S0b6
17 D2b4 S0d2 S0d6
18 D2b5 S0b3 S0b7
19 D2b6 UK0b3 S0d3 S0d7
20 D2b7 S0b4 S0b8
21 D2b8 S0d4 S0d8
22
23 UK0b4
24
25
Tab. 3.21 FMX2S Connectors X105 to X110, X113 to X118X123 to X128 und X131 to X136 (Part 2)
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Pin DSC6nx64C DSC104C CPF2
X105 to X110
X113 to X118
X123 to X128
X131 to X136
X105 to X110
X113 to X118
X123 to X128
X131 to X136
X105 to X110
X113 to X118
X123 to X128
X131 to X136
1 GND GND GND GND GND GND
2 D2out_a1 D2in_a1 D2outa1 D2in_a1 SN0_in_a SN2_in_a
3 D2out_a2 D2in_a2 D2outa2 D2in_a2 SN0_CNTL_a SN2_CNTL_a
4 D2out_a3 D2in_a3 D2outa3 D2in_a3 SN0_out_a SN2_out_a
5 D2out_a4 D2in_a4 D2outa4 D2in_a4 SN0_XCLK_a SN2_XCLK_a
6 D2out_a5 D2in_a5 D2outa5 D2in_a5 SN0_IND_a SN2_IND_a
7 D2out_a6 D2in_a6 D2outa6 D2in_a6 SN0_SCLK_a SN2_SCLK_a
8 T21_a1 Tin_a D2outa7 D2in_a7 SN1_out_a SN3_out_a
9 T22_a1 D2outa8 D2in_a8 SN1_in_a SN3_in_a
10 T21_a2 D2outa9 D2in_a9 SN1_CNTL_a SN3_CNTL_a
11 T22_a2 D2outa10 D2in_a10 SN1_XCLK_a SN3_XCLK_a
12 SN1_IND_a SN3_IND_a
13 SN1_SCLK_a SN3_SCLK_a
14 D2out_b1 D2in_b1 D2outb1 D2in_b1 SN0_in_b SN2_in_b
15 D2out_b2 D2in_b2 D2outb2 D2in_b2 SN0_CNTL_b SN2_CNTL_b
16 D2out_b3 D2in_b3 D2outb3 D2in_b3 SN0_out_b SN2_out_b
17 D2out_b4 D2in_b4 D2outb4 D2in_b4 SN0_XCLK_b SN2_XCLK_b
18 D2out_b5 D2in_b5 D2outb5 D2in_b5 SN0_IND_b SN2_IND_b
19 D2out_b6 D2in_b6 D2outb6 D2in_b6 SN0_SCLK_b SN2_SCLK_b
20 T21_b1 Tin_b D2outb7 D2in_b7 SN1_out_b SN3_out_b
21 T22_b1 D2outb8 D2in_b8 SN1_in_b SN3_in_b
22 T21_b2 D2outb9 D2in_b9 SN1_CNTL_b SN3_CNTL_b
23 T22_b2 D2outb10 D2in_b10 SN1_XCLK_b SN3_XCLK_b
24 SN1_IND_b SN3_IND_b
25 SN1_SCLK_b SN3_SCLK_b
Tab. 3.22 FMX2S Connectors X105 to X110, X113 to X118X123 to X128 und X131 to X136 (Part 3)
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Connectors X101 to X104 (SUE and ECC of CUDs)
Signal Abbreviations
Pin QD2 slave1 and T-Port
of the SUE
X101
QD2 slave2 and QD2-M
of the SUE
X102
Alarm inputs
of the SUE
X103
ECC of the
SUE and CUDs
X104
1 GND_S GND_S GND_S GND_S
2 QD2S1out_a QD2Min_a A1P ECC2in_a
3 QD2T1out_a QD2S2out_a A3P ECC1in_a
4 QD2S1in_a QD2Mout_a A5P ECC2out_a
5 QD2T1in_a QD2S2in_a A7P ECC1out_a
6 ECC3in_a
7 ECC3out_a
8 GND GND GND GND
9 QD2S1out_b QD2Min_b A2P ECC2in_b
10 QD2T1out_b QD2S2out_b A4P ECC1in_b
11 QD2S1in_b QD2Mout_b A6P ECC2out_b
12 QD2T1in_b QD2S2in_b A8P ECC1out_b
13 ECC3in_b
14 ECC3out_b
15 AM
Tab. 3.23 FMX2S Connectors X101 to X104
GND Operation groundGND-S Shielded groundQD2Sin_a1, b1, QD2Sout_a1, b1 Slave 1 from the SUEQD2Sin_a2, b2, QD2Sout_a2, b2 Slave 2 from the SUEQD2Min_a, b, QD2Mout_a, b Master interface from the SUEQD2Tin_a, b, QD2Tout_a, b T-connections of slave1 from the SUEA1P to A8P Alarm inputs of the SUEAM Negative operating voltage for alarm contactsECC2in_a, b, ECC2out_a, b ECC from the CUD 1, plug-in place 202ECC3in_a, b, ECC3out_a, b ECC from the CUD 2, plug-in place 209
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Connectors X119, X120, X121 and X138 (T3, T4, OH)
Signal Abbreviations
Pin T3out
X119
T3in
X120 X121
Overhead (LTx4 and LTx6)
X138
1 GND_S GND_S GND_S GND_S
2 T4out_a1 T3in_a2 PB0 O64out_a1
3 T4out_a5 T3in_a3 PB2 O64in_a1
4 T4out_a2 T3in_a1 O64out_a2
5 T4out_a6 O64in_a2
6 T4out_b1 T3in_b2 PB1 O64out_b1
7 T4out_b5 T3in_b3 PB3 O64in_b1
8 T4out_b2 T3in_b1 O64out_b2
9 T4out_b6 O64in_b2
Tab. 3.24 FMX2S Connectors X119 to X121 and X138
GND-S Shielded groundT4out_a1, b1 T3 output from the CUD1 plug-in places 2T4out_a2, b2 T3 output from the CUD2 plug-in places 9T3in_a2, b2, T3out_a3, b3 T3-loops input or output CUD1T4out_a5, T4out_b5 T3-output from LTx5 plug-in place 17T4out_a6, T4out_b6 T3-output from LTx6 plug-in place 18T3in_a1, T3in_b1 T3-input to LT-plug-in placesO64out_a1...O64in_b1 Overhead LTx4, plug-in place 16O64out_a2...O64in_b2 Overhead LTx6, plug-in place 18
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Connectors X139 and X140 (line interfaces)
Signal Abbreviations
Pin LTx 1, 2, 3
X139
LTx 4, 5, 6
X140
Signal Module
G.703
Module
Uk2
Module
SDSL
Module
T41)Module
Ethernet2)
1 GND_S GND_S H1a1 F1in_a1 F1in_a1 SHDSL_a1 T4out_a Rx_a_1
2 H1a1_3 H1a1_6 H1b1 F1in_b1 F1in_b1 SHDSL_b1 T4out_b Rx_b_1
3 H2a1_3 H2a1_6 H2a1 F1out_a1 F1out_a1 SHDSL_c11) Tx_a_1
4 H1a2_6 H2b1 F1out_b1 F1out_b1 SHDSL_d11) Tx_b_1
5 H2a2_6 H1a2 F1in_a2 F1in_a2 SHDSL_a2 T4out_a Rx_a_2
6 H1a1_2 H1a1_5 H1b2 F1in_b2 F1in_b2 SHDSL_b2 T4out_b Rx_b_2
7 H2a1_2 H2a1_5 H2a2 F1out_a2 F1out_a2 SHDSL_c21) Tx_a_2
8 H1a2_5 H2b2 F1out_b2 F1out_b2 SHDSL_d21) Tx_b_2
9 H2a2_5 1) only with SDSL4op
10 H1a1_1 H1a1_4 2) only LTx4 at X140
11 H2a1_1 H2a1_4
12 H1a2_4
13 H2a2_4
14 H1b1_3 H1b1_6
15 H2b1_3 H2b1_6
16 H1b2_6
17 H2b2_6
18 H1b1_2 H1b1_5
19 H2b1_2 H2b1_5
20 H1b2_5
21 H2b2_5
22 H1b1_1 H1b1_4
23 H2b1_1 H2b1_4
24 H1b2_4
25 H2b2_4
Tab. 3.25 FMX2S Connectors X139 and X140
GND-S Shielded groundH1a1, H1b1, H2a1, H2b1_y(y = 1...6)
Interface 1 from LTx1...LTx6
H1a2, H1b2, H2a2, H2b2_y(y = 1...6)
Interface 2 from LTx1...LTx6
e.g. H1a_5...H2b2_5 Interface 2 from 5. LTx placeT4out_a, b Clock output from T4 moduleRx_a_1/2, b_1/2 Ethernet data receive direction, 1. or 2. interfaceTx_a_1/2, b_1/2 Ethernet data transmit direction, 1. or 2. interface
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Connectors X111, X112, X129, X130 (2 Mbit/s G.703 CUD plug-in place 2, LTx)
Pin CUD place 2
X111
LTx5, LTx6
X112
LTx1, LTx2
X129
LTx3, LTx4
X130
Remark
1 GND_S GND_S GND_S GND_S
E1out81_a/b: output of the 1. interface of LTx1
E1in81_a/b: input of the 1. interface of LTx1
E1out82_a/b: output of the 2. interface of LTx1
E1in82_a/b: input of the 2. interface of LTx1
E1out151_a/b: output of the 1. interface of LTx2
E1in151_a/b: input of the 1. interface of LTx2
E1out152_a/b: output of the 2. interface of LTx2
E1in152_a/b: input of the 2. interface of LTx2
E1out31_a/b: output of the 1. interface of LTx3
E1in31_a/b: input of the 1. interface of LTx3
E1out32_a/b: output of the 2. interface of LTx3
E1in32_a/b: input of the 2. interface of LTx3
E1out41_a/b: output of the 1. interface of LTx4
E1in41_a/b: input of the 1. interface of LTx4
E1out42_a/b: output of the 2. interface of LTx4
E1in42_a/b: input of the 2. interface of LTx4E1
E1out181_a/b: output of the 1. interface of LTx5
E1in181_a/b: input of the 1. interface of LTx5
E1out182_a/b: output of the 2. interface of LTx5
E1in182_a/b: input of the 2. interface of LTx5
E1out191_a/b: output of the 1. interface of LTx6
E1in191_a/b: input of the 1. interface of LTx6
E1out192_a/b: output of the 2. interface of LTx6
E1in192_a/b: input of the 2. interface of LTx6
2 E1out21_a E1out181_a E1out81_a E1out31_a
3 E1in21_a E1in181_a E1in81_a E1in31_a
4 E1out22_a E1out182_a E1out82_a E1out32_a
5 E1in22_a E1in182_a E1in82_a E1in32_a
6 E1out91_a E1out191_a E1out151_a E1out41_a
7 E1in91_a E1in191_a E1in151_a E1in41_a
8 E1out92_a E1out192_a E1out152_a E1out42_a
9 E1in92_a E1in192_a E1in152_a E1in42_a
10
11
12
13
14 E1out21_b E1out181_b E1out81_b E1out31_b
15 E1in21_b E1in181_b E1in81_b E1in31_b
16 E1out22_b E2out182_b E1out82_b E1out32_b
17 E1in22_b E2in182_b E1in82_b E1in32_b
18 E1out91_b E1out191_b E2out151_b E2out41_b
19 E1in91_b E1in191_b E2in151_b E2in41_b
20 E1out92_b E2out192_b E2out152_b E2out42_b
21 E1in92_b E2in192_b E2in152_b E2in42_b
22
23
24
25
Tab. 3.26 FMX2S Connectors X111, X112, X129 and X130
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Connector X137 (ZA contacts)
Connectors X141, X142 (power supply connectors)
Assignment Pin Pin Assignment Remark
GND_S 1 Shielded ground
2 14 ZA_301 ZA contact from SUE
ZAA_302 3 15 ZAB_302 ZA contact from CUD, plug-in place 2
ZAA_309 4 16 ZAB_309 ZA contact from CUD, plug-in place 9
ZAA_308 5 17 ZAB_308 ZA contact from LT1, plug-in place 8
ZAA_314 6 18 ZAB_314 ZA contact from LT2, plug-in place 14
ZAA_315 7 19 ZAB_315 ZA contact from LT3, plug-in place 15
ZAA_316 8 20 ZAB_316 ZA contact from LT4, plug-in place 16
ZAA_317 9 21 ZAB_317 ZA contact from LT5, plug-in place 17
ZAA_318 10 22 ZAB_318 ZA contact from LT6, plug-in place 18
11 23
12 24
GND 13 25 GND Operation ground
Tab. 3.27 FMX2S Connector X137
X141 X142
1 1
− 48 V (MUP 1) 2 − 48 V (MUP 2) 2
+ 48 V (GND) 3 + 48 V (GND) 3
Tab. 3.28 FMX2S Connectors X141 and X142
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3.2.9 Technical Data
3.2.9.1 Environmental Conditions
3.2.9.2 Foreign Voltage Protection
3.2.9.3 Power Supply
Operation acc. to ETSI EN 300 019-1-3 V2.1.2 (04/2003), class 3.1 (+5 ° C to +40 ° C)
Transport acc. to ETSI EN 300 019-1-2 V2.1.4 (04/2003)class 2.3 (−40 ° C bis +70 ° C)
Storage acc. to ETSI EN 300 019-1-1 V2.1.4 (04/2003)class 1.3E (−45 ° C bis +45 ° C)
Product safety acc. to EN 60950-1:2001 (1st edition)EMV compatibility acc. to ETSI EN 300 386 V1.3.2 (05/2003) and
DTAG 1TR9 (Ed. 09.2001 Rev. 06/2002)
Protection against external voltages on the outdoor subscriber lines (OTC applications) is implemented in 2 stages within the entire system. For further information see Section 1.4.7 and UMN:IMN.
Classification for external voltage protection acc. to EN 300 386 V1.3.2 (05/2003) ITC applications according ITU-T K.20 (07/2003), basic1) levelOTC applications according ITU-T K.45 (07/2003), basic1) level
Compliance with the earth conditions according ITU-TIndoor applications (inside subscriber building) K.31 (03/1993)ITC applications (inside telecommunication building) K.27 (05/1996)Outdoor applications (remote electronic sites) K.35 (05/1996)
Units, which are not meet the requirements above, contain specific information about the foreign power protection, see technical data of the line cards.
Rated input voltage −48 V /−60 VPermissible voltage range −36 V to −72 V
1) On enquiry, some line cards can also be used according enhanced level.
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3.3 MXS19C Subrack
3.3.1 StructureThe MXS19C is a subrack in 19“ design, using adapters it is adapted to the fitting con-ditions for the ETSI housing and racks with a minimum depth of 300 mm. The shelfMXS19C can only be mounted in racks, shelter or housings according to installationconditions of IEC 60297.
There is no terminal panel. The shelf contains no front access connector panel, the con-nections will be realized via rear side located delivery connectors, see Fig. 3.20.
The shelf MXS19C can be equipped with plug-in units:• FMX2R3.2
– Central unit CUDThe CUD requires the FMX2R3.2 load.
– Narrowband line cards for voice, data and ISDN services as well as fast Ethernet over TDM
• Line termination units, feeder or leased lines– Access via copper cables with units LT2ME1– Access via optical fiber (units LTO/LT or LTO/NT)– Connection to devices with Ethernet 10/100Base-T interface.
The shelf MXS19C supports in maximum 12 line cards that can be controlled by one ortwo CUDs.
Fig. 3.20 Shelf MXS19C with Front Cover
If line termination units with optical modules (LTO/LT or LTO/NT) are equipped in theMXS19C shelf, the shelf can be supplemented with a glass fiber guide. This guide willbe mounted immediately above the MXS19C shelf on the rack spars. The glass fibersof optical line termination units are guided upwards over a holding device. The centralfront cover can be removed without any release of the glass fiber connections.
MXS19CSIEMENS
LASER KLASSE 1
LASER CLASS 1
ACHTUNG!LASER UND GLASFASER
MECHANISCHNICHT BELASTEN
ATTENTION!LASER AND GLASFIBER
MUST NOT BEPHYSICALLY DAMAGED
OR STRAinED
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For the CPF2 data interfaces, different front panels are available, which can be pluggedinto an external Main Distribution Field (MDF 180 or MDF 210), see UMN:IMN. For ca-bling the connectors of the shelf to the front panels, the adapter cable S42023-A799-S18has to be used.
Fig. 3.21 MXS19C Front View without Front Cover, Unequipped
Fig. 3.22 MXS19C Rear View
Connector forpower supply
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3.3.2 FittingThe MXS19C has 18 slots, which are fitted in the following way:
Fig. 3.23 MXS19C Equipping
201 210202 203 204 205 206 207 208 209 211 212 213 214 215 216 217 218
SU
E (
-B1)
LTx1
LC/L
Tx5
CU
D
CU
D/B
EC
SIS
AK
LTx2
LC/L
Tx3
LC/L
Tx4
LC LC LC LC LC LC LC/L
Tx6
LC/L
Tx7
LC/L
Tx8
Plug-in unit
Plug-in place
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
SUE (-B1) ×
CUD × 2) × 2)
BEC ×
SUB102 × × × × × × × × × × × ×
SLX102/E × × × × × × × × × × × ×
UAC68 × × × × × × × × × × × ×
SLB62 × × × × × × × × × × × ×
SEM106C × × × × × × × × × × × ×
SEM108HC × × × × × × × × × × × ×
LLA102/104C × × × × × × × × × × × ×
I8S0P × × × × × × × × × × × ×
I4UK2NTP × × × × × × × × × × × ×
IUL82C × × × × × × × × × × × ×
I4UK4NTP × × × × × × × × × × × ×
IUL84C × × × × × × × × × × × ×
CPF24) × × × × × × × × × × × ×
DSC6nx64C × × × × × × × × × × × ×
DSC104C × × × × × × × × × × × ×
LTO/LT × × × × × 1) × × ×
LTO/NT × × × × × 1) × × ×
LT2ME13) × × × × × × × ×
SISAK ×
1) If the LTO is plugged into slot 206 it is not possible to use the neighboring slot 207
2) The central units CUD required the FMX2R3.2 load.
3) Pluggable modules of the LT2ME1: UK2mp, G703sh, SDSLmp, SDSLop, Ethernet module, SDSL4op optionally with T4 module
4) Pluggable modules of the CPF2: CIM V.24, CIM X.21, CIM V.35, CIM V.36, CIM-nx64E
Tab. 3.29 MXS19C Equipping
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3.3.3 E1 InterfacesEach CUD contains two E1 interfaces. The E1 interfaces of both CUDs can be accessedat connectors X110/X111, which are located on the rear side connector panel. The im-pedances of the E1 interfaces are adjustable by switches on the CUD between 120 Ωbalanced and 75 Ω unbalanced.
The E1 interfaces of line termination units on the slot delivery connectors have to beconnected with an external distribution frame via special cables, see Section 3.3.4.
To connect the 2-Mbit/s signals with 75 Ω coax cable, the b pin should be connected tothe shield of the coax cable (GND). It is necessary that no cable shield is connected tothe shield of the grip plate, because the voltage potential of the grip plate shield isGND_S.
For cross connection of the unbalanced cable or for changing from balanced to unbal-anced cable it is advisable to use the Coax Distribution Field (CDF) S42023-A890-A75.
3.3.4 Line Termination InterfacesThe slots 202, 203, 204, 205, 206, 215, 216 and 217 can be equipped with line termina-tion units. The backplane of the MXS19C supports any connections on these slots to themanagement interfaces. All needed connections are realized inside the shelf.
Each LTx and combined LC/LTx slot contains two 4-wire interfaces (E1 interfaces),which can be used for the different balanced line interfaces (F1, SHDSL, Uk2 or10/100Base-T). The interfaces, available on the connectors X103, X104, X105, X106,X115, X116, and X117, have to be connected according to the pin assignment of the linetermination unit.
Fig. 3.24 External Interfaces of the Line Termination Units
Line
Unit
G.703
QD2
T3in
F1/SHDSL/Uk2/Ethernet 10/100bT
To the E1 distribution frame (DDF)
To the QD2 distribution frame
From external clock reference
LSA connecting strip forcopper line interfaces
Termination
or Ethernet adapter
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3.3.5 Ethernet Applikations of the LT2ME1The following Ethernet applications can be used with MXS19. An Ethernet adapter(see Fig. 3.85) must be used for the applications.• Slot 202 (LTx1) and slot 203 (LTx2) are equipped with LT2ME1, each with two SDSL
modules. The LT2ME1 with one Ethernet and one SDSL module can be equipped on a LC/LTx-combined slot. Port 2 of the Ethernet adapter is used. The G.703 inter-faces are connected via the Digital Distribution Frame (DDF).
Fig. 3.25 LT2ME1 Each With One Ethernet Module
• Slots 202 and 203 (LTx1 and LTx2) are used for Ethernet applications. One LT2ME1 with two Ethernet modules is inserted on slot 202, the second LT2ME1 with two SDSL modules is inserted on slot 203. Port 2 and port 3 of the Ethernet adapter are used. The G.703 interfaces are connected via the DDF, or they are directly bridged in the connector.
Fig. 3.26 LT2ME1 on Slots 202 and 203, Two Ethernet Modules
Module 1Ethernet
Module 2SDSL
LT2ME1
100bT (port 2) SHDSL
DDF
G.703 G.703
Slots204/205/ 206/215/216/217
Modul 1Ethernet
Modul 2Ethernet
LT2ME1
100bT (Port 2) 100bT (Port 3)
Modul 1SDSL
Modul 2SDSL
LT2ME1
SHDSL SHDSL
DDF
202 203
G.703 G.703 G.703 G.703
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3.3.6 Cables and Filters for Electromagnetic CompatibilityFor adherence of EMV requirements, some units need braided shield cables and/orhave to use EMC planar filters. The following table summarizes the possibilities to min-imize EMC disturbances.
For LT slots it is not necessary to equip the Din 41612 connector with an EMC planarfilter because at these slots a braided shield cable is used.
If a line card shall use an EMC planar filter set, the module S50034-H2-A1 must beequipped on the Din 41612 connector.
3.3.7 Clock SynchronizationIn principle, the FMX2R3.2 will be operated synchronously. A plesiochronous operatingmode is not possible. An internal clock source will be need for alarming purposes (AIS).
The system clock of the multiplexer and the LTx will be derived from one of the followingclock sources:• One of the two E1 receive signals• The external reference clock T3in• An internal free-running oscillator on CUD.
Line card/LTx Braided shield
cable required
With EMC planar filter
I8S0P x x
CPF2 x x
DSC6nx64C x x
DSC104C x x
LTO x
LT2ME1 x
UAC68 x
SUB102 x
SLX102/E x
SLB62 x
SEM106C x
SEM108HC x
LLA102/104C x
IUL82C x
IUL84C x
I4UK2NTP x
I4UK4NTP x
SUE x
SISAK x
CUD x
Tab. 3.30 Cables and Filters for EMC
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The distribution of the clock information to the peripheral line cards will be realized overthe PCM highway. The frame alignment on the peripheral units will be established byelastic stores.
The MXS19C provides a balanced clock input T3in via the common delivery connectorX101 for the T3 reference clock 2.048 MHz according to ITU-T G.703/13. By using theexternal reference clock T3in, both CUDs will be synchronized.
Both CUDs can derive a synchronization clock T4 from their receive signal to synchro-nize other functional units. The balanced clock signals T4out_210 and T4out_211 areconnected on the delivery connector X101.
Fig. 3.27 MXS19C Clock Distribution
The LT2ME1 receives the clock via the level converter as CMOS signal T3CM. For that,the DIL switch S3 must be set accordingly, see user manual UMN:LE2.
3.3.8 QD2 AccessThe internal wiring for operation and monitoring is shown in Fig. 3.28.
The TMN access for the subrack is the QD2 slave interface on connector X101. Thisleads to the QD2 slave port 1 of the SUE. The T terminals of the QD2 slave interface 1of the SUE are also accessible in the QD2 slave connector. The SUE will be addressedvia a DIL switch on the backplane.
The multiplexer, including the various line cards, forms the network element FMX2R3.TMN access to the FMX2R3 is via the QD2 slave interface of the central unit withbitrates of 9.6 kbit/s or 64 kbit/s autodetect. The network element is fix addressed bybackplane coding, with five bits for the CUD central unit.
It is possible to share the line cards in the shelf to two network elements FMX2R3 byequipping a second central unit CUD. In this case, each CUD takes over the control ofthe half from the shelf. The QD2 slave ports of both CUDs are switched in parallel, eachCUD has its own QD2 address.
If one multiplexer with more than 6 line cards is needed, a BEC can be plugged-in at thesecond CUD slot. This BEC connects automatically the both PCM busses and feeds theline cards on the right hand side of the shelf with voltage.
The internal QD2 bus is a 4-wire interface based on EIA RS485. The master of the in-ternal QD2 bus can be a SISAV, located outside of the MXS19C, e.g. the OSU in aCOMPS2 shelf, or it is the SUE plugged into the MXS19C. By using the QD2 switchesS2 and S3 the internal QD2 bus can be connected to the QD2 master port of the SUE(S2 open, S3 closed) or to the QD2 slave port of the MXS19C (S2 closed, S3 open).
Levelconverter
CUD 1LTx 2 CUD 2LTx1
T4
T3
120
Ω
X101X101
T3in (input)T4out_210
T4out_211
T3in (output)for synchronization of further shelves
S4
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Fig. 3.28 MXS19C QD2 Access
Fig. 3.29 QD2 Bus Switch-over
If the QD2 interface of the SISAK should be used, an external cable connection is nec-essary according to general cabling plan, see also Section 5.7.
The CUD can decouple an embedded control channel (ECC), which can be used fortransmission of management data. The ECC interfaces of both CUDs are led to the con-nector X101, where a connection to the SISAK can be established. A configured64-kbit/s time slot of one of the 4 possible E1 ports must be connected to the ECC port.
The shelf can be local operated via the F-interface of the SUE. The interface is acces-sible after removing the front cover.
SUE
QD2 slave
QD2 master
CUD#1
LCs
Operating system (OS)
Addr. 10
F
QD2-S
SISAV
SISA0
FMX2R3.2
SISA0
FMX2R3.2
SISA0
FMX2R3.2
CUD#2
LCs
Addr. 11
SISAV
SISA0
FMX2R3.2
SISA0
FMX2R3.2
SISA0
FMX2R3.2
SISAV
LT#1/LT
SISAV
LT#1/NT
SISAV
LT#8/LT
SISAV
LT#8/NT
SISAK
SISAV
SISAK
QD2 switchS2 and S3
Addr.-Switch1 ... 30
with SUEwithout SUE
Addr. xx Addr. xx
Addresses have to be seton the plug-in unit
Internal QD2 busQD2-S
Addr. SW1 ... 30
QD2-S
QD2-S
QD2-M
QD2SAN1 QD2SAB1Slave port 1
Masterport
QD2Min
QD2Mout
SUE
X101
QD2Sout QD2SinSlave port
CUD/LTx
Internal QD2 bus
S2
S3
QD2Sin1QD2Sout1
QD2Sout
QD2Sin
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3.3.9 AddressingAll units in this shelf, except SUE and SISAK, are assigned the slot addresses as QD2addresses. For the addresses which are assigned to the slots, see Tab. 3.31.
The SISA address of the SUE is set using the DIL switch S101 in the backplane. WithoutSUE, the SISA address must be set with a DIL switch on the CUD, see Section 3.6.3.
For line termination units in line card slots, some address bits are given by the coding ofthe line cards. This makes it necessary to change address bits to adapt the addressing,as it is shown in Tab. 3.31. The change is done using DIL switches, see UMN:LE2.
Unit Plug-in place Slot address
(fix)
QD2 address
SUE 201 DIL switch S101 on the backplane of the shelf, see
Fig. 3.31,
5 bit = 1 to 30
LTx#1 202 12 12
LTx#2 203 13 13
LC#1 204 1 -
LTx#3 204 16 16
LC#2 205 2 -
LTx#4 205 1 1
LC#3 206 3 -
LTx#5 206 17 17
LC#4 207 4 -
LC#5 208 5 -
LC#6 209 6 -
CUD 210 10 10 with SUE,
without SUE it is set with DIL switch 6 on the CUD
CUD/BEC 211 11 11 with SUE,
without SUE it is set with DIL switch 6 on the CUD
LC#7 212 1 -
LC#8 213 2 -
LC#9 214 3 -
LC#10 215 4 -
LTx#6 215 8 8
LC#11 216 5 -
LTx#7 216 24 24
LC#12 217 6 -
LTx#8 217 9 9
SISAK 218 set with LCT, see UMN:ITMN
Tab. 3.31 MXS19C Plug-in Units and Addresses
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3.3.10 AlarmingThe shelf MXS19C supports the ZA contacts of the CUDs and the SUE. Furthermoresupports the MXS19C 8 one-pin alarm contacts of the SUE. These contacts are con-nected to connector X101.
3.3.11 Power Supply and Dissipation in the ShelfThe supply voltage M48V, with a common return path P48V is fed via a terminal blockto the backplane connector X120. The nominal DC input voltage of M48V is −48 VDC or−60 VDC, the interface fulfills the requirements of ETS 300 132-2. The recommendedfuse value for the M48V is 16 A.
The joint GND potential is used as a reference potential for all signals within the shelfand is connected to GND on the backplane. There is also a potential GND-S for the EMCfilter and for the over voltage protection.
The shelf MXS19C does not support voltage redundancy; this feature can be realizedby an external diode module. An EMC circuit with feed through filters is used to fulfil theEMC requirements on the DC interface. The DC interface is also lightening protected.
Behind the EMC filter the supply voltage is fed to the supervision unit, line terminationunits, CUDs and SISAK. Line cards are fed from the CUD.
All line card and combined slots get the supply voltage MUKZU_11, MUKZU_12, whichis a filtered and fused supply voltage of M48V, from the CUD.
The power supply voltages MUP is necessary for the operation of the CUD, line termi-nation unit, supervision unit and the line cards. The following secondary voltages will beprovided by the SUE and CUD´s, the voltages are filtered to fulfil the EMC requirements.
The power dissipation is to be considered for equipping the shelf with plug-in units. Ap-proximately 126 W power dissipation is drawn off by free convection. The maximum per-missible over temperature is 20 °C. On condition of homogeneous distribution of theheat in the shelf with full equipping, a power dissipation of 7 W per slot is permitted.
Be careful, that enough free spaces are below and above the shelf. Once a pre-definedinternal temperature is exceeded, the power dissipation is drawn off by forced ventila-tion.
All boards allow hot board insertion without causing any disturbance to other boards in-side the MXS19C. To ensure these feature three capacitors (100 nF/200 V) per slot canbe equipped on the backplane if necessary. The capacitor is switched betweenMUKZU_11, MUKZU_12 or MUP and GND.
To supply the remote inventory EEPROM of MXS19C backplane the SUE supply volt-age SUE_5V or CDU supply voltage VCC_1, VCC_2 will be used. Via decoupling di-odes, the EEPROM can be fed from an external programming module over theconnector X354.
SUE_5V +5 V from the SUE for backplane EEPROM and T3 voltage level converter
VCC_1 +5 V from the left CUD for line cardsVCC_2 +5 V from the right CUD for line cardsM5V_1 -5 V from the left CUD for line cardsM5V_2 -5 V from the right CUD for line cards
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3.3.12 Front Panels for Data Interfaces of the CPF2For frontal access to the data interfaces of the line card CPF2, the main distributionframes MDF 210 or MDF 180 with front panels S42023-A862-S12, -S13, -S14, -S15,-S25 and -S26 can be used. A special connecting cable S42023-A799-S18 connects theCPF2 in the MXS19C with the front panels.
Fig. 3.30 Connecting Cable S42023-A799-S18
4) 4)
2
18
20
22
24
26
28
30
32
4
6
8
10
12
14
16
c a
1ws1bl1tk1vi4ws
2ws2or
3tk3vi2tk2vi
3ws3gn
4ws
S-02YS(St)CY 8x2x0,4/0,8-120(V42255-Z1001-A7)
2tk2vi3ws3gn
2ws2or1ws1bl
1tk1vi3tk3vi
4)
1);2)
1);2)
1ws1tk2ws2tk3ws3tk4ws
1bl1vi2or2vi3gn3vi
1ws1tk2ws2tk3ws3tk4ws
1bl1vi2or2vi3gn3vi
Port 1
Port 2
Parallel wire (gesw)
Parallel wire (gesw)
1
1
1ws1bl1tk1vi4ws
2ws2or
3tk3vi
2tk2vi3ws3gn
4ws
1);2)
1);2)
1ws1tk2ws2tk3ws3tk4ws
1bl1vi2or2vi3gn3vi
1ws1tk2ws2tk3ws3tk4ws
1bl1vi2or2vi3gn3vi
Port 3
Port 4
ca. 1,3 m3)
Par
alle
l wire
Par
alle
l wire
1
1
4)
2tk2vi
3ws3gn
2ws2or1ws1bl
1tk1vi3tk3vi
ca. 1,3 m3)
ca. 1,3m 3)ca. 1,3 m3)
(ges
w)
(ge
sw)
S-02YS(St)CH 8x2x0,4/0,8-120(V42255-Z1004-A8)
or
S-02YS(St)CY 8x2x0,4/0,8-120(V42255-Z1001-A7)
S-02YS(St)CH 8x2x0,4/0,8-120(V42255-Z1004-A8)
or
S-02YS(St)CY 8x2x0,4/0,8-120(V42255-Z1001-A7)
S-02YS(St)CH 8x2x0,4/0,8-120(V42255-Z1004-A8)
or
S-02YS(St)CY 8x2x0,4/0,8-120(V42255-Z1001-A7)
S-02YS(St)CH 8x2x0,4/0,8-120(V42255-Z1004-A8)
or
Wire color code:
wsorblgnvitkbr
whiteorangebluegreenvioletturquoisebrown
WHOGBUGNVTTQBN
per IEC1) Shielding braid: use installation instruction S42012-A124-Z25-*-312) Parallel wire to pin 1 (bei Schlussgefahr isolieren)3) If necessary, the lenghts will be adapted by the manufacturer
4) Shielding braid and parallel wire: use installation instruction C42165-Z25-C84-*-7431
corresponding to the project
gesw
yellowblack
YEBK
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3.3.13 ControlsIn the following Figure, the switches on the backplane of the MXS19C are shown:
Fig. 3.31 MXS19C Backplane, Shelf from Inside
Switch Settings
Address switch S101 for SUE, addressing in MXS19C see Section 3.3.9.
Switch S2 and S3 for QD2 bus switch-over
Switch S104, S105, S106 and S115, S116, S117 for LC/LTx switch-over
Switch S4 for clock T3
S2 S3 S104 S105 S106
S4 S115 S116 S117
S10
1
1
5
234
ON (0) OFF (1)
23
22
21
20
24
1 2 3 4
ON
1 2 3 4
ON Delivery state: All slides at S2 are switched to “OFF” and at S3 all slides are switched to “ON”, it means supervision of the MXS19C by SUE (stand alone, without OSU), see 3.3.8 and Fig. 3.29.
S2 S3
15 234
ON
If LCs are used, switches S104, S105, S106 and S115, S116, S117 have to be open (OFF) (Delivery state).
If LTx are plugged-in, the switches have to be closed (ON).
Slot assignmentS104S105S106S115S116S117
slot 204slot 205slot 206slot 214slot 215slot 216
12
ONS4 “ON”: Termination resistor connected
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UMN:TED InformationFlexible Multiplexer FMX2R3.2
3.3.14 Connector Assignment
SUE Plug-in place 201
Connec-
tor
Plug-in
place
Remark
X101 201 SUE
X103 202 and 203 Common connector for LTx#1 and LTx#2
X104 204 LC#1 or LTx#3
X105 205 LC#2 or LTx#4
X106 206 LC#3 or LTx#5
X107 207 LC#4
X108 208 LC#5
X109 209 LC#6
X110 210 CUD#1
X111 211 CUD#2 or BEC
X112 212 LC#7
X113 213 LC#8
X114 214 LC#9
X115 215 LC#10 or LTx#6
X116 216 LC#11 or LTx#7
X117 217 LC#12 or LTx#8
X118 218 SISAK
X120 Power supply M48V and P48V
Tab. 3.32 MXS19C Connector Overview
A B C
1
2 QD2Sin_b1 QD2Sin_a1 QD2Tin_a1
3 ZAA_210 ZAB_210
4 QD2Sout_b1 QD2Sout_a1 QD2Tin_b1
5 ZAA_211 ZAB_211
6 QD2Sin_b2 QD2Sin_a2 QD2Tout_a1
7 ZAB_201
8 QD2Sout_b2 QD2Sout_a2 QD2Tout_b1
9 RA_211(ECC) RB_211(ECC)
10 O64out_a_202 O64in_a_202 QD2Tin_a2
11 O64out_b_203 O64in_b_203
12 Qin_b Qin_a QD2Tin_b2
13 QD2_MCLK_a QD2_MCLK_b
Tab. 3.33 MXS19C Connector X101
104 A50010-A3-C701-6-7618
InformationFlexible Multiplexer FMX2R3.2
UMN:TED
Signal Abbreviations
14 Qout_b Qout_a QD2Tout_a2
15 O64out_b_202 O64in_b_202
16 PB0 PB1 QD2Tout_b2
17
18 PB2 PB3 A1P
19
20 RA_210(ECC) RB_210(ECC) A2P
21
22 TA_210(ECC) TB_210(ECC) A3P
23
24 TA_211(ECC) TB_211(ECC) A4P
25 T4out_a_211 O64out_a_203
26 A5P
27 T4out_b_211 O64in_a_203
28 A6P
29 T4out_a_210 T3in_a
30 A7P
31 T4out_b_210 T3in_b AM
32 GND A8P
A B C
Tab. 3.33 MXS19C Connector X101 (Cont.)
GND Operating groundGND-S Shielded groundQD2Sin_a1, b1QD2Sout_a1, b1
Slave 1 of the SUE
QD2Sin_a2, b2QD2Sout_a2, b2
Slave 2 of the SUE
QD2Min_a, bQD2Mout_a, b
Master of th SUE
QD2Tin_a, bQD2Tout_a, b
T connections of slave1 from the SUE
A1P bis A8P Alarm inputs of the SUEAM Negative operating voltage for alarm contactsT4out_a, b_210/211 T4 output from the CUD plug-in places 210 and 211T3in_a,b (input) T3in1 input to the CUDs and LTxZAA_210/211 Central alarming, urgent of CUD plug-in places 210 and 211ZAB_210/211 Central alarming, non-urgent of CUD plug-in places 210 and 211ZAB_201 Central alarming, non-urgent of SUE plug-in place 201O64in_a,b_202/203 O64out_a,b_202/203
Overhead LTx plug-in places 202/203
RA, RB_210/211 ECC input of CUD, plug-in places 210 and 211TA, TB_210/211 ECC output of CUD, plug-in places 210 and 211
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UMN:TED InformationFlexible Multiplexer FMX2R3.2
LTx plug-in places 202 and 203 (LTx#1 and LTx#2)
Pin A B C Module
G.703
Module
Uk2
Module
SDSL
Module
T41)Ethernet
module2)
1 F1in_a2 F1in_a1 F1in_a1 SHDSL_a1 T4out_a Rx_a_1
2 QD2Sout_a QD2Sout_b F1in_b1 F1in_b1 SHDSL_b1 T4out_b Rx_b_1
3 F1in_b2 F1out_a1 F1out_a1 SHDSL_c11) Tx_a_1
4 QD2Sin_a QD2Sin_b F1out_b1 F1out_b1 SHDSL_d11) Tx_b_1
5 F1in_a2_202 F1out_a2 F1in_a2 F1in_a2 SHDSL_a2 T4out_a Rx_a_2
6 F1in_b2 F1in_b2 SHDSL_b2 T4out_b Rx_b_2
7 F1in_b2_202 F1out_b2 F1out_a2 F1out_a2 SHDSL_c21) Tx_a_2
8 O16out_a O16in_a F1out_b2 F1out_b2 SHDSL_d21) Tx_b_2
9 F1in_a1_202 F1out_a2_202 1) only with SDSL4op
10 O16out_b F1out_a1_202 O16in_b 2) only plug-in place 202
11 F1in_b1_202 F1out_b2_202
12 O64out_a_203 F1out_b1_202 O64in_a_203
13 E1out2_a_202
14 O64out_b_203 O64in_b_203
15 E1out2_b_202
16 F1in_a1 RP1_b
17 E1out1_a_202
18 F1in_b1 E1in2_a_202 RP1_a
19 E1out1_b_202
20 F1out_a1 RP2_b
21 E1in2_b_202
22 F1out_b1 RP2_a
23
24 E1in2_a E1out2_a
25
26 E1in2_b E1out2_b
27
28 E1out1_a E1out1_b
29
30 E1in1_a E1in1_a_202 T3in_a
31
32 E1in1_b E1in1_b_202 T3in_b
Tab. 3.34 MXS19C Connector X103
106 A50010-A3-C701-6-7618
InformationFlexible Multiplexer FMX2R3.2
UMN:TED
Signal Abbreviations
GND-S Shielded groundF1in_a1, b1 1. interface of the LT2ME1, 1.wire pair (with 4-w. incoming)F1out_a1, b1 1. interface of the LT2ME1, 2.wire pair (with 4-w. outgoing)F1in_a2, b2 2. interface of the LT2ME1, 1.wire pair (with 4-w. incoming)F1out_a2, b2 2. interface of the LT2ME1, 2.wire pair (with 4-w. outgoing)E1in_a1, b1 G.703 interface 1 of the LTx (incoming)E1out_a1, b1 G.703 interface 1 of the LTx (outgoing)E1in_a2, b2 G.703 interface 2 of the LTx (incoming)E1out_a2, b2 G.703 interface 2 of the LTx (outgoing)T4out_a, b Clock output from the T4 moduleRx_a_1/2, b_1/2 Ethernet data receive direction, 1. or 2. interfaceTx_a_1/2, b_1/2 Ethernet data transmit direction, 1. or 2. interfaceQD2Sin_a, b, QD2Sout_a, b
Slave of the LTx
O64out_a, O64in_b_203 Overhead of the LTx plug-in place 203
A50010-A3-C701-6-7618 107
UMN:TED InformationFlexible Multiplexer FMX2R3.2
LC plug-in places #n (1 -12) and LTx plug-in places #n (3 - 8)
Connec-
tor
LC
n
LTx
n
Pin Row
A B C
X104 1 3 1 xB_a1_n xB_a33_n xB_a9_n
X105 2 4 2 xB_b1_n xB_b33_n xB_b9_n
X106 3 5 3 xB_a2_n xB_a34_n xB_a10_n
X107 4 - 4 xB_b2_n xB_b34_n xB_b10_n
X108 5 - 5 xB_a17_n xB_a35_n xB_a25_n
X109 6 - 6 xB_b17_n xB_b35_n xB_b25_n
X112 7 - 7 xB_a3_n xB_a36_n xB_a26_n
X113 8 - 8 xB_b3_n xB_b36_n xB_b26_n
X114 9 - 9 xB_a18_n xB_a37_n xB_a11_n
X115 10 6 10 xB_b18_n xB_b37_n xB_b11_n
X116 11 7 11 xB_a4_n xB_a38_n xB_a27_n
X117 12 8 12 xB_b4_n xB_b38_n xB_b27_n
13 xB_a5_n xB_a39_n xB_a12_n
14 xB_b5_n xB_b39_n xB_b12_n
15 xB_a19_n xB_a40_n xB_a28_n
16 xB_b19_n xB_b40_n xB_b28_n
17 xB_a20_n xB_a41_n xB_a13_n
18 xB_b20_n xB_b41_n xB_b13_n
19 xB_a6_n xB_a42_n xB_a14_n
20 xB_b6_n xB_b42_n xB_b14_n
21 xB_a21_n xB_a43_n xB_a29_n
22 xB_b21_n xB_b43_n xB_b29_n
23 xB_a7_n xB_a44_n xB_a15_n
24 xB_b7_n xB_b44_n xB_b15_n
25 xB_a8_n xB_a45_n xB_a16_n
26 xB_b8_n xB_b45_n xB_b16_n
27 xB_a22_n xB_a46_n xB_a30_n
28 xB_b22_n xB_b46_n xB_b30_n
29 xB_a23_n xB_a47_n xB_a31_n
30 xB_b23_n xB_b47_n xB_b31_n
31 xB_a24_n xB_a48_n xB_a32_n
32 xB_b24_n xB_b48_n xB_b32_n
Tab. 3.35 MXS19C Connectors X104 to X109, X112 to X117 (General)
108 A50010-A3-C701-6-7618
InformationFlexible Multiplexer FMX2R3.2
UMN:TED
Pin SUB102 SLX102/E UAC68 SLB62 LLA102/104C SEM106C
A A A C A A C A B C
1 F2_a1 SB_a1 F2in_a1 F2in_a4 a1 F2out_a1 F2in_a1 F2out_a1 S21out_1
2 F2_b1 SB_b1 F2in_b1 F2in_b4 b1 F2out_b1 F2in_b1 F2out_b1 S22out_1
3 F2_a2 SB_a2 F2out_a1 F2out_a4 F2out_a2 F2in_a2 F2out_a2
4 F2_b2 SB_b2 F2out_b1 F2out_b4 F2out_b2 F2in_b2 F2out_b2
5 S21in_1 S21out_2 S21in_2
6 S22in_1 S22out_2 S22in_2
7 F2_a3 SB_a3 F2in_a2 a2 F2out_a3 F2out_a3 S21out_3
8 F2_b3 SB_b3 F2in_b2 b2 F2out_b3 F2out_b3 S22out_3
9 F2in_a5 F2in_a3 S21out_4
10 F2in_b5 F2in_b3 S22out_4
11 F2_a4 SB_a4 F2out_a2 a3 F2out_a4 F2out_a4 S21out_5 S21in_4
12 F2_b4 SB_b4 F2out_b2 b3 F2out_b4 F2out_b4 S22out_5 S22in_4
13 F2_a5 SB_a5 F2in_a3 F2out_a5 F2out_a5 F2in_a4 F2out_a5 S21out_6
14 F2_b5 SB_b5 F2in_b3 F2out_b5 F2out_b5 F2in_b4 F2out_b5 S22out_6
15 S21in_3 S21in_6
16 S22in_3 S22in_6
17 F2in_a6 F2in_a5 S21in_5 S21out_7
18 F2in_b6 F2in_b5 S22in_5 S22out_7
19 F2_a6 SB_a6 F2out_a3 F2out_a6 a4 F2out_a6 F2in_a6 F2out_a6
20 F2_b6 SB_b6 F2out_b3 F2out_b6 b4 F2out_b6 F2in_b6 F2out_b6
21 S21in_7 S21out_8 S21in_8
22 S22in_7 S22out_8 S22in_8
23 F2_a7 SB_a7 F2out_a7 F2in_a7 F2out_a7
24 F2_b7 SB_b7 F2out_b7 F2in_b7 F2out_b7
25 F2_a8 SB_a8 a5 F2out_a8 F2in_a8 F2out_a8
26 F2_b8 SB_b8 b5 F2out_b8 F2in_b8 F2out_b8
27 S21in_9 S21out_9 S21in_10
28 S22in_9 S22out_9 S22in_10
29 F2_a9 SB_a9 F2out_a9 F2in_a9 F2out_a9
30 F2_b9 SB_b9 F2out_b9 F2in_b9 F2out_b9
31 F2_a10 SB_a10 a6 F2out_a10 F2in_a10 F2out_a10 S21out_10
32 F2_b10 SB_b10 b6 F2out_b10 F2in_b10 F2out_b10 S22out_10
Tab. 3.36 MXS19C Connectors X104 to X109, X112 to X117, Part 1
A50010-A3-C701-6-7618 109
UMN:TED InformationFlexible Multiplexer FMX2R3.2
Pin SEM108HC IUL82C,
IUL84C
I4Uk2NTP
I4Uk4NTP
I8S0P DSC104C
A B C A A A C A C
1 F2out_a1 S21out_1 F2in_a1 D2a1 Uk0a1 S0a1/c1 S0a5/c5 D2outa1 D2ina1
2 F2out_b1 S22out_1 F2in_b1 D2b1 Uk0b1 S0b1/d1 S0b5/d5 D2outb1 D2inb1
3 F2out_a2 F2in_a2 D2a2 S0c1/f1 S0c5/f5 D2outa2 D2ina2
4 F2out_b2 F2in_b2 D2b2 S0d1/e1 S0d5/e5 D2outb2 D2inb2
5 S21in_1 S21out_2 S21in_2
6 S22in_1 S22out_2 S22in_2
7 F2out_a3 S21out_3 D2a3 Uk0a2 S0a2/c2 D2outa3
8 F2out_b3 S22out_3 D2b3 Uk0b2 S0b2/d2 D2outb3
9 S21out_4 F2in_a3 S0a6/c6 D2ina3
10 S22out_4 F2in_b3 S0b6/d6 D2inb3
11 F2out_a4 S21out_5 S21in_4 D2a4 S0c2/f2 D2outa4
12 F2out_b4 S22out_5 S22in_4 D2b4 S0d2/e2 D2outb4
13 F2out_a5 S21out_6 F2in_a4 D2a5 S0a3/c3 S0c6/f6 D2outa5 D2ina4
14 F2out_b5 S22out_6 F2in_b4 D2b5 S0b3/d3 S0d6/e6 D2outb5 D2inb4
15 S21in_3 S21in_6
16 S22in_3 S22in_6
17 S21in_5 S21out_7 F2in_a5 S0a7/c7 D2ina5
18 S22in_5 S22out_7 F2in_b5 S0b7/d7 D2inb5
19 F2out_a6 F2in_a6 D2a6 Uk0a3 S0c3/f3 S0c7/f7 D2outa6 D2ina6
20 F2out_b6 F2in_b6 D2b6 Uk0b3 S0d3/e3 S0d7/e7 D2outb6 D2inb6
21 S21in_7 S21out_8 S21in_8
22 S22in_7 S22out_8 S22in_8
23 F2out_a7 F2in_a7 D2a7 S0a4/c4 S0a8/c8 D2outa7 D2ina7
24 F2out_b7 F2in_b7 D2b7 S0b4/d4 S0b8/d8 D2outb7 D2inb7
25 F2out_a8 F2in_a8 D2a8 S0c4/f4 S0c8/f8 D2outa8 D2ina8
26 F2out_b8 F2in_b8 D2b8 S0d4/e4 S0d8/e8 D2outb8 D2inb8
27 S21in_9 S21out_9 S21in_10
28 S22in_9 S22out_9 S22in_10
29 F2out_a9 F2in_a9 D2outa9 D2ina9
30 F2out_b9 F2in_b9 D2outb9 D2inb9
31 F2out_a10 S21out_10 F2in_a10 Uk0a4 D2outa10 D2ina10
32 F2out_b10 S22out_10 F2in_b10 Uk0b4 D2outb10 D2inb10
Tab. 3.37 MXS19C Connectors X104 to X109, X112 to X117, Part 2
110 A50010-A3-C701-6-7618
InformationFlexible Multiplexer FMX2R3.2
UMN:TED
Pin DSC6-nx64C CPF2 LTO LT2ME1
A C A C A C A B C
1 D2out_a1 D2in_a1 SN0_in_a SN2_in_a F1in_a2
2 D2out_b1 D2in_b1 SN0_in_b SN2_in_b Qout_a Qout_b Qout_a Qout_b
3 D2out_a2 D2in_a2 SN0_CNTL_a SN2_CNTL_a F1in_b2
4 D2out_b2 D2in_b2 SN0_CNTL_b SN2_CNTL_b Qin_a Qin_b Qin_a ZAB Qin_b
5 GND GND F1out_a2
6 ZAB ZAA ZAB ZAA
7 D2out_a3 SN0_out_a SN3_inD_a F1out_b2
8 D2out_b3 SN0_out_b SN3_inD_b O16out_a O16in_a
9 D2in_a3 SN2_out_a
10 D2in_b3 SN2_out_b O16out_b O16in_b
11 D2out_a4 SN0_XCLK_a
12 D2out_b4 SN0_XCLK_b O64out_a O64in_a O64out_a O64in_a
13 D2out_a5 D2in_a4 SN0_inD_a SN2_XCLK_a
14 D2out_b5 D2in_b4 SN0_inD_b SN2_XCLK_b O64out_b O64in_b O64out_b O64in_b
15 SN1_inD_a SN3_SCLK_a
16 SN1_inD_b SN3_SCLK_b F1in_a1 F1in_a1 RP1_b
17 D2in_a5 SN1_SCLK_a SN2_inD_a
18 D2in_b5 SN1_SCLK_b SN2_inD_b F1in_b1 RP1_a
19 D2out_a6 D2in_a6 SN0_SCLK_a SN2_SCLK_a
20 D2out_b6 D2in_b6 SN0_SCLK_b SN2_SCLK_b F1out_a1 F1in_b1 RP2_b
21
22 F1out_b1 RP2_a
23 T21_a1 Tin_a SN1_out_a SN3_out_a
24 T21_b1 Tin_b SN1_out_b SN3_out_b E1in2_a E1out2_a E1in_a2 F1out_a1 E1out_a2
25 T22_a1 SN1_in_a SN3_in_a
26 T22_b1 SN1_in_b SN3_in_b E1in2_b E1out2_b E1in_b2 F1out_b1 E1out_b2
27
28 E1out1_a E1out1_b E1out_a1 E1out_b1 E1out_b1
29 T21_a2 SN1_CNTL_a SN3_CNTL_a E1out_a1
30 T21_b2 SN1_CNTL_b SN3_CNTL_b E1in1_a Z_TXD E1in_a1 T3in_a
31 T22_a2 SN1_XCLK_a SN3_XCLK_a E1out_b1
32 T22_b2 SN1_XCLK_b SN3_XCLK_b E1in1_b Z_RXD E1in_b1
Tab. 3.38 MXS19C, Connectors X104 to X109, X112 to X117, Part 3
A50010-A3-C701-6-7618 111
UMN:TED InformationFlexible Multiplexer FMX2R3.2
CUD plug-in places 210 and 211
Module
G.703
Module
Uk2
Module
SDSL
Module
T41)Ethernet
module
F1in_a1 F1in_a1 SHDSL_a1 T4out_a Rx_a_1
F1in_b1 F1in_b1 SHDSL_b1 T4out_b Rx_b_1
F1out_a1 F1out_a1 SHDSL_c11) Tx_a_1
F1out_b1 F1out_b1 SHDSL_d11) Tx_b_1
F1in_a2 F1in_a2 SHDSL_a2 T4out_a
F1in_b2 F1in_b2 SHDSL_b2 T4out_b
F1out_a2 F1out_a2 SHDSL_c21)
F1out_b2 F1out_b2 SHDSL_d21)
1) only with SDSL4op
Tab. 3.39 MXS19C Signalzuordnung der LT2ME1-Module
A B C
1
2 RA (ECC) E1inA_b E1inA_a
3
4 RB (ECC) E1outA_b E1outA_a
5
6 SA6out_a T4out_b T4out_a
7
8 SA6out_b E1inB_b E1inB_a
9
10 Plug_210/Plug_211 SA5out_b SA5out_a
11
12 SA7out_b SA7out_a
13
14 QD2Sout_b QD2Sout_a
15
16 SA8out_b SA8out_a
17
18 E1outB_b E1outB_a
19
20 TA (ECC) SA5in_b SA5in_a
21
22 TB (ECC) SA7in_b SA7in_a
Tab. 3.40 MXS19C Connectors X110 and X111
112 A50010-A3-C701-6-7618
InformationFlexible Multiplexer FMX2R3.2
UMN:TED
Signal Abbreviations
SISAK plug-in place 218
23
24 SA8in_a QD2Sin_b QD2Sin_a
25
26 SA8in_b SA6in_b SA6in_a
27
28 T3in_b T3in_a
29
30
31
32
A B C
Tab. 3.40 MXS19C Connectors X110 and X111 (Cont.)
E1outA/B_a/b 2-Mbit/s transmit signal port A/B, a- and b wireE1inA/B_a/b 2-Mbit/s receive signal port A/B, a- and b wireGND Internal groundQD2Sout_a/b Transmit signal, slave port, a- and b wireQD2Sin_a/b Receive signal, slave port, a- and b wireRA/RB ECC interface, transmit signal, a- and b wireSAxout/in_a/b Transmit signal/receive signal SAx, a- and b wireTA ECC interface, receive signal, a wireTB ECC interface, receive signal, b wireT4out_a/b Outgoing 2048-kHz clock, a- and b wireT3in_a/b Incoming 2048-kHz clock, a- and b wire
A B C
1
2 UP GND2 S1D1outV
3
4 S1D1inV S1D1inb S1D1ina
5
6 GND1 S1D1outb S1D1outa
7
8 S1D2inV S1D2inb S1D2ina
9
10 S1D2outV S1D2outb S1D2outa
11
12 S2D1inV S2D1inb S2D1ina
Tab. 3.41 MXS19C Connector X118
A50010-A3-C701-6-7618 113
UMN:TED InformationFlexible Multiplexer FMX2R3.2
Signal Abbreviations
13
14 S2D1outV S2D1outb S2D1outa
15
16 S2D2inV S2D2inb S2D2ina
17
18 S2D2outV S2D2outb S2D2outa
19
20 MD1inV MD1inRb MD1inRa
21
22 MD1outV MD1outRb MD1outRa
23
24 MD2inV MD2inRb MD2inRa
25
26 MD2outV MD2outRb MD2outRa
27
28 S1TV S1TRb S1TRa
29
30 S2TV S2TRb S2TRa
31
32 MTV MTRb MTRa
A B C
Tab. 3.41 MXS19C Connector X118 (Cont.)
GND Ground
GND1 Signal ground
GND2 Ground (-60 V)
MDyoutRa Master data y (port) out RS485 wire a
MDyoutRb Master data y (port) out RS485 wire b
MDyinRa Master data y (port) in RS485 wire a
MDyinRb Master data y (port) in RS485 wire b
MDyoutV Master data y (port) out V.28
MDyinV Master data y (port) in V.28
MT Master clock
MTRa Master clock in RS485 wire a
MTRb Master clock in RS485 wire b
MTV Master clock in V.28
RXD Unsymmetrical receive (data)
S1T Slave clock 1
S2T Slave clock 2
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Power supply
SxDyina Slave x data y (port) in RS485/G.703 wire a
SxDyinb Slave x data y (port) in RS485/G.703 wire b
SxDyouta Slave x data y (port) out RS485/G.703 wire a
SxDyoutb Slave x data y (port) out RS485/G.703 wire b
SxDyinV Slave x data y (port) in V.28
SxDyoutV Slave x data y (port) out V.28
SxTra Slave x data in RS485/G.703 wire a
SxTrb Slave x data in RS485/G.703 wire b
SxTV Slave x data in V.28
TXD Unsymmetrical transmit (data)
UP Primary voltage
Pin Signal
1 M48V
2 P48V
Tab. 3.42 MXS19C Connector X120
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3.3.15 Technical Data
3.3.15.1 Environmental Conditions
3.3.15.2 Foreign Voltage Protection
3.3.15.3 Power Supply
Operation acc. to ETSI EN 300 019-1-3 V2.1.2 (04/2003), class 3.1 (+5 ° C to +40 ° C)
Transport acc. to ETSI EN 300 019-1-2 V2.1.4 (04/2003)class 2.3 (−40 ° C bis +70 ° C)
Storage acc. to ETSI EN 300 019-1-1 V2.1.4 (04/2003)class 1.3E (−45 ° C bis +45 ° C)
Product safety acc. to EN 60950-1:2001 (1st edition)
Protection against external voltages on the outdoor subscriber lines (OTC applications) is implemented in 2 stages within the entire system. For further information see Section 1.4.7 and UMN:IMN.
Classification for external voltage protection acc. to EN 300 386 V1.3.2 (05/2003) ITC applications according ITU-T K.20 (07/2003), basic1) levelOTC applications according ITU-T K.45 (07/2003), basic1) level
Compliance with the earth conditions according ITU-TIndoor applications (inside subscriber building) K.31 (03/1993)ITC applications (inside telecommunication building) K.27 (05/1996)Outdoor applications (remote electronic sites) K.35 (05/1996)
Units, which are not meet the requirements above, contain specific information about the foreign power protection, see technical data of the line cards.
Rated input voltage −48 V /−60 VPermissible voltage range −36 V to −72 V
1) On enquiry, some line cards can also be used according enhanced level.
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3.4 ONU 30 FTTB
3.4.1 DesignThe optical network unit ONU 30 FTTB is accommodated in a wall housing for indoorworking. Fig. 3.32 shows the structure of ONU 30 FTTB.
Fig. 3.32 Structure of ONU 30 FTTB
Fig. 3.33 Front View of ONU 30 FTTB
OVPPSBat.
ONU 30 FTTB
1× 2 Mbit/s
2× 2 Mbit/s
copper/FO
1
30
115/230 V AC
FAM
Alarms−48 V
FMX2R3.2
MSUE
MDF
2 × 2 Mbit/s (G.703)1)
POTSISDN Uk0, S0
LL analogLL n× 64 kbit/s
X.21V.24, RS530V.35, V.36, Eth
1) The interfaces can only be used externally,if no line terminating unit is equipped
LTx1)2 x
2 Mbit/sG. 703
Power supply
Splice cassette
AMXMS
AC connection
terminals
MDF
Fan
Mains
fuses
Battery unit
Tray for spare
FO cable
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The ONU 30 FTTB contains the following modules, see Fig. 3.33:• AMX mini shelf (AMXMS) equipped with:
– a multiplexer FMX2R3.2 (1 × CUD and a maximum of 3 line cards)– a line terminating unit LTO or LT2ME1– a fan and alarm module FAM
• Main distribution frame with 7 LSA-Plus terminal strips • Front panel connectors for CPF2 (V.24, V.35, RS530, V.36, X.21, Ethernet)• Power supply (SV 48 V/65 W)• Battery SBS15• Splice cassette (only for optical line terminating units)• Fan (FAM).
Fig. 3.34 ONU 30 FTTB Front View
The power is supplied via the local mains. The power line (110/230 V AC) is connectedwith the AC terminal clamps in a wall case and is protected by a 10 A mains fuse.
In the case of mains failure, the battery unit SBS 15 (12 V/14 Ah) takes over the powersupply and makes possible further operation of the ONU for at least 4 h (with 0.5 Erl).
For supervision functions, the following static alarms have been established:• Door contact• Mains failure• Failure of power supply• Battery failure• Fan failure.
Door contactCable feeding OF feedingMains feeding ESD jack
AC terminal
OVP for mains
LSA+ stripsfor LCs and LTx
Front panel connectors for CPF2
AMXMS
Battery cable
Power supply
Mains fuses
Batteryexhausting
Temperature
SBS15 Splicing cassette for LWL
inclusiveFAM
Pocket for optical fiber (OF)
Pigtail
OF
OVP forsubscriber lines
batterysensor
clamp
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The MDF of the ONU 30 FTTB has the following connection possibilities:• 3 × LSA-plus connection strips for 2-wire/4-wire subscriber connections
with E&M signaling, or2 × LSA-plus connection strips for 4-wire subscriber connections and 2 × LSA-plus connection strips for 2-wire subscriber connections
• 1 × LSA-plus connection strip for 1 or 2 line interfaces• 2 × LSA-plus connection strips free (up to now for 5-pin foreign voltage protection).
3.4.2 Shelf AMXMS
3.4.2.1 EquippingThe AMXMS accommodates the following double Eurocard units without front panel:• One central unit CUD• One measurement and supervision unit MSUE• Up to 3 line cards LC• One line terminating unit LTx (LT2ME1or LTO)
Detailed Information concerning the line terminating units is contained in the user manual UMN:LE2.
• Fan and alarm module FAM.
A backplane interconnects the units via external and internal interfaces. Fig. 3.35shows the equipping of the AMXMS.
Fig. 3.35 Equipping of the AMXMS
6541 32
FAM
MS
UE
CU
D LC LC LC LTx
Rear view
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The shelf AMXMS can be equipped as follows:
3.4.2.2 Switch Settings
SISA Addresses
The SISA address is set via the DIL switch on the AMXMS. The DIL switch is located onthe backplane behind the FAM module:
Plug-in unit Slot in the AMXMS
1 2 3 4 5 6
MSUE ×
CUD ×
LLA102/104C (2Dr) × × ×
SUB102 × × ×
SLX102/E × × ×
SLB62 × × ×
I4UK2NTP × × ×
I4UK4NTP × × ×
IUL82C × × ×
IUL84C × × ×
UAC68 ×
LLA102/104C (4Dr) ×
CM64/2 ×
I8S0P ×
CPF21) ×
LT2ME12) ×
LTO/NT, LTO/LT ×
1) CPF2 with up to 4 modules: CIM V.24, CIM X.21, CIM V.35, CIM V.36, CIM-nx64E
2 LT2ME1 with up to 2 modules: Uk2mp, G703sh, SDSLmp, SDSLop, SDSL4op
Tab. 3.43 AMXMS Equipping
iFor the data interfaces of the CPF2 instead of LSA-plus strips terminal modules are used containing Sub-D connectors. Another Sub-D connector makes the internal 2-Mbit/s interfaces (G.703) and the QD2 bus accessible from outside.
Connector of the FAM
module
Address switches for SISA address
setting of the ONU 30 FTTB
AMXMS
FAM
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Pull out the FAM and set the SISA address. Slide number 1 (right slide) has the value 20.The ON position means “logic 0” and the OFF position means “logic 1”.
Put the FAM back into the AMXMS after setting SISA address.
3.4.3 Supervision Unit MSUE
3.4.3.1 OverviewThe measurement and supervision unit MSUE provides functions for controlling and su-pervising the FMX2R3.2 and functions for measuring and testing the line cards and thesubscriber lines.
The MSUE provides a SISA-V which has the network element MEU present constantlyin its polling list. Other network elements are served via the MSUE according to the con-figuration of the QD2 master interface.
During the initialization phase the operating system of the MSUE performs self-tests onthe unit components and interfaces. In the event of a fault, the MSUE produces fault sig-nals. In addition, backplane and address recognitions are performed via the static in-puts.
The functions of the MSUE are:• Control and supervision
– Realization of a virtual concentrator (SISA-V)– Conversion of the QD2 slave interface of the MSUE to the QD2 master interface
of the MSUE– Operator control of the local F interface
1 2 3 4 5
SISA_0SISA_4
Value 20Value 24
Example address setting:
slide 1 to OFF is 20 = 1
slide 2 to OFF is 21 = 2
it follows address 3 for the ONUON (0)
−48 V/−60 V
QD2 master
MSUE
Supervision
Measurement unit MEU
Internal interfaces
Backplane
Addressrecognition
coding
QD2 master
Measure-
Mb0 to Mb3
External interfaces
F
MTAment bus
PCM highwayQD2 slave
ECC
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– Conducting self-tests– Visual indication of certain conditions via LEDs– Provision of the transparent transmission channel between the internal PCM
highway and ECC interface• Measuring and testing the line cards and subscriber lines
– Central control of the multiplexers when channels are connected to the measure-ment bus
– Testing the subscriber lines with resistance, capacitance and voltage measure-ments
– Verifying functions and parameters of the line cards– Time-programmable automatic test cycles.
The MSUE has the following interfaces:• F interfaces• QD2 master interface• QD2 slave interface• MTA interface• Measurement bus• Power supply• ECC interface• PCM highway.
3.4.3.2 Measurement Unit MEUThe measurement unit determines• Line parameters of a subscriber line,• Certain parameters of a subscriber terminal equipment and• Functions of the subscriber interfaces.
The measurement unit is used to measure voltages, resistances or capacitances. Vari-ous impedances can be selected to set and test defined loadings.
Measurements of the line parameters cover the line area from the interfaces of the linecards through to and including the subscriber terminal equipment and NTBA or NTU.
To perform a measurement the MSUE is connected via the central measurement bus inthe shelf to the relevant item under test. The measurement unit is connected to the itemunder test on a two-wire basis.
The MSUE incorporates an error sensor and a temperature sensor for remotely super-vising the primary voltage and the temperature inside the case.
The measurement unit can be operated in the following modes:• Measurement on demand and• Automatic measuring.
Measuring on demand acts via the F or QD2 interface to set automatically• the connection of the measurement bus to an LC• the type of measurement• the test parameters.
The results of these measurements are interrogated directly.
In the automatic measurement mode the test program preset via the relevant interfacesis run at the preprogramming time. Measured values which are out of tolerance and non-executable measurements are stored for subsequent retrieval.
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The following data are stored in the MSUE and can be overwritten or deleted for eachtype of channel to be tested:• Channel type• Type of measurement• Start times for the automatic measurement mode• Measured value thresholds.
Measurements of Central Parameters• Operating voltage• Internal case temperature.
Measurements of Line Parameters
Measurements of the line parameters can be performed at all analog and ISDN linecards. The only differences are in the test voltage required for determining resistanceand capacitance:• Analog interfaces: ≤60 V• ISDN interfaces: ≤10 V.
Measurements on Analog Line Cards
In order to measure the interface parameters of the line cards, switchable load imped-ances on the measurement unit of the MSUE are used to set defined operation modes.The following tests can be performed:• Application of the ringing tone signal after a loop closure and • Disconnection of ringing current after a loop closure in the ringing condition.
Measurements on ISDN Line Cards
In order to measure DC parameters of an ISDN channel on the line card, switchable loadimpedances on the measurement unit of the MSUE are used to set defined operationmodes.
3.4.3.3 Supervision and Alarm SignalingFor local supervision the MSUE has a red and a green LED on the front panel and ayellow LED recessed on the unit.
LED (green) LED (red) LED (yellow) Condition
off off off No operating voltage
on off off Undisturbed operation
on off on Undisturbed operation, connection made to next higher
hierarchy level in the OS
off on off MSUE in fault condition or self-testing
off on on Fault condition, connection retained
Tab. 3.44 Visual Signalizing of the MSUE
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3.4.3.4 Control Elements
Fig. 3.36 Control Elements of the MSUE
Settings with DIL Switch 24/1 to 4:
Settings with DIL Switch 24/5 and 24/6:
Assignment at Connector 12 and Test Jack 13:
Switch Status Control Function
24/1 OFF
ON
High impedance1)
120 ΩBus termination QD2-Sin
with 64 kbit/s or 9.6 kbit/s
1) As-delivered state
24/2 OFF
ON
High impedance1)
120 ΩBus termination QD2-Sout
with 64 kbit/s or 9.6 kbit/s
24/3 OFF
ON
High impedance1)
120 ΩBus termination QD2-Sin
with 1.2 kbit/s
24/4 OFF
ON
High impedance1)
120 ΩBus termination QD2-Sout
with 1.2 kbit/s
24/5 24/6 Control Function
OFF OFF ECC deactivated
OFF ON ECC selected in timeslot 15
ON OFF ECC selected in timeslot 21
ON ON Reserved (ECC deactivated)
10 Internal connector11 External connector12 Connectors for LCT13 Test jack
13
10
11redgreen
12
yellow
ON
241
8
!The channel configured for the ECC must not be assigned from a subscriber port on the CUD. For him, a cross connection must be created to the ECC2.
1
5
6
9
12 No. Assignment No. Assignment
1 – 6 –
2 RXD 7 –
3 TXD 8 –
4 – 9 –
5 GND
Pos. Assignment
1 Pb0
2 Pb1
3 Pb2
4 Pb3
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3.4.3.5 Connector Assignments
Fig. 3.37 MSUE Connector Assignment
b a1
5
10
15
20
25
30
11
b a10
1
5
10
15
20
25
30
Connector 11
No.
Row
b a
1
2 QD2Sin_a1 QD2Sin_b1
3
4 QD2Sout_a1 QD2Sout_b1
5
6 QD2Sin_a2 QD2Sin_b2
7
8 QD2Sout_a2 QD2Sout_b2
9
10 SESout_a SESout_b
11
12 QD2Min_a QD2Min_b
13
14 QD2Mout_a QD2Mout_b
15
16 CTXD CRXD
17
18 T2 T1
19
20 L1 RESET
21
22
23
24
25
26 L3 L2
27 Ein_a Ein_b
28 Eout_a Eout_b
29
30 MTA1 MTA0
31
32 MTA3 MTA2
Connector 10
No.
Row
b a
1
2 PUP GND
3
4 MUP_1
5
6 NZFAN GFAN
7
8 Pb0 Pb3
9
10 Pb2 Pb1
11
12
13
14 TXDSVB RXDSVB
15 AD6 AD5
16 RTSSVB CLKSVB
17 AD2 AD7
18 K2 K1
19 AD4 AD3
20 K3 K0
21 AD0 ALE_1
22 A2 A1
23 RD AD1
24
25 CS WR
26 A3
27 SYN_E
28 A0 A4
29 PCM_E CLK_4M
30 SK1
31 SYN_S PCM_S
32 GND
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Signal Abbreviations
3.4.4 Fan and Alarm Module FAM
3.4.4.1 OverviewThe fan and the alarm handler (AHA32) for the ONU 30 FTTB are located on the FAM(FAN and Alarm Module).
The fans make sure that heat is distributed evenly within the ONU 30 FTTB. If the uppertemperature threshold is exceeded the fans are activated and if the temperature dropsbelow a lower threshold they are deactivated. The MSUE handles measurement of tem-perature and activation of signal GFAN for the fans.
The power supply range for the fans is between −48 V and −59 V.
Both fans present on the module are monitored for faults and failure. If a fault occurs orif a fan fails an alarm is sent to the management system.
The alarm handler collects alarm information and reports this to the management sys-tem. Up to 5 alarms can be passed on by the alarm handler, one alarm for fan faults orfailure and also up to 4 external alarms (e.g. door contact, ac mains outage).
A0 to A4 NE addresses 0 to 30
CLKSVB SVB clock
CRXD PC monitor interface receive direction
CTXD PC monitor interface transmit direction
GFAN Line for fan control
GND Internal ground
K0 to K3 back plane coding for differing plug-in units by the MSUE
L1 to L3 Internal signals, for test department only
MTA0 to MTA3 Metallic access lines 0 to 3For external measuring equipment connection
MUP Neg. primary voltage -48 V/-60 V
NZFAN Error signal of the fan
PUP Pos. primary voltage +48 V/+60 V
QD2Mout_a/b Transmit signal master port, a and b wires
QD2Min_a/b Receive signal master port, a and b wires
QD2Sout_a/b Transmit signal slave port, a and b wires
QD2Sin_a/b Receive signal slave port, a and b wires
RESET External reset connection for controller
RTSSVB Request to send
RXDSVB SVB receive direction
SESout_a/b Send enable signal output, a and b wires
SK1 Control contact for battery allocation - preset
T1, T2 Internal signals, for test department only
TXDSVB SVB transmit direction
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The FAM module has the following interfaces:• QD2 slave interface,• 5 external alarm interfaces,• Interface to MSUE (GFAN),• Interface to EEPROM for type label data,• Power supply−36 V to −72 V, +5 V for alarm handler from the CUD.
3.4.4.2 QD2 InterfaceThe QD2 slave interface provides access to the alarm handler (AHA32) as well as beingused for passing on the alarms to the management system. The QD2 address of thealarm handler is set to a default of 7.
3.4.4.3 Alarm InterfacesThe alarm interfaces A_1 to A_4 and A_6 of the FAM are connected to external connec-tor X31 on the backplane of the ONU 30 FTTB. The alarm is activated for “Low” (GND).When the input is open (“high” potential), no alarms will be signaled.
The fans are controlled by the MSUE by means of the GFAN signal, depending on thetemperature in the ONU 30 FTTB. The signal in question is a TTL signal in which “High”means that the fans are switched on and “Low” means that the fans are switched off.The “External Contact 08” alarm indicates that a fan has failed.
Simultaneously the alarms are evaluated by the CUD and sent to the ACI using the QD2protocol.
Type label data
FAM
Fan Fan
AHA32
GFAN
A01A02A03A04
QD2-S
−48 V/−60 V
FAM
+5 V (from CUD)A05
Name within ACI Short name Cause Mode Alarm contact
on X1
External contact 01 Battery Battery deep discharging Single-pole A_3
External contact 02 Mains failure Single-pole A_1
External contact 03 Rectifier failure DC operating voltage failure Single-pole A_2
External contact 04 Over voltage Over voltage protection failure Single-pole A_6
External contact 05 Door alarm Door of the ONU 30 FTTB is open Single-pole A_4
External contact 08 FAN (1) Fan failure
Tab. 3.45 ONU 30 FTTB External Alarms
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3.4.4.4 Connector Assignments
Signal abbreviations
3.4.5 Power SupplyThe ONU 30 FTTB is supplied with 115 V/230 V mains power. The heavy current leadis connected to the terminals in the wall cabinet and is protected via a 10-A mains fuse.
For battery backup there is an SBS 15 (12 V/14 Ah) in the ONU 30 FTTB. The batteryensures that the ONU will continue to operate for at least 4 hours (at 0.5 Erlang) in theevent of a mains power failure.
3.4.5.1 WarningsThe power supply unit SV 65 W 12 V/48 V is a built-in device. For installation, pleaserefer to the appropriate Din/VDE specifications and country-specific regulations.
Pin A B C
1 A_1 A_2
2 M48V M48V
3 A_3 A_4
4 GFAN P5V
5 A_6
6
7 QD2Sin_a QD2Sin_b
8 PRE
9 QD2Sout_a QD2Sout_b
10 P48V P48V
Tab. 3.46 FAM Connector X1
A0 to A6 Alarm inputsM48V Negative primary voltage -48 V/-60 VP48V Positive primary voltage P5V +5 V for alarm handlerGFAN Fan control signalQD2Sout_a/b Send signal slave port, a and b wireQD2Sin_a/b Receive signal slave port, a and b wire
!When operating electrical devices, certain parts of these devices carry dangerous volt-ages. Activities on or in the vicinity of these devices should only be performed by ade-quately qualified personnel.
!The main switch must be deactivated and locked against reactivation before any instal-lation or maintenance work is started.
!The terminal with the ground symbol must be connected to the protective earth lead. Otherwise, contact with live parts can cause serious injury or death.
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3.4.5.2 FunctionThe 115-V or 230-V input voltage is used to generate an intermediate circuit voltage of12 V (nominal value) that is electrically isolated from the input. The actual value of thisvoltage corresponds to the charging end voltage of a 6-cell lead battery and is temper-ature-controlled in the range 13 V to 14,5 V by the external temperature sensor PT1000.When a 6-cell lead battery is connected, this output voltage is simultaneously used forbattery charging and trickle charging.
The 12-V intermediate circuit voltage is converted into an output voltage of 48 V (nomi-nal value).
A circuit is also provided to protect the batteries from deep discharging. If the batteryvoltage falls below 10 V, the battery is disconnected from the load terminal after 2 to 5seconds. In this case, the green “Batt” LED goes out and the relay contact connects the“Batt” and “Ms” terminals.
The battery is reconnected either when the mains power is restored or by pressing the“Batt” test button.
3.4.5.3 Operating Elements
Fig. 3.38 SV 65 W 12 V/48 V, Front View
Battery port
Signal inputs
Port for temperature sensor
Mains connection
Output voltage
Button for forced batteryconnection
Test jack for battery voltage
(battery, mains, and PS supervision)
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LED display
The following operating modes are indicated on the power supply unit:
Switching to 115-V Mains Input Voltage
The power supply unit is preset to 230 V by default. To use 115 V, proceed as follows:
1. Read carefully the Warnings in Section 3.4.5.1.2. Deactivate the power supply and wait at least 30 seconds for the battery to deep dis-
charge.3. Remove all feed lines to the power supply unit.4. Loosen the attachment screws and remove the power supply unit from the
ONU 30 FTTB.5. Loosen the screws on the front plate and remove it.6. Remove the Faston connector from the “230 V” position and insert it in the “115 V”
position.
Fig. 3.39 Switching from 230 V to 115 V
Name (color) Meaning
BATT (green) Battery not deep discharged
MAinS (green) Power supplied
PSU (red) 48-V output voltage failure
Tab. 3.47 LED Displays on SV 65 W 12 V/48 V
115
V23
0 V
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3.4.6 Management Access
Fig. 3.40 Management Access to the ONU 30 FTTB
Management access to the ONU 30 FTTB is via the ECC channel of the CUD. The PCMhighway with ECC connects the CUD to the MSUE, see Fig. 3.40. The MSUE is themaster of the QD2 bus. CUD, LT and FAM are the slaves. In addition the LTx units areconnected bidirectionally to the ECC of the MSUE via the overhead (OH).
3.4.7 Front Panel ConnectorsFor front access to the data interfaces of the line card CPF2, the front panel connectorsS42023-A862-S12, -S13, -S14, -S15, -S25, -S26 and -S16 can be used, see UMN:IMN.The mounting plate with front panel connector is snapped in to bar of the MDF.
The cable S42022-A768-S24 connects the transfer connectors in the ONU 30 FTTBwith the front panel connectors.
MSUE
CUD
LCT
External
QD2-M
Measurement bus
PCM
MTA
F
Subscriber lines
QD2-S
9.6 kbit/s or 64 kbit/s
ECC
OSQD2-S
test equipment
Internal PCM highway
LTx
QD2-S
FAM
QD2-SOH
QD2 bus
LC LC1 3
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3.4.8 Technical Data
3.4.8.1 Environmental Conditions
3.4.8.2 Foreign Voltage Protection
3.4.8.3 Power Supply and Power Consumption
Operation acc. to ETSI EN 300 019-1-3.1E V2.1.2 (04/2003)Temperature range −5 °C to +45 °C
Transport acc. to ETSI EN 300 019-1-2.3 V2.1.4 (04/2003)Storage acc. to ETSI EN 300 019-1-1.3E V2.1.4 (04/2003)Product safety IEC 60950-1/EN 60950-1:2001 (1st edition)Degree of protection IP 20 acc. to EN 60529Compliance with CE and EMC re-quirements
acc. to ETS 300 386 V1.3.2 (05/2003)and DTAG 1TR9 (Ed. 09.2001 Rev. 06/2002)
Safety chemical/biological acc. to ETS 300 753, Tab. 1 (Ed. 1, 10/1997)Mechanical stability acc. to ETSI EN 300 019-1-3.1E V2.1.2 (04/2003)
Protection against external voltages on the outdoor subscriber lines (OTC applications) is implemented in 2 stages within the entire system. For further information see Section 1.4.7 and UMN:IMN.
Classification for external voltage protection acc. to EN 300 386 V1.3.2 (05/2003) ITC applications according ITU-T K.20 (07/2003), basic1) levelOTC applications according ITU-T K.45 (07/2003), basic1) level
Compliance with the earth conditions according ITU-TIndoor applications (inside subscriber building) K.31 (03/1993)ITC applications (inside telecommunication building) K.27 (05/1996)Outdoor applications (remote electronic sites) K.35 (05/1996)
Units, which are not meet the requirements above, contain specific information about the foreign power protection, see technical data of the line cards.
Power supply/batteryNominal voltagePermissible operating voltage rangeorNominal voltagePermissible operating voltage rangeFrequency of the input voltage
115 VAC 95 V to 132 VAC
230 VAC196 V to 254 VAC45 Hz to 68 Hz
Power consumption < 92 W
1) On enquiry, some line cards can also be used according enhanced level.
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3.4.8.4 Supervision Unit MSUE
QD2 Slave Interface
QD2 Master Interface
F Interface
ConfigurationQD2 slave serial bus system in acc. with
EIA RS485 Bus users 1 Master and
up to 30 slavesTransmission lines, Send and receive lines separated Symmetrical, 4-wireBit rate, autodetect 9.6/64 kbit/s Transmission mode Synchronous to receive dataLine code NRZIPermitted length 500 mProtocol
Initiator of data connectionAddresses of secondaries, can be set usingbackplane coding (6-bit)
HDLC (NRM, Polling)Primary
1 to 30TXD Idle state high resistanceRXD expected idle state Permanent flagsTermination, switchable 121 Ω
Configuration serial bus system in acc. with EIA RS485
Bus users 1 master and up to 30 slaves
Transmission lines, Send and receive lines separated symmetrical, 4-wireBit rate, configurable 9.6/64 kbit/s Transmission mode (with asynchronous operation) plesiochronous Line code NRZIPermitted length 500 mProtocol
Initiator of the data connectionAddresses of the secondaries
HDLC (NRM, Polling)Primary (COSU)1 to 30
TXD idle state Permanent flagsRXD expected idle state log. “1” (high-resistance)Termination
TXDRXD voltage divider
121 Ω383 Ω-147 Ω-383 Ω
Configuration Point-to-point acc. V.28Transmission lines shielded, unsymmetricalBit rate, autodetect 9,6/19,2/38.4 kbit/sTransmission mode asynchronousLine code NRZ
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Power Supply
3.4.8.5 Fan and Alarm Module FAM
QD2 Slave Interface
Power Supply
Permitted length 15 mProtocol
Frame structureAddress and control byteInitiator of the data connectionAddress of the secondary
IEC TC57HDLC (NRM, Polling)Primary (LCT)1
Connectors acc. IEC 807-2 (TXD: Pin 3, RXD:Pin 2) 9-pin SUB-D connector
Input voltages −36 V to −72 V, +5 VPower consumption at −60 V ≤ 50 mAPower consumption at +5 V ≤ 500 mA
Configuration QD2 slave serial bus system in acc. with EIA RS485
Transmission lines, Send and receive lines separated Symmetrical, 4-wireBit rate, autodetect 9.6/64 kbit/s Transmission mode Synchronous to receive dataLine code NRZIPermitted length 500 mProtocol
Initiator of data connectionAddress of the FAM, is set via backpl.coding (6-bit)
HDLC (NRM, Polling)Primary (MSUE)7
Input voltages −36 V to −72 V, +5 VCurrent consumption at −48 V
Fans in operationFans off
≤ 60 mA≤ 13 mA
Current consumption at +5 VFans in operationFans off
≤ 34 mA≤ 26 mA
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3.5 ONU 20 FTTO
3.5.1 DesignThe ONU 20 FTTO (Fiber to the Office) is accommodated within a compact housing forindoor operation. It can be used as either a desktop unit or it can be wall-mounted witha wall bracket.
The full range of FMX2R3.2 are available for the ONU 20 FTTO as subscriber interfaces.Because only two line card slots are available, the number of subscriber interfaces ofthe ONU 20 FTTO is less than that of the FMX2R3.2 in e. g. SNUS/FMX2S. Mixed linecard equipping is possible.
Fig. 3.42 shows the installation of the ONU 20 FTTO.
Fig. 3.41 Use of FMX2R3.2 Multiplexer in an ONU 20 FTTO (Example)
In addition a leased line connection for 1 × 2 Mbit/s can be created with theONU 20 FTTO or a branch exchange (PMXA) can be connected if only one 2-Mbit/s in-terface is used by the line terminating unit for the multiplexer.
Fig. 3.42 Front View of the ONU 20 FTTO (with and without Front Plate)
It contains the following modules and plug-in units, see Fig. 3.43:• Multiplexer FMX2R3.2 with
– 1 central unit CUD and– 1 to 2 line cards (SLX102/E, SUB102, UAC68, SEM106C, SEM108HC, SLB62,
LLA102/104C, I8S0P, I4UK2NTP, IUL82C, IUL84C, I4UK4NTP, CM64/2, CPF2, DSC104C, DSC6-n× 64C)
• 1 line terminating unit LTx (LT2ME1, LTO/LT, LTO/NT)• Supervision unit COSU• Central terminal panel• Terminal panels for the LCs.
LTxFMX2R3.2 FMX2R3.2
ONU 20 FTTO
2 Mbit/sG.703/
2 Mbit/sG.703
2 x 2 Mbit/s opticalSHDSL, UK2
I.431
POTS
ISDN (UK0/S0)Data (G.703/V.24/V.35/V.36/RS530/X.21)
2Dr/4Dr LL
CUD LC1 LC2 COSULTx
LED COSULED LTx
LED CUD Case cover for the reset SISA address switch andF interface
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Fig. 3.43 Structure of ONU 20 FTTO
An externally located power supply, product number V39113-Z5270-A610, with or with-out backup battery provides the ONU 20 FTTO with the required operating voltage.They are delivered with the device. If the AC supply fails, the backup battery backs upthe operating voltage to power the ONU 20 FTTO for about 4 hours. A direct −48 Vpower supply can also be used.
Fig. 3.44 ONU 20 FTTO with Power Supply and Backup Battery
LC CUD LTx
Central terminal panelLC terminal panel
1 n...
QD2-M1
T3out
Port A
Port B(CUD)
Port A
Port B2)
QD2-S ECC (CUD) OH
OF2 Mbit/sG.703
OF plug
1)
1) Switch on the central terminal panel2) Only available with plug-in units LTO, LT2ME1
1 2
QD2-S
COSU
QD2-M2
S1
S3
S2
S4
QD2-S
QD2-M1QD2-S
PS
Batt.48 V
115/230
optionally
VACF IF
Fan
connectorSHDSL
Uk2
iThe AC interface of the ONU 20 FTTO should be secured with an element to prevent over voltage (10 kV) that is tested according to IEC 61643-1 Class III. CE conformity is only guaranteed with this over voltage protector.The over voltage protector, product number V39118-Z6004-A62, is supplied along with the power supply unit intended for the ONU 20 FTTO.
Mains power
Battery (+)
54 V
Hole for
Central terminal panel
LC 2 terminal panel
LC 1 terminal panel
1,6 A (Si4AT)
Batt. 48 V/5 Ah
(2 × Sub-D, 15-pin)QD2-M1 QD2-SGround clamp
OF cable
48 V (-)
(-) (+)
supply
Si M 6.3 A+ −
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3.5.2 Configuration and EquippingDepending on the equipping and switch setting, the configurations as shown inFig. 3.45 are obtained.
Fig. 3.45 Configuration of the 2-Mbit/s Interfaces of ONU 20 FTTO
The equipment for the ONU 20 is shown in Fig. 3.46.
The SISA address of the ONU 20 is set on the supervision unit COSU, see Section3.5.9.4.
Fig. 3.46 ONU 20 Equipping and Addressing
CUDLTO/
CUDLTO/
CUD
2 Mbit/s, G.703 2 Mbit/s, G.703
CUDLTO/
CUD
LT2ME1 LT2ME1
LT2ME1
LT2ME1
Config. 5Config. 2
Config. 3
Config. 4Config. 1
Slot
LTx5
LC24
LC13
CUD2 (2)
Plug-in unit
(Address of the CUD)
CO
SU
1(1
)
(Address for ASA32 on
the COSU)
The address of the
COSU can be set
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The equipment options for the individual units are displayed in Tab. 3.48.
3.5.3 Hardware Settings
Fig. 3.47 Rear Side of the ONU 20 FTTO
Fig. 3.48 displays the backplane in the module frame (front view into the housing of theONU 20 FTTO; the front cover has been removed and the slide-in units have not yetbeen plugged in)
Plug-in place 201 202 203 204 205
COSU ×
CUD ×
LC1 and LC21) × ×
LTx2) ×
1) LC: SLX102/E, SUB102, UAC68, SEM106C, SEM108HC, SLB62, LLA102/104C, I8S0P, I4UK2NTP,
IUL82C, IUL84C, I4UK4NTP, CM64/2, CPF2 with up to 4 modules: CIM-V24/CIM-V35/CIM-V36/
CIM-X21/CIM-nx64E, DSC104C, DSC6-n× 64C
2) LTx: LTO/LT/NT, LTCOH, LT2ME1 with up to 2 modules Uk2mp/G703sh/SDSLmp/SDSLop/SDSL4op
Tab. 3.48 Equipping the ONU 20 FTTO
(+)
(−)
Battery
48 V
(+)
(−) 56 V
Power supply connection
Opening for pigtail leading
Grounding sleeve
Not fitted plug-in place must be
closed with a delivered cover plate
81
9 15QD2 slave
81
9 15QD2 master
1A (Si 4 AT)
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Fig. 3.48 Switches and Connectors in the ONU 20 FTTO
The backplane board is in the rear part of the ONU 20 housing on the inside of the rearpanel. To set DIL switches S1 to S4 you might have to remove the front cover and thebottom plug-in units.
The plug-in units are plugged into sockets X1 to X9.
DIL switches S1 to S4 are used to select the transmission path for the QD2 information,see Section QD2 Structure in the Shelf.
SISA-Addresses
QD2 Structure in the Shelf
The supervision of the ONU 20 as a remote station can be realized by different variants.Possible are the following variants:– Access via overhead channel of a line terminating unit (LTx)– Access via ECC channel of the CUD.
Prefer one of the last two variants should be used.
The signal paths for the QD2 data must be set using the DIL switches S1 to S3 on thebackplane of the ONU 20 FTTO.
S1 S2 S3
X1
X2
X3
X4
X5
X6
X7
X8
S4
X9
Unit Used in Slot QD2 address
COSU 1 is set using the DIL switch S1 on the COSU,
valid values 1 to 30, see also “Commissioning the COSU”
CUD 2 fixed address = 2
LTx 5 fixed address = 5
iFor each of this three DIL switches, all 4 slides of a DIL switch must always be set to the same position. Switches S3 and S4 may never be set to “ON” at the same time (all slides of a DIL switch are either “OFF” or “ON”)!
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The different setting options are shown in the following table:
Setting the DIL Switches on the Central Terminal Panel
The DIL switch on the central terminal panel is used to define the signal path of the sec-ond 2-Mbit/s connection (port 2) (i.e. this DIL switch can be used to make a connectionfrom port 2 of the CUD to port 2 of the LTO/LT2ME1, see configurations Fig. 3.45.
Transmission variant DIL Switch (at a time Slides 1 to 4)
S1 (O64) S2 (ECC) S3 (Slave) S4 (Master
Overhead of a LTx to QD2 Slave of the COSU ON OFF ON OFF
Overhead of a LTx to QD2 Master of the COSU ON OFF OFF ON
ECC of the CUD to QD2 Slave of the COSU OFF ON ON OFF
ECC of the CUD to QD2 Master of the COSU OFF ON OFF ON
External QD2 Slave of the ONU20 is used for supervision OFF OFF OFF OFF
iSwitches S3 and S4 may never be set to “ON” together (if S3 is “ON”, S4 should be “OFF” and vice versa)!
!If port 2 of the CUD and port 2 of the LTO/LT2ME1 are connected to one another, the plug connectors of this interfaces may not have any external connections.
Configuration (see also Fig. 3.45) All slides of the DIL switch in the
central terminal panel
2 ON
1, 3, 4 or 5 OFF
Tab. 3.49 DIL Switch Setting in the Central Terminal Panel
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3.5.4 Terminal PanelsThe central interfaces (of CUD and LTx) are accessible via terminal panels as shown inTab. 3.50.
For the line card interfaces the following terminal panels are available depending on theline card type:
3.5.4.1 Central Terminal PanelsBesides the copper line interfaces and the clock output T3out, the central terminal panelhas the following 2-Mbit/s interfaces:• 2-Mbit/s interface of the CUD (port 1)• 2-Mbit/s interface of the CUD (port 2)• 2-Mbit/s interface of the LTx (port 2)
The signal path of the CUD’s second 2-Mbit/s connection (port 2) is defined with this DILswitch (i.e. with this DIL switch, port 2 of the CUD can be connected to port 2 of theLTO/LT2ME1, configuration 2).
Terminal panel Application
S42024-A1867-A1 2 Mbit/s G.703 at 120 Ω via Sub-D
S42024-A1867-A2 2 Mbit/s G.703 at 120 Ω via Western sleeves
S42024-A1867-A3 2 Mbit/s G.703 at 75 Ω via BNC
Tab. 3.50 Central Terminal Panels on the ONU 20 FTTO
Terminal panel Application Connectors
S42024-A1867-A10 Universal 4 x 25polar Sub D
S42024-A1867-A16 UAC 68 6 x 8polige western connector
S42024-A1867-A17 CPF2, data interfaces V.24, V.35, V.36 und X.21
additionally, adaptation cable S42022-A768-S56 for V.24 interfaces
4 x 15polar Sub D
1 x 25polar Sub D
S42024-A1867-A4 CPF2, Ethernet interfaces 4 x RJ-45
S42024-A1867-A18 SLX102/E, SLB62, SUB102, IUL82C, IUL84C, I4UK4NTP, I4UK2NTP 10 x 8polar western connector
S42024-A1867-A19 I8S0P 8 x 8polar western connector
S42024-A1867-A20 CM64/2 1 x 9polar Sub D; 1 x 25polar Sub D
S42024-A1867-A21 DSC104C and DSC6-nx64C 10 x 8polar western connector
Tab. 3.51 Terminal Panels of Line Cards in ONU 20 FTTO
!Should the first 2-Mbit/s interface (port 1) of the CUD be used externally, no line termi-nating plug-in unit may be equipped, see Fig. 3.45, config. 5.
!If port 2 of the CUD and port 2 of the LTO/LT2ME1 are connected with one another, the plug connectors of this interfaces may not be wired externally.
iTo set the DIL switch, the terminal panel has to be taken off.
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Terminal Panel S42024-A1867-A1
Connector Assignment:
Terminal Panel S42024-A1867-A2
HDSL 2 HDSL 1 2 Mbit/s G.703T3 2 Mbit/s G.7032 Mbit/s G.703
ON1
4
Nameplate
Sub-D plugs 9-contact
Western sleevesRJ45 8/8
Sub-D plugs 9-contact
Terminal panel removed and
view from the top:
CUD
Port 2 Port 1LTx
Port 2
X1X2
X8X7X6X5X4X3
X6 X7 X8 X5 X4 X3
Pin CUD Port 2 CUD Port 1 LTx Port 1 LTx Port 2 T3out HDSL1 HDSL2
1 GND_S GND_S GND_S GND_S GND_S H1a1 (F1in_a1) H1a2 (F1in_a2)
2 E1in2_a E1in1_a E1out1_a E1in2_a T3out_a H1b1 (F1in_b1) H1b2 (F1in_b2)
3 E1out2_a E1out1_a E1in1_a E1out2_a GND_S GND_S GND_S
4 − − − − − H2a1 (F1out_a1) H2a2 (F1out_a2)
5 − − − − − H2b1 (F1out_b1) H2b2 (F1out_b2)
6 E1in2_b E1in1_b E1out1_b E1in2_b T3out_b GND_S GND_S
7 E1out2_b E1out1_b E1in1_b E1out2_b GND_S − −
8 − − − − − − −
9 − − − − −
HDSL2 HDSL1 2 Mbit/s G.703 T32 Mbit/s G.703 2 Mbit/s G.703
1
4
ON
Nameplate
123
Western sleeves RJ45 8/8 Sub-D plugs
9-contact
Terminal panel removed and
view from the top:
CUD
Port 2Port 1LTx
Port 2
X1X2
X8X7X6X5X4X3
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Connector assignment:
Terminal Panel S42024-A1867-A3
Connector assignment:
X8 X5 X6 X7 X4 X3
Pin T3out LTx Port 2 CUD Port 1 LTx Port 1 CUD Port 2 HDSL1 HDSL2
1 GND_S E1out2_a E1out1_a E1in1_a E1out2_a H1a1 (F1in_a1) H1a2 (F1in_a2)
2 T3out_a E1out2_b E1out1_b E1in1_b E1out2_b H1b1 (F1in_b1) H1b2 (F1in_b2)
3 GND_S GND_S GND_S GND_S GND_S GND_S GND_S
4 − E1in2_a E1in1_a E1out1_a E1in2_a H2a1 (F1out_a1) H2a2 (F1out_a2)
5 − E1in2_b E1in1_b E1out1_b E1in2_b H2b1 (F1out_b1) H2b2 (F1out_b2)
6 T3out_b GND_S GND_S GND_S GND_S GND_S GND_S
7 GND_S − − − − − −
8 − − − − − − −
9 −
Pin T3out HDSL1 HDSL2
1 GND_S H1a1 (F1in_a1) H1a2 (F1in_a2)
2 T3out_a H1b1 (F1in_b1) H1b2 (F1in_b2)
3 GND_S GND_S GND_S
4 − H2a1 (F1out_a1) H2a2 (F1out_a2)
5 − H2b1 (F1out_b1) H2b2 (F1out_b2)
6 T3out_b GND_S GND_S
7 GND_S − −
8 − − −
9 −
Nameplate
Western sleeves RJ45 8/8 SUB-D
Terminal panel removed and
view from the top:
HDSL2 HDSL1 2 Mbit/s G.703 T32 Mbit/s G.703 2 Mbit/s G.703
ON
1 4
BNC BNC
X10 X11X9X8X7X6X5X4X3
LTx
Port 2 Port 1CUD
Port 2
X1X2
9-contact
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3.5.4.2 Terminal Panels for Line CardsTerminal panels according to Tab. 3.51 are usable as terminal panel for line cards 1 and 2 of the ONU 20 FTTO.
Terminal Panel S42024-A1867-A4
Connector assignment:
LTx Port 2 Port 1 CUD Port 2
X5 X6 X7 X8 X9 X10
CUD LTx CUD LTx
Wire E1in2_a E1out2_a E1in1a E1out1_a E1out1a E1in1_a E1in2a E1out2a
Cable
screen
E1in2_b E1out2_b E1in1b E1out1_b E1out1b E1in1_b E1in2b E1out2b
Mo
du
le 2
Mo
du
le 4
Link
Eth1 Eth2 Eth3 Eth4
Link
Eth1 Eth2 Eth3 Eth4CLI CLI
Terminal panel pulled out,top view:
Data plate
X5X4 X3
X1X2
X6
X5 X6 X3 X4
Pin Eth1 Eth2 Eth3 Eth4 Eth1 Eth2 Eth3 Eth4 CLI CLI
1 TX1_1_a TX2_1_a TX3_1_a TX4_1_a TX1_2_a TX2_2_a TX3_2_a TX4_2_a
2 TX1_1_b TX2_1_b TX3_1_b TX4_1_b TX1_2_b TX2_2_b TX3_2_b TX4_2_b RS232out_1 RS232out_2
3 RX1_1_a RX2_1_a RX3_1_a RX4_1_a RX1_2_a RX2_2_a RX3_2_a RX4_2_a RS232in_1 RS232in_2
4
5 GND_S GND_S
6 RX1_1_b RX2_1_b RX3_1_b RX4_1_b RX1_2_b RX2_2_b RX3_2_b RX4_2_b
7 − −
8 − −
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Terminal Panel S42024-A1867-A10 (Universal)
Connector assignment:
Pin X3 (Sleeve A) X4 (Sleeve B) X5 (Sleeve C) X6 (Sleeve D)
1 GND_S GND_S GND_S GND_S
2 L1_B25 L1_B17 L1_B9 L1_B1
3 L1_C26 L1_C18 L1_C10 L1_C2
4 L1_A26 L1_A18 L1_A10 L1_A2
5 L1_B27 L1_B19 L1_B11 L1_B3
6 L1_C28 L1_C20 L1_C12 L1_C4
7 L1_A28 L1_A20 L1_A12 L1_A4
8 L1_B29 L1_B21 L1_B13 L1_B5
9 L1_C30 L1_C22 L1_C14 L1_C6
10 L1_A30 L1_A22 L1_A14 L1_A6
11 L1_B31 L1_B23 L1_B15 L1_B7
12 L1_C32 L1_C24 L1_C16 L1_C8
13 L1_A32 L1_A24 L1_A16 L1_A8
14 L1_C25 L1_C17 L1_C9 L1_C1
15 L1_A25 L1_A17 L1_A9 L1_A1
16 L1_B26 L1_B18 L1_B10 L1_B2
17 L1_C27 L1_C19 L1_C11 L1_C3
18 L1_A27 L1_A19 L1_A11 L1_A3
19 L1_B28 L1_B20 L1_B12 L1_B4
20 L1_C29 L1_C21 L1_C13 L1_C5
21 L1_A29 L1_A21 L1_A13 L1_A5
22 L1_B30 L1_B22 L1_B14 L1_B6
23 L1_C31 L1_C23 L1_C15 L1_C7
24 L1_A31 L1_A23 L1_A15 L1_A7
25 L1_B32 L1_B24 L1_B16 L1_B8
Pin terms of the connectors A to D relating to pin terms of connected LC connector.
ON
14
ON
4 1
Data plate
universal access panel
A B C D
25polarS2S1 4xSub-D plugs
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Terminal panel S42024-A1867-A16
Connector assignment:
Terminal Panel S42024-A1867-A17
Pin X8 (Port 1) X7 (Port 2) X6 (Port 3) X5 (Port 4) X4 (Port 5) X3 (Port 6)
1 S21in_1 S21in_2 S21in_3 S21in_4 S21in_5 S21in_6
2 S22in_1 S22in_2 S22in_3 S22in_4 S22in_5 S22in_6
3 F2in_b1 F2in_b2 F2in_b3 F2in_b4 F2in_b5 F2in_b6
4 F2out_b1 F2out_b2 F2out_b3 F2out_b4 F2out_b5 F2out_b6
5 F2out_a1 F2out_a2 F2out_a3 F2out_a4 F2out_a5 F2out_a6
6 F2in_a1 F2in_a2 F2in_a3 F2in_a4 F2in_a5 F2in_a6
7 S21out_1 S21out_2 S21out_3 S21out_4 S21out_5 S21out_6
8 S22out_1 S22out_2 S22out_3 S22out_4 S22out_5 S22out_6
Port2 Port1Port4 Port3Port5Port6
Date plate
access panel for UAC68
Western sleeves RJ45 8/8
X1X2
X3 X4 X5 X6 X7 X8
access panel for CPF2
Data plate
15polarSub D sleeve
15polarSub D sleeve
15polarSub D sleeve
15polarSub D sleeve
X5 X6X4X3
X1X2
Port4 SN3 Port3 SN2 Port2 SN1 Port1 SN0
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Connector assignment:
Cable for standardized V.24 interface
The V.24 interface of the CPF2 can be attached to a 25-pin sub-D connector in a stan-dard connection with the S42022-A768-S56 cable, see the following figure, theUMN:IMN contains the pin assignment.
Fig. 3.49 Connecting Cable S42022-A768-S56
P X3 (Port 4) X4 (Port 3) X5 (Port 2) X6 (Port 1) P X3 (Port 4) X4 (Port 3) X5 (Port 2) X6 (Port 1)
1 GND_S GND_S GND_S GND_S 9 SN3_aN_b SN2_aN_b SN1_aN_b SN0_aN_b
2 SN3_in_a SN2_in_a SN1_in_a SN0_in_a 10 SN3_CNTL_b SN2_CNTL_b SN1_CNTL_b SN0_CNTL_b
3 SN3_CNTL_a SN2_CNTL_a SN1_CNTL_a SN0_CNTL_a 11 SN3_aB_b SN2_aB_b SN1_aB_b SN0_aB_b
4 SN3_aB_a SN2_aB_a SN1_aB_a SN0_aB_a 12 SN3_inD_b SN2_inD_b SN1_inD_b SN0_inD_b
5 SN3_inD_a SN2_inD_a SN1_inD_a SN0_inD_a 13 SN3_SCLK_b SN2_SCLK_b SN1_SCLK_b SN0_SCLK
_b
6 SN3_SCLK_a SN2_SCLK_a SN1_SCLK_a SN0_SCLK_a 14 SN3_XCLK_b SN2_XCLK_b SN1_XCLK_b SN0_XCLK
_b
7 SN3_XCLK_a SN2_XCLK_a SN1_XCLK_a SN0_XCLK_a 15 - - - -
8 GND GND GND GND
Parallel wire to pin 12)
per IECWHOGBUGNVTTQBN
Wire color code
wsorblgnvitkbr
whiteorangebluegreenvioletturquoisebrown
S-02YS(St)CH 8x2x0,4/0,8-120(V42255-Z1004-A8)
1);2)
1 1ws1tk2ws2tk3ws3tk4ws
1bl1vi2or2vi3gn3vi
1ws2ws1tk2or2tk4ws1vi
3gn
3ws3vi
1bl2vi
3tk
1
1);2)
Shielding braid: 1)
Parallel wire Parallel wire
use installation instruction S42021-A124-Z25-*-31
Front panelconnectorS42024-A1867-A17
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Terminal Panel S42024-A1867-A18
Connector assignment:
Terminal Panel S42024-A1867-A19
Connector assignment (terminal panel status 02):
X7 X8X5 X6X4X3
Data plate
access panel for UNI1
Western sleevesRJ45 8/8
X1X2
X11 X12X9 X10
10 9 8 7 6 4 3 2 1Connector5
Pin X3
(conn. 10)
X4
(conn. 9)
X5
(conn. 8)
X6
(conn. 7)
X7
(conn. 6)
X8
(conn. 5)
X9
(conn. 4)
X10
(conn. 3)
X11
(conn. 2)
X12
(conn. 1)
1 to 3
4 SBb10 SBb9 SBb8 SBb7 SBb6 SBb5 SBb4 SBb3 SBb2 SBb1
5 SBa10 SBa9 SBa8 SBa7 SBa6 SBa5 SBa4 SBa3 SBa2 SBa1
6 to 8
X7 X8X5 X6X4X3
Data plate
access panel for I8S0P
Western sleevesRJ45 8/8
X1X2
X9 X10
Port2 Port1Port4 Port3Port5Port6Port7Port8
Pin X3 (Port 8) X4 (Port 7) X5 (Port 6) X6 (Port 5) X7 (Port 4) X8 (Port 3) X9 (Port 2) X10 (Port 1)
1 and 2
3 S0b8 S0b7 S0b6 S0b5 S0b4 S0b3 S0b2 S0b1
4 S0d8 S0d7 S0d6 S0d5 S0d4 S0d3 S0d2 S0d1
5 S0c8 S0c7 S0c6 S0c5 S0c4 S0c3 S0c2 S0c1
6 S0a8 S0a7 S0a6 S0a5 S0a4 S0a3 S0a2 S0a1
7 and 8
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Connector assignment (terminal panel status 03):
Terminal Panel S42024-A1867-A20
Connector assignment:
Pin X3 (Port 8) X4 (Port 7) X5 (Port 6) X6 (Port 5) X7 (Port 4) X8 (Port 3) X9 (Port 2) X10 (Port 1)
1 and 2
3 S0a8 S0a7 S0a6 S0a5 S0a4 S0a3 S0a2 S0a1
4 S0c8 S0c7 S0c6 S0c5 S0c4 S0c3 S0c2 S0c1
5 S0d8 S0d7 S0d6 S0d5 S0d4 S0d3 S0d2 S0d1
6 S0b8 S0b7 S0b6 S0b5 S0b4 S0b3 S0b2 S0b1
7 and 8
Pin X3 (data) Pin X3 (data) Pin X4 (F2 port)
1 GND_S 14 out1b 1 GND_S
2 out1a 15 in1b 2 E1ina
3 in1a 16 out2b 3 E1outa
4 out2a 17 in2b 4 -
5 in2a 18 out3b 5 -
6 out3a 19 in3b 6 E1inb
7 in3a 20 out4b 7 E1outb
8 out4a 21 in4b 8 -
9 in4a 22 - 9 -
10 - 23 -
11 - 24 -
12 - 25 -
13 -
Data plate
access panel for CM64/29polar
Sub-D sleeve25polar
Sub-D sleeve
X1X2
X4X3
Daten-Port E1-Port 2Mbit/s G.703
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Terminal Panel S42024-A1867-A21
Connector assignment:
Terminal Panel S42024-A1867-A22
X7 X8X5 X6X4X3
access panel for DSC104CO
Shielded western sleeves RJ45 8/8
X1X2
X11 X12X9 X10
Port 10 Port 9 Port 8 Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1
Data plate
Pin X3
(Port 10)
X4
(Port 9)
X5
(Port 8)
X6
(Port 7)
X7
(Port 6)
X8
(Port 5)
X9
(Port 4)
X10
(Port 3)
X11
(Port 2)
X12
(Port 1)
1 D2outa10 D2outa9 D2outa8 D2outa7 D2outa6 D2outa5 D2outa4 D2outa3 D2outa2 D2outa1
2 D2outb10 D2outb9 D2outb8 D2outb7 D2outb6 D2outb5 D2outb4 D2outb3 D2outb2 D2outb1
3 GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S
4 D2ina10 D2ina9 D2ina8 D2ina7 D2ina6 D2ina5 D2ina4 D2ina3 D2ina2 D2ina1
5 D2inb10 D2inb9 D2inb8 D2inb7 D2inb6 D2inb5 D2inb4 D2inb3 D2inb2 D2inb1
6 GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S
7 - - - - - - - - - -
8 - - - - - - - - - -
9 GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S
10 GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S
X7 X8X5 X6X4X3
access panel for DSC6-nx64G
Shielded western sleevesRJ45 8/8 X1X2
X11X9 X10
Ch6 codi Ch5 codi Ch4 codi Ch3 codi Ch2 codi Ch2 Contra Ch1 codi Ch1 Contra TAN_A/B
Data plate
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Connector assignment:
3.5.5 Clock SupplyThe ONU 20 is supplied with a clock via the incoming signal of a line termination unit(synchronization via E1in). The central card can then provide a T3out via a SUB-D con-nector. Hardware settings are not required for this.
3.5.6 Power Supply
The following interfaces are available for power supply:• 1 × SUB-D jack (3W3) for connecting an external power pack, see Fig. 3.44 and
Fig. 3.47• 1 × 3-contact plug for connecting an optional 48-V battery with 5 Ah, see Fig. 3.44,
Fig. 3.47 and Fig. 3.50.In the case of mains failure during operation, an automatic switch-over to the battery takes place. Deep discharge protection for the battery is available.
Pin X31)
(chann. 6)
X41)
(chann. 5)
X51)
(chann. 4)
X61)
(chann. 3)
X71)
(chann. 2)
X82)
(chann. 2)
X91)
(chann. 1)
X102)
(chann. 1)
X11
(clock, central)
1 D2outa6 D2outa5 D2outa4 D2outa3 D2outa2 D2outa2 D2outa1 D2outa1
2 D2outb6 D2outb5 D2outb4 D2outb3 D2outb2 D2outb2 D2outb1 D2outb1
3 GND_S GND_S GND_S GND_S GND_S T22a2 GND_S T22a1 GND_S
4 D2ina6 D2ina5 D2ina4 D2ina3 D2ina2 D2ina2 D2ina1 D2ina1 Tina
5 D2inb6 D2inb5 D2inb4 D2inb3 D2inb2 D2inb2 D2inb1 D2inb1 Tinb
6 GND_S GND_S GND_S GND_S GND_S GND_S GND_S T22b1 GND_S
7 - - - - - T21a2 - T21a1
8 - - - - - T21b2 - T21b1
9 GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S
10 GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S GND_S
1) codirectional
2) contradirectional
iThe AC interface of the ONU 20 FTTO is to be secured with an over voltage element (10 kV) that has been tested according to IEC 61643-1 Class III. CE conformity is only assured with this over voltage element.The over voltage protector is supplied along with the power supply intended for the ONU 20 FTTO. The product number is V39118-Z6004-A62.
iPower is supplied to the cards in the ONU 20 FTTO by means of the monitoring module (COSU) and the CUD central card. These should not be removed for this reason.
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Fig. 3.50 Battery Block
As an alternative to the external power pack, a battery voltage in the range from –48 Vto –60 V can also be introduced via the SUB-D jack (3W3). In this case the battery maynot be connected.
3.5.7 Operating Status DisplayThe following operating states are displayed on the module:• Operating states of the MUX and the line terminal equipment with a red and green
LED respectively• Operating states of the COSU and of the power supply with a red and green LED
Presence of secondary voltage from the external power pack and battery voltage as well as internal temperature, fan failure and operation of exhaustive discharge pro-tection are displayed with one red and one green LED
If there is a loss of network voltage during operation, supply is automatically switched tothe rechargeable battery, providing further operation of the ONU for 8 hours with 0.6 Er-lang (e.g. equipment with two SUB102 and 20° C).Exhaustive discharge protection is available for the battery which switches the batterypower supply off immediately if 40 V is not reached.
3.5.8 Local Operation of the ONU 20 FTTOTo connect a local PC to the ONU 20 FTTO, the cover plate at the front cover must beremoved, see also Fig. 3.44.• Remove the two screws A and then the cover plate.• Keep the cover plate and the screws for that case, the ONU 20 FTTO shall be re-
mote controlled.
Battery 48 V/ 5 Ah
Si M 6.3 A
bkrd
Fuse
6.3 A middle quick
!The battery block is supplied pre-charged. Check the battery block for any damage which may have occurred in transit. Check if the battery is properly charged. Warning: do not short circuit the battery block during installation (by using an open end wrench)!
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3.5.9 Control and Supervision Unit COSU
3.5.9.1 OverviewModule COSU provides access for the operating system (OS) to the ONU 20 FTTO andhandles control and supervision functions.
Over and above this, the COSU controls the connection of the external battery, depend-ing on the mains adapter voltage available.
The COSU performs the following functions:• Implements a virtual concentrator (SISA-V/LMX V4)
The COSU implements a SISA-V/LMX V4 which maintains the network element ASA32 as permanently present in its polling list.
• Provision of a QD2 slave interface (L1 and L2 termination)• Provision of 2 × QD2 master interfaces (L1 and L2 termination)
– QD2 Master 1 for operating the modules within the ONU 20 FTTO– QD2 Master 2 or operating remote network elementsThe two master interfaces are combined to form one logical interface.
• Operation of a local F interface• Performing self tests
The operating system of the COSU performs self-tests of the module components and interfaces during the initialization phase. In the event of an error the correspond-ing error signals are generated.
• Supervision, control and alarm signaling functions(power failure, deep discharge of the battery, fan alarm, overtemperature)The internal temperature of the ONU 20 FTTO is recorded using measurement sen-sors. These connect a fan which ensures better distribution and dissipation of the heat as required.
• Provision of the system time (RTC)
Module COSU has the following interfaces:• QD2 slave in accordance with EIA RS485
A bus terminating resistor of 120 Ω can be connected.• 2 × QD2 masters in accordance with EIA RS485• F interface in accordance with ITU-T V.28• Inputs to read out the type label data• Input voltage +5 V from unit CUD• Power supply from external adapter and also backup battery• Output voltage−48 V for multiplexer and line equipment
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3.5.9.2 Battery controlThe COSU monitors and controls the AC line adapter voltage and the battery voltage.
With an input voltage greater than 20 V (typically 33 V) the DC/DC switches on theCOSU and the central unit CUD after a startup time of < 1 s. From a adapter voltage of43 V to 44 V the backup battery, if available will be connected via a relay.
If the adapter voltage drops below 43 V to 44 V an alarm is raised to indicate failure. Thesystem then continues to operate with battery backup. If the adapter voltage becomesavailable again during the battery backup, this is connected.
If the battery voltage falls below 41 V to 43 V with no adapter voltage, an alarm is issuedand this is signalled with LEDs. The unit is switched off with a delay of around 2 minutes.The delayed switch-off in the event of deep discharge is software-controlled. If the bat-tery voltage falls below 40 V in the absence of any adapter voltage, switch-off is imme-diate.
It is only possible to commission the ONU 20 FTTO if the adapter voltage is present.
SlavePort 1
−48 V
Internal interfaces
Type labeldata
QD2 master 1
External interfaces
F
ASA32
SISA-VQD2 slaveMaster
PortQD2 master 2
Localoperation
fromadapter
tothe NEsin the TMN
Processor
EMVDC
tobackupEMV
DC
battery
RTCMeas. sen.
Fan
F. 4 A
−48 V
+5 V−48 V
to MUXand LTx
from CUD
ONU20FTTO
COSU
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3.5.9.3 Supervision and Alarm SignallingThe operating state of the COSU and the supervision criteria relevant for power supplyto the ONU 20 FTTO are shown by two LEDs as well as external alarms in the OS inaccordance with the table below.
3.5.9.4 Switch Settings
Fig. 3.51 Supervision Unit COSU
LED (green) LED (red) Status External alarms in the OS
on off Operating normally, power being
correctly supplied via adapter
flashing − Failure of adapter supply AI 02 (power supply alarm)
flashing on Deep discharge protection active,
delayed switch-off
AI 01 (battery alarm)
flashing flashing Address detected equal to 0 or greater
than 30
− flashing Increased operating temperature
(60°C ≤ T ≤ 70°C)
− on Overtemperature (T > 70°C); AI 06 (temperature)
Fan failure AI 05 (fan 1 alarm)
off off No AC adapter power and no battery
backup
Tab. 3.52 Optical Signalling of the COSU
S12345
1
H1
H2
F1
X3
X4
X2
X1
ON
S212
ON
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Setting the SISA V/LMX Address for the Corresponding Unit (COSU)
The SISA V/LMX address is set using the slides of the DIL switch S1 on the COSU, seeFig. 3.51. This DIL switch can be found behind the removable housing cover betweenthe sub-D connector and the LEDs.
DIL switch for the SISA/QD2 address:
Slides 1 to 5 define the SISA-V/LMX address. This address can be set in the range of 1to 30. The ON position is logic 0 and the OFF position is logic 1. The address must beset according to the SISA network plan.
Address Switch S1
Setting the QD2 termination
The QD2 termination is set with the DIL switch S2, see Fig. 3.51. The switch settingsare described in the following table:
1 2 3 4 5
20 21 22 23 24
SISA-V/LMX-address (COSU) Bit 20-24
ON = LOW = log 0
Example:
Switch 1 to OFF in accordance with 20 = 1
Switch 5 to OFF in accordance with 24 = 16
In accordance with address 17 for the COSU of ONU20
5
ON (0)OFF (1)
24
23
22
21
20 1
Switch setting Meaning
OFF QD2S termination high-impedance
ON QD2S termination 120 Ohm
Tab. 3.53 Setting the DIL Switch S2
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3.5.10 Technical Data
3.5.10.1 Environmental Conditions
3.5.10.2 Foreign Voltage Protection
3.5.10.3 Power Supply and Power Consumption
Operation acc. to ETSI EN 300 019-1-3.1E V2.1.2 (04/2003)Temperature range −5 °C to +45 °C
Transport acc. to ETSI EN 300 019-1-2.3 V2.1.4 (04/2003)Storage acc. to ETSI EN 300 019-1-1.3E V2.1.4 (04/2003)Product safety IEC 60950-1/EN 60950-1:2001 (1st edition)Degree of protection IP 20 per EN 60529EMC acc. to ETS 300 386 V1.3.2 (05/2003)
and DTAG 1TR9 (Ed. 09.2001 Rev. 06/2002)Noise level max. 6.3 bels
per ETS 300 753 (Ed. 1, 10/1997)Safety chemical/biological acc. to ETS 300 753, Tab. 1 (Ed. 1, 10/1997)Mechanical stability acc. to ETSI EN 300 019-1-3.1E V2.1.2 (04/2003)
Protection against external voltages on the outdoor subscriber lines (OTC applications) is implemented in 2 stages within the entire system. For further information see Section 1.4.7 and UMN:IMN.
Classification for external voltage protection acc. to EN 300 386 V1.3.2 (05/2003) ITC applications according ITU-T K.20 (07/2003), basic1) levelOTC applications according ITU-T K.21 (07/2003), basic1) level
Compliance with the earth conditions according ITU-TIndoor applications (inside subscriber building) K.31 (03/1993)ITC applications (inside telecommunication building) K.27 (05/1996)Outdoor applications (remote electronic sites) K.35 (05/1996)
In the case of the ONU 20 FTTO, general protection is implemented on the connection panel intended for the relevant line card if the line card has outdoor ports (see the tech-nical data for the relevant line card).
Power supply/batteryNominal voltagePermissible operating voltage rangeorNominal voltagePermissible operating voltage rangeFrequency of the input voltage
115 VAC 95 V to 132 VAC
230 VAC196 V to 254 VAC45 Hz to 68 Hz
Power consumption < 56 W
1) On enquiry, some line cards can also be used according enhanced level.
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3.5.10.4 Control and Supervision Unit COSU
QD2 Slave Interface
QD2 Master Interface
F Interface
ConfigurationQD2 slave serial bus system in acc. with
EIA RS485 Bus users 1 Master and
up to 30 slavesTransmission lines, Send and receive lines separated Symmetrical, 4-wireBit rate, autodetect 9.6/64 kbit/s Transmission mode Synchronous to receive dataLine code NRZIPermitted length 500 mProtocol
Initiator of data connectionAddresses of secondaries, can be set usingbackplane coding (6-bit)
HDLC (NRM, Polling)Primary
1 to 30TXD Idle state high resistanceRXD expected idle state Permanent flagsTermination, switchable 121 Ω
Configuration serial bus system in acc. with EIA RS485
Bus users 1 master and up to 30 slaves
Transmission lines, Send and receive lines separated symmetrical, 4-wireBit rate, configurable 9.6/64 kbit/s Transmission mode (with asynchronous operation) plesiochronous Line code NRZIPermitted length 500 mProtocol
Initiator of the data connectionAddresses of the secondaries
HDLC (NRM, Polling)Primary (COSU)1 to 30
TXD idle state Permanent flagsRXD expected idle state log. “1” (high-resistance)Termination
TXDRXD voltage divider
121 Ω383 Ω-147 Ω-383 Ω
Configuration Point-to-point in acc. with V.28
Transmission lines shielded, unsymmetricalBit rate, autodetect 9,6/19,2/38.4 kbit/sTransmission mode asynchronousLine code NRZ
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Power Supply
Permitted length 15 mProtocol
Frame structureAddress and control byteInitiator of the data connectionAddress of the secondary
IEC TC57HDLC (NRM, Polling)Primary (LCT)1
Connectors 9-pin SUB-D connectorin acc. with IEC 807-2(TXD: Pin 3, RXD:Pin 2)
Input voltages −36 V to −72 V, +5 V
Power consumption at −60 V ≤ 50 mAPower consumption at +5 V ≤ 500 mA
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3.6 CUD Central Unit Drop/Insert
3.6.1 OverviewThe CUD unit forms the interface between the line cards of the multiplexer and the PCMsignals at the E1 ports, E1A and E1B. It works in a synchronous network, as a terminalmultiplexer or drop insert multiplexer.
The CUD has the following functions:• multiplex functions for data and speech signals,• provision of all clock and control signals,• monitoring and control of the multiplexer via the QD2 interface,• provision of an internal control channel ECC,• control and signaling of subscriber interfaces,• power supply for internal requirements of the CUD and LCs,• ZA(A)/ZA(B) interface for alarm signaling in the direction of the central service ob-
servation equipment,• insertion of busy tone.
Time slot control via a timed task is possible via the internal clock of the CUD for com-plete 64-kbit/s channels, or for n × 64 kbit/s. No timed tasks for subrates, conference orpoint-to-multipoint operation must be set up.
The following interfaces are implemented:• 2-Mbit/s interfaces E1A and E1B according to ITU-T G.703/9,• Clock interfaces T3in and T3out according to ITU-T G.703/13,• ZA(A)/ZA(B) interfaces to central service observation equipment,• QD2 slave interface according to EIA RS485,• ECC interface according to ITU-T V.11,• Sa5 to Sa8 interfaces for Sa bits in report word according to EIA RS485,• LC bus to channel plug-in units,• PCM highway,• −48 V or −60 V power supply.
CUD
External interfacesInternal interfaces
PCM highway
64 kHz
sync
clock
PCM4 Mbit/s
LC bus ADR0...4
−5 V+5 V
−48 V/−60 V −48 V/−60 V
power
T3in/T3out
PCM
2 Mbit/sE1A (G.703)
ZA(A), ZA(B)
Sa5 to Sa8
cent.serv.ob.
network elementaddress
QD2 slave
backplanecoding
supplyfor LCs
PCM
2 Mbit/sE1B (G.703)
ECC ECC channel
Sa bit channel
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3.6.2 Monitoring and AlarmsMultiplexer alarms are analyzed and signaled according to an alarm table.
Alarm table
The evaluation and signaling of alarms by the multiplexer is carried out as defined in thetable of alarms, see Tab. 3.54.
Action
Alarm criteria
Alarms Port A Port B AIS in switched
channels
Blo
ck T
3ou
t
E1out Block to the LC E1out Block to the LC A →B B → A
A B S
D-b
it
Dk-
bit
AIS
D2o
ut
(zd
)
Sig
. (zs
b)
NF
ou
t
VL
C
Sao
ut
D-b
it
Dk-
bit
AIS
D2o
ut
(zd
)
Sig
(zs
b)
NF
ou
t
VL
C
Sao
ut
TS
TS
16
TS
TS
16
E1in port A
LOS 10 10 × × × × × × × × (×)
AIS 10 × × × × × × × × (×)
SYN 10 10 × × × × × × × ×
BER−3 10 10 × × × × × × × ×
BER−5/−6 (10)
D-bit (A-bit) (10) 10 × ×
N-bit
AISK (10) 10 × × ×
SYNK (10) 10 × × ×
Dk-bit (10) 10 × ×
Nk-bit
E1in port B
LOS 10 10 × × × × × × × × (×)
AIS 10 × × × × × × × × (×)
SYN 10 10 × × × × × × × ×
BER−3 10 10 × × × × × × × ×
BER−5/−6 (× )
D-bit (A-bit) (10) 10 × ×
N-bit
AISK (10) 10 × × ×
SYNK (10) 10 × × ×
Dk-bit (10) 10 × ×
Nk-bit
Internal
Test mode 10 × × × × × × × × × × ×
LT 10
Tab. 3.54 Table of Alarms of the CUD
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Loss of −5 V × × × × × × × × × × × × × × × × × ×
Loss of +5 V × ×
ULC × × × × × × × ×
POW × ×
BEC unit × × × × × × × ×
LC unit × ×
D2/F2 port
Channel alarm 10
Urgent chan-
nel fault
10 10
Diagnosis
LL at port
A+KS
10 × × × × × × (×)
LL at port A 10 × × × (×)
RL at port A 10 × × × × ×
LL at port
B+KS
10 × × × × × × (×)
LL at port B 10 × × × (×)
RL at port B 10 × × × × ×
PM 10
× Αχτ ι ον ι σ περφορμεδ10 Action is performed after a delay of 10 s
(× ) Action is switchable
Action
Alarm criteria
Alarms Port A Port B AIS in switched
channels
Blo
ck T
3ou
t
E1out Block to the LC E1out Block to the LC A →B B → A
A B S
D-b
it
Dk-
bit
AIS
D2o
ut
(zd
)
Sig
. (zs
b)
NF
ou
t
VL
C
Sao
ut
D-b
it
Dk-
bit
AIS
D2o
ut
(zd
)
Sig
(zs
b)
NF
ou
t
VL
C
Sao
ut
TS
TS
16
TS
TS
16
Tab. 3.54 Table of Alarms of the CUD (Cont.)
Alarm criteriaLOS Loss of signal at E1in (more than 32 consecutive zeros)AIS AIS at E1in (continual ‘one’)SYN Loss of frame synchronization or loss of the E1in CRC4 frameBER−3 Bit error rate at E1in ≥10–3
BER−5/−6 Bit error rate at E1in with CRC4 frames: ≥10-6
without CRC4 frames: ≥10-5
D-bit Bit 3 (A-bit) of the service word receivedD-bit is “H” if the remote multiplexer is malfunctioning (remote alarm).
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N-bit Bit 4 (bit Sa4) of the service word received,can be used for swapping the synchronization clock source,N-bit = “L” is indicated.
AISK AIS (continuous ‘one) in time slot 16SYNK Loss of synchronization in the signaling multiframe at E1inDk-bit Bit 6 of time slot 16 in frame 0
Dk-bit in the received signal is “H” in the case of a multiframe remote alarm
Nk-bit Bit 7 of time slot 16 in frame 0 Nk-bit = “0” in the received signal is indicated
The criteria AISK, SYNK, Dk-bit and Nk-bit are only effective when the signaling frame is switched on.
Internal Test mode Self test by the CUD computer during the switch-on phaseSync. clock Failure of the synchronization clock T3in, or internal faultΛ οσσ οφ −5 V Failure of the −5 V operating voltage on the CUDLoss of +5 V Failure of the +5 V operating voltage on the CUDUKZU Failure of the −48 V/−60 V voltage for specific LCsBEU unit Failure of the −5 V voltage or VLC for LCs LC unit Malfunction of an LC
LCs 7 to 12 of an expanded multiplexer will be reported as faulty even if the +5 V voltage for the BEU has failed.
F2/D2 portChannel alarm The number of faulty channels is greater than or equal to a
specified threshold (depends on the specification of the LC).Urgent channel fault At least one channel is reporting an urgent channel fault (de-
pends on the specification of the LC).
DiagnosticsLL Local loop on the E1 portRL Remote loop on the E1 portPM At least one channel is in test mode (depends on the
specification of the LC).
Actions
AlarmsA A alarmB B alarmS S alarmAt the ZA(A) break contact, the output is either an A alarm or an S alarm, and if both apply an operating voltage failure is output.The ZA(B) make contact sends a B alarm to the ZBBeo.
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Operating state indications
The operating state of the CUD, and thus of the multiplexer, is indicated by one red andone green LED on the front of the CUD, see Tab. 3.55.
Monitoring transmission quality at E1in according to ITU-T G.821/G.826
The PCM signal which is received at the E1 port is continuously analyzed. Errors whichare identified in this signal (quality values) can be called up from the data memory.
If the CRC4 frame is switched on, the analysis is according to ITU-T G.826, and back-ground block errors (BBE) are identified. Without CRC4 frames, errors in the receivedsignal are identified according to ITU-T G.821.
The measurement intervals for quality monitoring are synchronized with the real timeclock of the central plug-in unit. At the start of a measurement interval, the counters arereset, and after the expiry of the measurement interval the results are stored in 15-minand 24-h records. A new interval is then started.
The operating voltage of the internal clock is buffered, so that the clock continues to runin spite of short power failures (< 1 h).
It is possible to display both the current quality counter and any stored record. The num-ber of quality records is configurable.
Port A and Port BD-bit Bit 3 (A-bit) of the service word in the send directionDk-bit Bit 6 of time slot 16 in frame 0 in the send directionAIS Continuous “H” signalD2out Outgoing data signals via LC are blockedSig Signaling to analog subscribers is blockedNFout Outgoing NF signals are blockedSaout The Sa-bits received at E1in are blocked in the Saout directionVLC Computer data supply voltage failure for LCs
AIS in channels switched through from port to portTS All time slots apart from time slot 16TS16 Time slot 16
Block T3out The outgoing clock signal is blocked
LED (green) LED (red) State
on off fault-free operation
on on fault/service (S alarm)
off on urgent alarm (A alarm)
on flashing non-urgent alarm (B alarm)
off off no +5 V operating voltage (A alarm)
Tab. 3.55 Optical Signaling of the CUD
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Test options
On the front of the CUD, there are sockets for measurement and disconnection:• Disconnection sockets for E1out A, B and E1in A, B
After the two short-circuit plugs are disconnected, the E1 interface is disconnected and the external interface and multiplexer interface are accessible.
• IEC socket for monitoring ±5 V voltages• Loop circuits
– Local loop (multiplexer), an AIS signal is output via E1out, optional blocking of LCs possible
– Remote loop (external), the channels on F2 of the multiplexer are blocked.
3.6.3 ControlsThe control elements on the CUD are used to realize the particular application and theassociated hardware configuration of the multiplexer, see Fig. 3.52 and Tab. 3.56.
Fig. 3.52 Controls of the CUD
Switch Position Setting Function
S1/2 in 1 - 3
2 - 31)75 Ω unbalanced
120 Ω balanced
Termination E1inA/B
S1/2 out 1 - 3
2 - 31)75 Ω unbalanced
120 Ω balanced
Termination E1outA/B
S3 OPEN1)
CLOSED
High-impedance
75 Ω/120 ΩTermination T3in
S42) OPEN1)
CLOSED
High-impedance
120 ΩBus termination slave port QD2-Sout
S52) OPEN1)
CLOSED
High-impedance
120 ΩBus termination slave port QD2-Sin
1) As delivered status
2) DIP-FIXs are even to switch equal
Tab. 3.56 Setting the Controls of the CUD
X10 Internal connector
X11 External connector
X14 Test jack
X1 Break/test jack port A, in
X2 Break/test jack port A, out
X3 Break/test jack port B, in
X4 Break/test jack port B, out
S1 Port A termination
S2 Port-B termination
S3 T3in termination
S4 QD2Sout termination
S5 QD2Sin termination
F1 Melting fuse 1 A for −60 V /CUD
F2 Melting fuse 2 A/−60 V for LCs
S6 Switch for setting the SISA address
slide switch 7 and 8 not used
RedGreen
x3
x4
X10
X11
x1
x2
3
21
3
21
S1inout
x14
3 21
3 21
S2in
out
S5
F2 F1
ON=0
3
5
7
1S6
Port A
Port B
in
in
out
out
OF
F
S3 OF
F
S4 OF
F
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Adaptation for Using in Several Shelves
The following SISA addresses have to be set in accordance of the shelves:
Break/Test Jacks
Assignments of Break/Test Jacks X1 and X2
Assignments of Break/Test Jacks X3 and X4
Connector Assignment of Test Jack X14
Shelf/ONU Slides of DIL switch S6 Delivery
state1 2 3 4 5 6 7 8
SNUS, FMX2S ON OFF OFF OFF ON ON OFF ON ×
MXS19C with SUE x x x x x OFF OFF OFF
without SUE QD2 address 1 ... 301) ON OFF OFF
ONU 20, ONU 30 OFF OFF OFF OFF OFF OFF ON ON
OFF = 1, ON = 0
1) If the value for the QD2 address is not valid, the CUD does not boot. The failure is displayed with
constant blinking of the red and green LEDs.
Tab. 3.57 Address Switch Settings on the CUD
3 4
1 2
X1Pos. Assignment
1 E1inA-A
2 E1inA-B
3 E1inA-A
4 E1inA-B
Pos. Assignment
1 E1outA-A
2 E1outA-B
3 E1outA-A
4 E1outA-B
1 2
3 4
To connector
Card side3 4
1 2
X2
Pos. Assignment
1 E1inB-A
2 E1inB-B
3 E1inB-A
4 E1inB-B
Pos. Assignment
1 E1outB-A
2 E1outB-B
3 E1outB-A
4 E1outB-B
1 2
3 43 4
1 2
X3
3 4
1 2
X4 To connector
Card side
Pos. Assignment
1 −5 V
2 GND
3 +5 V
4 GND
3 4
1 2
X14
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3.6.4 Connector Assignment
Fig. 3.53 Connector Assignment of the CUD
Leading contacts
External connector 11
No. c b a
2 E1inA_a E1inA_b RA
4 E1outA_a E1outA_b RB
6 T3out_a T3out_b SA6out_a
8 E1inB_a E1inB_b SA6out_b
10 SA5out_a SA5out_b
12 SA7out_a SA7out_b
14 QD2Sout_a QD2Sout_b
16 SA8out_a SA8out_b
18 E1outB_a E1outB_b
20 SA5in_a SA5in_b TA
22 SA7in_a SA7in_b TB
24 QD2Sin_a QD2Sin_b SA8in_a
26 SA6in_a SA6in_b SA8in_b
28 T3in_a T3in_b ZAA
30 ZAB
32 PZA
Internal connector 10
No. c b a
1 GND_S GND_S GND
2 PUP ZAA GND
3 SEL_0 GND GND
4 MUP ZAB MUKZU
5 SEL_1
6 Z_MODE Z_BEU2 NZUB
7
8 A0 A4 A3
9
10 P_TYP
11
12 A2 A1
13 GND
14
15 GND GND
16 T64K
17
18 AD7 AD6 AD5
19
20 AD4 AD3 AD2
21
22 AD1 AD0 ALE
23
24 NCS NWR NRD
25 GND
26 ADR3 T8K_E PCM_E
27 GND GND
28 P5V P5V
29
30 T4M T8K_S PCM_S
31 GND GND GND
32 M5V P5V GND
c b a
10
20
30
2
X11
c b a
10
20
30
2
X10
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Signal Abbreviations
A0 to A4 Address lines of NE 0 to 30AD0 to AD7 Address- and data bus linesADR3 Address line for slot-group indicationALE Address latch enableE1outA/B_a/b 2-Mbit/s transmit signal port A/B, a- and b wireE1inA/B_a/b 2-Mbit/s receive signal port A/B, a- and b wireGND Internal groundGNDS Ground of the shelfMUKZU Negative secondary voltage −48 V/−60 VMUP Negative primary voltage −48 V/−60 VM5V Negative secondary voltage −5 VNRD Read signal for LCsNWR Write signal for LCsNCS Chip-select signal for LCsNZUB Contact; BEU pluggedPCM_E PCM highway; receive directionPCM_S PCM highway; transmit directionPUP Positive primary voltage +48 V/+60 VPZA Positive reference potential for ZA(A) and ZA(B)P5V Positive secondary voltage +5 VP_TYP Test signal/write type-label dataQD2Sout_a/b Transmit signal, slave port, a- and b wireQD2Sin_a/b Receive signal, slave port, a- and b wireRA/RB ECC interface, transmit signal, a- and b wireSAxout/in_a/b Transmit signal/receive signal SAx, a- and b wireSEL_0/1 Lines for slot indication of the CUDTA ECC interface, receive signal, a wireTB ECC interface, receive signal, b wireT64K 64-kHz synchronous clock from digital LCsT4M 4-MHz system clock; PCM highway (CUD - LC)T8K_E Frame synchronization pulse of received PCM signalT8K_S Frame synchronization pulse of transmitted PCM signalT3out(in)_a/b Outgoing (incoming) 2048-kHz clock, a- and b wireZAA Bw7R output ZA(A)ZAB Bw7R output ZA(B)Z_BEU2 Contact; unit BEU disturbedZ_Mode Contact; test mode CUD
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3.6.5 Technical Data
3.6.5.1 E1 Interfaces (E1A, E1B)
3.6.5.2 Internal Clock Source
3.6.5.3 T3 Interface
T3in
T3out
Electrical interface conditions to ITU-T G.703/9Impedance, switchablesymmetricalasymmetrical
120 Ω75 Ω
Jitter compatibility to ITU-T G.823/3.1Max. permitted output jitter at E1outClock derived from E1in or T3in to CTR13
Multiplex signalBit rate 2048 kbit/s ±50 ppmFrame structure per ITU-T G.704/2.3Use of time slotsFrame synchronization status wordChannel informationCAS codes / channel information, switchableChannel information
01 to 151617 to 31
CRC4 multi-frame (optionally switchable) per ITU-T G.704/2.3.3Frame synchronization per ITU-T G.736CAS code frame, switchable per ITU-T G.704/5.1.3Monitoring criteria for multiplex signal per ITU-T G.736 and
G.821/G.826
Frequency 2048 kHz ±50 ppmInherent jitter at 20 Hz ≤ fj ≤ 100 kHz ≤ 0.05 UIpp
Electrical interface conditions per ITU-T G.703/13Clock frequency 2048 kHz ±50 ppmImpedance, switchable
High-resistanceLow-resistance,
symmetricalasymmetrical
≥ 1.6 kΩ ll ≤ 120 pF
120 Ω75 Ω
Inherent jitter at 20 Hz ≤ fj ≤100 kHz ≤ 0.05 UIppJitter compatibility per ITU-T G.823
Electrical interface conditions per ITU-T G.703/13Clock frequency 2048 kHz ±50 ppmImpedances
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3.6.5.4 QD2 Slave Interface
3.6.5.5 ECC Interface
3.6.5.6 Interfaces for Sa Bits
symmetrical 120 Ωasymmetrical 75 Ω
Jitter transmission from E1out to T3outfrom E1in to T3out
per CTR13per ITU-T G.736, Fig. 1
Configuration Serial bus systemper EIA RS485
Bus participants 1 master ≤ 30 slavesTransmission lines 4-wire, symmetricalBit rate (auto detect) 0.6 kbit/s
1.2 kbit/s9.6 kbit/s64 kbit/s
Transmission mode PlesiochronousLine code NRZIPermitted length ≤ 500 mProtocol HDLC (NRM, polling)Initiator of data connection PrimaryAddress of secondaries,can be set by backplane coding 1 to 30
Configuration Point-to-point connectionper EIA RS422
Transmission lines 4-wire, symmetricalBit rate
with oversamplingdata signal with HDLC frame
9.6 kbit/s64 kbit/s
Transmission mode Plesiochronous
Interface parameters per EIA RS485Sampling frequency 4 kHzTransmission channels Sa5, Sa6, Sa7, Sa8Transmission speed per Sa bit interface
at 15% sampling distortionat 30% sampling distortion
0.6 kbit/s 1.2 kbit/s
Asynchronous 16-kbit/s channelInterfaceSampling frequencyTransmission speed
at 15% sampling distortionat 30% sampling distortion
Sa716 kHz
2.4 kbit/s4.8 kbit/s
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3.6.5.7 ZA(A) and ZA(B) Interfaces
3.6.5.8 Power Supply
Working methodZA(A) interfaceZA(B) interface
Normally closed contactNormally open contact
Absent +5V operating voltage results in alarm on ZA(A).
Open contactPermitted voltage −8 V to −72 VPermitted alternating interference voltage 2 V0SMaximum residual current 20 mA
Closed contactMinimum current 1 mAMaximum continuous current 60 mAMaximum residual voltage against ground −2 VPermitted load types Ohmic resistance,
relay with suppressor diodes, LEDs
Lightning protection, core against ground, Ri = 40 ΩLightning 1.2/50 μs, 500 V ETS 300386-1, LFS
EN 50082-2, Criterion BEmission of line-associated radio frequency interference ETS 300386-1, Class B
EN 55102-1, 50 ΩImmunity from bursts ETS 300386-1, Tab. 2
500 V: NP, 1 kV: LFSEN50082-2: 1 kV, Criterion B
Input voltage −36 V to −72 VPV without load on sources by LCs ≤ 6 WWith ±5 V load on sources by LCs, the power dissipation resulting from the efficiency 0.8 of the DC-DC converters must also be taken into account.Nominal output voltages +5 V (1 ±5%)
−5 V (1 ±5 %)Permitted load current
at +5 Vat −5 V
2.5 A1 A
Fusesfor input voltage (−48 V/−60 V)for voltage for LCs (−48 V/−60 V)
1 A2 AT
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3.7 Bus Extension Unit BEC
3.7.1 OverviewThe job of the bus extension unit is to connect the system bus to six further LCs and tosupply these LCs with the necessary voltages. A CUD without a BEC can operate sixLCs, but with a BEC it can operate twelve.
The BEC is used if:• for full exploitation of the capacity of the 2-Mbit/s signal, more than six LCs are need-
ed (LC has a limited number of interfaces),• a variable set of different subscriber interfaces is to be provided.
The number of timeslots of the 2-Mbit/s signal is not increased by a BEC.
The BEC has the following interfaces:• PCM highway,• LC bus,• alarms,• power supply.
3.7.2 Monitoring and AlarmThe BEC is connected to the associated CUD via two alarm contacts, and is monitoredby it.
−48 V/−60 V
BEC PCM highway
alarms
LC bus
CUD
PCM highway
LC busLC
−5 V
+5 V
−48 V/−60 V
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3.7.3 Controls
Fig. 3.54 Controls of the BEC
31
42
10
X2
plug-connector Contact Signal
X2 1 +5 V via 10 kΩ
2 Ground
3 –5 V via 10 kΩ
4 Ground
X2 Test connector voltages +5 V/–5 V
10 plug connector
F1 Fuse for M48V-Primary voltage (1AT)
F2 Fuse for M48V-Primary voltage
of the LCs (2AT)
S1 Dip-Fix switch must be open
(X2)
F1
F2
1
2
3
4
S1
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3.7.4 Connector Assignment
Fig. 3.55 Connector Assignment BEC
Connector 10
No
.
c b a
1
2 PUP GND
3
4 MUP MUKZU
5 Z_BEU2 Z_BEU1
6
7
8 A0 A4 A3
9 ADR3_1 ADR2_1
10
11
12 A2 A1
13
14
15 CLK_64K1
16 CLK_64K2
17 AD71 AD61 AD51
18 AD72 AD62 AD52
19 AD41 AD31 AD21
20 AD42 AD32 AD22
21 AD11 AD01 ALE1
22 AD12 AD02 ALE2
23 CS1 WR1 RD1
24 CS2 WR2 RD2
25 SYN_E1 PCM_E1
26 ADR3_2 SYN_E2 PCM_E2
27 ADR2_2 SSYNC1
28 P5 V_LC P5 V_LC SSYNC2
29 CLK_4M1 SYN_S1 PCM_S1
30 CLK_4M2 SYN_S2 PCM_S2
31
32 M5 V_LC P5 V_LC GND
c b a1
5
10
15
20
25
30
10
1
5
8
16
Code part:
elements
representation of the missing code
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Signal Abbreviations
3.7.5 Technical Data
ADR2_1 and ADR3_1
Plug in place address for LCs in left system
ADR2_2 and ADR3_2
Plug in place address for LCs in right system
AD0 to AD7 Address- and data bus linesCLK_64K 64-kHz synchronous clock from digital LCsCLK_4M 4-MHz system clock PCM highway (CUA - LC)CS Chip selectGND Internal groundMUKZU Negative secondary voltage −48 V/−60 VMUP Negative primary voltage −48 V/−60 VPCM_E PCM highway; receive directionPCM_S PCM highway; transmit directionPUP Positive primary voltage +48 V/+60 VRD ReadSYN_E Synchronous pulse; receive directionSYN_S Synchronous pulse; transmit directionWR WriteZ_BEU1 Contact; unit BEC plugged (generating a Reset after undervoltage
for about 200 msZ_BEU2 Contact; unit BEC out of order (low active at loss of M5V_LC or
P5V_LC or breakdown of −48 V fuse)P5 V_LC Positive secondary voltage for LCsM5 V_LC Negative secondary voltage for LCs
Input voltage −36 V to −72 VPV without load on sources by LCs ≤ 6 WWith ±5 V load on sources by LCs, the power dissipation resulting from the efficiency 0.8 of the DC-DC converters must also be taken into account.Nominal output voltages +5 V (1 ±5%)
−5 V (1 ±5 %)Permitted load current
at +5 Vat −5 V
2.5 A1 A
Fusesfor input voltage (−48 V/−60 V)for voltage for LCs (−48 V/−60 V)
1 A2 AT
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3.8 SUB102 Subscriber Converter
3.8.1 OverviewThe SUB102 subscriber converter, an analog line card for ten channels with a/b inter-face, is used to connect conventional analog subscriber telephones or extension tele-phones to a transmission network.
The feed characteristics of individual subscriber line circuits can be adapted to powerterminal equipment performing special functions when idle (e.g. coin box telephones).The number of special interfaces is limited to 2 per line card.
The line card provides the following functions:• Electrical characteristics of the subscriber interfaces
– coding/decoding of the voice signals with filtering – application of balanced feeding– ground start– loop start
• Control of call processing procedures– reversal– feed interruption– sending a balanced ringing signal– sending of metering pulses (12 kHz/16 kHz)
• Signaling interface per CAS– class feature (CLIP) for direct connection to the exchange.
The SUB102 is equipped with the following interfaces:• F2 interface (subscriber interface)
The F2 interface is a two-wire interface which is used for transmission of the VF and signaling information.
External interfaces Internal interfaces
−48 V/−60 V
−5 V+5 V
a1
a10
b1
b10
PCM highway
LC bus
SUB102
F2
F2
......
iPort 1 and port 2 of the unit are suitable for connection of special terminals (e.g. coinbox telephones), which need a higher feed current in the idle (> 2 mA) as well as in the active status (> 25 mA).
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• Internal interfacesThe PCM highway and LC bus form the interface between the central unit and the SUB102.
• Power supply.
3.8.2 Connector Assignment
Fig. 3.56 Connector Assignment of SUB102
c b a1
5
10
15
20
25
30
11
c b a
10
20
30
2
10
No.
Connector 11
C B A
1 F2_a1
2 F2_b1
3 F2_a2
4 F2_b2
5
6
7 F2_a3
8 F2_b3
9
10
11 F2_a4
12 F2_b4
13 F2_a5
14 F2_b5
15
18
19 F2_a6
20 F2_b6
21
22
23 F2_a7
24 F2_b7
25 F2_a8
26 F2_b8
27
28
29 F2_a9
30 F2_b9
31 F2_a10
32 F2_b10
No.
Connector 10
C B A
2 PUKZU GND
4 MUKZU
6 PE
8
10 Pb1
12 Pb0
14
18 AD7 AD6 AD5
20 AD4 AD3 AD2
22 AD1 AD0 ALE
24 CS WR RD
26 ADR3 SYN_E PCM_E
28 ADR2 ADR1 ADR0
30 CLK_4M SYN_S PCM_S
32 −5 V +5 V GND
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Signal Abbreviations
3.8.3 Technical DataThe freely programmable interface parameters of the unit make it possible to configuremany project-specific features and implement special requirements on request.
3.8.3.1 VF Parameters as Defined by ITU-T Q.552
3.8.3.2 Signal ParametersThe specified signaling parameters are factory default settings. The majority of the pa-rameters can be adapted to suit the project.
AD0 to AD7 Address and data bus bit 0 to 7ADR0 to ADR3 Address of plug-in place 0 to 15 for LCALE Address latch enableCLK_4M 4-MHz system clock PCM highwayCS Chip selectF2_a1 to F2_a10 Interface analog 1 to 10, a wire F2_b1 to F2_b10 Interface analog 1 to 10, b wireGND Internal groundMUKZU Negative secondary voltage −48 V/−60 VPCM_E PCM highway receive directionPCM_S PCM highway transmit directionPE Write protection enable for EEPROMPUKZU Positive secondary voltage +48 V/+60 VRD ReadSYN_E Synchronous pulse receive directionSYN_S Synchronous pulse transmit directionWR Write+5 V Positive secondary voltage +5 V−5 V Negative secondary voltage −5 V
Characteristic impedance (configurable)resistive
complex
600 Ω900 Ω220 Ω + (820 Ω || 115 nF)
Input level range (A/D) −3.0 dBr to +5.0 dBrOutput level range (D/A) −8.0 dBr to +0.0 dBrLevel setting in 0.5 dB steps
a/b wire polarity with power supply and ringingnormal polarity (with a negative in relation to b,both negative in relation to ground)reversed polarity
a− (RinG)/b+ (TIP)a+/b−
Feed current for a+/b− or a−/b+ with constant current feed
Rated currentPort 1 and port 2 switchable for Iconst
25 mA ±2 mA33 mA ±2 mA
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3.8.3.3 Foreign Potentials
Idle currentPort 1 and port 2 switchable for Iidle
≤ 2 mA≤ 6 mA
It should be noted, that with Iconst < 25 mA, the impedance supply range is attained later and, with Iconst > 25 mA, it is attained earlier!
Monitoring for unnecessary loop closureSupply impedance per wire > 5 kΩ
Call injection performance-dependentNo-load voltage Uab for termination with ringer impedance without direct current ≥ −MUKZUMax. loop resistance (including network termination) ≤ 1800 ΩMean loop resistance (including network termination) ≤ 920 ΩCall charge pulses
Frequency (adjustable via the OS)
Levelon the MDF at 200 Ωat the subscriber at ≥ 200 Ω (2 Vrms)at the subscriber at ≥ 200 Ω (5 Vrms, only -A1)line loss at 12 kHz or 16 kHz(with 5 km line length and 6 dB/km)
12 kHz ±1%16 kHz ±1%
2.0 Vrms ±0.4 Vrms ≥ 60 mVrms≥ 140 mVrms
≤ 30 dBPulse length and min. pulse interval Distortion factor
specified by exchange≤ 5%
Ringing voltage (single-channel feed)FrequencyNominal voltage at the output on the a and b wires atringing load of Z ≥ 8.31 kΩ [≥ (3.6 kΩ + 850 nF)]
at ≤ −36 Vat ≤ −43 Vat ≤ −54 V
Voltage at a’ and b’ wires with a ringing loadZ ≥ 2.078 kΩ (≤ 4 × [≥ (3.6 kW + 850 nF)])(at the subscriber with a line resistance of 1500 Ω)
UB ≤ −36 VUB ≤ −43 V
Max. ringing voltageDistortion factorRinging sequence
25 Hz ±5 Hz or
48 Vrms53 Vrms60 Vrms
≥ 31 Vrms≥ 35 Vrms≤ 85 Vrms< 10%1 s ring, 4 s pause
Ring tripping timeDelay during disconnection of the ringing voltageafter removal of the handset by the subscriberuntil detection of off-hookuntil disconnection of the call
≤ 160 rms≤ 80 rms≤ 80 rms
Protection against external voltages on the outdoor user lines is implemented in 2 stag-es within the entire system. A 420 V gas tube arrestor must be installed directly preced-ing the line card.For further information see Section 1.4.7 and UMN:IMN.Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Outdoor Signal Lines
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3.8.3.4 Power Supply and Dissipation
Operating voltages −48 V/−60 V+5 V, −5 V ±5%
Current consumption for 10 channels in case of ready for seizure
+5 V−5 V
150 mA10 mA
Typical power dissipation at 0.5 Erl < 4.5 W
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3.9 SLX102 and SLX102E Subscriber Converters
3.9.1 OverviewWithin a digital link, the SLX102/E subscriber converter, an analog line card for ten chan-nels with a/b interface, connects conventional analog subscriber telephones or exten-sion telephones to analog exchange or to an analog subscriber access of digitalexchange. The grounding key function is transmitted for use in PABXs.
The SLX102/E has the following functions:• Implementation of the electrical subscriber interface on the network side,• Control of the sequence of call processing operations.
The SLX102/E is equipped with the following interfaces:• F2 interface (network interface)
The F2 interface is a two-wire interface which is used for transmission of the VF and the signaling information.
• Internal interfacesThe PCM highway and LC bus form the interface between the central unit and the SLX102/E.
• Power supply.
External interfaces Internal interfaces
−48 V/−60 V
−5 V+5 V
a1
a10
b1
b10
F2PCM highway
LC bus
SLX102/E
F2
......
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3.9.2 Connector Assignment
Fig. 3.57 Connector Assignment of the SLX102/E
a1
5
10
15
20
25
30
16
c b a1
5
10
15
20
25
30
15
Connector 16
No.
Row
C B A
1 SB_a1
2 SB_b1
3 SB_a2
4 SB_b2
5
6
7 SB_a3
8 SB_b3
9
10
11 SB_a4
12 SB_b4
13 SB_a5
14 SB_b5
15
16
17
18
19 SB_a6
20 SB_b6
21
22
23 SB_a7
24 SB_b7
25 SB_a8
26 SB_b8
27
28
29 SB_a9
30 SB_b9
31 SB_a10
32 SB_b10
Connector 15
No.
Row
C B A
1
2 GND PUKZU
3
4 MUKZU
5
6 PE
7
8
9
10
11
12
13
14
15
16
17
18 AD5 AD6 AD7
19
20 AD2 AD3 AD4
21
22 ALE AD0 AD1
23
24 RD WR CS
25
26 PCM_E SYN_E ADR3
27
28 ADR0 ADR1 ADR2
29
30 PCM_S SYN_S CLK_4M
31
32 GND P5 V M5 V
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Signal Abbreviations
3.9.3 Technical Data
3.9.3.1 VF Parameters as Defined by ITU-T Q.552
3.9.3.2 Signal Parameters
AD0 to AD7 Address and data bus bit 0 to 7ADR0 to ADR3 Address of plug-in place 0 to 15 for LCALE Address latch enableCLK_4M 4-MHz system clock PCM highwayCS Chip selectGND Internal groundMUKZU Negative secondary voltage −48 V/−60 VPCM_E PCM highway receive directionPCM_S PCM highway transmit directionPE Write protection enable for EEPROMPUKZU Positive secondary voltage +48 V/+60 VRD ReadSYN_E Synchronous pulse receive directionSYN_S Synchronous pulse transmit directionSB_a1 to 10 Data signals a1 to a10SB_b1 to 10 Data signals b1 to b10WR Write
Characteristic impedance (complex) 220 Ω + (820 Ω || 115 nF)1)
Input level range (A/D) −7.0 dBr to +1.0 dBrOutput level range (D/A) −8.0 dBr to +0 dBrLevel setting in 0.5 dB steps
Polarity detection for a/b wiresnormal polarity (with a negative in relation to b,both negative in relation to ground)reversed polarity
a− (RinG)/b+ (TIP)a+/b−
Loop current IS for a+/b− or a−/b+ with const. current 25 mA ±4 mALoop resistance (off-hook) 200 Ω ≤ RS ≤ 850 ΩLoop resistance (on-hook)
with a−/b+with a+/b−
≥ 500 kΩ≥ 100 kΩ
Line resistance per wire ≤ 100 ΩLeakage resistance, wire to ground ≥ 1 MΩNominal operating current for loop detection ≥ 12 mAOperating current for unnecessary loop closure 0.5 mA ≤ Iin ≤ 2.5 mA
1) only for S42024-A1809-C11, for plug-in unit variants see Tab. 3.58
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3.9.3.3 Foreign Potential Protection
3.9.3.4 Power Supply and Dissipation
Ringing detector voltage rangesuperimposed direct currentresultant additive peak voltage
35 Vrms to 100 Vrms≤ 40 V⏐≤ 180 V
with 50 ms off-hook detection delay in the exchangeand a min. ring feeding resistance of 2 × 150 Ωsuperimposed direct currentresultant additive peak voltage
≤ 70 V⏐≤ 210 V
Ringing detector frequencyRange due to software change
25 Hz/50 Hz ±20%15 Hz to 65 Hz
Load on the ringing voltage source 40 Ω +1.36 μF (Z = 4.7 kΩ)1)
Call charge pulse frequency 16 kHz ±80 Hz1)
Operate level, call charge pulsesat f = 15.920 kHz to 16.080 kHz ≥ 1 VrmsNon-operate level, call charge pulses
at f = 15.920 kHz to 16.080 kHzat f ≤ 13.5 kHz and f ≥ 20.5 kHz
≤ 0.5 Vrms≤ 2 Vrms
Characteristic impedance at 16 kHz (12 kHz) high impedanceMax. call charge pulse level 10 Vrms
Variant of plug-in
unit
Call charge
pulse frequency
Impedance Load on the
ringing voltage source
S42024-A1809-C11 16 kHz 220 Ω + (820 Ω II 115 nF) 40 Ω + 1,36 μF (Z = 4,7 kΩ)
S42024-A1809-A12 12 kHz 220 Ω + (820 Ω II 115 nF) 40 Ω + 1,36 μF (Z = 4,7 kΩ)
S42024-A1809-A13 16 kHz 600 Ω 40 Ω + 2,18 μF (Z = 2,9 kΩ)
S42024-A1809-A14 12 kHz 600 Ω 40 Ω + 2,18 μF (Z = 2,9 kΩ)
Tab. 3.58 SLX102/E Plug-in Unit Variants
Classification for foreign potential protection according EN 300 386 V1.3.2 (05/2003) Level Indoor Signal Lines
Operating voltages −48 V/−60 V+5 V ±5%, −5 V ±5%
Current consumption for 10 channels at−48 V/−60 V+5 V−5 V
2 mA200 mA50 mA
Typical power dissipation at 0.5 Erl < 4 W
1) only for S42024-A1809-C11, for variants of the plug-in unit see Tab. 3.58
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3.10 SLB62 Subscriber Converter
3.10.1 OverviewThe SLB62 (2-wire LB) line card is used as a signal converter in the FMX2R3.2 multi-plexer. It connects analog subscribers with a local battery power supply to the transmis-sion network.
The units for 6 independent interfaces are mounted on the line card; these units processthe VF signal and the transmission signals (call transmit, call receive).
The SLB62 performs the following functions:• Implementation of the electrical subscriber interfaces• Control of call processing operations.
The SLB62 is equipped with the following interfaces:• F2 interface (subscriber interface)
The F2 interface is a two-wire interface which is used for transmission of the VF and signaling information.
• Internal interfacesThe PCM highway and LC bus form the interface between the central unit and the SLB62.
• Power supply.
External interfaces Internal interfaces
SLB62
+5 V
−5 V
PCM highway
LC bus
−48 V/−60 V
F2
F2
a1b1
a6b6
......
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3.10.2 Controls The control elements on the SLB62 are used to realize the particular application and theassociated hardware configuration of the unit.
Fig. 3.58 Controls of the SLB62
3.10.3 Monitoring and Alarm SignalingOn the basis of the alarm criteria listed in Tab. 3.59, SISA messages conforming to theQD2 specification are generated and remedial action is taken.
All the alarm criteria result in non-urgent alarms (B-alarm).
12 3 849
15
16
Switch 849
Setting Meaning Delivery
state
1 - 3 Ringing voltage with offset x
2 - 3 Ringing voltage without offset
(connects additionally
coupling capacitor)
Alarm criterion Remedial action Message
Maintenance mode/loop NF activated, power on or test loop SER
Port of remote module not present Signaling converter of remote module not available SNP
Internal hardware fault Hardware is not according to transparent call mode inT-A
Tab. 3.59 Table of Alarms of the SLB62
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3.10.4 Connector Assignments
Fig. 3.59 Connector Assignment of the SLB62
Code part:
representation of the
missing code elements
Leading contacts
External connector 16
No. c b a
1 a1
2 b1
7 a2
8 b2
9
10
11 a3
12 b3
17
18
19 a4
20 b4
21
22
23
24
25 a5
26 b5
27
28
29
30
31 a6
32 b6
a1
5
10
15
20
25
30
16
c b a
10
20
30
2
15
1
7
9
16
Internal connector 15
No. c b a
1
2 MKZU GND
3
4 UKZU
9
10 PB1
11
12 PB0
17
18 AD7 AD6 AD5
19
20 AD4 AD3 AD2
21
22 AD1 AD0 ALE
23
24 /CS /WR /RD
25
26 ADR3 T8K-E PCM-E
27
28 ADR2 ADR1 ADR0
29
30 T4M T8K-S PCM-S
31
32 −5 V +5 V GND
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Signal Abbreviations
3.10.5 Technical Data
3.10.5.1 VF Wires (Conforming to Q.552)
3.10.5.2 Signal Parameters
3.10.5.3 Ringing Voltage
AD0 to AD7 Address- and data bus linesADR0 to ADR3 Address lines to plug-in placesALE Address latch enablea1 to a6 A wire channel 1 to 6b1 to b6 B wire channel 1 to 6/CS Chip selectGND Internal groundMKZU KZU groundPCM_E PCM highway; receive directionPCM_S PCM highway; transmit direction/RD ReadUKZU Fused primary voltage (-60 V)T4M 4-MHz system clock PCM highway (CUA - LC)T8K-E Synchronous pulse; receive directionT8K-S Synchronous pulse; transmit direction/WR Write
Input level (at 600 Ω in sequence to 2.2 μF) +3 dBr to −6 dBr1)
Output level (at 600 Ω in sequence to 2.2 μF) 0 dBr to −9 dBr1)
Stages of adjustment 0.1 dBCharacteristic resistance, in sequence to 2.2 μF 600 Ω1)
Ringing detection voltage range 14 Vrms to 90 VrmsFrequency range 15 Hz to 65 Hz
Call injection via 2 × 400 ΩRinging frequency 25 Hz ±10%1)
Maximum load on the ringing voltage source ≥ 3 kΩRinging generator voltage at maximum load ≥ 35 VrmsDistortion factor < 20%
1) Level exceeding the specified tolerances is available on request.
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3.10.5.4 Foreign Potential Protection
3.10.5.5 Current Consumption and Power Dissipation
Induced longitudinal voltage Urms (f = 16 2/3 Hz to 60 Hz) ≤ 65 VBriefly-induced longitudinal voltage Urms (for T ≤ 200 ms, f = 16 2/3 Hz to 60 Hz) ≤ 300 VAtmospheric discharge U
Wire to ground ≤ 1 kVPulse shape 10 μs/700 μs
Contact time with mains voltage (U = 220 V / f = 50 Hz (60 Hz)) 15 min
Current consumption+5 V ≤ 170 mA−5 V ≤ 70 mAUKZU −48 V ≤ 50 mAUKZU −60 V ≤ 40 mA
Power dissipation at −60 V six channels in the stable call state ≤ 1.4 Wchannel transmits ringing voltage ≤ 3.8 Wchannels receive call ≤ 3.5 W
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3.11 UAC68 Universal Analog Line Card
3.11.1 OverviewUniversal analog line card UAC68 for six channels is used if the FMX2R3 multiplexer isto provide either analog 2-wire or 4-wire interfaces with signaling (E&M operation) orwithout signaling (analog leased lines). With the leased line functionality, the unit canalso be employed in the access line multiplexer AMXC. The operating modes can beconfigured using SISA control. Each line card port can be set individually to operate withor without signaling.
The UAC68 allows constant signal throughput times. 32-kbit/s ADPCM coding based onITU-T G.726 can be performed for individual channels.
E&M mode
E&M mode is used if voice frequency as well as signaling transmission using E&M sig-naling is to be undertaken on a transmission link. In this mode, in addition to the 2-wireor 4-wire interface, the converter provides a 4-wire signaling interface for each channel.
The signals are transmitted transparently using channel-associated signaling CAS(KDU function). Signaling is carried out for ADPCM operation in accordance with ITU-TG.761.
For each system, a maximum of 60 E&M channels are permitted in each direction for asignal wire and a maximum of 30 E&M channels in each direction for two signal wires.
Leased lines
Leased line operation is used in a digital transmission link for a service-neutral, trans-parent point-to-point transmission of information, if analog terminals without signaling(e.g. modems without outband, dc and dc impulse signaling) are connected to each oth-er permanently.
In this mode of operation, the converter provides the 2-wire or 4-wire voice-frequencyinterfaces needed for connection to analog terminals.
The UAC68 line card implements the following functions:• Electrical properties for terminating the analog voice-frequency interfaces (F2) and
the signaling interfaces (S2)• Nesting the each of the voice-frequency channels in a PCM transmission channel• Transparent through connection for signals during E&M operation
The through connection can also be the other way around.• 1+1 protection switching for 64-kbit transmission channels
A protection path cannot be set up if ADPCM is used.• Implementation of test functions during service operation
The following functions are listed for each subscriber interface:• Coding/decoding the voice-frequency signals using filtration• Compressing the voice-frequency signals to 32 kbit/s during ADPCM operation• 2/4-wire conversion (splitting) during 2-wire operation• Sending signaling codes at S2out (ground potential active, high-impedance inactive)• Receiving signaling codes at S2in (ground potential active, high-imped. inactive)• Protection against overvoltage (ITU-T K.20 with external coarse protection).
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The UAC68 has the following interfaces:• F2 interface:
The F2 interface is a 2-wire interface (F2) or4-wire interface (F2in, F2out), via which voice-frequency signals are transmitted.
• S21 and S22 interface:The switching flags are transmitted via the S21 and S22 signaling leads, see Fig. 3.60 for the Sin internal interface circuit.
• Internal interfaces:The PCM highway and LC bus form an interface between the central unit and the UAC68.
• Power supply.
Fig. 3.60 Internal Sin Interface Circuit
−48 V/−60 V
UAC68
+5 V
−5 V
External interfaces Internal interfaces
PCM highway
LC bus
b1
a1b1
S21in1S21out1
S22in1S22out1
a1
b6
a6b6
S21in6S21out6
S22in6S22out6
a6
......
F2/11)
F2out12)
F2in12)
F2/61)
F2out62)
F2in62)
1) 2-wire interface, description on the F2out connector2) 4-wire interface
60 k
20 k
S2in
−48 V/−60 V
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Channel protection
Channel protection is possible for the UAC68 at the 64-kbit/s time slots level.
This protection involves sending voice-frequency signals via a number of time slots. If atransmission link fails, this situation is detected by the UAC68 which reports it to the op-eration system and switches over to the redundant time slots.
3.11.2 DiagnosisThe UAC68 converter provides additional functionalities for testing the analog interfacesand these can be activated using SISA control:• Connecting a 1000-Hz search tone in the transmit direction (D/A)• Activating or deactivating both output circuits (S21out, S22out).
3.11.3 Connector Assignment
No. a b c
1 GND
2 GND GND
4 MUKZU_1
5 GND GND
6 PWE
10 PB1 PB2 PB3
11
12 PB0
13 GND
17 GND GND GND
18 AD5 AD6 AD7
20 AD2 AD3 AD4
21 GND GND GND
22 ALE AD0 AD1
23 GND GND GND
24 NRW NRW NCS
25 GND GND GND
26 PCM_E1 SYN_E1 ADR3
27 GND GND GND
28 ADR0 ADR1 ADR2
29 PCM_E2 SYN_E2
30 PCM_S1 SYN_S1 CLK_4M
31 GND PCM_S2
32 GND P5V M5V
Tab. 3.60 System Connector of the UAC68 (Internal Interface)
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System processor bus:• Interface signals: AD0 to AD7, NCS, NDR, NWR, ALE
Slot address:• ADR0 to ADR3
System PCM bus 1:• interface signals: PCM_S1, PCM_E1, SYN_S, SYN_E1, CLK_4M
No. a b c
1 F2in_a1 F2in_a4
2 F2in_b1 F2in_b4
3 F2out_a1 F2out_a4
4 F2out_b1 F2out_b4
5
6
7 F2in_a2 S21in_6
8 F2in_b2 S22in_6
9 F2in_a5
10 F2in_b5
11 F2out_a2
12 F2out_b2
13 F2in_a3 F2out_a5
14 F2in_b3 F2out_b5
15 S21in_3 S21out_6
16 S22in_3 S22out_6
17 S21out_3 F2in_a6
18 S22out_3 F2in_b6
19 F2out_a3 F2out_a6
20 F2out_b3 F2out_b6
21
22
23 S21in_1 S21in_4
24 S22in_1 S22in_4
25 S21out_1 S21out_4
26 S22out_1 S22out_4
27
28
29 S21in_2 S21in_5
30 S22in_2 S22in_5
31 S21out_2 S21out_5
32 S22out_2 S22out_5
Tab. 3.61 Exchange Connector of the UAC68 (External Interface)
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System PCM bus 2:• Interface signals: PCM_S2, PCM_E2, SYN_E2
System bus operating voltages:• Interface signals: GND, P5V, M5V, MUKZU_1
Signal Abbreviations
AD0 to AD7 Address bus bits 0 to 7ADR0 to ADR3 Slot address pinsALE “Address Latch Enable” system processor bus lineCLK_4M 4-MHz system clockF2out_a1 to F2out_a6
Interface analog 1 to 6, a wire, transmission direction
F2out_b1 to F2out_b6
Interface analog 1 to 6, b wire, transmission direction
F2in_a1 to F2in_a6
Interface analog 1 to 6, a wire, receive direction
F2in_b1 to F2in_b6
Interface analog 1 to 6, b wire, receive direction
GND Internal chassis groundM5V Negative secondary voltage −5 VMUKZU_1 −48 V negative secondary voltageNCS “Chip select” system processor bus lineNWR “Write” system processor bus linePCM_E_1 PCM highway (4 Mbps) receiving end (from line card direction)PCM_E_2 PCM highway (4 Mbps) receiving end (from line card direction)PCM_S_1 PCM highway (4 Mbps) transmission end (from line card direction)PCM_S_2 PCM highway (4 Mbps) frame relay highway transmission end
(from line card direction)P5V Positive secondary voltage +5PWE Test position signalSYN_E_1 Frame synchronization signal for PCM_E1SYN_E_2 Frame synchronization signal for PCM_E2 frame relay highwaySYN_S_1
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3.11.4 Technical Data
3.11.4.1 2-wire VF Interface
3.11.4.2 4-wire VF Interface
3.11.4.3 Signal Wires
The interface is designed in accordance with G.712.The input level and output level are configurable in 0.5-dB steps.Input level at F2 −8 dBr to +10 dBrOutput level at F2 −16 dBr to + 4 dBrResistance 600 Ω /900 ΩReturn loss at
300 Hz to 600 Hz ≥ 12 dB600 Hz to 3400 Hz ≥ 15 dB
Symmetry loss at300 Hz to 600 Hz ≥ 40 dB600 Hz to 2400 Hz ≥ 46 dB2400 Hz to 3400 Hz ≥ 41 dB
Splitting resistance (Z value of F2 interface) 600 Ω real900 Ω real600 Ω with 2.16 μF in series900 Ω with 2.16 μF in series
Coding specifications A law
The interface is designed in accordance with ITU-T G.712 and ETS 300453.The input level and output level are configurable in 0.5-dB steps.Input level at F2 −17 dBr to +4 dBrOutput level at F2 −14 dBr to +9 dBrResistance 600 ΩReturn loss at 300 Hz to 3400 Hz ≥ 20 dBSymmetry loss at
300 Hz to 2400 Hz ≥ 46 dB2400 Hz to 3400 Hz ≥ 41 dB
Coding specifications A law
Line resistance ≤ 400 ΩPermissible leakage resistance (wire-wire, wire-ground) ≥ 20 kΩLine capacitance ≤ 0.3 μFNumber of signaling inputs (S21in, S22in) per telephony circuit (M) 2Number of signaling outputs (S21out, S22out) per tele-phony circuit (E) 2 Electronic output circuit (E)
Load circuit typically 1 kΩ, 4 Hperm. switch current ≤ 100 mAperm. switch voltage +30 V to −75 V
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3.11.4.4 Foreign Potential Protection
3.11.4.5 Power Supply and Dissipation
Limiting of relay switching peaks ≤ 120 VCode active Ground potentialRated current 60 mAResidual current at 20 mA ≤ 0.5 VResidual current at 85 mA ≤ 2 VCode inactive high resistanceResidual current ≤ 0.3 mA
Electronic input circuit (M)Signaling
activeinactive
Ground potentialhigh resistance
Permitted input voltage on activation 0 V to −12 VPermitted input voltage in high resistance state (signaling inactive) 0 V to −15 VSignal distortion(S21in to E1out without influence of line) ≤ 5 ms
Protection against external voltages on the outdoor user lines is implemented in 2 stag-es within the entire system. A 420 V gas tube arrestor must be installed directly preced-ing the line card.For further information see Section 1.4.7 and UMN:IMN.Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Outdoor Signal Lines
Operating voltages −48 V/−60 V, +5 V, −5 VPower consumption for 6 channels
−48 V/−60 Vall Sin high-resistanceone Sin per channel active
+5 V−5 V
≤ 10 mA≤ 28 mA≤ 500 mA≤ 100 mA
Typical power dissipation, all Sin high resistanceone Sin per channel active
≤ 3.6 W≤ 4.7 W
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3.12 SEM106C E&M Converter
3.12.1 OverviewThe SEM106C line card is used in the multiplexer for connection to exchange and trans-mission equipment which operates with E&M signaling. The line card incorporates unitsfor ten interfaces which process VF signals in two-wire operation. It also features twooutgoing and two incoming transparent signal channels for each VF interface.
The SEM106C is equipped with the following interfaces:• F2 interface
The F2 interface is a two-wire interface which is used for transmission of the VF in-formation.
• S21 and S22 interfaceThe call processing codes are transmitted via the S21 and S22 signaling wires, internal interface circuit of S2in see Fig. 3.61
• Internal interfacesThe PCM highway and LC bus form the interface between the central unit and the SEM106C.
• Power supply.
Fig. 3.61 Internal Interface Circuit of S2in
F2b1
SEM106C
External interfaces
Internal interfaces
PCM highway
LC bus
S21in1
S21out1
S22in1
S22out1
F2a1
F2b10
S21in10
S21out10
S22in10
S22out10
F2a10
......
+5 V
−5 V
−48 V/−60 V
60 k
20 k
S2in
−48 V/ −60 V
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3.12.2 Monitoring and Alarm SignalingOn the basis of the alarm criteria listed in Tab. 3.62, a SISA message conforming to theQD2 Specification is generated and remedial action is taken.
The alarm criteria result in a non-urgent alarm (B-alarm).
3.12.3 TestsThe following options are available for testing the signal path of the NF signals:• insert an analog loop from E1an to E1ab• insert a test tone at F2ab.
Alarm criterion Remedial action Message
Test mode//loop NF activated, power on or test loop SER
Tab. 3.62 Table of Alarms for the SEM106C
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3.12.4 Connector Assignment
Fig. 3.62 Connector Assignment of the SEM106C
External connector 16
No. c b a
1 S21out_1 F2out_a1
2 S22out_1 F2out_b1
3 F2out_a2
4 F2out_b2
5 S21in_2 S21out_2 S21in_1
6 S22in_2 S22out_2 S22in_1
7 S21out_3 F2out_a3
8 S22out_3 F2out_b3
9 S21out_4
10 S22out_4
11 S21in_4 S21out_5 F2out_a4
12 S22in_4 S22out_5 F2out_b4
13 S21out_6 F2out_a5
14 S22out_6 F2out_b5
15 S21in_6 S21in_3
16 S22in_6 S22in_3
17 S21out_7 S21in_5
18 S22out_7 S22in_5
19 F2out_a6
20 F2out_b6
21 S21in_8 S21out_8 S21in_7
22 S22in_8 S22out_8 S22in_7
23 F2out_a7
24 F2out_b7
25 F2out_a8
26 F2out_b8
27 S21in_10 S21out_9 S21in_9
28 S22in_10 S22out_9 S22in_9
29 F2out_a9
30 F2out_b9
31 S21out_10 F2out_a10
32 S22out_10 F2out_b10
Internal connector 15
No. c b a
1 GND
2 GND GND
3
4 MUKZU
5 GND-S GND-S
6 PWE
7
8
9
10 PB1
11
12 PB0
13 GND-S
14
15
16
17 GND GND GND
18 AD7 AD6 AD5
19
20 AD4 AD3 AD2
21 GND GND GND
22 AD1 AD0 ALE
23 GND GND GND
24 NCS NWR NRD
25 GND GND GND
26 ADR3 SYN_E1 PCM-E1
27 GND GND GND
28 ADR2 ADR1 ADR0
29
30 CLK_4M SYN-S PCM-S1
31 GND
32 −5 V +5 V GND
Codierteil:Darstellung fehlender Codierelemente
c b a1
5
10
15
20
25
30
16
c b a15
1
7
9
16
1
5
10
15
20
25
30
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Signal Abbreviations
3.12.5 Technical Data
3.12.5.1 2-Wires VF Interface
AD0 to AD7 Address- and data bus linesADR0 to ADR3 Address lines to plug-in placesALE Address latch enableF2_a1 to F2_a10 Analog interface 1 to 10, a wireF2_b1 to F2_b10 Analog interface 1 to 10, b wireGND Internal groundMUKZU Negative secondary voltage −48 V/−60 VPCM_E PCM highway; receive directionPCM_S PCM highway; transmit directionS21out (no.) Signal wire 1, outgoing, channel (no.)S21in (no.) Signal wire 1, incoming, channel (no.)S22out (no.) Signal wire 2, outgoing, channel (no.)S22in (no.) Signal wire 2, incoming, channel (no.)T4M Clock 4.096 MHzT8K-E Frame clock; receive directionT8K-S Frame clock; transmit directionUKZU Fused primary voltage (−48 V/−60 V)/CS Chip select/RD Read/WR Write
The interface complies with G.712.The input levels and output levels are adjustable in 0.1 dB increments.Input level at F2 at 600 Ω −6 dBr to +10 dBr Input level at F2 at 900 Ω −10 dBr to + 8 dBrOutput level at F2 at 600 Ω −16 dBr to + 4 dBrOutput level at F2 at 900 Ω −16 dBr to + 2 dBrResistance 600 Ω/900 ΩReflection attenuation at
300 Hz to 600 Hz ≥ 12 dB600 Hz to 3400 Hz ≥ 15 dB
Longitudinal balance at300 Hz to 600 Hz ≥ 40 dB600 Hz to 2400 Hz ≥ 46 dB2400 Hz to 3400 Hz ≥ 41 dB
Hook resistance (configurable) 600 Ω real900 Ω real600 Ω with 2.2 mF in sequence900 Ω with 2.2 mF in sequence
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3.12.5.2 Signal Wires
3.12.5.3 Foreign Potential Protection
3.12.5.4 Power Supply
Line resistance ≤ 400 Ω Line capacity ≤ 0.3 mFNumber of signaling inputs (S21in, S22in) per telephone circuit (M) 2Number of signaling outputs (S21out, S22out) per telephone circuit (E) 2 Electronic output circuit (E)Load circuit typical: 1 kΩ, 4 H
Permissible switching current max. 85 mAPermissible switching voltage −75 V to +36 VNominal current 60 mAResidual voltage at 20 mA ≤ 0.8 VResidual voltage at 85 mA ≤ 2 VResidual current ≤ 0.3 mALimitation on relay breaking peaks ≤ 200 V
Electronic input circuit (M)signaling ground potential (active) or
high impedance (inactive)permissible input voltage at activation −12 V bis 0 Vsignal distortion (S21in to E1out without influence by the line) ≤ 3 ms
Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Indoor Signal Lines
Operating voltages −48 V/−60 V, +5 V, −5 VCurrent drain for 10 channels at
−60 V, high impedance for all S2in−60 V, all S2in active+5 V, at maximum load−5 V, at maximum load
15 mA60 mA205 mA95 mA
Maximum power dissipation for −60 V and ±5 V,at maximum load 5 W
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3.13 SEM108HC E&M Converter
3.13.1 OverviewThe SEM108HC line card is used in the multiplexer for connection to exchange andtransmission equipment which operates with E&M signaling. The line card incorporatesunits for 10 interfaces each which process VF signals in four-wire operation and whichare equipped with two outgoing and two incoming transparent signal channels.
The SEM108HC is equipped with the following interfaces:• F2 interface
The F2 interface is a four-wire interface which is used for transmission of the VF in-formation.
• S21 and S22 interfaceThe call processing codes are transmitted via the S21 and S22 signaling wires, in-ternal interface circuit see Fig. 3.63.
• Internal interfacesThe PCM highway and LC bus form the interface between the central unit and the SEM108HC.
• Power supply.
Fig. 3.63 Internal Interface Circuit of S2in
F2inb1
F2outa1F2outb1
SEM108HC
External interfaces
Internal interfaces
PCM highway
LC busS21in1S21out1
S22in1S22out1
F2ina1
F2inb10
F2outa10F2outb10
S21in10S21out10
S22in10S22out10
F2ina10
......
+5 V
−5 V
−48 V/−60 V
60 k
20 k
S2in
−48 V/ −60 V
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3.13.2 Monitoring and Alarm SignalingOn the basis of the alarm criteria listed in Tab. 3.63, a SISA message conforming to theQD2 Specification is generated and remedial action is taken. The alarm criteria result ina non-urgent alarm (B-alarm).
3.13.3 TestsThe following options are available for testing the signal path of the NF signals:• insert an analog loop from E1in to E1out• insert a test tone at F2out.
Alarm criterion Remedial action Message
Test mode//loop NF activated, power on or test loop SER
Tab. 3.63 Table of Alarms for the SEM108HC
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3.13.4 Connector Assignment
Fig. 3.64 Connector Assignment SEM108HC
External Connector 16
No. c b a
1 F2in_a1 S21out_1 F2out_a1
2 F2in_b1 S22out_1 F2out_b1
3 F2in_a2 F2out_a2
4 F2in_b2 F2out_b2
5 S21in_2 S21out_2 S21in_1
6 S22in_2 S22out_2 S22in_1
7 S21out_3 F2out_a3
8 S22out_3 F2out_b3
9 F2in_a3 S21out_4
10 F2in_b3 S22out_4
11 S21in_4 S21out_5 F2out_a4
12 S22in_4 S22out_5 F2out_b4
13 F2in_a4 S21out_6 F2out_a5
14 F2in_b4 S22out_6 F2out_b5
15 S21in_6 S21in_3
16 S22in_6 S22in_3
17 F2in_a5 S21out_7 S21in_5
18 F2in_b5 S22out_7 S22in_5
19 F2in_a6 F2out_a6
20 F2in_b6 F2out_b6
21 S21in_8 S21out_8 S21in_7
22 S22in_8 S22out_8 S22in_7
23 F2in_a7 F2out_a7
24 F2in_b7 F2out_b7
25 F2in_a8 F2out_a8
26 F2in_b8 F2out_b8
27 S21in_10 S21out_9 S21in_9
28 S22in_10 S22out_9 S22in_9
29 F2in_a9 F2out_a9
30 F2in_b9 F2out_b9
31 F2in_a10 S21out_10 F2out_a10
32 F2in_b10 S22out_10 F2out_b10
Internal connector 15
No. c b a
1 GND
2 GND GND
3
4 MUKZU
5 GND_S GND_S
6 PWE
7
8 PB5 PB4
9
10 PB1
11
12 PB0
13 GND_S
14
15
16
17 GND GND GND
18 AD7 AD6 AD5
19
20 AD4 AD3 AD2
21 GND GND GND
22 AD1 AD0 ALE
23 GND GND GND
24 NCS NWR NRD
25 GND GND GND
26 ADR3 SYN_E1 PCM-E1
27 GND GND GND
28 ADR2 ADR1 ADR0
29
30 CLK_4M SYN_S PCM-S1
31 GND
32 −5 V +5 V GND
Codierteil:Darstellung fehlender Codierelemente
c b a1
5
10
15
20
25
30
16
c b a15
1
7
9
16
1
5
10
15
20
25
30
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3.13.5 Signal Abbreviations
3.13.6 Technical Data
3.13.6.1 4-Wires VF Interface
AD0 to AD7 Address- and data bus linesADR0 to ADR3 Address lines to plug-in placesALE Address latch enableF2outa1 to F2outa10 4wire signal outgoing, a wire; channels 1 to 10F2outb1 to F2outb10 4wire signal outgoing, b wire; channels 1 to 10F2ina1 to F2ina10 4wire signal coming, a wire; channels 1 to 10F2inb1 to F2inb10 4wire signal coming, b wire; channels 1 to 10GND Internal groundMKZU Switching groundPCM_E PCM highway; receive directionPCM_S PCM highway; transmit directionS21out1 to S21out10 Signal wire 1, outgoing; channels 1 to 10S21in1 to S21in10 Signal wire 1, coming; channels 1 to 10S22out1 to S22out10 Signal wire 2, outgoing; channels 1 to 10S22in to S22in10 Signal wire 2, coming; channels 1 to 10T4M Basic clock 4.096 MHzT8K-E Frame clock; receive directionT8K-S Frame clock; transmit directionUKZU Fused primary voltage (-48 V/-60 V)/CS Chip select/RD Read/WR Write+5 V Positive secondary voltage-5 V Negative secondary voltage
The interface complies with ITU-T G.712.Output level at F2out
SEM108HC –17.0 dBr to +8.3 dBrInput level at F2in
SEM108HC −15.0 dBr to +9.0 dBrAll levels are adjustable in 0.1 dB increments. Characteristic resistance 600 Ω realReflection attenuation at 300 Hz to 3400 Hz ≥ 20 dBLongitudinal balance at
300 Hz to 2400 Hz ≥ 46 dB2400 Hz to 3400 Hz ≥ 41 dB
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3.13.6.2 Signal Wiresconforming to SEM106C, see Section 3.12.5.2
3.13.6.3 Foreign Potential Protectionconforming to SEM106C, see Section 3.12.5.3
3.13.6.4 Power Supplyconforming to SEM106C, see Section 3.12.5.4
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3.14 Analog Leased Line LLA102/104C
3.14.1 OverviewThe analog leased line unit LLA102/104C is employed for up to 10 fixed analog connec-tions within digital transmission links for service-independent, transparent, point-to-pointtransmission of information via the multiplexer. These channels can be operated with2-or 4-wire interfaces.
The LLA102/104C has the following interfaces:• F2 interface:
The F2 interface is a two-wire or four-wire interface for transmitting VF signals.• Internal interfaces:
PCM highway and LC bus form the interface between the CUD and the LLA102/104C.
• Power supply.
3.14.2 Supervision and Alarm SignalingFor certain alarm criteria SISA messages are generated as per QD2 specification andconsequential action is performed, see Maintenance Manual MMN.
All alarm criteria result in a non-urgent alarm (B-alarm). In addition a local loop can beset on a digital-digital basis for VF measurements.
a1b1
F2out2)
a10b10
a10b10
a1b1
F2in2)
LLA102/104C
−5 V
+5 V
LC bus
External interfaces Internal interfaces
a1b1
a10b10
...F21)
1) Two-wire version
2) Four-wire version
PCM highway...
......
......
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3.14.3 Connector Assignment
Fig. 3.65 Connector Assignment of LLA102/104C
c b a1
5
10
15
20
25
30
16
c b a
10
20
30
2
15
External Connector 16
No.
Row
C B A
1 F2in_a1 F2out_a1
2 F2in_b1 F2out_b1
3 F2in_a2 F2out_a2
4 F2in_b2 F2out_b2
5
6
7 F2out_a3
8 F2out_b3
9 F2in_a3
10 F2in_b3
11 F2out_a4
12 F2out_b4
13 F2in_a4 F2out_a5
14 F2in_b4 F2out_b5
15
16
17 F2in_a5
18 F2in_b5
19 F2in_a6 F2out_a6
20 F2in_b6 F2out_b6
21
22
23 F2in_a7 F2out_a7
24 F2in_b7 F2out_b7
25 F2in_a8 F2out_a8
26 F2in_b8 F2out_b8
27
28
29 F2in_a9 F2out_a9
30 F2in_b9 F2out_b9
31 F2in_a10 F2out_a10
32 F2in_b10 F2out_b10
Internal Connector 15
No.
Row
C B A
1 GND
2 GND GND
3
4
5 GND_S GND_S
6 PWE
7
8
9
10
11
12
13 GND_S
14
15
16
17 GND GND GND
18 AD7 AD6 AD5
19
20 AD4 AD3 AD2
21 GND GND GND
22 AD1 AD0 ALE
23 GND GND GND
24 NCS NWR NRD
25 GND GND GND
26 ADR3 SYN_E1 PCM_E1
27 GND GND GND
28 ADR2 ADR1 ADR0
29
30 CLK_4M SYN_S PCM_S1
31 GND
32 −5 V +5 V GND
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Signal Abbreviations
3.14.4 Technical Data
3.14.4.1 VF Parameters per ITU-T G.712
AD0 to AD7 Address and data bus bit 0 to 7ADR0 to ADR3 Address of plug-in place 0 to 15 for LCALE Address latch enableCLK_4M 4-MHz system clock PCM highwayNCS Chip selectF2out_a1 to F2out_a10 Interface analog 1 to 10, a wire, transmission directionF2out_b1 to F2out_b10 Interface analog 1 to 10, b wire, transmission directionF2in_a1 to F2in_a10 Interface analog 1 to 10, a wire, receive directionF2in_b1 to F2in_b10 Interface analog 1 to 10, b wire, receive directionGND Internal groundPCM_E1 PCM highway receive directionPCM_S1 PCM highway transmit directionPWE Write protection enable for EEPROMPUKZU Positive secondary voltage +48 V/+60 VNRD ReadSYN_E Synchronous pulse receive directionSYN_S Synchronous pulse transmit directionNWR Write+5 V Positive secondary voltage +5 V−5 V Negative secondary voltage −5 V
4-wire interfaceoutput levelinput levellevel settingreturn loss at 300 Hz to 3400 Hzlongitudinal conversion loss at 300 Hz to 2400 Hzlongit. conversion loss at 2400 Hz to 3400 Hz
+4 dBr to −14 dBr+4 dBr to −14 dBrin 0.5-dB steps≥ 20 dB≥ 46 dB≥ 41 dB
2-wire interfaceoutput levelinput levellevel settingreturn loss at 300 Hz to 600 Hzreturn loss at 600 Hz to 3400 Hzlongitudinal conversion loss at 300 Hz to 600 Hzlongit. conversion loss at 600 Hz to 2400 Hzlongit. conversion loss at 2400 Hz to 3400 Hz
+4 dBr to −14 dBr+9 dBr to −8 dBrin 0.5-dB steps≥ 12 dB≥ 15 dB≥ 40 dB≥ 46 dB≥ 41 dB
Impedance, resistive 600 ΩHybrid balance, resistive 600 Ω
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3.14.4.2 Foreign Potential Protection
3.14.4.3 Power Supply
Protection against external voltages on the outdoor user lines is implemented in 2 stag-es within the entire system. A 420 V gas tube arrestor must be installed directly preced-ing the line card.For further information see Section 1.4.7 and UMN:IMN.Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Outdoor Signal Lines
Operating voltages +5 V, −5 VCurrent drain for 10 channels at
+5 V−5 V
245 mA110 mA
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3.15 ISDN I8S0P Line Card
3.15.1 OverviewThe I8S0P unit enables an ISDN basic access to be established for remote subscriberterminal equipment or PBXs with S0 port.
The ISDN-S0 interface conforms to ITU-T Recommendation I.430. The unit converts thedata of the S0 interface directly to the 2-Mbit/s level and vice versa.
The I8S0P contains 8 independent S0 interfaces that are used in NT mode or in TEmode. User channel information (B1, B2 and D) is transmitted at the S0 interface on a4-wire basis using a modified AMI code.
The line card provides the following functions:• Implementation of the S0 interfaces
The S0 interfaces of the unit are suitable for connection of ISDN equipment both as point-to-point or point-to-multipoint connections (passive bus) with a maximum of eight terminals.
• Control of call processing procedures of layer 1• Power supply management
The line card is fed exclusively locally. Feed power will not be taken from the S0 in-terface even in TE mode.
For feeding of the S0 bus, the line card supplies an emergency feed for the TEs of 420 mW for each S0 interface in NT mode. This guarantees operation of terminals with emergency power feed authorization.
• Self-test function (feeding and layer 1 at the S0 interface, feeding status of the S0 interface can be requested).
The I8S0P has the following interfaces:• S0 interface:
The S0 interface is a four-wire interface according to ITU-T I.430 through which the ISDN user information (B1 + B2 + D) and the emergency feed is passed.
• Internal interfaces:PCM highway and LC bus form the interface between the central unit and the I8S0P.
• Power supply.
!Only point-to-point operation is possible in TE mode. Point-to-multipoint operation can lead to D channel collisions. Moreover, a permanent sychronization of the line card is necessary on the NT (Master).
iAn external feed device (product number V39113-Z5240-A680) must be used for normal feeding of the S0 bus. If there are only terminals with their own power supply or a terminal with emergency power feed authorization on the S0 bus, no additional feed unit is required.
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3.15.2 Time Slot Allocation and SignalingA distinction is to be made between the following cases:• CAS signaling
Within the multiplex signal any number of 64-kbit/s time slots can be occupied by the data (B1, B2) of the 8 ISDN ports in the format 1 × 64 kbit/s, 2 × 64 kbit/s and 128 kbit/s. For the D-channel a 16-kbit/s time slot can additionally be assigned for each port. The transmission of the signaling data of the D-channel can be configured via the line card. Signaling can optionally be multiplexed in sub time slots of 16 kbit/s each per port within a common 64-kbit/s time slot for ports 1 through 4 or 5 through 8 with static assignment or transmitted (non multiplexed) within a 64-kbit/s time slot for each port in a sub time slot.
• FA signalingWithin the multiplex signal any number of 64-kbit/s time slots (except B* time slots used for signaling) can be occupied by data (B1, B2) of the 8 ISDN-Ports in the for-mat 1 × 64 kbit/s, 2 × 64 kbit/s and 128 kbit/s.
• Standalone mode (in menu option “Leased line”)Within the multiplex signal any number of 64-kbit/s time slots can be occupied by data (B1, B2) of the 8 ISDN-Ports in the format 1 × 64 kbit/s, 2 × 64 kbit/s and 128 kbit/s. For the D channel an additional 16-kbit/s time slot can be assigned for each port. No layer-1 information will be transmitted.If required, D channel transmission can be configured via the line card. Signaling can optionally be multiplexed in sub time slots of 16 kbit/s each per port within a common 64-kbit/s time slot for ports 1 through 4 or 5 through 8 with static assign-ment or transmitted (non multiplexed) within a 64-kbit/s time slot for each port in a sub time slot.
PCM highway
External interfaces Internal interfaces
1) In TE mode transmission is at c, d and receiving at e, f
S0
c1 (Rx1 a-wire)I8S0P
−5 V
+5 V
−48 V/−60 V
d1 (Rx1 b-wire)e1 (Tx1 a-wire)f1 (Tx1 b-wire)
......
NT mode1)
NT mode1)
c8 (Rx8 a-wire)d8 (Rx8 b-wire)e8 (Tx8 a-wire)f8 (Tx8 b-wire)
Rx receiveTx transmit
LC bus
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3.15.3 Supervision and Alarm Signaling and DiagnosticsThe following functions are provided:• Self-test function
The self-test is performed after the unit has been booted. This allows power feeding (emergency feed) and transmission performance to be tested at each S0 interface:– feeding voltage, feeding power, current limiting– S0 interface layer 1.
• Detection of faults and disturbances with consequential action.• Test mode
For test and measurement purposes a continuous 96-kHz signal or a continuous 2-kHz signal can be generated at the S0 interface.
• Layer 1 test basic accessFor test purpose error rates can be measured in connection with a local loop 2 on the unit or via an external loop (in NT mode only, send and receive side connected externally).In NT mode the local HW loop can be used additionally for test activation and for error rate measurement.
Fig. 3.66 Loops on the I8S0P
• Forced activationThe ISDN connection (layer 1) can be forcibly activated from the deactivated state.
• Status info (in NT mode only), retrievable via the OS:– presence of an external feeding voltage at the S0 interface– polarity of an external feeding voltage at the S0 interface– emergency feed active.
Rx
Tx
I8S0P
S0Local loop External loop
2 x 2 μF/63 V
e
d
f
cRx
Tx
I8S0PS0
e
d
f
c
NT mode1) NT-Mode1)
1) In TE mode transmission is at c, d and receiving at e, f
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3.15.4 Controls
Fig. 3.67 Control Elements of the I8S0P
Jumper Position Value Function
1002)not plugged-in
plugged-in
High-impedance
100Ω1)S0-bus terminating resistor channel 1
5002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 5
2002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 2
6002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 6
3002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 3
7002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 7
4002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 4
8002)not plugged-in
plugged-in
High-impedance
100 Ω1)S0-bus terminating resistor channel 8
1) Delivery state
2) Jumper 1 for transmit side (from LC-view)
Jumper 2 for receive side (from LC-view)
Tab. 3.64 Controls on the I8S0P (S0-Bus)
X1
X2
O
O
O
O
O
O
O
O
S10
S50
S20
S60
S30
S70
S40
S80
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
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3.15.5 Connector Assignment
Fig. 3.68 Connector Assignment of I8S0P
External connector X2
Row
No. a b c
1 S0a1 (c1) S0a5 (c5)
2 S0b1 (d1) S0b5 (d5)
3 S0c1 (e1) S0c5 (e5)
4 S0d1 (f1) S0d5 (f5)
5
6
7 S0a2 (c2)
8 S0b2 (d2)
9 S0a6 (c6)
10 S0b6 (d6)
11 S0c2 (e2)
12 S0d2 (f2)
13 S0a3 (c3) S0c6 (e6)
14 S0b3 (d3) S0d6 (f6)
15
16
17 S0a7 (c7)
18 S0b7(d7)
19 S0c3 (e3) S0c7 (e7)
20 S0d3 (f3) S0d7 (f7)
21
22
23 S0a4 (c4) S0a8 (c8)
24 S0b4 (d4) S0b8 (d8)
25 S0c4 (e4) S0c8 (e8)
26 S0d4 (f4) S0d8 (f8)
27
28
29
30
31
32
Internal connector X1
Row
No. a b c
1 GND
2 GND PUKZU
3
4 MUKZU_1
5
6 PE
7
8
9
10
11
12
13
14
15
16 CLK_64K
17 GND GND GND
18 AD5 AD6 AD7
19
20 AD2 AD3 AD4
21 GND GND GND
22 ALE AD0 AD1
23 GND GND GND
24 RD WR CS
25 GND GND GND
26 PCM_E1 SYN_E1 ADR3
27 GND GND GND
28 ADR0 ADR1 ADR2
29
30 PCM_S1 SYN_S CLK_4M
31 GND
32 GND VCC (P5V) M5V
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Signal Abbreviations
3.15.6 Technical Data
3.15.6.1 S0 Interface
AD0 to AD7 Address and data bus bit 0 to 7ADR0 to ADR3 Address of plug-in place ALE Address latch enableCLK_4M Clock 4.096 MHzCLK_64K Clock 64 KHz for synchronization of the CUDCS Chip select NBICGND Internal groundMUKZU_1 Negative secondary voltage +48 V/+60 VM5V Negative secondary voltagePCM_E PCM highway receive directionPCM_S PCM highway transmit directionPE Write protection enable for EEPROMPUKZU Positive secondary voltage +48 V/+60 VRD ReadS0a1 to S0a8 Subscriber line c (channel no.), a-wire, input (NT mode),
output (TE mode)S0b1 to S0b8 Line d (channel no.), b-wire, input (NT mode), output (TE mode)S0c1 to S0c8 Line e (channel no.), a-wire, output (NT mode), input (TE mode)S0d1 to S0d8 Line f (channel no.), b-wire, output (NT mode), input (TE mode)SYN_E Frame clock receive direction, externalSYN_S Frame clock transmit direction, internalVCC Positive secondary voltage WR Write
Line connection two balanced Cu wire pairsPoint-to-point connection
number of subscribersreachattenuation at 96 kHz
1≤ 1000 m≤ 6 dB
Point-to-multipoint connection1)
short passive busnumber of subscribersreach (TE at any point)
extended passive busnumber of subscribersreach (TE 35 m max. from bus end)
bus termination
1 to 8≤ 150 m
1 to 4≤ 500 m100 Ω, resistive
Output impedance > 2500 ΩTransmit amplitude across 50 Ω 750 mV0PLongitudinal conversion loss
10 kHz to 300 kHz300 kHz to 1000 kHz
> 54 dB20 dB/decade
1) only possible in NT mode
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3.15.6.2 Power Feeding
3.15.6.3 EMC and Foreign Potential Protection
3.15.6.4 Power Supply and Dissipation
Common mode rejection of output signal96 kHz96 kHz to 1000 kHz
> 54 dB20 dB/decade
Permissible sinusoidal input jitter5 Hz5 Hz to 50 Hz50 Hz to 10000 Hz
0.5 UI20 dB/decade0.05 UI
Power feeding method phantom feedingFeeding voltage, reverse polarity 40 V (+2 V/−8 V)Max. feeding power per interface (emergency) 420 mWCurrent limiting ≥ 16 mAMaximum power consumption at S0 in TE mode 1 mW
RF interference suppression VDE 0878, Part 1 and 30 GWK B, 10 kHz to 30 MHz
Immunity to sinusoidal interference FTZ12 TR1, Part 21, 10 kHz to 150 MHz
Immunity to bursts IEC 801-4Immunity to surge
longitudinal voltagetransverse voltage
prETS 300126 §8.3, 1.2/50 ms±1 kV ±0.25 kV
Operating voltages −48 V (−36 V to −72 V)+5 V (1 ±5%)−5 V (1 ±5%)
Current drainTotal current drain with emergency power activated and feeding 420 mW to S0
at −48 Vat −60 V
≤ 110 mA≤ 80 mA
Total current drain with feed deactivated at −48 Vat −60 V
≤ 10 mA≤ 15 mA
Current drain, all ports in the NT modeat +5 Vat −5 V
≤ 350 mA≤ 10 mA
Power dissipated by the unit With 420 mW fed to S0 per channelWithout feed to S0
≤ 2.8 W≤ 1.8 W
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3.16 IUL82C and IUL84C ISDN Line Cards
3.16.1 OverviewThe IUL82C and IUL84C line cards with 8 Uk0 interfaces are employed within digitaltransmission links between subscribers and switching equipment on the subscriber sidewhen ISDN network termination units are to be connected to the multiplexer.
The IUL82C line card is used for 2B1Q code, while the IUL84C line card implements the4B3T code.
The Uk0 ISDN interface conforms to standard TS 102 080.
Data transmission is also possible in the format 128 kbit/s via the B1- and B2-channelsof an ISDN line. The framing integrity of the 128-kbit/s connection is ensured.
Connected NTBAs are fed per port with up to 1.1 W power as consumed at the NTBA.
IUL82C and IUL84C are further developed IUL82 respectively IUL84 with integrated ov-ervoltage protection against power contact. Therefore, the 5-pin protection element waschanged to a standard 3-pin gas tube arrestor for IUL82C and IUL84C. IUL82 and IUL84can be upgraded to IUL82C respectively IUL84C without changing the protection ele-ments. But there is not full overvoltage protection for the predecessor variants (IUL82,IUL84) with 3-pin gas tube arrestors.
The IUL82C and IUL84C line cards provide the following functions:• Implementation of the Uk0 interfaces• Control of call processing procedures of layer 1• Feeding connected network termination units from the remote feed units• Self-test function (feeding and layer 1 at the Uk0 interface)• Automatic measurement of transmission performance quality parameters with
layer 1 activated• Test of subscriber-side layer 1 at the Uk0 interface (loop 1) and/or in the NTBA close
to S0 (loop 2) or in the NTU for a basic access not involved in call processing func-tions as an operator control measurement function (BER on demand).
PCM highway
External interfaces Internal interfaces
Uk0
a1
IUL82C/IUL84C
−5 V
+5 V
−48 V/−60 V
b1
a8b8
......
LC bus
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The IUL82C and IUL84C units have the following interfaces:• 8 × Uk0 interfaces
The Uk0 interface is a two-wire interface carrying the data in the 2B1Q code (IUL82C) or in the 4B3T code (IUL84C) and power feeding.
• Internal interfacesPCM highway and LC bus form the interface between the central unit CUD and the IUL82C or IUL84C.
• Power supply.
3.16.2 Time Slot Allocation and SignalingA distinction is to be made between the following cases:• CAS signaling
Within the multiplex signal any number of 64-kbit/s time slots can be occupied by the data (B1, B2) of the 8 ISDN ports in the format 1 × 64 kbit/s, 2 × 64 kbit/s and 128 kbit/s. For the D-channel a 16-kbit/s time slot can additionally be assigned for each port. The transmission of the signaling data of the D-channel can be configured via the line card. Signaling can optionally be multiplexed in sub time slots of 16 kbit/s each per port within a common 64-kbit/s time slot for ports 1 through 4 or 5 through 8 with static assignment or transmitted (non multiplexed) within a 64-kbit/s time slot for each port in a sub time slot.
• Standalone mode (in menu option “Leased Line”)Within the multiplex signal any number of 64-kbit/s time slots (except B* time slots used for signaling) can be occupied by data (B1, B2) of the 8 ISDN-Ports in the for-mat 1 × 64 kbit/s, 2 × 64 kbit/s and 128 kbit/s. For the D channel an additional 16-kbit/s time slot can be assigned for each port which can be used for data trans-mission.If required, D channel transmission can be configured via the line card. Signaling can optionally be multiplexed in sub time slots of 16 kbit/s each per port within a common 64-kbit/s time slot for ports 1 through 4 or 5 through 8 with static assign-ment or transmitted (non multiplexed) within a 64-kbit/s time slot for each port in a sub time slot.
3.16.3 Supervision and Alarm Signaling and DiagnosticsThe following functions are provided:• Self-test function
The self-test is performed after the unit has been booted. This allows the power feeding to be tested at each Uk0 interface.
• Detection of faults and disturbances with consequential action, see maintenance manual MMN
• Automatic measurement of transmission performance quality parameters with layer 1 activated
• Layer 1 test basic access (BER on demand)Test of subscriber-side layer 1 at the Uk0 interface (loop 1) and/or in the NTBA close to S0 (loop 2) or in the NTU for a basic access not involved in call processing func-tions as an operator control measurement function.
• Forced activationThe ISDN connection (layer 1) can be forcibly activated from the deactivated state.
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3.16.4 Connector Assignment
Fig. 3.69 Connector Assignment of IUL82C and IUL84C
c b a
10
20
30
2
10
c b a
10
20
30
2
11 External connector11
Row
No. c b a
1 D2a1
2 D2b1
3 D2a2
4 D2b2
5
6
7 D2a3
8 D2b3
9
10
11 D2a4
12 D2b4
13 D2a5
14 D2b5
15
16
17
18
19 D2a6
20 D2b6
21
22
23 D2a7
24 D2b7
25 D2a8
26 D2b8
27
28
29
30
31
32
Internal connector 10
Row
No. c b a
2 PUKZU GND
4 MUKZU
6 PE
8
10 MB1
12 MB0
14 SSYNC
16
18 AD7 AD6 AD5
20 AD4 AD3 AD2
22 AD1 AD0 ALE
24 NCS NWR NRD
26 ADR3 T8K_E PCM_E
28 ADR2 ADR1 ADR0
30 T4M T8K_S PCM_S
32 M5V P5V GND
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Signal Abbreviations
3.16.5 Technical Data IUL82C
3.16.5.1 Uk0 Interface Parameters
3.16.5.2 Data Format
AD0 to AD7 Address and data bus bit 0 to 7ADR0 to ADR3 Address of plug-in place for the unitALE Address latch enableD2a1 to D2a8 Data signal, a wire (channel number)D2b1 to D2b8 Data signal, b wire (channel number)GND Internal groundM5V Negative secondary voltagePCM_E PCM highway receive directionPCM_S PCM highway transmit directionP5V Positive secondary voltageT4M Clock 4.096 MHzT8K_E Frame clock receive direction, externalT8K_S Frame clock transmit direction, internalNCS Chip Select SBICNRD ReadNWR Write
Line connection balanced Cu wire pair 0.4 mm to 0.8 mm,AWG 22, AWG 24, AWG 26
Reach loop # 1 to 7 in ETSI DTR/ TM-3002, Sct. 4.2.1, p.13 e.s.
Permissible line attenuation at 40 kHz ≤ 36 dBTransmission method bit-transparent duplex trans-
missionDirectional isolation by adaptive echo cancelationCoding 2B1QInternal impedance (nominal) 135 ΩTransmit pulse UPP (discrete pulses across 135 Ω) ±2.5 V0P (1 ±5%)Return loss (relative to 135 Ω resistive)
1 kHz to 10 kHz10 kHz to 25 kHz25 kHz to 250 kHz
20 dB/decade> 20 dB20 dB/decade
Data B1 + B2 and signaling D 72 kBaud (144 kbit/s)Transmission rate 80 kBaud
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3.16.5.3 Remote Power Feeding
3.16.5.4 Foreign Potential Protection
3.16.5.5 Power Supply and Dissipation
Feeding voltage (NTBA operation), tied to ground,disconnectable for each channel separately −95 VLoop resistance ≤ 1250 ΩFeed current limiting ≤ 55 mARestoral function < 30 s
Protection against external voltages on the outdoor user lines is implemented in 2 stag-es within the entire system. A 420 V gas tube arrestor must be installed directly preced-ing the line card.For further information see Section 1.4.7 and UMN:IMN.Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Outdoor Signal Lines
Operating voltages −48 V (−36 V to −72 V)+5 V (1 ±5%)−5 V (1 ±5%)
Total current drain with 1.1 W consumed at the NTBA per channel and with maximum feeding reach(emergency mode with 420 mW fed to the TE)
at −48 Vat −60 V
315 mA250 mA
Total current drain, with normal NTBA powering per channel and with maximum feeding reach
at −48 Vat −60 V
165 mA130 mA
Current drainat +5 Vat −5 V
800 mA10 mA
Power dissipation PV, with undisturbed ISDN signal transmission and a feeding voltage of 95 V,
with 1.1 W consumed at the NTBA per channel andmaximum feeding lengthwith normal NTBA powering and maximum feeding length
approx. 7 W
approx. 5 W
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3.16.6 Technical Data IUL84C
3.16.6.1 Uk0 Interface Parameters
3.16.6.2 Data Format
3.16.6.3 Power Feeding
3.16.6.4 Foreign Potential Protection
Line connection balanced Cu wire pair0.4 mm to 0.8 mm,AWG 22, AWG 24, AWG 26
Reachconductor diameter 0.4 mmconductor diameter 0.6 mm
≤ 3.8 km≤ 8.0 km
Transmission method bit-transparent duplex trans-mission
Directional isolation by adaptive echo cancelationCoding 4B3TInternal impedance (nominal) 150 ΩTransmit pulse UPP (discrete pulses across 150 Ω) 2 V (1 ±10%)Return loss (relative to 150 Ω resistive)
5 kHz to 12.5 kHz, attenuation roll-off12.5 kHz to 50 kHz50 kHz to 100 kHz, attenuation roll-off
from > 16 dB to > 8 dB> 16 dBfrom >16 dB to > 10 dB
Data B1 + B2 and signaling D 108 kBaud (144 kbit/s)Transmission rate 120 kBaud
Feeding voltage (NTBA operation), tied to ground, disconnectable for each channel separately −95 VLoop resistance ≤ 1250 ΩFeed current limiting ≤ 55 mADisconnect threshold 50 mA ±5 mAOverload disconnectionon crossing the disconnect threshold > 1.5 s Restoral function < 30 s
Protection against external voltages on the outdoor user lines is implemented in 2 stag-es within the entire system. A 420 V gas tube arrestor must be installed directly preced-ing the line card.For further information see Section 1.4.7 and UMN:IMN.Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Outdoor Signal Lines
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3.16.6.5 Power Supply and Dissipation
Operating voltages −48 V (−36 V to −72 V)+5 V (1 ±5%)−5 V (1 ±5%)
Total current drainwith 1.1 W consumed at the NTBA per channel and with maximum feeding reach(emergency mode with 420 mW fed to the TE)
at −48 Vat −60 V
315 mA250 mA
Total current drain, with normal NTBA powering per channel and with maximum feeding reach
at −48 Vat −60 V
165 mA130 mA
Current drainat +5 Vat −5 V
800 mA10 mA
Power dissipation PV, with undisturbed ISDN signal transmission and a feeding voltage of 95 V,
with 1.1 W consumed at the NTBA per channel andmaximum feeding lengthwith normal NTBA powering and maximum feeding length
approx. 7 W
approx. 5 W
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3.17 I4UK2NTP/I4UK4NTP ISDN Line Cards
3.17.1 OverviewISDN line cards I4UK2NTP and I4UK4NTP with 4 interfaces provide the Uk0 interfacebetween multiplexer FMX2R3.2 and ISDN switching equipment on the switching side.Data from the I4UK2NTP is transmitted using the 2B1Q code and the data from theI4UK4NTP is transmitted using the 4B3T code. The signaling codes will be transmittedusing channel-associated signaling in time slot 16 of the multiplex signal.
The I4UK2NTP and I4UK4NTP have the following functions:• Implementation of the electrical subscriber interfaces on the exchange side• Control of the call processing procedures• Transmission of the overhead bits of the Uk0 interface.
The I4UK2NTP/I4UK4NTP is equipped with the following interfaces:• 4 × Uk0 interface
The Uk0 interface is a two-wire interface with 2B1Q coding (I4UK2NTP) or 4B3T coding (I4UK4NTP), which is used for routing the data and the remote power feed from the exchange.
• Internal interfacesThe PCM highway and LC bus form the interface between the central unit and the I4UK2NTP/I4UK4NTP.
• Power supply.
3.17.2 Time Slot Assignment and SignalingUnits I4UK2NTP and I4UK4NTP will be used exclusively in CAS/FA dial-up connec-tions.
Within the multiplex signal any 64-kbit/s time slots (except for time slot 16 and the timeslots reserved for the D channels) can be occupied by the data (B1, B2) of the 8 ISDN-ports in the format 1 × 64 kbit/s, 2 × 64 kbit/s and 128 kbit/s.
For data rate 128 kbit/s in the B1 and B2 channels the time slot alignment is prescribedfor reasons of frame integrity:
External interfaces Internal interfaces
Uk0
a1
b1
I4UK2NTP/I4UK4NTP
a4
b4
−5 V
+5 V
PCM highway
LC bus
−48 V/−60 V
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For the two B channels only time slots within a time slot group may be selected. In theevent of transmission at a data rate of 2 × 64 kbit/s via user channels B1 and B2 of anISDN channels, the restriction described above does not apply.
ISDN port PCM time slot port A PCM time slot port B
1 to 3 1 to 2,
or 3 to 10,
or 11 to 31
−2 to 9,
or 10 to 31
4 1 to 2,
or 3 to 12,
or 13 to 31
−2 to 11,
or 12 to 31
Tab. 3.65 Restricted Time Slot Occupancy of the I4UK2NTP at 128 kbit/s
ISDN port PCM time slot port A PCM time slot port B
1 to 3 1 to 8
or
9 to 31
1 to 7
or
8 to 31
4 1 to 10
or
11 to 31
1 to 9
or
10 to 31
Tab. 3.66 Restricted Time Slot Occupancy of the I4UK4NTP at 128 kbit/s
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3.17.3 Connector Assignment of I4UK2NTP
Fig. 3.70 Connector Assignment of I4UK2NTP
c b a1
5
10
15
20
25
30
14
c b a
10
20
30
2
13
Connector 14
No.
Row
c b a
1 Uk0_a1
2 Uk0_b1
3
4
5
6
7 Uk0_a2
8 Uk0_b2
9
10
11
12
13
14
15
16
17
18
19 Uk0_a3
20 Uk0_b3
21
22
23
24
25
26
27
28
29
30
31 Uk0_a4
32 Uk0_b4
Connector 13
No.
Row
c b a
2 MUKZU GND
4 MUH UKZU
6 PUH PE
8
10 Pb3 Pb2 Pb1
12 Pb0
14
16 T64K
18 AD7 AD6 AD5
20 AD4 AD3 AD2
22 AD1 AD0 ALE
24 /CS /WR /RD
26 ADR3 T8K_E PCM_E
28 ADR2 ADR1 ADR0
30 T4M T8K_S PCM_S
32 −5 V +5 V GND
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Signal Abbreviations of I4UK2NTP
AD0 to AD7 Address- and data bus bit 0 to 7ADR0 to ADR3 Plug-in place address 0 to 15 for LCALE Address latch enableMUKZU Negative secondary voltage −48 V/−60 VMUH Negative primary heating voltage −48 V/−60 VPCM_E PCM highway receive directionPCM_S PCM highway transmit directionPE Write protection enable for EEPROMPUH Positive primary heating voltage +48 V/+60 VT64K 64-kHz synchronous clockT4M 4-MHz synchronous clock PCM highway (CUA - LC)T8K_E Synchronous clock receive directionT8K_S Synchronous clock transmit directionUk0_a1 to Uk0_a4 Digital interface 1 to 4, a wireUk0_b1 to Uk0_b4 Digital interface 1 to 4, b wireUKZU Positive secondary voltage +48 V/+60 V+5 V Positive secondary voltage−5 V Negative secondary voltage/CS Chip select/RD Read/WR WriteGND Internal ground
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3.17.4 Connector Assignment of the I4UK4NTP
Fig. 3.71 Connector Assignment of the I4UK4NTP
Leading contacts
External connector 14
No. c b a
1 Uk0a1
2 Uk0b1
3
4
5
6
7 Uk0a2
8 Uk0b2
9
10
11
12
13
14
15
16
17
18
19 Uk0a3
20 Uk0b3
21
22
23
24
25
26
27
28
29
30
31 Uk0a4
32 Uk0b4
Internal connector 13
No. c b a
2 MKZU GND
4 UKZU
6 PE
8
10 PB1
12 PB0
14
16 T64K
18 AD7 AD6 AD5
20 AD4 AD3 AD2
22 AD1 AD0 ALE
24 /CS /WR /RD
26 ADR3 T8K-E PCM-E
28 ADR2 ADR1 ADR0
30 T4M T8K-S PCM-S
32 −5 V +5 V GND
c b a1
5
10
15
20
25
30
14
c b a
10
20
30
2
13
1
7
9
16
Code part:
representation of the
missing code elements
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Signal Abbreviations of the I4UK4NTP
3.17.5 Technical Data I4UK2NTP
3.17.5.1 Interface Parameters
AD0 to AD7 Address- and data bus linesADR0 to ADR3 Address lines to plug-in placesALE Address latch enableGND Internal groundMKZU Switching groundPCM_E PCM highway; receive directionPCM_S PCM highway; transmit directionPE Write protection enable for EEPROMPUH Positive primary heating voltage +48 V/+60 VT4M 4-MHz system clock; PCM highway (CUA - LC)T64K 64-kHz synchronous clockT8K-E Synchronous pulse; receive directionT8K-S Synchronous pulse; transmit directionUk0a1 to Uk0a4 ISDN interface (2wire), a wire, channel 1 to 4Uk0b1 to Uk0b4 ISDN interface (2wire), b wire, channel 1 to 4UKZU Negative primary voltage -48 V/-60 V/CS Chip select/RD Read/WR Write+5 V Positive secondary voltage-5 V Negative secondary voltage
Line connection balanced copper wire pairs, 0.4 mm to 0.8 mm,AWG 22, AWG 24, AWG 26
Range loops 1 to 7 in ETSI DTR/TM-3002
Permissible line loss at 40 kHz ≤ 36 dBTransmission procedure bit-transparent duplex
transmissionDirectional separation by adaptive echo
compensationCoding 2B1QInternal resistance (nominal) 135 ΩTransmit pulse (discrete pulses at 135 Ω) 2.5 V ±5% peak valueReturn loss (in relation to 135 Ω true)
1 kHz to 10 kHz10 kHz to 25 kHz25 kHz to 250 kHz
20 dB/decade> 20 dB20 dB/decade
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3.17.5.2 Data Format
3.17.5.3 Remote Power Feed
3.17.5.4 Foreign Potential Protection
3.17.5.5 Power Supply and Dissipation
3.17.6 Technical Data I4UK4NTP
3.17.6.1 Interface Parameters
B1 + B2 data and D signaling 72 kBaud (144 kbit/s)Transmission rate 80 kBaud
Detection threshold for the remote feed voltage 25 V to 40 VCurrent consumption from the remote power feed < 1 mACurrent limitation for short-circuit simulation < 55 mATest capacitance at Uk0 2.2 μF
Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Indoor Signal Lines
Operating voltages −48 V/−60 V+5 V ±5%−5 V ±5%
Current consumption at+5 V−5 V
300 mA10 mA
Power dissipation(with non-disrupted ISDN signal transmission) 1.5 W
Line connection balanced copper wire pairs, 0.4 mm to 0.8 mm,AWG 22, AWG 24, AWG 26
Rangefor 0.4 mm diameter wirefor 0.6 mm diameter wire
≤ 3.8 km≤ 8.0 km
Transmission procedure bit-transparent duplex transmission
Directional separation by adaptive echocompensation
Coding 4B3TLongitudinal voltage at a/b and ground (Ri = 40 Ω) 1.5 kV; 10/700 μsCross voltage at a/b (Ri = 40 Ω) 0.8 kV; 1.2/50 μs
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3.17.6.2 Data format
3.17.6.3 Remote Power Feed
3.17.6.4 Foreign Potential Protection
3.17.6.5 Power Supply
Internal resistance (nominal) 150 ΩTransmit pulse (discrete pulses at 150 Ω) 2 V ±10% peak valueReturn loss (in relation to 150 Ω true)
5 kHz to 12.5 kHz12.5 kHz to 50 kHz50 kHz to 100 kHz
20 dB/decade> 20 dB20 dB/decade
B1 + B2 data and D signaling 108 kBaud (144 kbit/s)Transmission rate 120 kBaud
Detection of remote feed voltage 35 V +5 V/−10 VCurrent consumption from the remote power feed < 5 mACurrent limiting for short-circuit simulation > 55 mATest capacitance at Uk0 2 μF
Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Indoor Signal Lines
Operating voltages −48 V/−60 V+5 V ±5%−5 V ±5%
Current consumption at+5 V−5 V
440 mA10 mA
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3.18 DSC104C Digital Signal Channel
3.18.1 OverviewThe DSC104C (Digital Signal Channel) line card will be employed in the FMX2R3 mul-tiplexer for the transmission of digital signals at a bit rate of 64 kbit/s. The unit incorpo-rates ten codirectional interfaces which conform to ITU-T Recommendation G.703. If asignal is being transmitted, signaling bits a, b, c, d are given the fixed values 1 1 0 1.
In the case of plesiochronous operation, frame slips occur at the codirectional input, andthese always comprise one octet. Nevertheless, octet synchronization is preserved.Only synchronous operation of the multiplexer’s 2 Mbit/s port (E1) is permissible.
The DSC104C has the following interfaces:• 10 codirectional 64 kbit/s interfaces conforming to ITU-T G.703.• Internal interfaces
The PCM highway and LC bus comprise the interface between the central unit and the DSC104C.
• Power supply.
3.18.2 Point-to-Multipoint ConnectionWhen operated in a CAS multiplexer, it is possible to configure point-to-multipoint con-nections for the DSC104C. In a point-to-multipoint connection, one master terminalequipment operates with several slave terminal equipment on a second multiplexer.Several data channels from different LCs occupy the same time slot. In the transmit di-rection the data bits are combined by an AND operation. A software protocol, appliedbetween the data terminals, must ensure that only one slave terminal device transmitsat any one time, while the others output continuous ones. The interfaces on a card whichparticipate in a point-to-multipoint connection must be either all even numbered or allodd numbered.
External interfaces Internal interfaces
1) Interfaces 2 to 10 take the same form
D2in_a
D2out_b
D2out_a
D2in_bIF11)
DSC104C
G.703
+5 V
PCM highway
LC bus
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3.18.3 Conference Modes of the Central Unit Drop/Insert, CUDIn a multipoint network, it is possible simultaneously to switch through and drop/insert64 kbit/s time slots.
In this case, the DSC104C line card can make use of all the conferencing modes of theCUD unit. A software protocol, applied between the data terminals, must ensure thatonly one item of terminal equipment transmits at any one time, while the others outputcontinuous ones.
3.18.4 Clock SynchronizationThree options are provided for synchronizing the interface:• The DTE synchronizes itself to its receive clock in the D2out signal. The transmit and
receive directions of the multiplexer operate synchronously.• The DTE and the multiplexer are synchronized by a central clock.• The multiplexer is synchronized with the clock from D2in.
3.18.5 Supervision and Diagnosis
Byte clock monitoring at D2in
If byte clock monitoring at D2in is switched on, then the data channel which is beingmonitored will trigger an alarm if its byte structure is lost. A loss of byte structure is as-sumed if three bytes are not recognized. An item of data terminal equipment can thus,in the event of a fault on the DSC - terminal equipment connection, trigger a remotealarm by switching off the byte clock. If byte monitoring is inactive, byte synchronizationwill be retained while there is a byte signal. Only the triggering of the alarm is blocked.
Byte clock at D2out in the event of LOS at D2in
If a loss of signal occurs at D2in, the data channel can report a remote alarm to the ter-minal equipment by switching off the byte clock at D2out.
Test Facilities
Two test loops are switchable within the DSC104C:• Loop E1in −> E1out, from the received to the transmitted PCM signal• Loop D2in −> D2out, from the data input to the data output.
These test loops are switched via LCT or OS.
The line card is provided with monitor sockets for the D2 interfaces.
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3.18.6 Controls
Fig. 3.72 Controls of the DSC104C
Subunit 1
15
16Subunit 2
Subunit 3
Subunit 4
Subunit 5
Subunit 6
Subunit 7
Subunit 8
Subunit 9
Subunit 1013
24
1 D2ina
3 D2outa2 D2inb
4 D2outb
Seen from back to connectors
(Subunit n)
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3.18.7 Connector Assignment
Fig. 3.73 Connector Assignment of the DSC104C
External connector 16
No. c b a
1 D2ina1 D2outa1
2 D2inb1 D2outb1
3 D2ina2 D2outa2
4 D2inb2 D2outb2
5
6
7 D2outa3
8 D2outb3
9 D2ina3
10 D2inb3
11 D2outa4
12 D2outb4
13 D2ina4 D2outa5
14 D2inb4 D2outb5
15
16
17 D2ina5
18 D2inb5
19 D2ina6 D2outa6
20 D2inb6 D2outb6
21
22
23 D2ina7 D2outa7
24 D2inb7 D2outb7
25 D2ina8 D2outa8
26 D2inb8 D2outb8
27
28
29 D2ina9 D2outa9
30 D2inb9 D2outb9
31 D2ina10 D2outa10
32 D2inb10 D2outb10
Internal connector 15
No. c b a
GND
2 GND GND
4 MUKZU
GND_S GND_S
6 PE
8
10
12
GND_S
14
GND GND GND
16 CLK_64K
GND GND GND
18 AD7 AD6 AD5
GND GND GND
20 AD4 AD3 AD2
GND GND GND
22 AD1 AD0 ALE
GND GND GND
24 NCS NWR NRD
GND GND GND
26 ADR3 SYN_E PCM_E
GND GND GND
28 ADR2 ADR1 ADR0
30 CLK_4M SYN_S PCM_S
32 P5V GND
c b a1
5
10
15
20
25
30
16
15c b a
10
20
30
2
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Signal Abbreviations
3.18.8 Supervision and Alarm SignalingTab. 3.67 shows alarm criteria and faults, together with the associated remedial ac-tions.
Byte clock monitoring at D2in
If byte clock monitoring at D2in is switched on, then the data channel which is beingmonitored will trigger an alarm if its byte structure is lost. A loss of byte structure is as-sumed if three bytes are not recognized. An item of data terminal equipment can thus,
AD0 to AD7 Address- and data bus linesADR0 to ADR3 Address lines to plug-in placesALE Address latch enableNCS Chip select NBICD2outa(no.) Data signal, a wire (channel -no.); outgoingD2outb(no.) Data signal, b wire (channel -no.); outgoingD2ina(no.) Data signal, a wire (channel -no.); incomingD2inb(no.) Data signal, b wire (channel -no.); incomingPCM-E PCM receive signalPCM-S PCM transmit signalNRD ReadT64K Clock 64 kHz for synchronization of the CUT2ME Receive clock; 2.048 MHzT4M Basic clock 4.096 MHzT8K-E Frame clock, external; receive directionT8K-S Frame clock, external; transmit directionNWR WritePE Write protection enable for EEPROM
Action Channel
alarm1)
AIS in direction Disconnect
byte clock at
D2out
SISA
alarmAlarm criterion/operator re-
sponse
E1out D2out
MUX alarm E1in2) × × 2)
Loss signal at D2in × × × 3) ×
Loss of byte clock at D2in × 3) × 3)
AIS at D2in × ×
Block channel × ×
Loop on MUX side × ×
External loop × ×
× Action is performed
1) Contact ZA(B) and red LED on central unit
2) Alarms LOS, AIS, SYN or BER-3 on central unit
3) Action can be canceled
Tab. 3.67 Table of Alarms for the DSC104C
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in the event of a fault on the DSC - terminal equipment connection, trigger a remotealarm by switching off the byte clock. If byte monitoring is inactive, byte synchronizationwill be retained while there is a byte signal. Only the triggering of the alarm is blocked.
Byte clock at D2out in the event of LOS at D2in
If a loss of signal occurs at D2in, the data channel can report a remote alarm to the ter-minal equipment by switching off the byte clock at D2out.
3.18.9 Technical Data
3.18.9.1 Modes of Operation
3.18.9.2 G.703 Interfaces
3.18.9.3 Foreign Potential Protection
3.18.9.4 Power Supply
Synchronous mode (duplex) point-to-point point-to-multipointconference
No. of 64 kbit/s interfaces per line card 10Bit rate 64 kbit/sTransmission mode codirectionalTransmission rate 256 kBaudPulse form as per ITU-T G.703, Fig. 5Nominal pulse width value 3.9 μsConnecting wires for each channel and direction one wire pair (symmetric)Impedance 120 Ω realInput level at 128 kHz 0 dB to −3 dBOutput level “L” 0 V ±0.1 VOutput level “H” ±1.0 V ±0.1 VImmunity to input jitter as per ITU-T G.823Immunity to noise signals as per ITU-T G.703
Para. 4.2.1.3
Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Indoor Signal Lines
Operating voltage +5 VCurrent consumption at +5 V (typical) 200 mA
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3.19 DSC6-n× 64C Digital Signal Channel
3.19.1 OverviewDigital Signal Channel DSC6-n× 64C with 6 interfaces in accordance with ITU-T Recom-mendation G.703 will be used as a digital leased-line connection for transmission of dig-ital signals with bit rates of n × 64 kbit/s in the multiplexer (n = 1 to 30/31).
There is the option of operating the six interfaces in Multiplexer FMX2R3.2 codirection-ally (n = 1 to 8) or with centralized clock (n = 1). Two of the interfaces can also beswitched over to contradirectional mode (n = 1 to 30/31).
If a signal is being transmitted, signaling bits a, b, c, d are given the fixed values 1 1 0 1.
The DSC6-n× 64C is equipped with the following interfaces:• 6 interfaces conforming to ITU-T G.703, either codirectional or with a centralized
clock, of which two may be contradirectional• Internal interfaces
The PCM highway and LC bus form the interface between the central unit and the DSC6-n× 64C.
• Power supply.
3.19.2 Codirectional InterfaceFor each direction, the codirectional interface uses a symmetrical wire pair, D2in_a/band D2out_a/b. Data, bit and byte clocks are transmitted together.
Three options are provided for synchronizing the interface:• The DTE synchronizes itself to its receive clock in the D2out signal. The transmit and
receive directions of the multiplexer operate synchronously.• The DTE and the multiplexer are synchronized by a centralized clock.• The multiplexer is synchronized with the clock from D2in.
1) Interfaces 2 to 6 take the same form
2) Only used, if one interface of the plug-in unit is used in the centralized clock mode
3) Only for contradirectional operation at interfaces 1 and 2
External interfaces Internal interfaces
D2in_a
T21_b3)T21_a3)
D2out_bD2out_aD2in_b
Tin_a2)
T22_a3)
T22_b3)
Tin_b2)G.703
DSC6-n× 64C
+5 V
PCM highway
LC busIF11)
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3.19.3 Centralized Clock InterfaceFor each direction, the centralized clock interface uses a symmetrical wire pair,D2in_a/b and D2out_a/b, for the data and, for each plug-in unit, a symmetrical wire pair,Tin_a/b, for the clock. The bit and byte clocks are transmitted together.
The DTE and the plug-in unit are synchronized by a 64-kHz centralized clock.
3.19.4 Contradirectional InterfaceFor each direction, the contradirectional interface uses a symmetrical wire pair,D2in_a/b and D2out_a/b, for the data and a symmetrical pair, T21_a/b and T22_a/b, forthe clock. The bit and byte clocks are transmitted together.
3.19.5 Point-to-Multipoint ConnectionIf the line card is in a CAS multiplexer, several interfaces may be associated with onetime slot. Two point-to-multipoint connections can be set up on one DSC6-n× 64C linecard, with the interfaces participating in each point-to-multipoint connection always be-ing either even numbered ones or odd numbered ones. If there are three or more par-ticipants, additional DSC6-n× 64C line cards are required. A software protocol, appliedbetween the data terminals, must ensure that only one slave terminal device transmitsat any one time, while the others output continuous ones.
Point-to-point connections are only possible in the FMX2R3 multiplexer.
3.19.6 Conference Modes of the Central Unit Drop/Insert, CUDIn a multipoint network, it is possible simultaneously to switch through and drop/insert64 kbit/s time slots.
The DSC6-n× 64C line card can make use of all the conferencing modes of the CUD unit(digital conference, point-to-multipoint, broadcast), see the system technical descriptionTED, SSD:FMX2R3. A software protocol, applied between the data terminals, must en-sure that only one slave terminal device transmits at any one time, while the others out-put continuous ones.
3.19.7 Test FacilitiesTwo test loops are switchable using the LCT or using the NCT within the DSC6-n× 64C:• Loop E1in → E1out, from the received to the transmitted PCM signal• Loop D2in → D2out, from the data input to the data output.
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3.19.8 Connector Assignment
Fig. 3.74 Connector Assignment of DSC6-nx64C
15
c b a1
5
10
15
20
25
30
16
External connector 16
No
Row
c (-A1) c (-C1)1) b a (-A1) a (-C1)1)
1 D2in_a1 D2out_a1 D2out_a1
2 D2in_b1 D2out_b1 D2out_b1
3 D2in_a1 D2in_a2 T21_a1 D2out_a2
4 D2in_b1 D2in_b2 T21_b1 D2out_b2
5
6
7 T22_a1 D2out_a3
8 T22_b1 D2out_b3
9 D2in_a3
10 D2in_b3
11 D2out_a2 D2out_a4
12 D2out_b2 D2out_b4
13 D2in_a2 D2in_a4 T21_a2 D2out_a5
14 D2in_b2 D2in_b4 T21_b2 D2out_b5
15
16
17 D2in_a5
18 D2in_b5
19 D2in_a3 D2in_a6 T22_a2 D2out_a6
20 D2in_b3 D2in_b6 T22_b2 D2out_b6
21
22
23 D2in_a4 Tin_a D2out_a3 T21_a1
24 D2in_b4 Tin_b D2out_b3 T21_b1
25 D2in_a5 D2out_a4 T22_a1
26 D2in_b5 D2out_b4 T22_b1
27
28
29 D2in_a6 D2out_a5 T21_a2
30 D2in_b6 D2out_b5 T21_b2
31 Tin_a D2out_a6 T22_a2
32 Tin_b D2out_b6 T22_b2
Internal connector 15
No
Row
c b a
1 GND
2 GND GND
3
4 MUKZU
5 GND_S GND_S
6 PE
7
8
9
10
11
12
13 GND_S
14
15 GND GND GND
16 CLK_64K
17 GND GND GND
18 AD7 AD6 AD5
19 GND GND GND
20 AD4 AD3 AD2
21 GND GND GND
22 AD1 AD0 ALE
23 GND GND GND
24 NCS NWR NRD
25 GND GND GND
26 ADR3 SYN_E PCM_E
27 GND GND GND
28 ADR2 ADR1 ADR0
29
30 CLK_4M SYN_S PCM_S
31
32 P5V GND
c b a
10
20
30
2
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Signal Abbreviations
3.19.9 Technical Data
3.19.9.1 Modes of Operation
3.19.9.2 G.703 Interfaces
AD0 to AD7 Address- and data bus bit 0 to 7ADR0 to ADR3 Plug-in place addressALE Address latch enableCLK_64K 64-kHz synchronous clock CLK_4M 4-MHz synchros clock PCM highwayCS Chip selectD2out_a1 to D2out_a6 Digital interfaces 1 to 6, a wire, transmit directionD2in_a1 to D2in_a6 Digital interfaces 1 to 6, a wire, receive directionD2out_b1 to D2out_b6 Digital interfaces 1 to 6, b wire, transmit directionD2in_b1 to D2in_b6 Digital interfaces 1 to 6, b wire, receive directionGND Internal groundMUKZU Negative secondary heating voltage −48 V/−60 VPCM_E PCM highway receive directionPCM_S PCM highway transmit directionPE Write protection enable for EEPROMPUKZU Positive secondary voltageRD/WR Read/WriteSYN_E Synchronous puls receive directionSYN_S Synchronous puls transmit directionTin_a/b Clock input centralized clock, a and b wireT21_a1/a2 Clock output contradirectional, a wire, transmit directionT21_b1/b2 Clock output contradirectional, b wire, transmit directionT22_a1/a2 Clock output contradirectional, a wire, receive directionT22_b1/b2 Clock output contradirectional, b wire, receive direction+5 V Positive secondary voltage
Synchronous mode (duplex) point-to-point, point-to-multi-point,conference
Input level 0 to −3 dBOutput level 0 V/1.0 VPulse shape (calculated in proportion to the bit rate) as defined by ITU-T G.703,
Figs. 5, 8, 9Immunity to input jitter(boundary values for 64 kbit/s) as defined by ITU-T G.823Immunity to noise signals as defined by ITU-T G.703,
Para. 4.2.1.3 and 4.2.3.3
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3.19.9.3 Codirectional Interface
3.19.9.4 Centralized Clock Interface
3.19.9.5 Contradirectional Interface
3.19.9.6 Foreign Potential Protection
3.19.9.7 Power Supply and Dissipation
Number per line card 6Bit rate n × 64 kbit/s, n = 1 to 8Balanced wire pairs in each direction 1 (data and clock)Electrical interface conditions as per ITU-T G.703, S. 4.2.1
Number per card 6Bit rate 64 kbit/sBalanced wire pairs in each direction 1 (data)Balanced wire pairs per card 1 (clock)Electrical interface conditions as defined by ITU-T G.703,
Para. 4.2.2, Variant a
Number per card 2Bit rate n × 64 kbit/s (n = 1 to 31)Balanced wire pairs in each direction 2 (data and clock)Electrical interface conditions as defined by ITU-T G.703,
Para. 4.2.3
Classification for foreign potential protection accordingEN 300 386 V1.3.2 (05/2003) Indoor Signal Lines
Operating voltage +5 VCurrent consumption at +5 V 350 mAPower dissipation (typical) 1.75 W
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3.20 CM64/2 Channel Multiplexer
3.20.1 OverviewThe CM64/2 line card is used for network branch to the 2-Mbit/s level in the FMX2R3.2multiplexer. The CM64/2 combines any number of time slots and the associated signal-ing information (CAS) of the E1 ports (2 Mbit/s) of a multiplexer with a 2-Mbit/s signal.The time slots of this signal can be allocated as required. AIS are assigned to the un-used time slots. The frame integrity of the time slots is retained but not the integrity ofthe signals.
In addition to the branch, the following functions are adjustable:• Duplex operation, broadcasting or data conference for each branched channel
The line card can make use of all the conferencing modes of the central unit drop/in-sert, CUD.
• Connection of the signals in time slot 16 (during operation with a signaling channel)The settings for CAS transmission are common for all channels of the F2 port.
• Synchronization of the receive signal, as defined by ITU-T G.732 or G.736 • Clock synchronization of the multiplexer via the incoming F2 signal• Fault or AIS detection and alarm handling• Transmission of up to four transparent data channels of 0.6 kbit/s each at a sampling
distortion of 15 % via the Sa bits (RS485 port).
A number of CM64/2’s can be used in a multiplexer. It is not possible to through-connectchannels between a number of CM64/2’s or between the CM64/2’s and other line cardsin the multiplexer.
External interfaces Internal interfaces
F2out
F2in
T64 CM64/2
2 Mbit/sG.703
+5 V
PCM highway
LC bus
Sa5...Sa8
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The CM64/2 is equipped with the following interfaces:• 2-Mbit/s interface conforming to ITU-T G.703 (F2)• Sa bit interfaces Sa5 to Sa8, conforming to EIA RS485• Internal interfaces
The PCM highway and the LC bus form the interface between the central unit and the CM64/2.
• Power supply.
3.20.2 2-Mbit/s InterfaceThe 2-Mbit/s interface conforms to ITU-T G.703. With separate switches for the transmitand receive directions, the interface can be adapted for use with balanced and unbal-anced cables.
3.20.3 Sa Bit InterfaceBits Sa5 to Sa8 of the service word can be assigned and evaluated via the asynchro-nous RS485 interface of the F2 interface. Four transparent transmission channels areprovided for this purpose, each with a transmission capacity of 0.6 kbit/s at 15 % signaldistortion (sampling at 4 kHz). If the F2in signal is disturbed, the outputs are switched tohigh impedance. Diodes protect the interface against overvoltage.
The Sa bits of the E1 port of the central unit and of the F2 port of the CM64/2 cannot beinternally linked.
Assignment of bits Sa5 to Sa8 of the service word to F2out (for each bit individually):• Internal 0 or 1• From the Sa bit interface• Injection of a 1 0 1 0 bit pattern sequence into Sa6.
Use of the RS485 interface (common for all Sa bit interfaces):• High impedance• From the service word to F2in• Switching between high impedance and F2in by Sa6.
Bits Sa5 and Sa6 are separately evaluated. With Sa5 = 0, the diagnostic message “Loopin the terminal equipment” is displayed, see operating manual UMN, UMN:OMN.
The Sa6 bit detects and displays the following pattern after series/parallel conversion:• 1 0 0 0 Signal failure or synchronous failure at the terminal equipment (S2Min)• 1 1 1 0 Signal failure or synchronous failure at the terminal equipment (UK2in)• 1 1 1 1 Terminal equipment receives AIS at UK2in.
3.20.4 Clock SynchronizationIn the same way as the transmit frame phase relationship, the transmit clock is deter-mined by the central unit. Clock recovery takes place on the receive side. If required,after subdivision to 64 kHz (T64) this clock can be used to synchronize the entire multi-plexer. The receive frame phase relationship is adjusted by means of an elastic store,whereby frame slips can occur without loss of synchronization.
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3.20.5 Supervision and Alarm Signaling
Possible faults and the remedial actions performed are shown in Tab. 3.68.
SISA
alarm
Message in the direction
of the central unit
Action in the
F2out direction
Action at the
central unit
Block
synchron.
clock
Sa-bit
interface
output
high
impedance
Event Source Channel
disturbed3)Channel
test mode4)D
bit
Dk-
bit
AIS AIS in
TS
AIS in
Bus TS1)AIS in SI
-> PCM1)
LOS F2in × × × × × × × ×
AIS F2in × × × × × × ×
SYN F2in × × × × × × × ×
BER-3 F2in × × × × × × × ×
BER-5/-6 F2in × (× ) (× ) (× ) (× ) (× ) (× ) (× )
D-bit F2in × (× ) × ×
AISK F2in × × ×
SYNK F2in × × × ×
DK-bit F2in × (× ) ×
LL operat. × × × ×
RL operat. × × × × ×
Block
channel
operat. × × ×
Not initial-
ized
internal × × × × ×
E1 alarm2) E1in × 2) × 2) × 2)
× Action is performed
(× ) Actions can be masked out together for this event
1) AIS is set within 2 ms.
2) One of the alarms LOS, AIS, SYN, BER-3, D-bit, AISK, SYNK, Dk-bit at E1in, reactions at F2out in the individual time slots
can be different
3) Contact ZA(A) or ZA(B) (switchable) and red LED on the central unit
4) Service alarm and red/green LEDs on the central unit
Tab. 3.68 Table of Alarms of the CM64/2
Alarm criteriaLOS Reports the failure of the received PCM signal if either 32 consecutive ze-
ros are detected or the input amplitude is < 0.25 V.AIS Alarm indication signal in the incoming PCM signal. Detection is in
accordance with ITU-T G.797 if less than 3 zeros occur in each of 2 consecutive double frames.
SYN Frame synchronization failure:- frame synchronization word incorrect 3 times in succession- if the CRC4 multiframe is active, failure of the CRC4 frame is also indi-cated.
BER-3 Error rate in the receive signal at least 10-3 (evaluation of the framesynchronization word in accordance with ITU-T G.732).
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Two test loops are switchable within the CM64/2:• Loop E1in → E1out, from the received to the transmitted PCM signal.• Loop F2in → F2out, from the input to the output of the line card.
These test loops are switched via operations system.
The line card is fitted with an isolating test socket for F2in and F2out, and a monitorsocket for the F2 interface.
3.20.6 Controls For control settings see Fig. 3.75 and Tab. 3.69. Line signals can be measured, seeFig. 3.76.
Fig. 3.75 Controls of the CM64/2
BER-5/6 Error rate in the receive signal- without CRC4:at least 10-5 (invalid frame synchronization words)- with CRC4:at least 10-6 (invalid CRC4 checksums).
AISK Alarm indication signal in time slot 16. Detected in accordance with ITU-T G.797 Para. 9.1.2.4.6 if less than 4 zeros occur in each of 2 consecutive multiframes in time slot 16.
SYNK Multiframe synchronous failure in time slot 16, as defined by ITU-T G.732, if two consecutive multiframe synchronous words are incorrect.
D-bit Bit 3 of the service word. It is “high” in the event of error in the frame synchronization of the remote multiplexer.
Dk-bit Bit 2 of the multiframe service word. It is “high” in the event of error in the signal processing of the remote multiplexer.
LL Loop F2out to F2inRL Loop F2in to F2out
1 2
3
1 2
322
21
20
40
41
10
11
10 Internal connector
11 External connector
20 Monitor jack
21 Break/test jack F2in
22 Break/test jack F2out
40 Impedance at F2in
41 Impedance at F2out
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Fig. 3.76 Connector Assignment of the Jacks 20, 21 and 22
Meaning Position Setting Value As delivered
status
Impedance at F2in 40 1-3
2-3
75 Ω120 Ω
×
Impedance at F2out 41 1-3
2-3
75 Ω120 Ω
×
1) As delivered status
Tab. 3.69 Controls of the CM64/2
1
3
5
2
4
6
Pin Assignment
(20)
Assignment
F2in (21)
Assignment
F2out (22)
1 Receive clock
(CMOS, 1 kΩ)
F2in; a wire F2out; a wire
2 Ground F2in; b wire F2out; b wire
3 Receive signal F2in
(CMOS, 1 kΩ)
F2in; a wire F2out; a wire
4 Ground F2in; b wire F2out; b wire
5, 6 F2out (reducer 1:10)
1 2
3 4
20 21/22
1, 2 Internal connection at 21 and 22
3, 4 External connection 21 and 22
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3.20.7 Connector Assignment
Fig. 3.77 Connector Assignment of the CM64/2
Code part:
representation of the missing
code elements
Leading contacts
External connector 11
No. c b a
1
2 F2inb F2ina
3
4 F2outb F2outa
5
6
7
8
9
10 yout1b yout1a
11
12 yout2a
13
14 yout2b yout3a
15
16
17
18 yout3b
19
20 yout4b yout4a
21
22
23
24 yin1b yin1a
25
26 yin2b yin2a
27
28
29
30 yin3b GND yin3a
31
32 yin4b yin4a
Internal connector 10
No. c b a
2 GND
4
6 PE
8
10
12
14
16 T64K
18 AD7 AD6 AD5
20 AD4 AD3 AD2
22 AD1 AD0 ALE
24 /CS /WR /RD
26 ADR3 T8KE PCME
28 ADR2 ADR1 ADR0
30 T4M T8KS PCMS
32 +5 V GND
c b a1
5
10
15
20
25
30
11
c b a
10
20
30
2
101
7
9
16
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Signal Abbreviations
3.20.8 Technical Data
3.20.8.1 2-Mbit/s InterfaceThe technical data of the F2 interface conform to ITU-T G.703/9 and ETS 300166.
+5 V Supply voltage
/CS Chip select
/RD Read
/WR Write
AD0...7 Bidirectional data lines 0 to 7
ADR0...3 Plug-in place address of plug-in units
ALE Address latch enable
F2outa/b 2-Mbit/s transmit signal
F2ina/b 2-Mbit/s receive signal
GND Ground
PCME PCM; receive direction
PCMS PCM; transmit direction
T4M Basic clock 4.096 MHz
T64K Clock 64 kHz
T8KE Frame clock 8 kHz; receive direction
T8KS Frame clock, 8 kHz; transmit direction
yout1 to 4 RS-485 interface, for evaluationof bits Sa 5 to Sa 8 in service word; transmit direction
yin1 to 4 RS-485 interface, for occupationof bits Sa 5 to Sa 8 in service word; receive direction
Bit rate 2048 kbit/s ±50 ppmCoding HDB3 as per ITU-T G.703,
Annex AInputs and outputs (selectable with dip-fix switch)
coaxialbalanced
75 Ω120 Ω
InputMaximum attenuation (at 1024 Hz) 6 dBImmunity to jitter as defined by G.823/3.1.1
≤ 1.2 × 10-5 Hz 36.9 Ul1.2 × 10-5 Hz to 20 Hz declining 20 dB/decade
36.9 Ul to 1.5 Ul20 Hz to 2.4 kHz 1.5 Ul2.4 kHz to 18 kHz declining 20 dB/decade
1.5 Ul to 0.2 Ul18 kHz to 100 kHz 0.2 Ul
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3.20.8.2 Sa Bit InterfaceThe Sa bit interface conforms to EIA RS485 and ITU-T V.11
3.20.8.3 Power Supply and Dissipation
Return loss as per ITU-T G.703/9.351 kHz to 102 kHz102 kHz to 2048 kHz2048 kHz to 3072 kHz
≥ 12 dB≥ 18 dB≥ 14 dB
Insensitivity to reflections, no errors when overlaid with a digital pseudo-random signal (215-1) with 18 dB signal interval as defined by G.703/9.3
OutputOutput signal symmetry as defined by ETS 300 166
at 1024 kHz ≥ 40 dB1024 kHz to 30 MHz ≥ 40 dB, declining with
20 dB/decadeReturn loss as defined by ETS 300 166
51.2 kHz to 102.4 kHz ≥ 6 dB102.4 kHz to 3072 kHz ≥ 8 dB
Multiplex signalFrame structure as per ITU-T G.704/2.3 and
G.704/5CRC4 multiframe (optional) as per ITU-T G.704/2.3.3Frame synchronization optional ITU-T G.704/2.3.3 or
ITU-T G.736Signal transmission (optional), if CASis also used at the E1 ports CAS as defined by
ITU-T G.704/5.1.3
Transmission rate at 15% sampling distortion30% sampling distortion
0.6 kbit/s1.2 kbit/s
Sampling frequency 4 kHzDifferential switching threshold < ±0.2 VCommon mode input voltage < ±6 VDifferential open-circuit voltage < ±5 VDifferential output voltage at 54 Ω load > ±1.5 VCommon mode output voltage < 3 VOutputs short-circuit protectedOvervoltage protection at all inputs and outputs,Pulse, 1.2/50 μs ±500 V
Operating voltage +5 VCurrent consumption at +5 V 150 mAPower dissipation (typical) 0.75 W
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3.21 CPF2 Digital Signal Channel
3.21.1 OverviewThe CPF2 is a universal digital signal channel unit for providing various local data inter-faces (V.24, V.35, V.36, X.21), for connecting to X.50 or X.51 data networks as well asfor data transmission via Ethernet.
The following interface modules are available:
There are 4 interfaces on the channel unit which can be implemented with four plug-inchannel interface modules (CIM-V24, CIM-V35, CIM-V36 or CIM-X.21). The function,electrical interface and speed of the 4 ports can be configured individually and indepen-dently of each other.
Up to 2 Ethernet interface modules CIM-nx64E can be equipped per CPF2. EachCIM-nx64E module provides 4 Ethernet ports The Ethernet module uses either the mod-ule slots 1 and 2 or 3 and 4 of the CPF2. The use of the Ethernet modules requires asoftware upgrade for the CPF2 and the ACI version 8.3.
Beside the unlimited use of CIM-nx64E module in combination with all other CPF2 mod-ules (CIM-V.24/-V.35/-V.36/-X.21) is possible via separate time slots. The number ofline cards CPF2 is only limited by the shelf or ONU equipment rules.
For the SNUS shelf the 4 Ethernet interfaces of one CIM-nx64E module are accessibleat one front panel connector. This connector also provides the RS232 interface and thesignals for the link status LEDs.
Different front panel connectors are intended to simplify matters wiring of the CPF2 datainterfaces with external data terminals, which can be connected to an external Main Dis-tribution Field (MDF 180 or MDF 210).
The CPF2 allows numerous different types of connection:• Local connection• Tidying up of connections (separation of different services)• Interface converters (also from CIM to TM and vice versa)• Point-to-point connections• Point-to multipoint connections• Loopbacks.
The data is processed according to frame criteria on the send and receive side.
A test generator and/or a test loop generator in accordance with recommendation V.54can be looped into the individual channels.
Module Interfaces Operating mode Bit rates
CIM-V.24 V.24 synchronous
asynchronous
0.6 to 64 kbit/s and 128 kbit/s
0.3 to 38.4 kbit/s and 115.2 kbit/s
CIM-V.35 V.35 synchronous
asynchronous
0.6 to 56 kbit/s, n × 64 kbit/s (n ≤ 30 with CAS/
31 without CAS)
0.3 to 38.4 kbit/s and 115.2 kbit/sCIM-V.36 V.35/RS530
CIM-X.21 X.21
CIM-nx64E 10/100Base-T n × 64 kbit/s (n ≤ 30 with CAS/31 without CAS)
Tab. 3.70 Interface Modules for Use on the CPF2
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The interfaces on the unit are as follows:• Subscriber interfaces according with interface and or transmission modules used:
V.24/V.35/V.36/X.21/10/100Base-T, see sections 3.21.10 to 3.21.13.• Internal interfaces:
PCM highway and LC bus form the interface between the central unit and the CPF2.• Power Supply.
3.21.2 Clock SynchronizationThe send clock, like the send frame phase position, will be determined by the centralunit CUD. On the receive side phase and frame adaptation is undertaken on the unit, inwhich case frame slips can occur without loss of synchronization. The receive clock ofa port can if necessary after division into 64 kHz (T64) be used for synchronization ofthe entire multiplexer.
3.21.3 Sub Bitrate MultiplexingThe V.110/ X.30 frames will be generated on the interface module. On the motherboardthe various subbit rate channels can be multiplexed into a 64-kbit/s time slot. The func-tionality of the non-blocked multipoint is used for this purpose which leads to logicalANDing of the various V.110/ X.30 frames.
This procedure corresponds to ITU-T I.460.
A maximum of two sub bitrate multiplexers can be created on a line card. Individualchannels of a multiport connection cannot be users of a sub bitrate multiplexer.
V.36/RS530/
Ta/TbRa/RbSa/SbCa/Cb
CPF2
External interfaces Internal interfaces
LC bus
Ia/Ib
Xa/Xb
...
Test loop Test
FR highway
Slots for interface and transmission modules
Cross-Connect
PCM highwaye.g.CIM-X.21
X.211)
V.35/
generator
1) The X.21 has been shown in detail by way of an example
V.24/
+5 V
−5 V
−48/−60V
10/100Base-T
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3.21.4 Point-to-Multipoint ConnectionsIt is possible to switch one or two point-to-multipoint connections on the CPF2. Whenthis is done one or more time slots function as the central channel. A maximum of fourusers can be connected as multipoint (port 1 to 4). With two point-to-multipoint connec-tions only two users are possible in each case.
Individual channels of a multiport connection cannot be users of a point-to-multipointconnection.
The return channel can be switched in two different modes:• Blocked mode
As the request for through connection of the return channel the control line and/or the data field can be evaluated. Evaluation is undertaken in real time by the CPF2 hardware and it is ensured that (dynamically) only one terminal will be through con-nected and the remaining terminals will be blocked. This is only possible within a line card.
• Non-blocked Mode:All return channels will be logically ANDed. This mode will be used with subbit rate multiplexing for example.
3.21.5 Channel ProtectionWith the CPF2 channel protection) at 64-kbit/s time slot level is possible.
This involves sending the data redundantly via various time slots. If a link fails, this willbe detected on the CPF2 (AIS detection or V.110/ X.30 supervision), signaled to the op-eration system and a switchover to the redundant time slots will be made.
MP user 1
MP user 2
MP user 3
MP user 4
CPF2
System busCentral channel
Ports 1 to 4
Broadcast to ports 1 to 4, in the return direction one of users 1 to 4 transmits depending on the data field and/or the control line
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3.21.6 Supervision and Diagnosis
3.21.6.1 AlarmsThe following alarms are supported on the CPF2 by the hardware:• AIST AIS receive (monitors aggregate bit rate from the module)• AIS RAIS time slot (monitors aggregate bit rate to the module)• LOC Phase hit• PSA Power supply alarm (central alarm: 5V from DCDC converter on
CPF2 failed or linear controller to supply 3.3 V to the module failed)
The occurrence of the alarms listed in Tab. 3.72 will be signalled to the higher-rankingoperation system and the alarms will also, as specified, be displayed on LEDs LED 1,LED 2, LED 3, LED 4.
The LEDs are assigned to the ports as follows:
3.21.6.2 MonitoringThe data will be tested in both directions for “All 1s”. It is possible to display individualbytes from the data stream on the OS.
LED LED 1 LED 2 LED 3 LED 4
Port Port 1 Port 2 Port 3 Port 4
Tab. 3.71 Assignment of the LEDs to the Ports of the Unit
Alarm LED indication
Hardware alarm fast flashing
Level failure permanently on
Sync failure permanently on
AIS Transmit flashing
AIS Receive flashing
Phase error flashing
Local test loop flashing
Local test loop applied from the remote end or
loopback request detected by the user (PSL)
flashing
All 0s (103/T = 0) flashing
DTE not ready flashing
Fault on inactive path with protection flashing
Clock failure permanently on
Tab. 3.72 LED Control when the Alarm Occurs
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3.21.6.3 BER Analyzer/Generator (Test Generator)To support the fault management functions of the operation system a test generator isimplemented on the CPF2. This test generator can be switched to any desired channelusing OS and a test text can be transmitted or received to allow long-term testing of theconnection. There are two fixed patterns (1100; 1010) available as the test text and twopseudo noise patterns (211-1; 215-1). The pseudo noise patterns correspond to ITU-TRecommendation O.152 or O.151. In addition the pattern can be inverted.
Statistical values in accordance with G.821 are made available.
3.21.6.4 Loopback RequestThe following loopbacks can be switched on the CPF2:• Local loop in time slot direction
This loop will be applied on the motherboard or on the module, depending on the module type
• Local Loop in the Port Direction
• Compatibility to FMX2R3.2 with loop switching:– automatic loop detection (only with X.21 and V.24 interfaces)– via OS
In addition the transparent V.54 test loop in the connected terminal can be activated onthe CPF2 and then the test generator can be used to run tests over the loop. A test loopgenerator and analyzer which complies with Recommendation V.54 is available on theCPF2 for this purpose. It will be used to apply or remove a remote test loop for this pro-cess with the slots to be tested in the desired direction:• Remote Loop in Port Direction
• Remote Loop in Time Slot Direction
CPF2SN
CPF2 SNor
CPF2 SN
CPF2
SNV.54request
V.54detected,acknowledged and applied
V.54detected,acknowledged and applied
CPF2
SNNet-
work
V.54request
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3.21.7 Controls
Fig. 3.78 Controls of the CPF2
The following modules can be plugged into the CPF2:– X.21 module (see Section 3.21.10)– V.24 module (see Section 3.21.11)– V.35 module (see Section 3.21.12)– V.36 module (see Section 3.21.13)
X15
X16
LED1LED2LED3LED4
11
20 20
11
20 20
11
20 20
11
20 20
F1
X11 X12
X21 X22
F1 Soldered-in fuse for +5V from the central card (1.5A)
F2 Soldered-in fuse for −48V/ −60V from the central card (1.5A)
LED1 LED (red) for Port 1(marked as H3 in the equipment plan)
LED2 LED (red) for Port 2(marked as H3 in the equipment plan)
LED3 LED (red) for Port 3(marked as H3 in the equipment plan)
LED4 LED (red) for Port 4(marked as H3 in the equipment plan)
X15 Internal connector
X16 External connector (office connector)
X11 Module connector for Port 1
X12 Module connector for Port 2
X21 Module connector for Port 3
X22 Module connector for Port 4
F2
A BA B
A B A B
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3.21.8 Connector Assignment
System connector X15
No. a b c
1 GND
2 GND PUKZU
3
4 MUKZU_1
5 GND_S GND_S
6 PWE
7
8
9
10
11
12
13 GND_S
14
15
16 CLK_64K
17 GND GND GND
18 AD5 AD6 AD7
19
20 AD2 AD3 AD4
21 GND GND GND
22 ALE AD0 AD1
23 GND GND GND
24 NRW NWR NCS
25 GND GND GND
26 PCM_E1 SYN_E1 ADR3
27 GND GND GND
28 ADR0 ADR1 ADR2
29 PCM_E2 SYN_E2
30 PCM_S1 SYN_S1 CLK_4M
31 GND PCM_S2
32 GND P5V
Tab. 3.73 Connector Assignment X15 of the CPF2
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External connector X16
External connector X16 is connected, as shown in Tab. 3.74, to the 4 module connec-tors (X11, X12, X21 and X22 A and B row Pin1 to Pin20 respectively). The assignmentof the individual signals can be found in the relevant module description.
The individual interface/transmission lines of the modules are transparent on the CPF2,i.e. they are through connected from the module connector to external connector X16without any outside effects.
X16 A B C
1 X11, A20 X21, A20
2 X11, B20 X21, B20
3 X11, A19 X21, A19
4 X11, B19 X21, B19
5 GND GND
6
7 X11, A18 X22, A13
8 X11, B18 X22, A14
9 X21, A18
10 X21, B18
11 X11, A17
12 X11, B17
13 X11, A13 X21, A17
14 X11, A14 X21, B17
15 X12, A13 X22, B6
16 X12, A14 X22, B10
17 X12, B6 X21, A13
18 X12, B10 X21, A14
19 X11, B6 X21, B6
20 X11, B10 X21, B10
21
22
23 X12, A18 X22, A18
24 X12, B18 X22, B18
25 X12, A20 X22, A20
26 X12, B20 X22, B20
27
28
29 X12, A19 X22, A19
30 X12, B19 X22, B19
31 X12, A17 X22, A17
32 X12, B17 X22, B17
Tab. 3.74 Terminal Assignment X16 (General) of the CPF2
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The following table shows the pinouts of external connector X16 of the CPF2 (exchange connector), if four X.21 modules are connected:
This corresponds to:– SN0_* = Port 1– SN1_* = Port 2– SN2_* = Port 3– SN3_* = Port 4
No. a b c
1 SN0_in_a SN2_in_a
2 SN0_in_b SN2_in_b
3 SN0_CNTL_a SN2_CNTL_a
4 SN0_CNTL_b SN2_CNTL_b
5 GND GND
6
7 SN0_out_a SN3_IND_a
8 SN0_out_b SN3_IND_b
9 SN2_out_a
10 SN2_out_b
11 SN0_XCLK_a
12 SN0_XCLK_b
13 SN0_IND_a SN2_XCLK_a
14 SN0_IND_b SN2_XCLK_b
15 SN1_IND_a SN3_SCLK_a
16 SN1_IND_b SN3_SCLK_b
17 SN1_SCLK_a SN2_IND_a
18 SN1_SCLK_b SN2_IND_b
19 SN0_SCLK_a SN2_SCLK_a
20 SN0_SCLK_b SN2_SCLK_b
21
22
23 SN1_out_a SN3_out_a
24 SN1_out_b SN3_out_b
25 SN1_in_a SN3_in_a
26 SN1_in_b SN3_in_b
27
28
29 SN1_CNTL_a SN3_CNTL_a
30 SN1_CNTL_b SN3_CNTL_b
31 SN1_XCLK_a SN3_XCLK_a
32 SN1_XCLK_b SN3_XCLK_b
Tab. 3.75 Connector Assignment X16 (for X.21-Modules) of the CPF2
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The following table shows the pinouts of external connector X16 of the CPF2 (exchange connector), if two Ethernet modules CIM-nx64E are connected:
This corresponds to:– M1/2_* = 1. module via module connectors 1 and 2– M3/4_* = 2. module via module connectors 3 and 4
No a b c
1 M1/2_Rx2_a M3/4_Rx2_a
2 M1/2_Rx2_b M3/4_Rx2_b
3 M1/2_Tx2_a M3/4_Tx2_a
4 M1/2_Tx2_b M3/4_Tx2_b
5
6
7 M1/2_Tx3_a M3/4_LED_1
8 M1/2_Tx3_b M3/4_LED_2
9 M3/4_Tx3_a
10 M3/4_Tx3_b
11 M1/2_Tx4_a
12 M1/2_Tx4_b
13 M1/2_Rx3_a M3/4_Tx4_a
14 M1/2_Rx3_b M3/4_Tx4_b
15 M1/2_LED_1 M3/4_LED_3
16 M1/2_LED_2 M3/4_LED_4
17 M1/2_LED_3 M3/4_Rx3_a
18 M1/2_LED_4 M3/4_Rx3_b
19 M1/2_Rx4_a M3/4_Rx4_a
20 M1/2_Rx4_b M3/4_Rx4_b
21
22
23 M1/2_Tx1_a M3/4_Tx1_a
24 M1/2_Tx1_b M3/4_Tx1_b
25 M1/2_Rx1_a M3/4_Rx1_a
26 M1/2_Rx1_b M3/4_Rx1_b
27
28
29 - -
30 M1/2_LED_GND M3/4_LED_GND
31 M1/2_RS232in M3/4_RS232in
32 M1/2_RS232out M3/4_RS232out
Tab. 3.76 CPF2 Connector X16 (with CIM-nx64E Modules)
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Signal Abbreviations
AD0 to AD7 Address bus bits 0 to 7ADR0 to ADR3 Slot address pinsALE “Address Latch Enable” system processor bus lineCLK_4M 4-MHz system clockCLK_64 64-kHz clock input for CUGND Internal chassis groundGND_S Chassis ground (shelf)MUKZU_1 −48 V negative secondary voltageNCS “Chip select” system processor bus lineNRD “Read” system processor bus lineNWR “Write” system processor bus lineP5V (VCC) Plus 5VPCM_E_1 PCM highway (4 Mbps) receiving end (from line card direction)PCM_E_2 PCM highway (4 Mbps) frame relay highway receiving end (from
line card direction)PCM_S_1 PCM highway (4 Mbps) transmission end (from line card direction)PCM_S_2 PCM highway (4 Mbps) frame relay highway transmission end
(from line card direction)PUKZU Chassis ground to MUKZUPWE Test position signalSYN_E_1 Frame synchronization signal for PCM_E1SYN_E_2 Frame synchronization signal for PCM_E2 frame relay highwaySYN_S Frame synchronization signal for PCM_S1 and PCM_S2M1/2_Rx1_a/bto M1/2_Rx4_a/b
Receive signal Ethernet port 1 from the 1. module, a- or b-wireto Ethernet port 4 from the 1. module, a- or b-wire
M3/4_Rx1_a/bto M3/4_Rx4_a/b
Receive signal Ethernet ports from the 2. module
M1/2_Tx1_a/bto M1/2_Tx4_a/b
Transmit signal Ethernet port 1 from the 1. module, a- or b-wireto Ethernet port 4 from the 1. module, a- or b-wire
M3/4_Tx1_a/bto M3/4_Tx4_a/b
Transmit signal Ethernet ports from the 2. module
M1/2_LED_1to M1/2_LED_4
LED signal to display at shelf SNUS, 1. module, Ethernet port 1 to 4
M3/4_LED_1to M3/4_LED_4
LED signal 2. module, Ethernet port 1 to 4
M1/2_LED_GND Ground for LED signals, 1. moduleM3/4_LED_GND Ground for LED signals, 2. module
M1/2_RS232in/out CLI signal, 1. module, incoming or outgoingM3/4_RS232in/out CLI signal, 2. module
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3.21.9 Overview CIM Interface ModulesThe interface modules are installed in line card CPF2 as plug-in modules. Line cardCPF2 is used in multiplexer FMX2R3.
The modules are used for direct connection of subscribers in accordance withITU-T V.24, V.35, V.36 or X.21 synchronous both with subrates and with n × 64 kbit/s(n = 1 to 30/31 in accordance with V.35, V,36, X.21 and n = 1, 2 in accordancewith V.24). In addition the modules support asynchronous subrates.
The mechanical design of the interface module corresponds to the OMIX Specification(Open Module Interface for XDSL, Version 1.2, 20.1.1998), Dimensions: 65 mm x 83.5 mm with a maximum component height of 12.5 mm. Up tofour interface modules are connected to the motherboard via modified OMIX interfaces(40-way female connectors).
In conjunction with the CPF2 basic module, for example, flexible subrate multiplexingconforming to ITU-T I.460/P2.1.2 with a bit rate ≤19.2 kbit/s is supported, i.e. a numberof sub-time slots can be nested on the basic module in one 64 kbit/s time slot.
With subrate multiplexing, any combination of subrate data signals is possible, wherebythe total number of bits required for each time slot is equal to or less than eight. Unusedbits are set to high level.
The following table shows the relationship between the required number of bits and thetransmission speed:
Linesignals
Clocksynchronization
RDO
TDI
Communicationinterface
OM
IX c
onne
ctor
FPGA
FlashEPROM
μP C161
Sendsignals
Receivesignals
Driv
erR
ecei
ver
DataAddress
ControlSRAM 32k x 8
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The software of the module and the hardware functions implemented in a freely-pro-grammable gate array (FPGA) are stored in a flash EPROM. If required, an update canbe downloaded from the central unit CUD.
Power is supplied to the modules, at +5 V and +3.3 V, by the central module. Power issupplied, at +3.3 V, to the programmable device (FPGA); power is supplied to all the oth-er devices at +5 V.
3.21.10 CIM-X.21 Interface Module
3.21.10.1 OverviewThe CIM-X.21 module realizes the following functions:• Adaptation the flow of data at the DCE subscriber interface - conforming to X.24,
electrical interfaces conforming to X.27 (identical to V.11) - to the OMIX interface to the basic module.
• In synchronous mode, the bit rates of the data from and to the subscriber can be n × 64 kbit/s, where n = 1 to 30/31 or < 64 kbit/s (0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/ 56 kbit/s). The data are transmitted in the receive direction (CIM -> subscriber) and transmit direction with the transmit line clock (S) of the CIM module or with the sub-scriber’s receive line clock (X).
• In asynchronous mode, speeds of 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s are supported.
• The bit rate of the data from and to the basic module is always 2048 kbit/s. • Support for Control and Indication.• If the subscriber uses a byte clock, in the receive direction (CIM -> basic module)
the data are adapted to the byte or frame structure of the basic module.• A data scrambler/data descrambler, conforming to V.38 or PCM, can be inserted
into the data path.• The following test loops can be switched on the CIM-X.21:
– Loop 2 (in the direction of the time slot)– Loop 3 (in the direction of the X.21 interface port)– compatibility with the FMX2 V2 for loop switching: automatic loop detection
• Control of the loops:– by TMN– detection of remote Loop 2, conforming to V.54– test loops conforming to X.150.
Number of bits 1 2 4 8 16
Intermediate rate 8 kbit/s 16 kbit/s 32 kbit/s 64 kbit/s 128 kbit/s
Transmission speed
0.3 to 4.8 kbit/s X
9.6 kbit/s X
19.2 kbit/s X
48; 56; 64 kbit/s X
115.2 kbit/s X
Tab. 3.77 Relationship between Number of Bits and Transmission Speed
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3.21.10.2 InterfacesThe OMIX interface is divided into a series of functional interfaces:• Line interface
12 line signals, conforming to X.24, which are routed to the subscriber via the basic module:
• Data interfaceDigital signals (data, timing, control, indication and - depending on the operating mode - byte clock)
• Control interfaceAdjustment of the module via a serial channel
• Hardware codingModule detection for serially-controlled modules, compatible with existing modules
• Power supply (5 V and 3.3 V)
3.21.10.3 Subrate MultiplexingOn the CIM-X.21 module, subbit rates (≤ 64 kbit/s) are compressed into one 64-kbit/stime slot in accordance with X.30, and 115.2 kbit/s into two 64-kbit/s time slots in accor-dance with a proprietary process.
3.21.10.4 Signaling
Overview
The list below provides an overview of the various setting options. This is followed by amore detailed description:
1. CONTROL:
2. DATA:
Transmit data Ta / Tb
Receive data Ra / Rb
Line clock (transmit) Sa / Sb
Control Ca / Cb
Indication Ia / Ib
Line clock (receive) Xa / Xb or (depending on the operating mode)
Byte / frame clock Ba / Bb
(1.1) Internal CIM status of Control: permanently set to ON
(1.2) Internal CIM status of Control = status of the Control interface line
(2.1) Data independent of the internal CIM status of Control
(2.2) Data dependent on the internal CIM status of Control
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3. inDICATION:
Detailed description of the types of alarm signaling• Data transfer without alarm signaling to the far end (3.1) or (3.2)
Signals T and R are transmitted transparently. Signals C and I are either inactive (3.1) (static status configurable; C set to ON and I set to ON or OFF) or C is switched after I (3.2).In this case, the CIM module assumes total control of the C/I line. The information about the configured states originates from the basic module.
• Data transfer with alarm signaling to the far end (inband in the X.30 frame) (3.3)This type of alarm signaling permits inband transmission of the ‘C to I’ alarm signal-ing information to the remote DCE. The information about the alarm signaling states of C and I is transmitted in the S-bit of the X.30 frame.It is also possible to preset the Control line (C) and the Indication line (I).Inband alarm signaling for C and I is also possible at transmission rates of up to56 kbit/s and for 115.2 kbit/s.The establishment of a point-to-point connection is dependent upon duplex local frame synchronization.
• Data transfer with alarm signaling to the far end (auxiliary channel) (3.4)For applications in which alarm signaling must be of short duration, the Control/ In-dication signal can be transmitted in an additional 64-kbit/s time slot (auxiliary chan-nel) of the PCM frame, at a transmission speed of 1.6 kbit/s with a signal distortion of 20 % (sampling at 8 kbit/s).The ‘High’ status of the auxiliary channel corresponds to an OFF status and the ‘Low’ status corresponds to an ON status.The CIM-X.21 modules sample the Control line (C) and always transmit the status of the line to time slot 0 of the OMIX connector. The basic module then cross-con-nects time slot 0 to the correct position. On the receive side, the arrangement is re-versed.
• Data transfer with alarm signaling to the far end (CAS) (3.5)The speed can be up to 50 bit/s, with 20 % signal distortion (sampling at 250 bit/s).Signals T, R, C and I are transmitted transparently. The C/I alarm signaling informa-tion is transmitted in signaling bit ‘a’ of the (CAS) signaling channel. The polarity of signaling bit ‘a’ can be inverted. In the non-inverted state, a-bit = 0 corresponds to the ON status of the alarm signaling information to be transmitted.The module supplies the CAS information and then relays it to the basic module.
In this case, the following options apply:– The alarm signaling information is transmitted in the signal of the first occupied
time slot (basic time slot). All the other signaling bits of the occupied time slots carry the idle signal (abcd = 1101).
(3.1) Indication is preset to ON or OFF
(3.2) Indication corresponds to the internal CIM status of Control of the local CIM module
(3.3) Indication corresponds to the internal CIM status of Control of the remote subscriber, with transmission via X.30
(3.4) Indication corresponds to the internal CIM status of Control of the remote subscriber, with transmission via a auxiliary channel
(3.5) Indication corresponds to the internal CIM status of the remote subscriber, with transmission via CAS
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– The alarm signaling information is transmitted in the signals from all the occupied time slots.
Transmission in the CAS is performed by the basic module.
If the signaling channel in the CAS multiplexer is activated and if data transfer with CASalarm signaling to the far end (3.5) is not selected, the value 1111 is assigned to the sig-nal.
Automatic loop switching to Loop 2 is performed in accordance with X.21 and not via thesignaling channel.
The sequence (priority) of the test loop request to the far end is:• V.54• Auxiliary channel• CAS
Signal C Internal CIM status
for Transmit
Internal CIM status
for Control
I R
Source: DTE CIM CIM CIM CIM
Status:
Port not activated X Duration 1 Duration 1 High imp. High imp.
Port status X Alst. T Alst. C Alst. I Alst. R
Data transfer X T* C i* R
Loop 3 X Alst.
Loop status
Alst. C C T
Loop 2 X r i Alst. I Alst.
Loop status
Error status
X.21 interface
XX Alst. T Alst. C I R
AIS detection
receive direction
XX T C Alst. I Alst. R
x Signal status: any
xx Any or as error criterion with C = OFF in LOS or DTE not ready
Alst. Configurable alarm states: Off for I and C or 0/1 for R and t
t* The transmit data which the port transmits to the far end in the transmission channel.
In protocol mode, data transmission is influenced by C.
r The receive data which the port in the alarm signaling channel receives from the far end
c The alarm signaling information which is transmitted by the port in the alarm signaling channel
i The alarm signaling information which is received by the port from the alarm signaling channel
(different from I = Indication
i* The outputs for i are dependent on the type of alarm signaling:
a) No alarm signaling / Loop C to I OFF: i = ON
b) No alarm signaling / Loop C to I ON: i = C
c) Alarm signaling in the signaling channel: i = a-bit on the receive side
d) Alarm signaling in the auxiliary channel: i = status of the auxiliary channel receive side
e) X.30 inband alarm signaling: i = status of the S-bit on the receive side
Tab. 3.78 Signal States at the X.21 Interface
Loop status: In the idle state, the following bit patterns can be transmitted to the far end:0000000, 11111111, 10101010, 01111110 or data
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3.21.10.5 Clock synchronizationIt is possible to operate with either a receive clock or with a byte/frame clock (receiveclock as input for the module, byte clock as output from the module). A slide switch isprovided for this purpose (see test and installation manual ITMN).
During operation with a byte/frame clock, receive and transmit data are timed with thecentral transmit line clock specified by the basic module. If transmit (S) and receive (X)clocks are available, receive and transmit operations can be timed independently andflexibly.
If required, the receive (X) clock can be used to synchronize the multiplexer (in n × 64-kbit/s mode only).
3.21.10.6 MonitoringAll the line signals are monitored for Duration 1/Duration 0/ON/OFF.
3.21.10.7 Alarms
Measure Chan-
nel
alarm
SISA
alarm
Configurable
alarms in direction
Display
Alarm criterion/operator action PCM for
T and C
DTE for
R and I
LED
CU*
MENU
CU*
MENU LED
MUX alarm Central fault X X X X X X
LOC Loss of clock X X(1) X X X(1) X X
AIS T = 1 X(1) X X X(1) X X
Permanent 0 T = 0 X(1) X X X(1) X X
LOS T = 1, C = OFF
Loss of signal
X(1) X X X(1) X X
LOF X.30 - loss of frame X(1) X X X(1) X X
DTE not ready T = 0, C = OFF X(1) X X X(1) X X
Channel dis-
able
Channel disable X X X X
HWA Hardware alarm X(1) X X X X(1) - X X
PNV Firmware file invalid X(1) X X X X(1) - X X
KP Channel in test state
(P3 via TNM or X.150)
X(2) X X X(2) X X
PSL Remote request for test loop 2 X(2) X X X(2) X X
1) switchable non-urgent/urgent channel alarm (default: non-urgent)2) loop alarm
Tab. 3.79 Alarm Table CPF2 with X.21 Module
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3.21.10.8 Test loops• On the CIM-X.21 module, Test Loop 2 can be switched to the direction of the time
slot:
• Compatibility with the FMX2 during loop switching:– automatic loop detection– per Network Management
• For the functionality of the test loops, conforming to V.54 (detect and execute, ac-knowledge and cancel), the CIM-X.21 module performs the tasks of the network ter-mination unit. The CIM-X.21 is always operated as a single port unit.
• Loop 3b from the data input to the data output of the interface is inserted on the basic module. The task of the CIM module is to detect Loop 3b (X.150 detection by the subscriber).
3.21.10.9 Configuration
CPF2
CIM
X.2
1 po
rt
Basic module X.21CIM
P2FLoop request
I = OFF, R = 1orI = OFF, R = 0orI = OFF, R = 0101
X.2
1 po
rt
CPF2
CIM
Clock modes:• The port is the clock master (i.e. using the clock centrally specified by the multi-
plexer). The port and the DTE only use clock line S and, as an option, clock line B or F.
• The port is the clock master. The port and the DTE only use clock line S in the receive direction and clock line X in the transmit direction.
• Selectable sampling edge of S in relation to T• Selectable sampling edge of X in relation to T• Type of clock mode: receive (X) clock only• Type of clock mode: receive clock only with DTE as master (n × 64 kbit/s)
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Transmission speeds:Synchronous mode:
• Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/s via X.30
• n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1 to 30/31)
Asynchronous mode: 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s
• Start/stop bit process:(character format)
Via X.30 with stop bit manipulation (asyn-chronous/synchronous conversion)115.2 kbit/s with proprietary stop process in 128 kbit/s 8 data bits / 7 data bitsParity: none, even or odd1 or 2 stop bits with/without parity
Oversampling: (the sampling rate must be set in each case)
• Oversampling: (sampling rate n × 64 kbit/s)
Subscriber speed0 to 12 kbit/s or0 to m × 64 kbit/s, where n ≥ 4 × m (synchro-nous), with n = 1 to 30/31, m follows ≤ 7.5
• Oversampling with subrates:(sampling rate 4.8, 9.6, 19.2, 38.4, 48 and 56 kbit/s) 0 to 12 kbit/s via X.30
Clock synchronization:• Master CIM: S/B or S/F; (B/F at n × 64 kbit/s only)• Selection of the sampling edge of S ↑ / ↓• Master CIM: X/S• Master DTE:X/S (at n × 64 kbit/s only)• Selection of the sampling edge of X ↑ / ↓
Operating modes:• Synchronous X.30• Synchronous n × 64 kbit/s• Asynchronous X.30 • Oversampling with X.30• Oversampling n × 64 kbit/s
Signaling:• CAS:
- OFF (not used)- in the signal from the basic time slot- in all signals- a-bit inverted
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• C to I signaling:- local only (local loop OFF/ON)- inband signaling, conforming to X.30 (< 64 kbit/s)- signaling in the signaling channel (n × 64 kbit/s)- signaling in the auxiliary channel (n × 64 kbit/s)
• Interface:- C permanently open (ON/switch)- I permanently open (ON/OFF/switch)- X.21 conditions for C and I
Scrambler/Descrambler:• · V.38/PCM (for n × 64 kbit/s only)
Maintenance:• Channel disable• Loops:
- TMN - loop to the DTE/loop 3- TMN - loop to the system/local loop 2- ≤ 38.4 kbit/s, conforming to V.38- n × 64 kbit/s, conforming to V.54- n × 64 kbit/s, FMX2 V2-compatible- Automatic loop 2/remote loop 2- Automatic loop 3/local loop to the DTE
• Optional disabling of the automatic loop circuit and the remote loop circuit• Monitor: channel states• Status request from the interface lines
Alarm criteria:• Urgent/non-urgent channel alarm• LOF/LOS/AIS/Continuous zeros/DTE not ready
Alarms:• LOF (X.30 loss of frame synchronization)• LOS (C = OFF; T =1)• AIS (T = 1)• Continuous zeros (T = 0)• DTE not ready (C = OFF; T=0)• LOC (loss of clock X)• HWA hardware alarm (e.g. switch setting does not correspond to the selected op-
erating mode)• PNV (firmware file not valid)
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3.21.10.10 Control elements and connectorsOn the X.21 module there is a switch (S1) which can be used to switch between byteclock (as shown in the diagram) and X clock.
There are no display elements on the X.21
Fig. 3.79 Controls of the X.21 Module
The 12 interface lines of the X.21 are routed via the motherboard to the external con-nector. The motherboard connection is made via 40-way module connector X11.
Name Signal Connector
X11
Ta Transmit a A20
Tb Transmit b B20
Ra Receive a A18
Rb Receive b B18
Ca Control a A19
Cb Control b B19
Ia Indication a A13
Ib Indication b A14
Sa Signal element timing a B 6
Sb Signal element timing b B10
Xa Transmit clock/byte clock/frame clock a A17
Xb Transmit clock/byte clock/frame clock b B17
Tab. 3.80 Interface Signals X.21 at the Module Connector
Module connector X11
S1
D12D13 D9
S1 switch setting:
= Byte clock (as-delivered condition)
= X clock
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3.21.11 CIM-V.24 Interface Module
3.21.11.1 Overview The CIM-V.24 module realizes the following functions:• Adaptation the flow of data at the DCE subscriber interface - conforming to V.24 - to
the OMIX interface to the basic module. • In synchronous mode, the bit rates of the data from and to the subscriber can be 0.6/
1.2/2.4/4.8/9.6/19.2/38.4/48/56/64/128 kbit/s. The data are transmitted in the re-ceive direction (CIM -> subscriber) with the receive line clock of the DCE (115) of the CIM module and, in the transmit direction, with the transmit line clock of the DTE (113) or with the transmit line clock of the DCE (114) of the CIM module.
• In asynchronous mode, speeds of 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s are supported. In this case, the microcontroller exchanges the data with the subscriber interface.
• The bit rate of the data from and to the basic module is always 2048 kbit/s. • Lines 105, 106, 107, 108.2, 109, 140, 141 are supported.• The following test loops can be switched on the CIM-V.24:
– Loop 2 (in the direction of the time slot)– Loop 3 (in the direction of the port of the V.24 interface)
Row A Dir Row Dir Row B
1 TFCL Transmitter Frame Clock
K-DAT Command Data 3
Start external Programming / Reset 4 RWCLK clock for serial communication
HW-Code CD2 ( Gnd ) 5 Signal element timing
digital control signal 6 O Signal element timing a
7 Power Supply 3.3V
Receive TDI 8 HW code CD1 ( Gnd )
Digital indication signal 9
Transmit RDO 10 O Signal element timing b
11
Indication data MDAT 12 RT1 X clock
Indication a O 13 RFCL Receiver Frame Clock
Indication b O 14 Mode external programming
VCC Power Supply 5V 15 HW code CD3 (Vcc)
GND Power Supply 0V 16 GND Power Supply 0V
X clock a/byte clock a/frame clock a I/O 17 I/O X clock a/byte clock a/frame clock b
Receive a O 18 O Receive b
Control a I 19 I Control b
Transmit a I 20 I Transmit b
I/O Input/output for the/from module
line signals
Tab. 3.81 Terminal Assignment of the X.21 Module Connector
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– compatibility with the FMX2V2 for loop switching: automatic loop detection• Control of the loops:
– by TMN– by line 140, 141
3.21.11.2 InterfacesThe OMIX interface is divided into a series of functional interfaces:• Line interface, 12 line signals, conforming to ITU-V.24, which are routed to the sub-
scriber via the basic module:
• Data interfaceDigital signals (data and timing and 105, 109)
• Control interfaceAdjustment of the module via a serial channel.
• Hardware codingModule detection for serially-controlled modules, compatible with existing modules.
• Power supply (5 V and 3.3 V)
3.21.11.3 Subrate multiplexingOn the CIM-V.24 module, subbit rates (≤ 64 kbit/s) are compressed into one 64-kbit/stime slot in accordance with X.30 and 115.2 kbit/s into two 64-kbit/s time slots in accor-dance with a proprietary process.
3.21.11.4 Signaling
Overview
The list below provides an overview of the various setting options. This is followed by amore detailed description:
1. 105:
Transmit data 103
Receive data 104
Transmit line clock from the DTE 113
Transmit line clock from the DCE 114
Receive line clock from the DCE 115
Transmit request 105
Ready to transmit 106
DCE ready for service 107
DTE ready for service 108.2
DCE ready to receive 109
Activate remote loop 140
Activate local loop 141
(1.1) Internal CIM status of 105: permanently set to ON
(1.2) Internal CIM status of 105 = status of interface line 105
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2. Data
3. 109:
4. 106:
5. 107:
Detailed description of the types of alarm signaling• Data transfer without alarm signaling to the far end: (3.1) or (3.2)
Data signals 103 and 104 are transmitted transparently. Signals 105 and 109 are ei-ther inactive (3.1) (static status configurable; 105 preset to ON and 109 preset to ON or OFF) or 105 is switched through after 109 (3.2)In this case, the CIM module assumes total control of the 105/109 line. The settings for the configured states originate from the basic module.
• Data transfer with alarm signaling to the far end (inband in the V.110 frame) (3.3):This type of alarm signaling permits inband transmission of the ‘105 to 109’ signaling information to the remote DCE. The information about the alarm signaling states of 105 and 109 is transmitted in the Sb-bit of the V.110 frame.It is also possible to preset lines 105 and 109.Inband alarm signaling for 105 and 109 is also possible at transmission rates of up to 56 kbit/s and for 115.2 kbit/s.The establishment of a point-to-point connection is dependent upon duplex local frame synchronization.
(2.1) Data independent of the internal CIM status of 105
(2.2) Data dependent on the internal CIM status of 105
(3.1) 109 is preset to ON or OFF
(3.2) 109 corresponds to the internal CIM status 105 of the local CIM module
(3.3) 109 corresponds to the internal CIM status of 105 of the remote subscriber, with transmission via ITU-T V.110
(3.4) 109 corresponds to the internal CIM status of 105 of the remote subscriber, with transmission via CAS
(4.1) 106 is preset to ON
(4.2) 106 is set to ON and, in the event of a system fault and test loop 2, it is set to OFF
(4.3) 106 is preset to OFF
(4.4) 106 follows the internal CIM status of interface line 105, with an adjustable delay (configurable 0 ms and 130 ms) and, in the event of a system fault and test loop 2, it is set to OFF
(5.1) 107 is preset to ON
(5.2) 107 is set to ON and, in the event of a system fault and test loop 2, it is set to OFF
(5.3) 107 is preset to OFF
(5.2) 107 corresponds to interface line 108.2 of the remote subscriber, with trans-mission via ITU-T V.110. If no V.110 frame is set, 107 follows the local inter-face line 108.2
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• Data transfer with alarm signaling to the far end (CAS). (3.4)The speed can be up to 50 bit/s, with 20 % signal distortion (sampling at 250 bit/s).Alarm signaling information for lines 105/109 is transmitted in signaling bit ‘a’ of the (CAS) signaling channel. The polarity of bit ‘a’ can be inverted. In the non-invertedstate, a-bit = 0 corresponds to the ON status of the alarm signaling information to be transmitted.The module supplies the CAS information and then relays it to the basic module.
In this case, the following options apply:– The alarm signaling information is transmitted in the signal of the first occupied
time slot (basic time slot). All the other signaling bits of the occupied timeslots car-ry the idle signal (abcd = 1101).
– The alarm signaling information is transmitted in the signals from all the occupied timeslots.
Transmission in the CAS is performed by the basic module.
If the signaling channel in the CAS multiplexer is activated and if data transfer with CASalarm signaling to the far end (3.5) is not selected, the value 1111 is assigned to the sig-nal.
Settings: 108.2/105/106/107/109: SwitchedTransparent mode: OFF
Signal: dtr
108.2
rts
105
cts*
106
txd
transmit data
rts* dsr
107
dcd
109
rxd
104
Output: DTE DTE CPF2 CPF2 CPF2 CPF2 CPF2 CPF2
Status:
Port not activated 1) X X High imp. Duration 1 Duration 1 High imp. High imp. High imp.
Port disabled 2) X X OFF Duration 1 OFF OFF OFF Duration 1
DTE not ready OFF X OFF Duration 1 OFF OFF OFF Duration 1
Ready to receive ON OFF OFF Duration 1 OFF ON dcd* rxd
Data transfer ON ON ON 103 ON ON dcd* rxd
Loop 3 ON X 105 Duration 1 OFF ON 105 103
Loop 2 ON X OFF rxd dcd OFF OFF Duration 1
Error status ON XX OFF Duration 1 OFF ON dcd* rxd
Legend see Tab. 3.83
Tab. 3.82 Signal States at the V interface, Part 1(not for V.110 protocol operation)
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Settings: 108.2/105/106/107/109: SwitchedTransparent mode: ON
Signal: dtr
108.2
rts
105
cts*
106
txd
transmit
data
rts* dsr
107
dcd
109
rxd
104
Output: DTE DTE CPF2 CPF2 CPF2 CPF2 CPF2 CPF2
Status:
Port not activated 1) X X High imp. Duration 1 Duration 1 High imp. High imp. High imp.
Port disabled 2) X X OFF Duration 1 OFF OFF OFF Duration 1
Data transfer X X 105* 103 105 108.2, dsr* dcd* rxd
Loop 3 X X 105 Duration 1 OFF 108.2 105 103
Loop 2 X X OFF rxd dcd OFF OFF Duration 1
Error status
V interface
X XX OFF Duration 1 OFF 108.2 dcd* rxd
AIS detection
receive direction
X X 105 103 105 ON OFF Duration 1
X Signal status: any
XX Any or as LOS error criterion: (105 = OFF and 103 = Duration 1)
txd The transmit data which the port transmits to the far end in the transmission channel
rxd The receive data which the port receives from the far end
rts The alarm signaling information which is transmitted by the port in the alarm signaling channel
dcd The alarm signaling information which is received by the port from the alarm signaling channel
rts* The output of alarm signaling information on the receive side during Loop 2 is only significant in the case of alarm signaling to
the far end (alarm signaling in the signaling channel, auxiliary channel or V.110 inband transmission). In each case, the alarm
signaling information on the receive side is looped.
dcd* The outputs for dcd are dependent on the type of alarm signaling:
a) No alarm signaling / Loop 105 to 109 OFF: dcd = ON
b) No alarm signaling / Loop 105 to 109 ON: dcd = 105 (RTS)
c) Alarm signaling in the signaling channel:d cd = a-bit on the receive side
d) Alarm signaling in the auxiliary channel: dcd = status of the auxiliary channel on the receive side
e) V.110 inband alarm signaling: dcd = status of the Sb-bit on the receive side
dsr* The status corresponds to the receive-side Sa-bit during V.110 inband alarm signaling
cts*106The ready-to-transmit signal is transmitted with a configurable delay.1) No connections are switched to this port2) The port is switched to inactive
Tab. 3.83 Signal States at the V Interface, Part 2 (V.110 protocol operation)
Loop status: In the idle state, the following bit patterns can be transmitted to the far end:0000000, 11111111, 10101010 or data
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3.21.11.5 Clock synchronizationIf required, the transmit line clock of the DTE 113 can be used to synchronize the multi-plexer if it is available as 64 kbit/s or 128 kbit/s.
3.21.11.6 MonitoringAll the line signals are monitored for duration 1/duration 0/ON/OFF.
3.21.11.7 Alarms
Measure Chan-
nel
alarm
SISA
alarm
Configurable
alarms in direction
Display
Alarm criterion/operator action PCM for
T and C
DTE for
R and I
LED
CU*
MENU
CU*
MENU LED
MUX alarm Central fault X X X X X X
LOC Loss of clock X X(1) X X X(1) X X
AIS 103 = 1 X(1) X X X(1) X X
Permanent 0 103 = 0 X(1) X X X(1) X X
LOS 103 = 1, 105 = OFF
Loss of signal
X(1) X X X(1) X X
LOF X.110 - loss of frame X(1) X X X(1) X X
DTE not ready 108.2 = OFF X(1) X X X(1) X X
Channel dis-
able
Channel disable X X X X
HWA Hardware alarm X(1) X X X X(1) - X X
PNV Firmware file invalid X(1) X X X X(1) - X X
KP Channel in test state
(P3 via TNM)
X(2) X X X(2) X X
PSL Remote request for test loop 2 X(2) X X X(2) X X
1) switchable non-urgent/urgent channel alarm (default: non-urgent)2) loop alarm
Tab. 3.84 Alarm Table CPF2 with V.24 Module
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3.21.11.8 Test loops• On the CIM-V.24 module, test loop 2 can be switched to the direction of the time slot
• Compatibility with the FMX2 V2 during loop switching:– automatic loop detection– loop request by Line 140– per Network Management
• For the functionality of the test loops, conforming to V.54 (detect and execute, acknowledge and cancel), the CIM-V.24 module performs the tasks of the network termination unit. The CIM-V.24 is always operated as a single port unit.
• Loop 3b from the data input to the data output of the interface is inserted on the basic module (loop requested by TMN or via 141)
CPF2
CIM
V.2
4 po
rt
Basis module V.24CIM
P2FLoop request
109 = OFF, 104= 1or109 = OFF, 104 = 0or109 = OFF, 104 = 0101
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3.21.11.9 Configuration
CPF2
CIM
V.24
Po
rt
Clock synchronizationMode 1:The port is the clock master. The port and the DTE use clock line 114 in the transmit direction and clock line 115 in the receive direction.Mode 2:The port is the clock master. The port and the DTE use clock line 115 in the receive direction and clock line 113 in the transmit direction.Mode 3:113 clock only
Transmission speeds:V.24 Synchronous: 64/128 kbit/sV.24 Synchronous via V.110: 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/sV.24 Asynchronous:
Start/stop bit process:(character format)
0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4 kbit/svia V.110 with stop bit manipulation (asyn-chronous/synchronous conversion)115.2 kbit/s with proprietary stop process in 128 kbit/s 8 data bits1 or 2 stop bits with/without parity
Oversampling at 64 kbit/s: 0 to 12 kbit/s Oversampling with subrates:(4.8/9.6/19.2/38.4/48 kbit/s)
0 to 12 kbit/s via V.110
Signaling:• Transparent/non-transparent (protocol mode)• CAS
- OFF (not used)- signal from basic time slot- signals in all time slots- a-bit inverted
• 105 to 109 signaling:- local only (local loop 105 to 109 OFF/ON)- inband signaling, conforming to V.110 (< 64 kbit/s)- signaling in the signaling channel n × 64 kbit/s (during oversampling)- configurable delay 105 to 106
• Interface:- 108.2 permanently open (ON/switch)- 105 permanently open (ON/switch)- 106, 107, 109 permanently open (ON/OFF/switch)- status = OFF for 106, 107, 109 switchable if ‘... is preset to ON’
Scrambler/Descrambler:
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3.21.11.10 Control elements and connectorsThere are no display elements on the V.24.
Fig. 3.80 Controls of the V.24 Module
• · V.38/PCM (for n × 64 kbit/s only)
Maintenance:• Channel disable• Loops:
- TMN - loop to the DTE/Loop 3- TMN - loop to the system/local Loop 2- compatible with the FMX2 V2 (at n × 64 kbit/s)- ≤ 38.4 kbit/s, conforming to V.38- n × 64 kbit/s per V.54
• Disabling of the automatic and remote loop circuit• Monitor: channel states• Status request from the interface lines
Alarms:• LOF (V.110 loss of frame synchronization)• LOS (105 = OFF; 103 = 1)• AIS (103 = 1)• Continuous zeros (103 = 0)• DTE not ready (108.2 = OFF)• LOC (loss of clock 113)• PNA• PNV
Alarm criteria:• Urgent/non-urgent channel alarm• LOC/LOF/LOS/AIS/Continuous zeros/DTE not ready
Module connector X16
D13 D9D12Flash
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The 12 interface lines of the V.24 are routed via the motherboard to the external con-nector. The motherboard connection is made via 40-way module connector X16:
103 Transmitted data A20
104 Received data A18
113 Transmitter signal element timing (DTE) A17
114 Transmitter signal element timing (DCE) B10
115 Receiver Signal Element Timing (DCE) B6
105 Request to Send A19
106 Ready for Sending B18
107 Data Set Ready A13
108.2 Data Terminal Ready B20
109 Data Channel Received Line Signal Detec-
tor
B19
140 Loopback/Maintenance Test A14
141 Local Loopback B17
Tab. 3.85 V.24 Interface Signals at the Module Connector
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3.21.12 CIM-V.35 Interface Module
3.21.12.1 Overview The CIM-V.35 module realizes the following functions:• Adaptation the flow of data at the DCE subscriber interface - conforming to V.35,
electrical interfaces conforming to V.28 or V.35 - to the OMIX interface to the basic module.
• In synchronous mode, the bit rates of the data from and to the subscriber can be n × 64 kbit/s, where n = 1 to 30/31 or < 64 kbit/s (0.6/1.2/2.4/4.8/9.6/19.2/38.4/ 48/56 kbit/s). The data are transmitted in the receive direction (CIM -> subscriber) with the receive line clock of the DCE (115) of the CIM module and, in the transmit direction, with the transmit line clock of the DTE (113) or with the transmit line clock of the DCE (114) of the CIM module.
• In asynchronous mode, speeds of 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s are supported. In this case, the microcontroller exchanges the data with the subscriber interface.
• The bit rate of the data from and to the basic module is always 2048 kbit/s.
Row A Dir Row Dir Row B
Control GBG 1 TFCL Transmitter Frame Clock GBG (OMIX)
2
K-DAT Command Data (OMIX) 3
Start external Programming (OMIX) 4 CCLK Command Indication Clock/ RWC (OMIX)
HW-Code CD2 (Gnd) (OMIX) 5 Signal element timing from the DTE
RMD Receive Management Data (C*)l 6 O 115
7 Optional: VCC Power Supply 3.3V
Receive TDI (OMIX) 8 HW code CD1 (Gnd) (OMIX)
TMD Transmit Management Data 9
Transmit RDO (OMIX) 10 O 114
11
Indication MDAT 12 RT1 X clock to GBG (OMIX)
107 O 13 RFCL (OMIX)
140 I 14 Mode external programming
VCC Power Supply 5V (OMIX) 15 HW code CD3 (Vcc) (OMIX)
GND Power Supply 0V (OMIX) 16 GND Power Supply 0V (OMIX)
113 I 17 I 141
104 O 18 O 106
105 I 19 O 109
103 I 20 I 108.2
I/O Input/output for the/from module
line signals
Tab. 3.86 Terminal Assignment of the V.24 Module Connector
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• Support for 105 and 109.• A data scrambler/data descrambler, conforming to V.38 or PCM, can be inserted
into the data path.• The following test loops can be switched on the CIM-V.35:
– Loop 2 (in the direction of the time slot)– Loop 3 (in the direction of the port of the V.35 interface)– compatibility with the FMX2 V2 for loop switching: automatic loop detection
• Control of the loops:– per TMN– detection of remote Loop 2, conforming to V.54
3.21.12.2 InterfacesThe OMIX interface is divided into a series of functional interfaces:• Line interface 12 line signals, conforming to ITU-V.28 or ITU-V.35, which are routed
to the subscriber via the basic module:
• Data interfaceDigital signals (data and timing and 105, 109)
• Control interfaceAdjustment of the module via a serial channel
• Hardware codingModule detection for serially-controlled modules, compatible with existing modules
• Power supply (5 V and 3.3 V)
3.21.12.3 Subrate MultiplexingOn the CIM-V.35 module, subbit rates (≤ 64 kbit/s) are compressed into one 64-kbit/stime slot in accordance with X.30 and 115.2 kbit/s into two 64-kbit/s time slots in accor-dance with a proprietary process.
Transmit data 103a / 103b conforming to ITU-V.35
Receive data 104a / 104b conforming to ITU-V.35
Receive line clock from the DTE 113a / 113b conforming to ITU-V.35
Transmit line clock from the DCE 114a / 114b conforming to ITU-V.35
Receive line clock from the DCE 115a / 115b conforming to ITU-V.35
Transmit request 105 conforming to ITU-V.28
DCE ready to receive 109 conforming to ITU-V.28
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3.21.12.4 Signaling
Overview
The list below provides an overview of the various setting options. This is followed by amore detailed description:
1. 105:
2. DATA:
3. 109:
Detailed description of the types of alarm signaling• Data transfer without alarm signaling to the far end: (3.1) or (3.2)
Signals 103 and 104 are transmitted transparently. Signals 105 and 109 are either inactive (3.1) (static status configurable; 105 preset to ON and 109 preset to ON or OFF) or 105 is switched after 109 (3.2).In this case, the CIM module assumes total control of the 105/109 line. Information about the configured states originates from the basic module.
• Data transfer with alarm signaling to the far end (inband in the V.110 frame) (3.3)This type of alarm signaling permits inband transmission of the ‘105 to 109’ alarm signaling information to the remote DCE. The information about the alarm signaling states of 105 and 109 is transmitted in the Sb-bit of the V.110 frame.It is also possible to permanently set the 105 and 109 lines.Inband alarm signaling for 105 and 109 is also possible at transmission rates of up to 56 kbit/s and for 115.2 kbit/s.The establishment of a point-to-point connection is dependent upon duplex local frame synchronization.
• Data transfer with alarm signaling to the far end (auxiliary channel) (3.4)For applications in which alarm signaling must be of short duration, the 105/109 sig-nal can be transmitted in an additional 64 kbit/s time slot (auxiliary channel) of the
(1.1) Internal CIM status of 105: permanently set to ON
(1.2) Internal CIM status of 105 = status of interface line 105
(2.1) Data independent of the internal CIM status of 105
(2.2) Data dependent on the internal CIM status of 105
(3.1) 109 is preset to ON or OFF
(3.2) 109 corresponds to the internal CIM status of 105 of the local CIM module
(3.3) 109 corresponds to the internal status of 105 of the remote subscriber, with transmission via ITU-T V.110
(3.4) 109 corresponds to the internal CIM status of 105 of the remote subscriber, with transmission via an auxiliary channel
(3.5) 109 corresponds to the internal CIM status of105 of the remote subscriber, with transmission via CAS
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PCM frame at a maximum transmission speed of 1.6 kbit/s, with a signal distortion of 20 % (sampling at 8 kbit/s).The ‘High’ status of the auxiliary channel corresponds to an OFF status and the ‘low’ status corresponds to an ON status.The CIM-V.35 modules sample the 105 line and always transmit the status of the line to time slot 0 of the OMIX connector. The basic module then cross-connects time slot 0 to the correct position. On the receive side, the arrangement is reversed.
• Data transfer with alarm signaling to the far end (CAS) (3.5)The speed can be up to 50 bit/s, with 20 % signal distortion (sampling at 250 bit/s).Alarm signaling information for lines 105/109 is transmitted in signaling bit ‘a’ of the (CAS) signaling channel. The polarity of signaling bit ‘a’ can be inverted. In the non-inverted state, a-bit = 0 corresponds to the ON status of the alarm signaling informa-tion to be transmitted.The module supplies the CAS information and then relays it to the basic module.
In this case, the following options apply:– The alarm signaling information is transmitted in the signal of the first occupied
time slot (basic time slot). All the other signaling bits of the occupied time slots carry the idle signal (abcd = 1101).
– The alarm signaling information is transmitted in the signals from all the occupied time slots.
Transmission in the CAS is performed by the basic module.
If the signaling channel in the CAS multiplexer is activated and if data transfer with CASalarm signaling to the far end (3.5) is not selected, the value 1111 is assigned to the sig-nal.
If the signaling channel is not in use, time slot 16 can be used for data transfer. In thiscase, a maximum transmission speed of 1984 kbit/s is possible.
The sequence (priority) of the test loop request to the far end is:• V.54• V.110• CAS
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Settings: 105/107/109: SwitchedTransparent mode: OFF
Signal rts
105
txd:
int. CIM status
Transmit data 103
int. CIM status
rts 105
109 rxd
104
Output: DTE CPF2 CPF2 CPF2 CPF2
Status:
Port not activated1) X Duration 1 Duration 1 High imp. High imp.
Port disabled 2) X Duration 1 OFF OFF Duration 1
DTE not ready X Duration 1 OFF OFF Duration 1
Ready to receive OFF Duration 1 OFF dcd* rxd
Data transfer ON 103 ON dcd* rxd
Loop 3 X Duration 1 OFF 105 103
Loop 2 X rxd dcd OFF Duration 1
Error status XX Duration 1 OFF dcd* rxd
AIS detection
receive direction
X 103 105 OFF Duration 1
Legend see Tab. 3.88
Tab. 3.87 Signal States at the V Interface, Part 1 (not for V.110 protocol operation)
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3.21.12.5 Clock synchronizationIf required, the transmit line clock of the DTE 113 can be used to synchronize the multi-plexer, if it is available as n × 64 kbit/s.
3.21.12.6 MonitoringAll the line signals are monitored for duration 1/duration 0/ON/OFF.
Settings: 105/107/109: SwitchedTransparent mode: OFF
Signal rts
105
txd:
int. CIM status
Transmit data 103
int. CIM status
rts 105
dcd
109
rxd
104
Output: DTE CPF2 CPF2 CPF2 CPF2
Status:
Port not activated1) X Duration 1 Duration 1 High imp. High imp.
Port disabled 2) X Duration 1 OFF OFF Duration 1
Data transfer X 103 105 dcd* rxd
Loop 3 X Duration 1 OFF 105 103
Loop 2 X rxd dcd OFF Duration 1
Error status
V interface
XX Duration 1 OFF dcd* rxd
AIS detection
receive direction
X 103 105 OFF Duration 1
x Signal status: any
xx Any or as LOS error criterion (105 = OFF and 103 = Duration 1)
txd The transmit data which the port transmits to the far end in the transmission channel
rxd The receive data which the port receives from the far end
dcd The alarm signaling information which is received by the port from the alarm signaling channel
rts The alarm signaling information which is transmitted by the port in the alarm signaling channel
dcd* The outputs for dcd are dependent on the type of alarm signaling:
a) No alarm signaling / Loop 105 to 109 OFF: dcd = ON
b) No alarm signaling / Loop 105 to 109 ON: dcd = 105 (rts)
c) Alarm signaling in the signaling channel: dcd = a-bit on the receive side
d) Alarm signaling in the auxiliary channel: dcd = status of the auxiliary channel on the receive side
e) V.110 inband alarm signaling: dcd = status of the S-bit on the receive side
1) No connections are switched to this port
2) Port is switched to inactive
Tab. 3.88 Signal States at the V Interface, Part 2 ( V.110 protocol operation)
Loop status: In the idle state, the following bit patterns can be transmitted to the far end:0000000, 11111111, 10101010, or data
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3.21.12.7 Alarms
3.21.12.8 Control elements and connectorsThere are no display elements on the V.35
Fig. 3.81 Controls of the V.35 Module
The 12 interface lines of the V.35 are routed via the motherboard to the external con-nector. The motherboard connection is made via 40-way module connector X16.
Measure Chan-
nel
alarm
SISA
alarm
Configurable
alarms in direction
Display
Alarm criterion/operator action PCM for
T and C
DTE for
R and I
LED
CUD
MENU
CUC
MENU LED
MUX alarm Central fault X X X X X X
LOC Loss of clock X X(1) X X X(1) X X
AIS 103 = 1 X(1) X X X(1) X X
Permanent 0 103 = 0 X(1) X X X(1) X X
LOS 103 = 1, 105 = OFF
Loss of signal
X(1) X X X(1) X X
LOF X.110 - loss of frame X(1) X X X(1) X X
DTE not ready 103 = 0, 105 = OFF X(1) X X X(1) X X
Channel disab Channel disable X X X X
HWA Hardware alarm X(1) X X X X(1) - X X
PNV Firmware file invalid X(1) X X X X(1) - X X
KP Channel in test state (P3 TNM) X(2) X X X(2) X X
PSL Remote request for test loop 2 X(2) X X X(2) X X
1) switchable non-urgent/urgent channel alarm (default: non-urgent
2) loop alarm
Tab. 3.89 Alarm Table CPF2 with V.35 Module
Module connector X16
D12Flash
D13 D9
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Name Signal Connector X16
103a Transmitted data a A20
103b Transmitted data b B20
104a Received data a A18
104b Received data b B18
105 Request to Send A19
109 Data Channel Received Line Signal Detector B19
114a Transmitter signal element timing (DCE a) A13
114b Transmitter signal element timing (DCE b) A14
115a Receiver Signal Element Timing (DCE a) B 6
115b Receiver Signal Element Timing (DCE b) B10
113a Transmitter signal element timing (DTE a) A17
113b Transmitter signal element timing (DTE b) B17
Tab. 3.90 V.35 Interface Signals at the Module Connector
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3.21.12.9 Test loops• On the CIM-V.35 module, Test Loop 2 can be switched in the direction of the time
slot:
• Compatibility with the FMX2 during loop switching:– automatic loop detection– per Network Management
• For the functionality of the test loops, conforming to V.54 (detect and execute, ac-knowledge and cancel), the CIM-V.35 module performs the tasks of the network ter-mination unit. The CIM-V.35 is always operated as a single port unit.
Row A Dir Row Dir Row B
1 TFCL Transmitter Frame Clock
2
K-DAT Command Data 3
Start external Programming / Reset 4 RWCLK clock for serial communication
HW-Code CD2 ( Gnd ) 5 Signal element timing
digital control signal 6 O 115a
7 Power Supply 3.3V
Receive TDI 8 HW code CD1 ( Gnd )
Digital indication signal 9
Transmit RDO 10 O 115b
11
Indication data MDAT 12 RT1 X clock
114a O 13 RFCL Receiver Frame Clock
114b O 14 Mode external programming
VCC Power Supply 5V 15 HW code CD3 (Vcc)
GND Power Supply 0V 16 GND Power Supply 0V
113a I/O 17 I/O 113b
104a O 18 O 104b
105 I 19 I 109b
103a I 20 I 103b
I/O Input/output for the/from module
line signals
Tab. 3.91 Terminal Assignment of the V.35 Module Connector
CPF2
CIM
V.3
5 po
rt
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• Loop 3b from the data input to the data output of the interface is inserted on the basic module (via TMN).
3.21.12.10 Configuration
Basic module V.35CIM
P2FLoop request
109 = OFF, 104= 1or109 = OFF, 104 = 0or109 = OFF, 104 = 0101
CPF2
CIM
V.3
5 po
rt
Transmission speeds:Synchronous mode:
• Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/svia V.110
• n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1 to 30/31)Asynchronous mode:
• Start/stop bit process:(character format)
0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4 kbit/svia V.110 with stop bit manipulation(asynchronous/synchronous conversion)115.2 kbit/s with proprietary process in128 kbit/s 8 data bits1 or 2 stop bits with/without parity
Oversampling:(The sampling rate must be set in each case; signal distortion is dependent on the sampling rate.)
• OversamplingSampling rate: n × 64 kbit/s Subscriber speed
0 to 12 kbit/s (n = 1) or0 to m × 64 kbit/s where n ≥ 4 × m (synchro-nous),with n = 1 to 30/31 m follows ≤ 7.5
• Oversampling with subrates:(4.8/9.6/19.2/38.4/48/56 kbit/s) 0 to 12 kbit/s via V.110
Signaling:• CAS:
- OFF (not used)- in the signal from the basic time slot- in all signals- a-bit inverted
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• 105 to 109 signaling:- local only (local loop OFF/ON)- inband signaling conforming to V.110 (< 64 kbit/s)- signaling in the signaling channel (n × 64 kbit/s)- signaling in the auxiliary channel (n × 64 kbit/s)
• Interface:- 105 permanently open (ON/switch)- 109 permanently open (ON/OFF/switch)- V.35 conditions for 105 and 109
Scrambler/descrambler:• ·V.38/PCM (for n × 64 kbit/s only)
Maintenance:• Channel disable
Loops:- TMN - loop to the DTE/Loop 3- TMN - loop to the system/Local Loop 2- ≤38.4 kbit/s, conforming to V.38- n × 64 kbit/s, conforming to V.54- n × 64 kbit/s, FMX2 V2-compatible
• Optional disabling of the remote loop circuit• Monitor: channel states• Status request from the interface lines
Alarms:• LOF (V.110 loss of frame synchronization)• LOS (105 = OFF; 103 = 1)• AIS (103 = 1)• Continuous zeros (103 = 0)• DTE not ready (103 = OFF; 105 = 0)• LOC (loss of clock 113)• HWA (hardware alarm) • PNV (firmware file not valid)
Alarm criteria:• Urgent/non-urgent channel alarm• LOC/LOF/LOS/AIS/Continuous zeros/DTE not ready
Clock synchronization:• Master CPF2: 114, 115• Selection of the sampling edge of 114↑ / ↓• Master CPF2: 113, 115• Master DTE: 113, 115 (at n × 64 kbit/s only)• Optional selection of the sampling edge for either 113 or 103• Type of clock mode: 113 clock only • Type of clock mode: 113 clock only with DTE as master (n × 64 kbit/s)
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3.21.13 CIM-V.36 Interface Module
3.21.13.1 Overview The CIM-V.36 module realizes the following functions:• Adaptation the flow of data at the DCE subscriber interface - conforming to V.36/
RS530, electrical interfaces conforming to V.11 or V.10, at the OMIX interface to the basic module.
• In synchronous mode, the bit rates of the data from and to the subscriber can be n × 64 kbit/s, where n = 1 to 30/31 or < 64 kbit/s (0.6/1.2/2.4/4.8/9.6/19.2/38.4/ 48/56 kbit/s). The data are transmitted in the receive direction (CIM -> subscriber) with the receive line clock of the DCE (115) of the CIM module and, in the transmit direction, with the transmit line clock of the DTE (113) or with the transmit line clock of the DCE (114) of the CIM module.
• In asynchronous mode, speeds of 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s are supported. In this case, the microcontroller exchanges the data with the subscriber interface.
• The bit rate of the data from and to the basic module is always 2048 kbit/s. • Support for 105 and 109.• A data scrambler/data descrambler, conforming to V.38 or PCM, can be inserted
into the data path.• The following test loops can be switched on the CIM-V.36:
– Loop 2 (in the direction of the time slot)– Loop 3 (in the direction of the port of the V.36 interface)– compatibility with the FMX2V2 for loop switching: automatic loop detection
• Control of the loops:– per TMN– detection of remote Loop 2, conforming to V.54
3.21.13.2 InterfacesThis OMIX interface is divided into a series of functional interfaces:• Line interface, 12 line signals, conforming to ITU-V.11 or ITU-V.10, which are routed
to the subscriber via the basic module:
• Data interfaceDigital signals (data and timing and 105, 109)
• Control interfaceAdjustment of the module via a serial channel
• Hardware codingModule detection for serially-controlled modules, compatible with existing modules
• Power supply (5 V and 3.3 V)
Transmit data 103a / 103b conforming to ITU-V.11
Receive data 104a / 104b conforming to ITU-V.11
Transmit line clock from the DTE 113a / 113b conforming to ITU-V.11
Transmit line clock from the DCE 114a / 114b conforming to ITU-V.11
Receive line clock from the DCE 115a / 115b conforming to ITU-V.11
Transmit request 105 conforming to ITU-V.10
DCE ready to receive 109 conforming to ITU-V.10
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3.21.13.3 Subrate MultiplexingOn the CIM-V.36 module, subbit rates (≤ 64 kbit/s) are compressed into one 64-kbit/stime slot in accordance with X.30 and 115.2 kbit/s into two 64-kbit/s time slots in accor-dance with a proprietary process.
3.21.13.4 Signaling
Overview
The list below provides an overview of the various setting options. This is followed by amore detailed description:
1. 105:
2. DATA:
3. 109:
Detailed description of the types of alarm signaling• Data transfer without alarm signaling to the far end: (3.1) or (3.2)
Signals 103 and 104 are transmitted transparently. Signals 105 and 109 are either inactive (3.1) (static status configurable; 105 preset to ON and 109 preset to ON or OFF) or 105 is switched after 109 (3.2).In this case, the CIM module assumes total control of the 105/109 line. The informa-tion about the configured states originates from the basic module.
• Data transfer with alarm signaling to the far end (inband in the V.110 frame) (3.3)This type of signaling permits inband transmission of the ‘105 to 109’ alarm signaling information to the remote DCE. The information about the alarm signaling states of 105 and 109 is transmitted in the Sb-bit of the V.110 frame.It is also possible to preset the 105 and 109 lines.Inband alarm signaling for 105 and 109 is also possible at transmission rates of up to 56 kbit/s and for 115.2 kbit/s.The establishment of a point-to-point connection is dependent upon duplex local frame synchronization.
(1.1) Internal CIM status of 105: permanently set to ON
(1.2) Internal CIM status of 105 = status of interface line 105
(2.1) Data independent of the internal CIM status of 105
(2.2) Data dependent on the internal CIM status of 105
(3.1) 109 is preset to ON or OFF
(3.2) 109 corresponds to the internal CIM status of 105 of the local CIM module
(3.3) 109 corresponds to the internal CIM status of 105 of the remote subscriber, with transmission via ITU-T V.110
(3.4) 109 corresponds to the internal CM status of 105 of the remote subscriber, with transmission via an auxiliary channel
(3.5) 109 corresponds to the internal CIM status of 105 of the remote subscriber, with transmission via CAS
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• Data transfer with alarm signaling to the far end (auxiliary channel) (3.4)For applications in which alarm signaling must be of short duration, the 105/109 sig-nal can be transmitted in an additional 64 kbit/s time slot (auxiliary channel) of the PCM frame, at a maximum transmission speed of 1.6 kbit/s with a signal distortion of 20 % (sampling at 8 kbit/s).The ‘High’ status of the auxiliary channel corresponds to an OFF status and the ‘Low’ status corresponds to an ON status.The CIM-V.36 modules sample the 105 line and always transmit the status of the line to time slot 0 of the OMIX connector. The basic module then cross-connects time slot 0 to the correct position. On the receive side, the arrangement is reversed.
• Data transfer with alarm signaling to the far end (CAS) (3.5)The speed can be up to 50 bit/s, with 20 % signal distortion (sampling at 250 bit/s).Alarm signaling information for lines 105/109 is transmitted in signaling bit ‘a’ of the (CAS) signaling channel. The polarity of the signaling bits ‘a’ can be inverted. In the non-inverted state, a-bit = 0 corresponds to the ON state of the alarm signaling in-formation to be transmitted.The module supplies the CAS information and then relays it to the basic module.
In this case, the following options apply:– The alarm signaling information is transmitted in the first occupied time slot (basic
time slot). All the other signaling bits of the occupied time slots carry the idle signal (abcd = 1101).
– The alarm signaling information is transmitted in the signals from all the occupied time slots.
Transmission in the CAS is performed by the basic module.
If the signaling channel in the CAS multiplexer is activated and if data transfer with CASalarm signaling to the far end (3.5) is not selected, the value 1111 is assigned to the sig-nal.
If the signaling channel is not in use, time slot 16 can be used for data transfer. In thiscase, a maximum transmission speed of 1984 kbit/s is possible.
The sequence (priority) of the test loop request to the far end is:• V.54• V.110• CAS
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Settings: 105/109: SwitchedTransparent mode: OFF
Signal rts
105
txd:
int. CIM status
Transmit data 103
int. CIM status
rts 105
109 rxd
104
Output: DTE CPF2 CPF2 CPF2 CPF2
Status:
Port not activated1) X Duration 1 Duration 1 High imp. High imp.
Port disabled 2) X Duration 1 OFF OFF Duration 1
DTE not ready X Duration 1 OFF OFF Duration 1
Ready to receive OFF Duration 1 OFF dcd* rxd
Data transfer ON 103 ON dcd* rxd
Loop 3 X Duration 1 OFF 105 103
Loop 2 X rxd dcd OFF Duration 1
Error status XX Duration 1 OFF dcd* rxd
AIS detection
receive direction
X 103 105 OFF Duration 1
Legend see Tab. 3.93
Tab. 3.92 Signal States at the V Interface, Part 1 (not for V.110 protocol operation)
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3.21.13.5 Clock synchronizationIf required, the transmit line clock of DTE 113 can be used to synchronize the multiplex-er, if it is available as n × 64 kbit/s.
3.21.13.6 MonitoringAll the line signals are monitored for duration 1/duration 0/ON/OFF.
Settings: 105/109: SwitchedTransparent mode: OFF
Signal rts
105
txd:
int. CIM status
Transmit data 103
int. CIM status
rts 105
109 rxd
104
Output: DTE CPF2 CPF2 CPF2 CPF2
Status:
Port not activated 1) X Duration 1 Duration 1 High imp. High imp.
Port disabled 2) X Duration 1 OFF OFF Duration 1
Data transfer X 103 105 dcd* rxd
Loop 3 X Duration 1 OFF 105 103
Loop 2 X rxd dcd OFF Duration 1
Error status
V interface
XX Duration 1 OFF dcd* rxd
AIS detection
receive direction
X 103 105 OFF Duration 1
x Signal status: any
xx Any or as LOS error criterion (105 = OFF and 103 = Duration 1)
txd The transmit data which the port transmits to the far end in the transmission channel
rxd The receive data which the port receives from the far end
dcd The alarm signaling information which the port receives from the alarm signaling channel
rts The alarm signaling information which the port transmits in the alarm signaling channel
dcd* The outputs for dcd are dependent on the type of alarm signaling:
a) No alarm signaling / Loop 105 to 109 OFF: dcd = ON
b) No alarm signaling / Loop 105 to 109 ON: dcd = 105 (rts)
c) Alarm signaling in the signaling channel: dcd = a-bit on the receive side
d) Alarm signaling in the auxiliary channel: dcd = status of the auxiliary channel on the receive side
e) V.110 inband alarm signaling: dcd = status of the Sb-bit on the receive side
1) No connections are switched to this port
2) The port is switched to inactive
Tab. 3.93 Signal States at the V Interface, Part 2 (V.110 protocol operation)
Loop status: In the idle state, the following bit patterns can be transmitted to the far end:0000000, 11111111, 10101010 or data
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3.21.13.7 Alarms
3.21.13.8 Test loops• On the CIM-V.36 module, Test Loop 2 can be switched to the direction of the time
slot:
• Compatibility with the FMX2 during loop switching:– automatic loop detection– per Network Management
• For the functionality of the test loops, conforming to V.54 (detect and execute, ac-knowledge and cancel) the CIM-V.36 module performs the tasks of the network ter-mination unit. The CIM-V.36 is always operated as a single port unit
Measure Chan-
nel
alarm
SISA
alarm
Configurable
alarms in direction
Display
Alarm criterion/operator action PCM for
T and C
DTE for
R and I
LED
CU*
MENU
CU*
MENU LED
MUX alarm Central fault X X X X X X
LOC Loss of clock X X(1) X X X(1) X X
AIS 103 = 1 X(1) X X X(1) X X
Permanent 0 103 = 0 X(1) X X X(1) X X
LOS 103 = 1, 105 = OFF
Loss of signal
X(1) X X X(1) X X
LOF X.110 - loss of frame X(1) X X X(1) X X
DTE not ready 103 = 0, 105 = OFF X(1) X X X(1) X X
Channel disab Channel disable X X X X
HWA Hardware alarm X(1) X X X X(1) - X X
PNV Firmware file invalid X(1) X X X X(1) - X X
KP Channel in test state
(P3 via TNM)
X(2) X X X(2) X X
PSL Remote request for test loop 2 X(2) X X X(2) X X
1) switchable non-urgent/urgent channel alarm (default: non-urgent)
2) loop alarm
Tab. 3.94 Alarm Table CPF2 with V.36 Module
CPF
CIM
V.3
6
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• Loop 3b from the data input to the data output of the interface is inserted on the basic module (via TMN).
3.21.13.9 Configuration
Basic module V.36CIM
P2FLoop request
109 = OFF, 104= 1or109 = OFF, 104 = 0or109 = OFF, 104 = 0101
CPF
CIM
V.3
6 po
rt
Transmission speeds:Synchronous mode:
• Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/svia V.110
• n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1 to 30/31)Asynchronous mode:
Start/stop bit process:(character format)
0.3/0.6/1.2//2.4/4.8/9.6/19.2/38.4 kbit/s via V.110 with stop bit manipulation (asyn-chronous/synchronous conversion)115.2 kbit/s with proprietary stop process in 128 kbit/s 8 data bits1 or 2 stop bits with/without parity
Oversampling:(the sampling rate must be set in each case; signal distortion is dependent on the sampling rate)
• Oversampling at n × 64 kbit/s: Subscriber speed0 to 12 kbit/s or0 to m × 64 kbit/s where n ≥ 4 × m (synchro-nous)with n = 1 to 30/31, m follows ≤ 7.5
• Oversampling with subrates:(4.8/9.6/19.2/38.4/48/56 kbit/s) 0 to 12 kbit/s via V.110
Signaling:• Transparent/non-transparent (protocol mode)• CAS:
- OFF (not used)- in the signal from the basic time slot- in all signals- a-bit inverted
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• 105 to 109 signaling:- local only (local loop 105 to 109 OFF/ON)- inband signaling conforming to V.110 (< 64 kbit/s)- signaling in the signaling channel (n × 64 kbit/s)- signaling in the auxiliary channel (n × 64 kbit/s)
• Interface:- 105 permanently open (ON/switch)- 109 permanently open (ON/OFF/switch)
Scrambler/descrambler:• · V.38/PCM (for n × 64 kbit/s only)
Maintenance:• Channel disable• Loops:
- Optional disabling of the remote loop- TMN - loop to the DTE/Loop 3- TMN - loop to the system/Local Loop 2- ≤ 38.4 kbit/s, conforming to V.38- n × 64 kbit/s, conforming to V.54- n × 64 kbit/s, FMX2 V2-compatible
• Optional disabling of the remote loop circuit• Monitor: channel states• Status request from the interface lines
Alarms:• LOF (V.110 loss of frame synchronization)• LOS (105 = OFF; 103 = 1)• AIS (103 = 1)• Continuous zeros (103 = 0)• DTE not ready (103 = 0; 105 = OFF)• LOC (loss of clock 113)• PNA (hardware alarm)• PNV (invalid firmware file)
Alarm criteria:• Urgent/non-urgent channel alarm• LOC/LOF/LOS/AIS/Continuous zeros/DTE not ready
Clock synchronization:• Master CPF2: 114/115• Selection of the sampling edge of 114↑ / ↓• Master CPF2: 113/115• Master DTE: 113/115 (at n × 64 kbit/s only)• Optional selection of the sampling edge for either 113 or 103• Type of clock mode: 113 clock only • Type of clock mode: 113 clock only with DTE as master (n × 64 kbit/s)
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3.21.13.10 Control elements and connectorsThere are no display elements on the V.36
Fig. 3.82 Controls of the V.36 Module
The 12 interface lines of the V.36 are routed via the motherboard to the external con-nector. The motherboard connection is made via 40-way module connector X11.
Name Signal Connector X11
103a Transmitted data a A20
103b Transmitted data b B20
104a Received data a A18
104b Received data b B18
105 Request to Send A19
109 Data Channel Received Line Signal Detector B19
114a Transmitter signal element timing (DCE a) A13
114b Transmitter signal element timing (DCE b) A14
115a Receiver Signal Element Timing (DCE a) B 6
115b Receiver Signal Element Timing (DCE b) B10
113a Transmitter signal element timing (DTE a) A17
113b Transmitter signal element timing (DTE b) B17
Tab. 3.95 V.36 Interface Signals at the Module Connector
Module connector X11
D12Flash
D13 D9
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Row A Dir Row Dir Row B
1 TFCL Transmitter Frame Clock
2
K-DAT Command Data 3
Start external Programming / Reset 4 RWCLK clock for serial communication
HW-Code CD2 ( Gnd ) 5 Signal element timing
digital control signal 6 O 115a
7 Power Supply 3.3V
Receive TDI 8 HW code CD1 ( Gnd )
Digital indication signal 9
Transmit RDO 10 O 115b
11
Indication data MDAT 12 RT1 X clock
114a O 13 RFCL Receiver Frame Clock
114b O 14 Mode external programming
VCC Power Supply 5V 15 HW code CD3 (Vcc)
GND Power Supply 0V 16 GND Power Supply 0V
113a I/O 17 I/O 113b
104a O 18 O 104b
105 I 19 I 109b
103a I 20 I 103b
I/O Input/output for the/from module
line signals
Tab. 3.96 Terminal Assignment of the V.36 Module Connector
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3.21.14 Ethernet Module CIM-nx64E
3.21.14.1 OverviewThe functionality of the CIM-nx64E module is comparable to a multiport Ethernet switch.Only Ethernet frames between the both uplink ports to other FMX2R3.2 stations andeach local Ethernet port are forwarded.
The Ethernet interfaces belonging to the uplink ports are not direct accessible. TheEthernet traffic of that interfaces is mapped to TDM timeslots of the E1 link by the CPF2module. The available Ethernet bandwidth depends on the number of used TDM time-slots, 31 timeslots per E1 link are possible, equal to 1.984 Mbit/s bandwidth.
Since the boards CUD and CPF2 need not be changed and the Ethernet switch is locat-ed at the CPF2 submodule, there are some restrictions regarding the possible Ethernetconnections:• Ethernet traffic between two or more FMX2R3.2 stations is only possible, if the same
TDM time slots of the E1 link will be used.• Only the Ethernet data of one CPF2 board is mapped into n x 64 kbit/s timeslots of
an E1 link, the traffic of a second CPF2 board must be mapped into further n x 64 kbit/s timeslots.
• Ethernet traffic can not be switched between different CPF2 boards of the same multiplexer.
• A TDM conference must not be used to combine Ethernet traffic.• The direct connection to an E1 interface of a router is not supported.
The module is connected to the CPF2 via 2 OMIX connectors. The submodule uses twosubmodule slots, either 1 and 2 or 3 and 4 of the CPF2.
Fig. 3.83 Functional Diagram of CIM-nx64E
The L2 switch works as a usual configurable Ethernet switch with 7 ports. The ports 1 to4 use the internal physical ports. They are connected to the subscriber. Port 5 and 6 areconnected to the TDM converter. The adaptations of the bit rates from the switch to theTDM interfaces are done by the converter. A programmable double PLL on the module
CPF2
4 x 10/100Base-T
PLLs
RAM
Flash
ProductEthernet
Time slot assignment
TDM/Ethernet converter
dataLayer 2 switch Phy
MAC
Por
t 1
Por
t 2
Por
t 3
Por
t 4
Por
t 5
Por
t 6
Port 0
Ctr
l
Clo
ck
Clo
ck
OMIX interface
2 x 2 Mbit/s
Network interfacecontroller
Serial comm. interface
DC/DC5 V/3.3 V/1.5 V
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is used to derive the necessary clocks, which are used to operate both TDM directionswith different numbers of time slots. For inband connection the switch port 0 is used. AnEEPROM for product identification data is controlled via an I2C bus interface.
All modules combined deliver full function 10/100 Mbit/s Media Access Control.
The MAC address for the board is stored in the second half of the serial EEPROM, thatalso stores the product identification data.
The IP address is stored in the flash beside the loads.
3.21.14.2 Clock SynchronizationThe module gets a 2.048 MHz clock from the motherboard via connector 2 or 4. Thisclock is sent to the PLLs as input signals. The PLLs divide this frequency with there predivider by 32. The result is the frequency of 64 kHz, which is used for the comparison ofthe input with the feedback of the PLLs. The feedback dividers are programmable be-tween 1 and 32. The output frequencies of the PLLs are n times 64 kHz. They are usedby the TDM/Ethernet converter and the network interface controller.
For the internal data processing the TDM/Ethernet converter needs the number of bear-er channels. For that the TDM/Ethernet converter compares the frequencies from thePLLs with the 2.048 MHz. The result is the number of timeslots which have to be usedfor the data transfer. The data processing is done with the clock from the PLLs.
3.21.14.3 ConfigurationThe Ethernet module is configured with the ACI graphical user interface. In some cases,configuration via CLI (Command Line Interface) at the Ethernet adapter may be neces-sary, see “Release Notes” that are delivered with the software.
These functions are implemented in the ACI:• Time slot assignment• Speed setting• Firmware download and activation per module• Read and write user file per functional unit Flexnx64.
The Ethernet module can be used in the operation modes "terminal" and "drop insert"resulting from the assigned timeslots. In the "terminal" mode, only one functional unit isconnected. In the "drop insert" mode, both functional units are connected. All TDM con-nections apply to all 4 physical Ethernet ports of the module together.
Rules for time slot connections:• One functional unit is connected to only one E1 port, timeslots are always used in
ascending order• No conferences possible between E1 Port A, E1 Port B and internal system bus• All NE operation modes possible (terminal, drop-insert and 1+1 protection modes)• Both functional units can be connected to the same E1 port, but to different timeslots• No point-to-multipoint operation, no subrate operation, no multiple use of timeslots
between internal system bus and line card ports are possible.
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The nonvolatile memory on the Ethernet module stores:• Ethernet related configuration data,
without time slot assignment, TDM speed setting and user data• Inventory data• Two firmware files• Information about active firmware file.
Per physical Ethernet link, the module provides 4 independent messages with the stateson/off/toggling. For the 2 TDM links the module provides only the activity and state mes-sage:• Speed mode: 10Base-T/100 Base-T• Duplex mode/collision: half/full• Link activity• State: blocked/operational
3.21.14.4 Controls and ConnectorsThere are no display elements on the CIM-nx64E module.
Fig. 3.84 Controls Ethernet Module
iChanging the Ethernet module requires new configuration since data is not stored at the central unit CUD and not stored on the mother board CPF2.
Mod
ule
conn
ecto
r X
2
FlashD30
D12
0
Mod
ule
conn
ecto
r X
1
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The interface lines of the CIM-nx64E are routed via the motherboard to the external con-nector. The motherboard connection is made via 40-way module connector X16.
Row A Direction Pin Direction Row B
1
2
3
4
5
6 Rx4_a
7
TD2_I Transmit data 2 I 8
9
RD2_O Receive data 2 O 10 Rx4_b
11
12 O RT2_O Receive clock 2 (2.048 MHz)
Rx3_a 13 O RFCL2_O Receive frame synchr. pulse 2 (8 kHz)
Rx3_b 14
15
GND Ground 16 GND Ground
Tx4_a 17 Tx4_b
Tx3_a 18 Tx3_b
Tx2_a 19 Tx2_b
Rx2_a 20 Rx2_b
I/O Input/ Output from the module
Line signals
Tab. 3.97 CIM-nx64E Module Connector X1
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Front panel connectors are available for the Ethernet interfaces. The single interfacescan be connected via adapter cables, which are different depending on the shelf.
Fig. 3.85 Ethernet Adapter
Row A Direction Pin Direction Row B
MCL_O Management clock O 1 I TFCL_I Transmit frame synchron. pulse (8 kHz)
2
K-DAT Command Data I 3
PROG_I causes an FPGA reload I 4 I RWCLK Clock for serial communication
HW-Code CD2 (GND) 5 I TT_I Transmit clock (2.048 MHz)
RMD_O Receive management data O 6 O LED_3
7
TD1_I Transmit data 1 I 8 CD1
TMD_I Transmit management data I 9
RD1_O Receive data 1 O 10 O LED_4
11
Message data MDAT O 12 O RT1_O Receive clock 1 (2.048 MHz)
LED_1 13 O RFCL1_O Receive frame synchr. pulse 1 (8 kHz)
LED_2 14 I MODE_I FPGA programming or SW activity
VCC Power Supply 5 V 15 CD3
GND Ground 16 GND Ground
RS232_an 17 I/O RS232_ab
Tx1_a 18 O Tx1_b
19 I LED_GND
Rx1_a 20 I Rx1_b
I/O Input/ Output from the module
Line signals
Tab. 3.98 CIM-nx64E Module Connector X2
Eth. port 3
Eth. port 4
Eth. port 1
Eth. port 2
Eth. port 1 Eth. ports2, 3, 4
Adaptercable
Front view Rear view
CLI
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3.21.15 Technical Data CPF2
3.21.15.1 Data Interfaces
3.21.15.2 Power Supply
3.21.15.3 Environmental Conditions
3.21.15.4 Technical Data CIM-X.21 Interface Module
Number of interfaces 4 Interface types, equipping options X.21, V.24, V.35, V.36/
RS530Transmission speeds module-dependent
Input voltage −36 V to −72 VMax. power consumption at −48 V (no modules) 13 mA
Input voltage +5 VMax. power consumption (no modules) max. 100 mA
Max. power consumption of modulesInput voltage +5 V 170 mA per moduleInput voltage +3.3 V 80 mA per module
Operation Ε ΤΣ 3000191−3, χλασσ 3.1Ε(−25 °C to +55 °C outdoor)
EMV
EMC emission in residential areaEMC resistance in industrial area
EN60950EN61000ETS 300 386-1, Tab. 2ETS 300 386-2FTZ 1TR9EN55022-BEN50082-A
Operating modesSynchronous mode (duplex) point-to-point
point-to-multipoint (via CUD or CPF2)conference (central via CUD)
Transmission speedsSynchronous mode
Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/ 48/56 kbit/s via X.30
n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1 to 30/31)
Asynchronous modeStart/stop bit process (character format) 0.3/0.6/1.2/2.4/4.8/9.6/19.2/
38.4/115.2 kbit/s
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Oversamplingsampling rate n × 64 kbit/s 0 to 12 kbit/s or
0 to m × 64 kbit/s, with n ≥ 4 × m (synchronous), with n = 1 to 30/31,m ≤ 7.5
with subrates:(sampling rate 4.8/9.6/19.2/38.4/48/56 kbit/s) 0 to 12 kbit/s via X.30
X.21/V.11 interfaceElectrical properties conforming to ITU-T X.27 or RS422Line type balancedSignal assignment for Uab (logical)
'1' or OFF ≤ −0.3 V'0' or ON ≥ +0.3 V
Quiescent voltage (Uab) < 5 VOutput level for (Uab) at RL=100 Ω ≥ 2 VReceiver input resistance 100 ΩPermissible timing tolerance of the receive clock during synchronization by DTE ±50 ppmRecommended line length for 100 Ω terminating resistor and with receive clock in use at:
64 kbit/s ≤ 1000 m1024 kbit/s ≤ 100 m2048 kbit/s ≤ 50 m
Cable type for 2048 kbit/sSpecified shieldedRecommended S-09YS (St) CY 8 x 2 x 0.6
Supported interface lines G/T/R/S/C/I/X or B or FFront panel connector (recommended) via connecting cable to con-
nector per ISO 4903, 15-pinSurge voltage protectionMax. permissible interference voltage,conforming to ENV50142 for shielded cables ±1 kVESD resistance, conforming to IEC1000-4-2, Level 4:
Contact discharge 8 kVAir discharge 15 kV
Power supplySupply voltage +5 V ±5%
+3.3 V ±5%Power consumption at +5 VPower consumption at +3.3 V
typical 120 mA, max. 170 mA typical 10 mA, max. 35 mA
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3.21.15.5 Technical Data CIM-V.24 Interface Module
Operating conditionsPermissible ambient temperature
Indoor operationDuring transport and storage
0 °C to +45 °C−20 °C to +60 °C
Licenses/conformityCE License:EN60950 - SafetyEN55022-B (EMC radiation, residential applications)EN50082-2 (EMC resistance, industrial applications)ETSI 300 386-2Telekom 1TR9TBR1Conformity to ITU-T X.27
Operating modesSynchronous mode (duplex) point-to-point
point-to-multipoint (via CUD or CPF2)conference (central via CUD)
Transmission speedsSynchronous mode
Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/s via V.110
n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1, 2)Asynchronous mode
Start/stop bit process (character format) 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s
Oversamplingsampling rate 64 kbit/s 0 to 12 kbit/swith subrates:(sampling rate 4.8/9.6/19.2/38.4/48/56 kbit/s) 0 to 12 kbit/s via V.110
V.24 interfaceElectrical properties conforming to ITU-T V.28 or RS232CLine type unbalancedSignal assignment for Uab (logical)
'1' or OFF ≤ −0.3 V'0' or ON ≥ +0.3 V
Output level U 5 V to 15 VReceiver input resistance 3 kΩ to 7 kΩRecommended line length for 20 kbit/s ≤ 15 mCable type for 2048 kbit/s
Specified shieldedRecommended S-09YS (St) CY 2 x 2 x 0.6
Supported interface lines 103/104/105/106/107/108.2/109/113/114/115/140/141
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3.21.15.6 Technical Data CIM-V.35 Interface Module
Front panel connector (recommended) via connecting cable to connector per V.24: ISO2110,25-pin
Surge voltage protectionMax. permissible interference voltage,conforming to ENV50142 for shielded cables ±1 kVESD resistance, conforming to IEC1000-4-2, Level 4:
Contact discharge 8 kVAir discharge 15 kV
Power supplySupply voltage +5 V ±5%
+3.3 V ±5%Power consumption at +5 VPower consumption at +3.3 V
typical 120 mA, max. 170 mA typical 10 mA, max. 35 mA
Environmental conditionsPermissible ambient temperature
Indoor operationDuring transport and storage
0 °C to +45 °C−20 °C to +60 °C
Licenses/conformityCE License:EN60950 - SafetyEN55022-B (EMC radiation, residential applications)EN50082-2 (EMC resistance, industrial applications)ETSI 300 386-2Telekom 1TR9Conformity to ITU-T V.28
Operating modesSynchronous mode (duplex) point-to-point
point-to-multipoint (via CUD or CPF2)conference (central via CUD)
Transmission speedsSynchronous mode
Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/s via V.110
n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1 to 30/31)Asynchronous mode
Start/stop bit process (character format) 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s
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Oversamplingsampling rate n × 64 kbit/s 0 to 12 kbit/s or
0 to m × 64 kbit/s, with n ≥ 4 × m (synchronous), with n = 1 to 30/31,m ≤ 7.5
with subrates:(sampling rate 4.8/9.6/19.2/38.4/48/56 kbit/s) 0 to 12 kbit/s via V.110
V.35 interfaceElectrical properties conforming to ITU-T V.28 or RS422 for interface lines 105,109Line type unbalancedSignal assignment (logical)
'1' or OFF ≤ −0.3 V'0' or ON ≥ +0.3 V
Output level U 5 V to 15 VReceiver input resistance 3 kΩ to 7 kΩ
Electrical properties conforming to ITU-T V.35 for interface lines 103,104,113,114 and 115:Line type balancedSignal assignment for Uab (logical)
‘1’ or OFF −0.55 V ± 20%‘0’ or ON +0.55 V ± 20%
Cable type for 2048 kbit/sSpecified shieldedRecommended S-09YS (St) CY 8 x 2 x 0,6
S-09YS (St) CY 2 x 2 x 0.6Supported interface lines 102/103/104/105/109/113/
114/115Front panel connector (recommended) via connecting cable to con-
nector perISO 2593, 34-pinISO 4902, 37-pin
Surge voltage protectionMax. permissible interference voltage,conforming to ENV50142 for shielded cables ±1 kVESD resistance, conforming to IEC1000-4-2, Level 4:
Contact discharge 8 kVAir discharge 15 kV
Power supplySupply voltage +5 V ±5%
+3.3 V ±5%Power consumption at +5 VPower consumption at +3.3 V
typical 120 mA, max. 170 mA typical 10 mA, max. 35 mA
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3.21.15.7 Technical Data CIM-V.36 Interface Module
Environmental conditionsPermissible ambient temperature
Indoor operationDuring transport and storage
0 °C to +45 °C−20 °C to +60 °C
Licenses/conformityCE License:EN60950 - SafetyEN55022-B (EMC radiation, residential applications)EN50082-2 (EMC resistance, industrial applications)ETSI 300 386-2Telekom 1TR9TBR-1Conformity to ITU-T V.35
Operating modesSynchronous mode (duplex) point-to-point
point-to-multipoint (via CUD or CPF2)conference (central via CUD)
Transmission speedsSynchronous mode
Subbit rate mode 0.6/1.2/2.4/4.8/9.6/19.2/38.4/48/56 kbit/s via V.110
n × 64 kbit/s multiplexer n × 64 kbit/s (n = 1 to 30/31)Asynchronous mode
Start/stop bit process (character format) 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/115.2 kbit/s
Oversamplingsampling rate n × 64 kbit/s 0 to 12 kbit/s or
0 to m × 64 kbit/s, with n ≥ 4 × m (synchronous), with n = 1 to 30/31,m ≤ 7.5
with subrates:(sampling rate 4.8/9.6/19.2/38.4/48/56 kbit/s) 0 to 12 kbit/s via V.110
V.36/RS530 interfaceElectrical properties conforming to ITU-T V.11 (X.27,RS422) for interface lines103, 104, 113, 114 and 115Line type balancedSignal assignment (logical)
'1' or OFF ≤ −0.3 V'0' or ON ≥ +0.3 V
Quiescent voltage (Uab) < 5 VOutput level (Uab) at RL = 100 Ω > 2 V
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Receiver input resistance 100 kΩ (0.25 W)
Electrical properties conforming to ITU-T V.10 for interface lines 105.109:Line type unbalancedSignal assignment for Uab (logical)
‘1’ or OFF ≤ −0.3 V‘0’ or ON ≥ +0.3 V
Quiescent voltage (U) 4 V to 6 VOutput level (U) at RL = 450 Ω ≥ 3.6 VReceiver input resistance high impedanceCable type for 2048 kbit/s
Specified shieldedRecommended S-09YS (St) CY 8 x 2 x 0.6
Supported interface lines 102/102A/102B/103/104/105/109/113/114/115
Front panel connector (recommended) via connecting cable to con-nector per V.36: ISO 4902, 37-pinRS530: ISO 2110, 25-pin
Surge voltage protectionMax. permissible interference voltage,conforming to ENV50142 for shielded cables ±1 kVESD resistance, conforming to IEC1000-4-2, Level 4:
Contact discharge 8 kVAir discharge 15 kV
Power supplySupply voltage +5 V ±5%
+3.3 V ±5%Power consumption at +5 VPower consumption at +3.3 V
typical 120 mA, max. 170 mA typical 10 mA, max. 35 mA
Environmental conditionsPermissible ambient temperature
Indoor operationDuring transport and storage
0 °C to +45 °C−20 °C to +60 °C
Licenses/conformityCE License:EN60950 - SafetyEN55022-B (EMC radiation, residential applications)EN50082-2 (EMC resistance, industrial applications)ETSI 300 386-2Telekom 1TR9TBR-1Conformity to ITU-T V.36 (with the proviso that only 12 interface signals are supported)
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3.21.15.8 Technical Data Ethernet Module CIM-nx64E
10/100BaseT Ethernet interfaces per module 4Transmission speed (auto detect) 10 Mbit/s or 100 Mbit/sElectrical interface conditions acc. IEEE 802.3
CLI interface acc. RS232
Power supplySupply voltage +5 V ±5 %
Environmental conditionsPermissible ambient temperature
Indoor operationDuring transport and storage
0 °C to +45 °C−20 °C to +60 °C
Licenses/conformityCE License:EN60950 - SafetyEN55022-B (EMC radiation, residential applications)EN50082-2 (EMC resistance, industrial applications)ETSI 300 386-2Telekom 1TR9 TBR-1
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3.22 Supervision Unit, SUE
3.22.1 OverviewThe supervision unit, SUE, realizes control and monitoring functions in the SNUS,FMX2S and MXS19C shelves.
Fig. 3.86 Operation and Monitoring via the SUE’s QD2-Interface
The SUE performs the following functions:• Creating a virtual concentrator (SISA-V/LMX V2)
The SUE establishes an SISA-V/LMX V2 which manages the ASA32 network ele-ment as being continuously present in its polling list.
• Operating the NEs in the shelf via QD2 master interface• Protocol conversion of layer 7 according to SISA into a system-internal SVB protocol
protocol conversion• Duplicating the QD2 slave interface to provide additional system access• Establishing the T functionality of both QD2 slave interfaces to set up multipoint net-
work structures• Operation of a local F interface• Evaluating up to 8 external alarms.
If, among the network elements in a station, the SISA-V is the highest network elementin the OS hierarchy, then the SISA-V is designated as “Top of Station (TOS)”. A data-base is maintained with details of the network elements which comprise the station andabout the connections to other stations which are linked to the station addressed (in thedescending direction).
During its initialization phase, the SUE’s operating program carries out self-tests on theplug-in unit components and the interfaces. In the event of a fault, the SUE outputs faultsignals. In addition, card identification is carried out using static inputs.
The SUE has the following interfaces:• 2 × QD2 slave interfaces
– QD2 slave 1 with control line (SE) and transparent operating mode (T)– QD2 slave 2 with transparent operating mode (T)
• F interface,• 2 × QD2 master interfaces (QD2-M 2 in SNUS, FMX2S and MXS19C not used),• 8 × alarm inputs (A1+ to A8+ and negative reference potential A−),
QD2-M164 kbit/s QD2-S1
QD2-S2
F-SST
OS
LCT
SUE
NE QD2-S
QD2-M2
T
TCMXC
SMX1/4c
QD2-S QD2-S QD2-S
LTxFMX2R3
QD2-S
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• Rear panel coding (K0 to K4),• Switch in the rear panel of the shelf to set the SISA address (5 bits),• 6-pin switch for bus termination with 120 Ω per QD2 slave port and for the T ports,• 6-pin switch to set the operating mode of the QD2 slave port,• 2 × 8-pin switches to switch over the configuration of the QD2 interfaces either ac-
cording to RS232 or RS485• Power supply.
F Interface
The F interface is used to access the virtual concentrator on the plug-in unit, and its sub-ordinate network elements. The F interface can be access by a 9-pin plug connector onthe front of the unit. It conforms to ITU-T V.28.
QD2 Slave Interfaces
The QD2 slave interfaces are arranged as specified by EIA RS485. QD2 slaveinterface 1 is always used for the primary network access, while QD2 slave interface 2is used as a redundant network access. In addition, QD2 slave interface 1 has an SEcontrol line for connecting to a remote QD2 bus.
QD2 Master Interfaces
The QD2 master interfaces conform to EIA RS485. QD2 master interface 1 provides aserial bus system for connecting further network elements. QD2 master interface 2 canbe used as an extension to the serial bus system, e.g. for connecting to interfaces onthe system-internal SISA transport channels, which are not bus compatible.
ZA Interface
The ZA interface signals urgent alarms (A alarms) or service alarms to the centralservice observation equipment. The interface takes the form of a break contact, so thatif the operating power fails an alarm is output.
SUE
SlavePort 1
−48 V/−60 V
Internal interfaces
Rear panelcoding
QD2 master 1
External interfaces
F
ASA32
SISA-V
QD2 slave 1
MasterPortQD2 master 2
A1+ to A8+
Alarm inputs
Localoperation
and A−
Powersupply
To NEsin the shelf
SlavePort 2
QD2 slave 2
PrimaryTMN access
RedundantTMN access
T
TSE
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3.22.2 Control and MonitoringControl and monitoring by the SUE is effected by the OS through the QD2 slave inter-face, or by the LCT via the F interface. The QD2 master interfaces are preinitialized at64 kbit/s. For the F interface, a bit rate of 9.6 kbit/s is preset. There are 4-pin switches on the unit, which can be used to terminate the bus for the QD2slave interfaces. An additional switch (8-pin) is used to set the SISA address.
For local monitoring, one red and one green LED is fitted on the front of the SUE, and ayellow LED further back on the unit- see the following table.
3.22.3 Controls
Fig. 3.87 Controls of the SUE
LED (green) LED (red) LED
(yellow)1)Status
Off Off Off No operating voltage
On Off Off Fault-free operation
On Off On Fault-free operation, connection established to the next
higher hierarchical level in the OS
Off On Off SUE in a fault state or self-test
Off On On Fault state, connection is maintained
1) Only visible when the cover plate for the unit is removed
Tab. 3.99 Visual Signals Output by the SUE
S3
View from
front:S2
S1
10
11
greenred
yellow
ON
3 8
1
6
8
1ON
1ON
S4
6
1ON
F2 F112
142
X4
31
42 X5
D3
10 Internal connector
11 External connector
12 Connector for LCT (F-Inter-
face)
X4 Test jack
X5 Test jack
F1 Solder-in fuse for –48 V/–60 V
(2,5 A)
F2 Solder-in fuse for –48 V/–60 V
(2,5 A)
D3 Initial program loader
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Switch S1 and S2:
Switch S3:
Switch S4: T-Interface
Connector 12 (F Interface)
Switch S1 Switch S2
Slides 1 to 4 Slides 5 to 8 Slides 1 to 4 Slides 5 to 8 Function Setting
OFF1) ON1) Interface settings at master- port 1 RS485 interface
ON OFF Interface settings at master- port 1 RS232
OFF1) ON1) Interface settings at slave-Port 1 RS485 interface
ON OFF Interface settings at slave-Port 1 RS232
1) As delivered state
Slide Function Position Meaning
1 Interface termination for QD2 slave port 1 (transmit direction) OFF1)
ON
High-impedance
120 Ω
2 Interface termination for QD2 slave port 1 (receive direction) OFF1)
ON
High-impedance
120 Ω
3 Interface termination for QD2 slave port 2 (transmit direction) OFF1)
ON
High-impedance
120 Ω
4 Interface termination for QD2 slave port 2 (receive direction) OFF1)
ON
High-impedance
120 Ω
5 Interface termination for T-Port on slave 1 (transmit direction) OFF1)
ON
High-impedance
120 Ω
6 Interface termination for T-Port on slave 2 (transmit direction) OFF1)
ON
High-impedance
120 Ω
1) As delivered state
Slide Port Position Function
4 Slave port 1 OFF1)
ON
64 kbit/s or 9,6 kbit/s T port
9,6 kbit/s with T port signal regeneration
5 Slave port 2 OFF1)
ON
64 kbit/s or 9,6 kbit/s T port
9,6 kbit/s with T port signal regeneration
1) As delivered state
1
5
6
9
12No. Assignment No. Assignment
1 – 6 –
2 RXD 7 –
3 TXD 8 –
4 – 9 –
5 GND
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3.22.4 Connector Assignment
Fig. 3.88 Connector 11 of the SUE
Row
No
.
c b a
2 QD2Tin_a1 QD2Sin_a1 QD2Sin_b1
4 QD2Tin_b1 QD2Sout_a1 QD2Sout_b1
6 QD2Tout_a1 QD2Sin_a2 QD2Sin_b2
8 QD2Tout_b1 QD2Sout_a2 QD2Sout_b2
10 QD2Tin_a2 SESout_a SESout_b
12 QD2Tin_b2 QD2Min_a1 QD2Min_b1
QD2_MCLK_b QD2_MCLK_a
14 QD2Tout_a2 QD2Mout_a1 QD2Mout_b1
CTXD1) CRXD1)
16 QD2Tout_b2 S0in_a S0in_b
T11)
18 A1P AM
L11) RESET1)
20 A2P A0out_a S0out_b
22 A3P QD2Min_a2 QD2Min_b2
24 A4P QD2Mout_a2 QD2Mout_b2
L31) L21)
26 A5P Ein_a Ein_b
Ein_a Ein_b
28 A6P Eout_a Eout_b
30 A7P EDS_out EDS_in
32 A8P GND
1) Pins are used only for test purposes
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Fig. 3.89 Connector 10 of the SUE
Row
No
.
c b a
GND_S GND_S GND_S
2 GND/PUP GND
GND K4
4 MUP_2 MUP_1 ZA
6 O3 I7 O2
O4 PB4 PB7
8 PB0 PB3
GND PB6 PB5
10 PE1) PB2 PB1
P5V_EEP GND GND
12 GND GND
SCL GND GND
14 TXDSVB RXDSVB
SDA
16 RTSSVB CLKSVB
GND
18 K2 K1
20 K3 K0
22 GND I2 I1
24 GND
26 I3 GND
GND GND SYN_E
28 I0 I4
PCM_E CLK_4M
30 GND O1
SYN_S PCM_S
32 GND GND GND
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3.22.5 Technical Data
3.22.5.1 F Interface
3.22.5.2 QD2 Slave Interface
3.22.5.3 QD2 Master Interface
Configuration point-to-point, as per V.28Transmission lines screened, unbalancedBit rate, auto detect 9.6/19.2/38.4 kbit/sTransmission mode asynchronousLine code NRZPermissible length 20 mProtocol
Frame structureAddress and control byteInitiator of the data circuitSecondary addresses
IEC TC57HDLC (NRM, polling)primary (LCT)1
Data format 8 data bits, even parity1 stop bit
Plug connector plug (TXD:pin 2; RXD:pin 3)
Configuration serial bus as per EIA RS485Format back-to-back structureAdditional SE option on QD2 slave 1 point-to-point per EIA RS422Bus users 1 master and up to 30 slavesTransmission lines, separate transmit and receive lines
QD2 slave 1 including T and SE linesQD2 slave 2 including T lines
balanced, 10-wirebalanced, 8-wire
Bit rate, auto detect 0.6/1.2/9.6/64 kbit/s Transmission mode plesiochronousLine code NRZIPermissible length 500 mProtocol
Initiator of the data circuitSecondary addresses, which can be set using 5-pin switches
HDLC (NRM, polling)primary (NCT, LCT)
1 to 30TXD idle state logical “1” (high-impedance)RXD expected idle state continuous flagsTermination, switchable 121 Ω
Configuration serial bus as per EIA RS485Format back-to-back structureAdditional SE option on QD2 slave 1 point-to-point per EIA RS422Bus users 1 master and up to 30 slaves
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3.22.5.4 Signal Output, ZA
3.22.5.5 Signal Inputs A1+ / A1- to A8+ / A8-
3.22.5.6 Backplane Detection
3.22.5.7 Power Supply
Transmission lines, separate transmit and receive lines
QD2 slave 1 including T and SE linesQD2 slave 2 including T lines
balanced, 10-wirebalanced, 8-wire
Bit rate, auto detect 0.6/1.2/9.6/64 kbit/s Transmission mode plesiochronousLine code NRZIPermissible length 500 mProtocol
Initiator of the data circuitSecondary addresses, which can be set using 5-pin switches
HDLC (NRM, polling)primary (NCT, LCT)
1 to 30TXD idle state logical “1” (high-impedance)RXD expected idle state continuous flagsTermination, switchable 121 Ω
Form switching contact, to ground potential, 1-pin
Malfunction or fault situation (closed contact)CurrentResidual voltage
≥ 1 mA, ≤ 60 mA≥ −2 V
Fault-free operation (open contact)Applied DC voltagePermissible operating rangeMaximum residual current
≥ −30 V−8 V to −30 V≤ 20 μA
Configuration DC interfaces, isolated from ground
Transmission lines per input balanced, 2-wireInput voltage (floating)
In the active state 20 V to 60 V Passive state 0 V
Configuration TTL input, internal pull-upNumber of contacts 4, unbalanced
Input voltage −36 V to −72 VPower consumption (at −60 V) ≤ 3 W
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3.23 Supervision Unit, OSU
3.23.1 OverviewSupervision unit OSU forms the access of the operating system to the FMX2R3.2. It per-forms functions to operate and supervise the shelves.
Fig. 3.90 Operation of the System Modules with OSU (Example)
The operation and supervision functions of the unit include the following:• Providing 2 × QD2 slave interfaces (can be switched over between synchronous and
asynchronous operation) with T functionality for integration in line and ring struc-tures, QD2 slave 2 is used for redundant system access
• Establishing a virtual concentrator SISA-V/LMX or SISA-V/LMXV2,which can be selected via jumpers in the rear panel of COMPS/COMPS2 (identifi-cation K0 to K7)SISA-V/LMX combines the two QD2 slave ports for redundant system access into a logical interface.SISA-V/LMXV2 treats the two QD2 slave ports as separate interfaces (d and d2) for parallel operation with two management systems.
• Providing 3 × QD2 master interfaces – QD2 master 3 to operate the modules within ONU/shelves– QD2 master 1 and 2 to operate remote network elements with DCN protection
(can be switched over between synchronous and asynchronous operation)The three master interfaces are combined into a logical interface.
• Operation of the local F interface,• Recording and processing external alarms (network element ASA32),• Carrying out self tests,• Operating mode indication via LEDs,• Identifying the SISA address
QD2-M364 kbit/s QD2-S1
QD2-S2
F-IF
OS
LCT
OSU
NE QD2-S
QD2-M1/2
T
TCMXC SMX1/4c
QD2-S QD2-S QD2-S
LTx
LC1
CUD
QD2-S
LCn
LC1
CUD
QD2-S
LCn
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Supervision unit OSU has the following interfaces:• 2 × QD2 slave interface according to EIA RS485,• 3 × QD2 master interface according to EIA RS485,• F interface,• 6 × 2-wire alarm inputs,
symmetrical, not connected to ground• 16 × 1-wire alarm inputs,
unsymmetrical, reference voltage to ground• Identification K0 to K7 (application in standalone, SISA-V/LMX or SISA-V/LMXV2,• Address identification,• Power supply.
QD2 slave interfaceThe interface has two ports (QD2-S 1 and QD2-S 2). It sets up DCN line and ring net-works since it can be switched over from bus mode to line mode (T functionality). Bothports can be set via a DIL switch to synchronous or asynchronous operation.
The interfaces can be used for the following:• To create a redundant system access (SISA-V/LMX)
Layers 2 and 3 of the interface correspond to the SISA specification (issue 6/93) with the following special features:– Both ports are checked alternately for signal reception. As soon as a signal ar-
rives at a port, this transmission route is engaged.– For malfunctioning on the active transmission route (e.g. LOS), switching over to
the second port takes place automatically.• To supervise via two separate management systems
(SISA-V/LMXV2); to establish asynchronous DCN line networks, a clock of the sig-nal arriving from the master port direction is regenerated to reduce sampling distor-tion (9.6 kbit/s asynchronous operating mode).
OSU
External interfacesInternal interfaces
CSB interface
+5 V Power
QD2 master 1
F
6 x alarm inputs
QD2 master 3
Address identification
supply
I2C bus
QD2 slave 1QD2 slave 2
Presence
Identification K0 to K7
signals
16 x alarm inputs(1 wire)
QD2 master 2
(2 wire)
iIn the delivery state of the OSU, both QD2 slave ports are set to asynchronous opera-tion with automatic bit rate identification.
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QD2 master interfaceThe interface has three ports (QD2-M 1 to 3).
Fig. 3.91 Application of QD2 Master Ports
The three ports have the following characteristics:• Port 1 and port 2 control remote network elements and allow operation with DCN
protection. Port 1 and port 2 can be set via a DIL switch to synchronous or asynchro-nous operation and always work with the same bit rate.
• Port 3 controls and supervises local network elements. Port 3 can only be operated in the 64 kbit/s asynchronous operating mode.
3.23.2 Supervision and Alarm SignalingThe OS supervises the OSU via the QD2 slave interface or the LCT via the F interface.Parallel to this, the OSU operating mode is indicated directly via four LEDs. Two of thefour LEDs (red, green) are arranged on the front panel of the unit and the other two LEDs(yellow) are recessed on the unit.
The following table contains an overview of the OSU operating modes.
SISA-V/LMX1)
Master
Master port select
portMaster
portMaster
port
OSU
SISA-V
Slave
Slave port select
portSlaveport
NE m
NE 1 NE 2 NE n
Control of local NEswith the same position as OSU
1 2 3
Control of remote NEswith DCN protection
Asynchr. 64 kbit/s
1) Optionally SISA-V/LMX or SISA-V/LMXV2
LED
(green)
LED
(red)
LED 1
(yellow)
LED 2
(yellow)
Mode
off off off off No operating voltage
on off off off Interference-free operation
off flashes off off Error when booting or set address 0 or > 30
off on off off Unit in error condition or boot phase
on off on off Interference-free operation, TMN link via QD2 slave port 1
on off on flashes Interference-free operation, TMN link via QD2 slave port 1,
redundant TMN link via QD2 slave port 2
on off off on Interference-free operation, TMN link via QD2 slave port 2
on off flashes on Interference-free operation, TMN link via QD2 slave port 2,
redundant TMN link via QD2 slave port 1
Tab. 3.100 LED Displays of OSU
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The as-delivered state of the interfaces is shown in Tab. 3.101:
3.23.3 Controls
Fig. 3.92 Controls of the OSU
On the module OSU there are the DIL switches S1 and S2. In normal operation (defaultvalues) all the slides are “OFF“. The default settings should be kept.
Interface As-delivered state
QD2 slave interfaces Both asynchronous, BUSMODE, autodetecting
QD2 master interfaces All asynchronous, 64 kbps
F interface Autodetecting
Tab. 3.101 As-delivered State of the Interfaces of the OSU
green
red
X2
1 2
3 4
5 6
ON 4
3 2
1
ON
S2 S1
Link 1 (yellow)
Link 2 (yellow)
X1
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The operating mode is set with the DIL switch S2:
With the DIL switch S1, the 120 Ω terminating resistor of the QD2 bus is set:
Port of the OSU Slide “ON” / “OFF” Set mode
Master port 1 Slide 3 ON
Slide 3 OFF
Synchronous
Asynchronous
Master port 2 Slide 4 ON
Slide 4 OFF
Synchronous
Asynchronous
Slave port 1 Slide 1 OFF and Slide 5 OFF 1)
Slide 1 OFF and Slide 5 ON
Slide 1 ON and Slide 5 OFF
Bus mode
Synchronous (T function 2) 3))
Asynchronous (T function 2) 4))
Slave port 2 Slide 2 OFF and Slide 6 OFF 1)
Slide 2 OFF and Slide 6 ON
Slide 2 ON and Slide 6 OFF
Bus mode
Synchronous (T function 2) 3))
Asynchronous (T function 2) 4))
1) Delivery state
2) Slave-up/Slave-down are active for Port1 and Port2
3) T function synchronous (synchronous clocks from the Feeder must be cabled)
4) T function asynchronous (9.6 kbit/s with 64 kbit/s oversampling)
Tab. 3.102 DIL Switch on the OSU
Port of the OSU Slide Position Terminating resistor
Slave 1 out 1 OFF 1)
ON
high-ohmic
120 Ω
Slave 1 in 2 OFF 1)
ON
high-ohmic
120 Ω
Slave 2 out 3 OFF 1)
ON
high-ohmic
120 Ω
Slave 2 in 4 OFF 1)
ON
high-ohmic
120 Ω
1) Delivery state
Tab. 3.103 DIL Switch on the OSU
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3.23.4 Connector Assignment
Fig. 3.93 Connector of the OSU
1
2 F_RXD
3 F_TXD
4
5 GND
6
7
8
9
Internal connector X1
No.
Row
a b c d e
1 GND GND PUP VCC VCC
2 MUP SISAA0 SISAA1 SISAA2
3 SISAA3 SISAA4 SISAA5
4 QD2S1in_a QD2S1in_b GND QD2S1out_a QD2S1out_b
5 QD2S1TCin_a QD2S1TCin_b GND QD2T1TCin_a QD2T1TCin_b
6 QD2T1in_a QD2T1in_b GND QD2T1out_a QD2T1out_b
7 ANW5 ANW6 GND ANW7 ANW8
8 K0 K1 K2 K3 Z_PSRA
9 K4 K5 K6 K7 Z_PSRB
10 QD2S2in_a QD2S2in_b GND QD2S2out_a QD2S2out_b
11 QD2S2TCin_a QD2S2TCin_b GND QD2T2TCin_a QD2T2TCin_b
12 QD2T2in_a QD2T2in_b GND QD2T2out_a QD2T2out_b
13 I_DAT1 I_CLK1 NRST LED_YW1 LED_YW2
14 CTXD CRXD T1 L1 L2
15 I_DAT I_CLK AI1 AI2 AI3
16 VCC_OSU1) OSUPLUG AI4 AI5 AI6
17 ANW1 FANCTRL_1 AI7 AI8 AI9
18 ANW2 AI10 AI11 AI12
19 ANW3 AI13 AI14 AI15
20 ANW4 FANCTRL_2 AI16
21 PE AI17_P AI17_M
22 QD2M3out_a QD2M3out_b GND_S AI18_P AI18_M
23 QD2M3in_a QD2M3in_b GND_S AI19_P AI19_M
24 GND AI20_P AI20_M
25 QD2M2out_a QD2M2out_b GND AI21_P AI21_M
26 GND AI22_P AI22_M
27 QD2M2in_a QD2M2in_b GND
28 QD2M2TCin_a QD2M2TCin_b GND QD2M1out_a QD2M1out_b
29 GND
30 CSBout_a CSBout_b GND QD2M1in_a QD2M1in_b
31 CSBin_a CSBin_b GND QD2M1TCin_a QD2M1TCin_b
32 GND GND GND VCC VCC
Contacts 1, 4 and 6 connected
Contacts 7 and 8connected
1) only for OSU S42024-A1871-B1
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Signal Abbreviations
AI1 to AI16 ONU internal alarm inputs (single wire)
AI17_M to AI22_M External alarm inputs (two-wire); negative
AI17_P to AI22_P External alarm inputs (two-wire); positive
ANW1 to ANW4 Presence signals
CRXD Debug interface
CSBout_a/b CSB interface (internal COMPS supervision BUS)
CSBin_a/b CSB interface (internal COMPS supervision BUS)
CTXD Debug interface
FANCTRL_1 Fan control for fan 1 to 3
FANCTRL_2 Fan control for fan 4
GND + 60 V (internal ground)
GND_S Ground of the shelf (protective ground)
F_RXD, F_TXD F interface for ACI (only for test purposes)
I_CLK I2C master interface (serial data interface)
I_CLK1 I2C1 master interface; SSP (synchronous serial port) (serial data interface temperature sensor)
I_DAT I2C master interface (serial data interface)
I_DAT1 I2C1 master interface; SSP (synchronous serial port) (serial data interface temperature sensor)
K0 to K7 ONU identification (8 bit address)
L1, L2 Alarm, LED output
LED_YW1, LED_YW2 Signals for test purposes
MUP - 60 V primary voltage; supply voltage
NRST I2C1 master interface; SSP (synchronous serial port) (serial data interface temperature sensor)
OSUPLUG Fan control by means of the OSU
PE Program Enable
PUP + 60 V
QD2M1in/out_a/b QD2 master interface 1
QD2M1TCin/out_a/b Timing signal for QD2 master interface 1
QD2M2in/out_a/b QD2 master interface 2
QD2M2TCin/out_a/b Timing signal for QD2 master interface 2
QD2M3in/out_a/b QD2 master interface 3
QD2S1in/out_a/b QD2 slave interface 1
QD2S1TCin/out_a/b Timing signal for QD2 slave interface 1
QD2S2in/out_a/b QD2 slave interface 2
QD2S2TCin/out_a/b Timing signal for QD2 slave interface 2
QD2T1in/out_a/b QD2 T1 interface
QD2T1TCin_a/b Timing signal QD2 T1 interface
QD2T2in/out_a/b QD2 T2 interface
QD2T2TCin_a/b Timing signal QD2 T2 interface
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3.23.5 Technical Data
QD2 Slave Interfaces
QD2 Master Interfaces
SISAA0 to SISAA5 SISA address for the NE COMPS
T1 Test mode activation
VCC + 5 V
Z_PSRA Alarm lines of the PSR (prompt alarm)
Z_PSRB Alarm lines of the PSR (deferred alarm)
Configuration Serial bus systemaccording to EIA RS485
Bus users 1 master, ≤ 30 slavesTransmission lines 4 wire, symmetricalClock lines (for synchronous operation only) 4 receive lines
according to V.11Bit rate for asynchronous operation (autodetect) 9.6 kbit/s
64 kbit/sBit rate for synchronous operation 64 kbit/sTransmission mode PlesiochronousLine code NRZIPermissible length ≤ 500 mProtocol HDLC (NRM, polling)Data connection initiator PrimaryAddresses of secondaries(can be set via rear panel coding) 1 to 30
Configuration Serial bus systemaccording to EIA RS485
Bus users 1 master, ≤ 30 slavesTransmission lines 4 wire, symmetricalClock lines (for synchronous operation operation) 4 receive lines
according to V.11Bit rate for port 1 and port 2 (can be configured) 9.6 kbit/s
64 kbit/sBit rate for port 3 (fixed) 64 kbit/sTransmission mode PlesiochronousLine code NRZIPermissible length ≤ 500 mProtocol HDLC (NRM, polling)Data connection initiator Primary (OSU)Addresses of secondaries(can be set via rear panel coding) 1 to 30
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F Interface
Alarm Inputs
Presence Signal
Identification K0 to K7
Address Identification
Power Supply
Configuration Point-to-point acc. to V.28Transmission lines Shielded, unsymmetricalBit rate (autodetect) 9.6 kbit/s
19.2 kbit/s38.4 kbit/s
Transmission mode AsynchronousLine code NRZPermissible length ≤ 15 mProtocol HDLC (NRM, polling)Frame structure IEC TC 57Data connection initiator Primary (LCT)Address of secondary 1
Configuration Direct current interfaceNumber of contacts 22
6 × transmission lines
Input voltage (active mode)Input voltage (passive mode)
2 wire, symmetrical,not connected to ground36 V to 72 V≤ 1 V
16 × transmission lines
Activation (active mode)Activation (passive mode)
1 wire, unsymmetrical, nega-tive reference voltage to groundGround contact, closedGround contact, open
Configuration TTL input stage with internal pull-up resistor
Number of contactsModule insertedModule pulled
4, unsymmetricalL levelH level
Configuration 8 contacts, TTL input stage with internal pull-up resistor
Configuration 6 contacts, TTL input stage with internal pull-up resistor
Input voltage +5 V (1 ±5%)Max. dissipation 5 W
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3.24 SISA Concentrator SISAK
3.24.1 OverviewThe SISAK is a switching node in the SISA monitoring and control system. The telegramtraffic between a higher level hierarchy and a number of subordinate network elementsand/or concentrators is specified in the SISA protocol.
The interfaces on the SISAK mean that it can be incorporated into existing systems, foruse in transmitting TMN information.
The following transmission channels can be used by the SISAK’s interfaces in SISAnetworks:
The SISAK has:• One master port• Two slave ports• One F interface.
For purposes of matching to external electrical circuits, various output and input stagesare provided at each port for the data channels and the clock inputs, and these can beactivated as necessary via the LCT.
Transmission channels Interfaces Remarks
QD2 bus RS485
Point-to-point connection Asynchronous V.11 or V.28 in-
terface
Connection between a slave and master
via D1in/out; connection between a slave
and other slaves via D2in/out
Transparent 64-kbit/s channel Synchronous V.11 or V.28 in-
terface
In each case as a synchronous, contra-
directional link
Tab. 3.104 SISAK Transmission Channels
Data channels/clock inputs Input and output stages
Master port data channel RS485/V.11/V.28
Master port clock input V.11/V.28
Slave port data channel RS485/V.11/V.28
Slave port clock input V.11/V.28
Tab. 3.105 SISAK Input and Output Stages for the Data Channels and Clock Inputs
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QD2 Slave Interfaces
The slave port has two data channels with separate transmit and receive lines. Thefollowing interfaces can be implemented at the slave ports:
QD2 Master Interfaces
The master port has a data transmission channel which is electrically capable of servic-ing up to two interfaces, which can be configured independently of each other. Thesecould be, for example, a synchronous V.11 interface for a SISA transport channel andthe QD2 bus interface conforming to EIA RS485, for the connected network elements.
D2in/out
D1in/out
Master port
D1in/out
SISAK
F interfaceV.24 LCT
−48 V/−60 V
D2in/out
Slave port 1
D1in/out
D2in/out
Slave port 2
EIA RS485V.11 syn./asyn.V.28 syn./asyn.
V.11 syn./asyn.V.28 syn./asyn.
V.11 asyn.V.28 asyn.
EIA RS485V.11 syn./asyn.V.28 syn./asyn.
V.11 asyn.V.28 asyn.
EIA RS485V.11 syn./asyn.V.28 syn./asyn.
QD2 slave interfacesQD2 master interfaces
D1in/out D2in/out Bit rate in kbit/s
EIA RS485 (QD2-Bus) 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64
V.11 synchronous 64
V.11 asynchronous V.11 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64
V.28 synchronous 64 1)
V.28 asynchronous V.28 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64 1)
1) V.28 standard ≤ 19.2 kbit/s
Tab. 3.106 Interfaces and Bit Rates at the SISAK’s Slave Ports
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3.24.2 Control and MonitoringThe SISAK is operated and monitored via the QD2 slave interface, and via the F inter-face using an LCT.
The unit has one green and one red LED for indicating its operating state. The greenLED is on during normal operation, and goes out if there is a power failure. The red LEDis on during the switch-on phase until initialization and the first polling cycle have beencompleted. While the unit is operating, it signals any fault states on the SISAK.
The unit incorporates a fuse for the power feed (−48 V/−60 V).
D1in/out D2in/out Bit rate in kbit/s
EIA RS485 (QD2 bus) 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64
EIA RS485 (QD2 bus) V.11 synchronous 64
EIA RS485 (QD2 bus) V.28 synchronous 64 1)
EIA RS485 (QD2 bus) V.11 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64
EIA RS485 (QD2 bus) V.28 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64 1)
V.11 asynchronous V.11 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64
V.28 asynchronous V.28 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64 1)
V.11 asynchronous V.28 asynchronous 1.2; 2.4; 4.8; 9.6; 19.2; 38.4; 64 1)
1) V.28 standard ≤ 19.2 kbit/s
Tab. 3.107 Interfaces and Bit Rates at the SISAK’s Master Port
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3.24.3 Controls
Fig. 3.94 Controls of the SISAK
13rdgn
50
13 External connector
15 Fuse for −48 V/−60 V
1555
57
23
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
5623
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
Switch Slide Pos. Control Function
55 1 to 8
–
–
1 –31)
2–3
Interface settings at slave port 1
G.703
RS 485/V.11
56 1 to 8
–
–
1 –31)
2–3
Interface settings at slave port 2
G.703
RS 485/V.11
57 –
1
–
OFF
ON1)
Termination - driver D1in/out of the QD2 master port
V.11 asynchronous mode (termination out)
QD2 bus mode (termination 121 Ω in)
1) As-delivered variant
Tab. 3.108 Settings by Control Elements of the SISAK
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Connector 50 (F interface) used for connecting an LCT has the following contact assign-ment, see Fig. 3.95
Fig. 3.95 Contact Assignment of the F Connector
The operating status and the alarms of the SISAK are displayed by means of one redand one green LED on the front panel of the SISAK, see Tab. 3.109.
LED (green) LED (red) Alarm and Status signalling
ON OFF Normal operation
OFF OFF No operating voltage
OFF ON Fault status or self-test (10 s to 15 s)
Tab. 3.109 Optical Signalling of the SISAK
1
5
6
9
50 No. Assignment No. Assignment
1 – 6 –
2 TXD 7 –
3 RXD 8 –
4 – 9 –
5 GND
Nos. 1, 4, 6 and Nos. 7, 8 are interconnected
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3.24.4 Terminal Assignment
Fig. 3.96 Terminal Assignment of the SISAK
Connector 13
No.
Row
c b a
2 S1D1outV GND2 UP
4 S1D1ina S1D1inb S1D1inV
6 S1D1outa S1D1outb GND1
8 S1D2ina S1D2inb S1D2inV
10 S1D2outa S1D2outb S1D2outV
12 S2D1ina S2D1inb S2D1inV
14 S2D1outa S2D1outb S2D1outV
16 S2D2ina S2D2inb S2D2inV
18 S2D2outa S2D2outb S2D2outV
20 MD1inRa MD1inRb MD1inV
22 MD1outRa MD1outRb MD1outV
24 MD2inRa MD2inRb MD2inV
26 MD2outRa MD2outRb MD2outV
28 S1TRa S1TRb S1TV
30 S2TRa S2TRb S2TV
32 MTRa MTRb MTV
Connector 50
No.
1
2 TXD
3 RXD
4
5 GND
6
7
8
9
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Signal Abbreviations
3.24.5 Technical Data
3.24.5.1 F Interface
GND Ground
GND1 Signal ground
GND2 Ground (-60 V)
MDyoutRa Master data y out RS485 wire a
MDyoutRb Master data y out RS485 wire b
MDyinRa Master data y in RS485 wire a
MDyinRb Master data y in RS485 wire b
MDyoutV Master data y out V.28
MDyinV Master data y in V.28
MT Master clock
MTRa Master clock in RS485 wire a
MTRb Master clock in RS485 wire b
MTV Master clock in V.28
RXD Unsymmetrical receive (data)
S1T Slave clock 1
S2T Slave clock 2
SxDyina Slave x data y in RS485/G.703 wire a
SxDyinb Slave x data y in RS485/G.703 wire b
SxDyouta Slave x data y out RS485/G.703 wire a
SxDyoutb Slave x data y out RS485/G.703 wire b
SxDyinV Slave x data y in V.28
SxDyoutV Slave x data y out V.28
SxTra Slave x data y in RS485/G.703 wire a
SxTrb Slave x data y in RS485/G.703 wire b
SxTV Slave x data y in V.28
TXD Unsymmetrical transmit (data)
UP Primary voltage
Configuration point-to-point, as per V.24/V.28
Transmission lines screened, unbalancedBit rate 9.6 kbit/sTransmission mode asynchronousLine code NRZPermissible length 20 m
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3.24.5.2 QD2 Interface in accordance with EIA RS485
3.24.5.3 QD2 Interface in accordance with V.11, Synchronous
ProtocolFrame structureAddress and control byteInitiator of the data circuitSecondary addresses
IEC TC57HDLC (NRM, polling)primary (LCT)1
Withstand voltageProtectionTest as per Direction of test voltagePulse formPositive and negative longitudinal voltage
suppressor diodesG.703, Appendix Bwire against ground 1.2/50 μs100 V
Connectors (on front)Format as perWired as
IEC807-23-wire null modem
Configuration serial bus system as perEIA RS 485
Bus users 1 master and up to 30 slaves
Transmission lines balanced, 4-wireBit rate (in appropriate steps) 0.6 kbit/s to 64 kbit/s Transmission mode plesiochronousLine code NRZIPermissible length 500 mProtocol
Initiator of the data circuitSecondary addresses
HDLC (NRM, Polling)primary 1 to 30
TXD/IDLEAt the slaveAt the master
logical “1” (high-impedance)Continuous flags
Termination at the masterD1in
D1out
voltage divider,383/147/383 Ω 121 Ω, switchable
Withstand voltageProtectionTest as perDirection of test voltagePulse formPositive and negative longitudinal voltage
suppressor diodesG.703, Appendix Bwire against ground1.2/50 μs100 V
Configuration point-to-point, as per EIA RS422
Transmission lines balanced, 4-wireBit rate 64 kbit/sTransmission mode(separate transmit and receive lines)
synchronous, contradirectional, half-duplex
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3.24.5.4 QD2 Interface in accordance with V.11, Asynchronous
3.24.5.5 QD2 Interface in accordance with V.28, Synchronous
Line code NRZIPermissible length 500 mProtocol
Initiator of the data circuitSecondary addresses
HDLC (NRM, polling)primary 1 to 30
TXD/IDLEAt the slaveAt the master
logical “1” (high-impedance)continuous flags
Termination at the ‘Tin’ clock input 147 ΩWithstand voltage
ProtectionTest as perDirection of test voltagePulse formPositive and negative longitudinal voltage
suppressor diodesG.703, Appendix Bwire against ground1.2/50 μs100 V
Configuration point-to-point, as per EIA RS422
Transmission lines balanced, 4-wireBit rates (in appropriate steps) 0.6 kbit/s to 64 kbit/sTransmission mode(separate transmit and receive lines) asynchronous, half-duplexLine code NRZIPermissible length 500 mProtocol
Initiator of the data circuitSecondary addresses
HDLC (NRM, Polling)primary 1 to 30
TXD/IDLEat the slaveat the master
logical “1” (high-impedance)continuous flags
Termination at the masterD1in
D1out
voltage divider 383/147/383 Ω 121 Ω
Withstand voltageprotectiontest as perdirection of test voltagepulse formpositive and negative longitudinal voltage
suppressor diodesG.703, Appendix Bwire against ground1.2/50 μs100 V
Configuration point-to-point, as per ITU-T V.28
Transmission lines screened, unbalancedBit rate
generalas per V.28
64 kbit/s ≤ 19.2 kbit/s
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3.24.5.6 QD2 Interface in accordance with V.28, Asynchronous
3.24.5.7 Power Supply
Transmission mode(separate transmit and receive lines) synchronous,
contradirectional, half-duplexLine code NRZIPermissible length 5 mProtocol
initiator of the data circuitaddresses of the secondaries
HDLC (NRM, polling)primary 1 to 30
TXD/IDLEat the slaveat the master
logical “1” (high-impedance)continuous flags
Withstand voltageprotectiontest as perdirection of test voltagepulse formpositive and negative longitudinal voltage
Z diodesG.703, Appendix Bwire against ground1.2/50 μs100 V
Configuration point-to-point, as per ITU-T V.28
Transmission lines screened, unbalancedBit rate (in appropriate steps)
generalas per V.28
0.6 kbit/s to 64 kbit/s ≤ 19.2 kbit/s
Transmission mode(separate transmit and receive lines) asynchronous, half-duplexLine code NRZIPermissible length
at 0.6 kbit/s to 19.2 kbit/sat 38,4 kbit/s and 64 kbit/s
20 m5 m
Protocol initiator of the data circuitaddresses of the secondaries
HDLC (NRM, polling)primary 1 to 30
TXD/IDLEat the slaveat the master
logical “1” (high-impedance)continuous flags
Withstand voltageprotectiontest as perdirection of test voltagepulse formpositive and negative longitudinal voltage
Z diodesG.703, Appendix Bwire against ground1.2/50 μs100 V
Input voltage, UP -36 V to -72 VPower consumption (at -60 V) ≤ 4.2 W
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4 Functions
4.1 Operating Modes of the Multiplexer
4.1.1 Drop Insert MultiplexerThe drop/insert multiplexer provides the option of switching one of the following trans-mission paths for the timeslots:• Connecting a 2-Mbit/s signal, see Fig. 4.1
Fig. 4.1 Connecting a 2-Mbit/s Signal
• Tapping off and inserting 64-kbit/s signals including the relevant sections in time slot 16, see Fig. 4.2Channels which are not tapped off are connected.
Fig. 4.2 Tapping off and Inserting 64-kbit/s Signals
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
FMX2R3.2
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
FMX2R3.2
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• Conference and point-to-multipoint for data signals– digital conference, see Fig. 4.3– point-to-multipoint with port E1A as point, see Fig. 4.4– point-to-multipoint with port E1B as point, see Fig. 4.5– point-to-multipoint with time slot as point, see Fig. 4.6
Fig. 4.3 Digital Conference
Fig. 4.4 Point (Port E1A)-to-Multipoint
Fig. 4.5 Point (Port E1B)-to-Multipoint
Fig. 4.6 Point (Time Slot)-to-Multipoint
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
..
.
FMX2R3.2
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
. FMX2R3.2
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
.
FMX2R3.2
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
.
FMX2R3.2
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• Broadcasting (unidirectional) for analog and data signals– broadcasting with port E1A as point, see Fig. 4.7– broadcasting with port E1B as point, see Fig. 4.8– broadcasting with time slot as point, see Fig. 4.9.
Fig. 4.7 Broadcasting with E1A as Point
Fig. 4.8 Broadcasting with E1B as Point
Fig. 4.9 Broadcasting with Time Slot as Point
4.1.2 Terminal MultiplexerIn “terminal multiplexer” operating mode, up to 60 (62) signals in the sending and receiv-ing directions can be distributed by the line cards to ports E1A and E1B, and sent or re-ceived as 2-Mbit/s signals, with 30 (31) channels to E1A and 30 (31) channels to E1B.Unoccupied timeslots carry AIS.
4.1.3 Terminal Multiplexer with 1+1 Protection SwitchingIn the “terminal multiplexer with 1+1 protection switching” operating mode TMX30(1+1),both ports in the sending direction are occupied by the multiplex signal. If a fault occursin the receiving direction at the port which carries the signal, there is a changeover tothe other port.
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
. FMX2R3.2
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
.
FMX2R3.2
E1Bout
E1Bin
Port E1BPort E1A
E1Ain
E1Aout
TSTS
.
FMX2R3.2
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Fig. 4.10 Terminal Multiplexer TMX30(1+1)
Operating mode TMX30(1+1) of the multiplexer is used for protection switching of2-Mbit/s transmission links. The signals of up to 30 (31) channels are transmitted viaboth ports of the CUDs. After a fault is detected on the normal path, there is achangeover within 10 ms to the protection path, without the channel initialization datahaving to be changed, i.e. existing calls are retained.
The following priorities apply to the alarm criteria of protection switching:
If a high-priority alarm occurs at one port and a low-priority alarm occurs at the otherport, the one with low priority is used as the transmission path.
It is possible to choose between two functional principles:• Non-revertive mode
If there has been a changeover to the protection path because of a fault on the nor-mal path, there is no automatic reverse changeover when the fault is cleared.
• Revertive modeIf there has been a changeover to the protection path because of a fault on the nor-mal path, there is an automatic reverse changeover when the fault is cleared.
The distant station which is used must be entered in the CUD menu. If the distant stationis fitted with FMX (not FMX2*), other alarm criteria than those in Tab. 4.1 apply.
Changeover to the normal or protection path can be forced by an operating command.
Changeover of the clock source takes place independently of 1+1 protection switchingin the case of the LOS, AIS, SYN, BER-3 and local loop alarms, according to the clockpriority list, see Section 4.5.
Criteria Criterion causes changeover Priority
LOS, AIS, SYN, BER-3, local loop, distant loop always high
SYNK, AISK if CAS on high
BER-5/-6 if alarm criterion switched on low
D bit, Dk bit no -
Tab. 4.1 Priorities of Alarm Criteria for Protection Switching
Station 1
normal path
stdby path
TMX30(1+1)
Port A
Port B
Station 2
TMX30(1+1)
Port A
Port B
T3in
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4.1.4 Ethernet Connection Configuration
Traffic using different time slot groups
The traffic using different time slot groups is separately transmitted. A cross connect canroute the time slot groups to different locations. Different time slot groups are not provid-ed for the same Ethernet module.
Fig. 4.11 Ethernet Traffic in Different Time Slot Groups
Station 2
CUD
FMX2R3.2
CPF2
Port A Port B Port A Port BE1G.703G.704
E1
E1
E1
Eth
1E
th 2
Eth
3E
th 4
Station 1
CUD
FMX2R3.2
CPF2
CIMnx64E
CIMnx64E
Network 1time slot group 1time slots 1 ... n
Netz 2time slot group 2
time slots n + 1 ... 31
Oil pipelinemaintenance
center
Router
Ethernet10Base-T
FMX2R3.2E
th 1
Eth
2E
th 3
Eth
4
Eth
1E
th 2
Eth
3E
th 4
CIMnx64E
CIMnx64E
Eth
1E
th 2
Eth
3E
th 4
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Combining traffic of two n x 64 kbit/s time slot groups with one Ethernet module
Combining traffic of two n x64 kbit/s time slot groups with one Ethernet module is pos-sible at central station. A cross connect can route the time slot groups to different loca-tions.
Fig. 4.12 Ethernet Traffic of 2 Time Slot Groups
Combining traffic of n time slot groups
Combining traffic of n time slot groups as star configuration is only possible by convert-ing traffic from TDM to Ethernet. Up to 4 interfaces can be combined with an Ethernetmodule. To combine more Ethernet interfaces, also an external switch can be used.
Fig. 4.13 Ethernet Traffic in Star Configuration
Ethernet ports
Terminationpoint FU 1
Terminationpoint FU 2
CPF2
E1 port Atime slot group 2
time slots n + 1 ... 31
E1 port Atime slot group 1time slots 1 ... n
TDM connection
CIM-nx64E
CIM-nx64E
CUDCPF2
CIM-nx64E
CUDCPF2
CIM-nx64E
CUDCPF2
CIM-nx64E
CUDCPF2
CIM-nx64E
CUDCPF2
Eth. 10/100bT Eth. 10/100bTEth. 10/100bT
Eth. 10/100bT
TDM connection TDM connection
TDM connection TDM connection TDM connection
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4.2 End-to-End Protection for Subrates and n × 64 kbit/sWith the CPF2 or the UAC68 channel protection at 64-kbit/s time slot level is possible.
Fig. 4.14 End-to-end Protection
This involves sending the data redundantly via various time slots. If a link fails, this willbe detected on the unit (AIS detection or V.110/X.30 supervision), signaled to the oper-ation system and a switchover to the redundant time slots will be made. • With protection, both transmission paths are used for sending.• The receiver selects a fault-free path. If both paths are fault-free, the end points can
select different receiving paths.• The protection mode is always non-revertive.• Only whole 64-kbit/s timeslots are switched, not subtime slots. Any subtime slot can
trigger the changeover. Subrate channels that use a shared normal path must also use a shared protection path. The subtime slots (bit positions) are the same for the normal and protection path.
• With ≥ 64 kbit/s, protection is only possible if data is transmitted scrambled.• Protection is not possible with multiport.
AIS monitoring of the normal path takes place per port for the entire 64-kbit/s timeslot(s).V.110 monitoring of the normal path (only with subrates) takes place for the subchannel.The protection path procedure is controlled and performed by the basic module, whichresults in changeover with delay. The redundant channel (standby path) is not moni-tored for V.110/X.30 failure prior to changeover. The channel reports the AISR or LOFalarms detected.
AIS monitoring of the inactive path for the entire 64 kbit/s timeslot(s) is implemented per port. A fault is detected after approximately 2 seconds. With faults on the inactive path, RPA is reported.
A (sub)channel performs a changeover if the active path is faulty (AISR or LOF) and theinactive path is not faulty (no RPA).
After a changeover to the redundant channel, there is only reversion to the normal pathif the redundant path fails (non-revertive mode).
The changeover criterion is:• for subbit rates: V.110/X.30 failure or AIS alarm from the network side• for n x 64 kbit/s: AIS alarm of the scrambled signal on the network side.
Channel protection is therefore only possible with nx64kbps if data is sent scrambled.
Single port subrates Single port ≥ 64 kbit/s
Send direction TS send entire 64-kbit/s timeslot simulta-
neously on normal and protection path
send simultaneously on normal
and protection path
Receive from direction TS V.110 and AIS monitoring of the current
path, AIS monitoring on protection path
AIS monitoring simultaneously on
normal and protection path
Tab. 4.2 Functions with Channel Protection
Port A
Port B
Port A
Port BCUDUAC68CPF2 CUD
UAC68CPF2
subscribersubscriber
FMX2R3.2 FMX2R3.2
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Single port subrates
If protection is set up, the entire 64-kbit/s time slot is sent simultaneously on the normal and protection path direction TS, also the subrate channels it contains without protec-tion.
In the receiving direction from the port, one of the two paths is selected and the signalof the other path is not connected. In the auto protection state, if V.110 frame synchro-nization of the subrate channel fails on the current path, there is a changeover to theother path. If V.110 frame synchronization is not achieved on the new path, the port triesto achieve synchronization alternately on both transmission paths. The changeovertakes place every 3 seconds. If V.110 synchronization is achieved on one of the paths,this transmission path is selected.
The “forced“ changeover is always performed.
Single port ≥ 64 kbit/
If protection is set up, the timeslots are sent simultaneously on the normal and protec-tion path. There are no further changeovers.
In the receiving direction, one of the two paths is selected and the signal of the otherpath is not connected.
In the auto protection state, if AIS is detected on the current path, there is onlychangeover to the other path if no AIS has been detected on the latter.
The “forced“ changeover is always performed.
If both transmission paths are faulty, both paths are monitored for AIS without achangeover taking place.
Fig. 4.15 Actions for Channel Protection
Connection does not exist
Connection without PSPstate created
Connection with PSPstate created
Connection without PSPstate connected
Normal path in usePstate: auto
Protection path in usePstate: auto
Normal path in usePstate: lockout
Protection path in usePstate: forced
manual
intern
forcedclear
disconnect
create
add PSP
delete
forced forced
manual
clearforced
delete PSP
createdelete
connect Connection with PSP state connected
add PSP
delete PSP
disconnectconnect
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Path segment protection
The network element can carry out automatic changeovers between the normal and pro-tection paths according to internal changeover criteria. These are possible on a one-time basis (non-revertive) (protection state: auto).• A manual changeover from the normal to the protection path and vice versa is pos-
sible. In the auto protection state, however, only if the path to which the changeover occurs is fault-free. The protection state is not affected by a manual changeover.
• If the internal changeover criteria are to be taken out of service, in the auto protec-tion state, the forced activation of a path is possible, independently of its fault state (protection state: lockout or forced). If faults that would cause a changeover to the auto state occur on the used path in the lockout or forced state, there is no changeover to the other path.
• A clear command can be used to reactivate the automatic changeover following a forced activation.
• The connection states “normal path in use, protection state: forced“ and” protection path in use, protection state: lockout“ may not occur.
• Automatic changeover according to internal criteria is only possible for UAC68 and CPF2.
Non-revertive mode
Non-revertive protection mode is used, meaning that when the normal path is disturbedthe system changes over to the protection path if this path is fault-free. A reversechangeover occurs if there is a fault on the protection path, and the normal path is fault-free.
4.3 Timed Tasks for ConnectionsOne connection can be set up for each subscriber port with protection, and two for eachsubscriber port without protection, to be controlled by a timed task. Timed tasks are alsopossible in combination with subrate multiplexing, port-to-port connections and multi-point connections. The following time schemes are possible:• periodic timed task (weekday and hour mask, to full hour)• once-off timed task with start and end of connection (to full minute)• periodic timed task (weekday and hour mask) from date of start of connection to date
of end of connection (to full hour).
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4.4 Signaling of the ISDN Line Cards
4.4.1 Dial-up LinesThe following signaling modes are possible:• CAS signaling
Time slot 16 contains the channel-associated codes. The D channel, with two bits per ISDN port, is either transmitted in another time slot (non multiplexed) or multi-plexed for four ISDN ports in a dedicated time slot.
Fig. 4.16 CAS Signaling on ISDN Dial-up Lines
• FA signalingThe D channel (2 bits) and the signaling codes (6 bits C/I, alarm) of each ISDN port occupy one time slot of the 2-Mbit/s signal.
Fig. 4.17 FA Signaling on ISDN Dial-up Lines
4.4.2 Leased LinesThe following signaling modes are possible:• without signaling (stand-alone operation: select “leased line” in the menu)
Only the B channels are transmitted.• D channel signaling only (stand-alone operation: select “leased line” in the menu)
The D channel, with two bits per ISDN port, is either transmitted in any time slot or multiplexed for four ISDN ports in a dedicated time slot.
Fig. 4.18 Stand-alone Operation with D Channel Signaling
• FA signalingThe D channel (2 bits) and the signaling codes (6 bits C/I, alarm) of each ISDN port occupy one time slot of the 2-Mbit/s signal.
Fig. 4.19 FA Signaling in ISDN Leased Lines
1) The most significant bit is sent first
TS16signaling...TS1 to TS15 and TS17 to TS31
2 to 8 D bits
multiplexed
non multiplexed
D1D0 D1D0 D1D0 D1D0
D1D0 1)
B1 (8 bits) B2 (8 bits)
1) The most significant bit is sent first
TS16...B*
D1D0 6 bits C/I, alarm
1)
TS1 to TS15 and TS17 to TS31B1 (8 bits) B2 (8 bits)
1) The most significant bit is sent first
TS16...TS1 to TS15 and TS17 to TS312 to 8 D bits
multiplexed
non multiplexed
D1D0 D1D0 D1D0 D1D0
D1D0 1)
B1 (8 bits) B2 (8 bits)
1) The most significant bit is sent first
TS16...B*
D1D0 6 bits C/I, alarm
1)
TS1 to TS15 and TS17 to TS31B1 (8 bits) B2 (8 bits)
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4.5 Clock Generation and Synchronization
Clock Sources
The basic clock (the sending clock of E1out) for the multiplexer is supplied by the centralunit.
The 4.096 MHz system clock which is used internally for synchronization of the trans-mission modules is generated using PLL and synchronized externally by an internal orexternal clock source.
The following can be used as clock sources:• T3in signal.• 2.048-MHz clock, derived from E1in input signal.
On the CUD, the 2-MHz clock can be derived from E1Ain or E1Bin.• 64-kHz clock, derived from the input signal of a DSC, CPF2 or ISDN line card.
For synchronization via an ISDN line card, only a permanently active ISDN port must be used.
• Internal clock source.
For clock synchronization, a clock priority list, into which up to eight clock sources canbe entered in priority order, can be created. Synchronization is by the clock source withhighest priority (in the menu, the lowest priority number). If there is a fault in the currentsynchronization clock source, synchronization is taken over by the next reserve clocksource. If the fault is cleared, the higher-priority clock source takes over again.
The multiplexer can also be synchronized on the frame. In this way a constant signaltransit time is achieved.
If the frame synchronization option has been selected from the menu, the sent frame issynchronized by the port of the active clock source, E1in port A or E1in port B. The Sabits cannot be used in this case, see Sa Bit Interfaces (Section 2.3).
Clock Source Changeover with N bit or Sa5 bit
The receiving clock E1in must be synchronized with the sending clock E1out. In linearnetworks, therefore, protection switching of the clock source can be set up. The masterclock T3in is fed in at both end points of the linear network. To control the clockchangeover, the Sa4 bit (N bit) or Sa5 bit can be used.
Fig. 4.20 Clock Control in Linear Network (T3 Available at both End Points)
The following changeover criteria apply:• N bit = 1 / Sa5 bit = 0 in E1in means valid clock• N bit = 0 / Sa5 bit = 1 in E1in means invalid clock.
In the case of the clock master or clock slave in the linear network, if the clock sourcewith the highest priority is faulty, the facility is switched to internal generator, since theE1in reserve clock sources before the changeover are marked as unavailable by
in E1out
clock master reserve clockmaster
in E1Aout
out E1B
in
in E1Aout
out E1B
in
in E1Aout
out E1B
in
out E1in
N = 1
N = 0
N = 1 N = 1 N = 1
N = 0 N = 0 N = 0
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N bit = 0. If all facilities between the site of the fault and the reserve clock master haveswitched to internal generator, the reserve clock master switches to T3. From the re-serve clock master to the site of the fault, the synchronization is reconstructed.
General notes:• Network sections with external clock masters and external reserve clock sources
In the case of simultaneous failure of all clock sources, there is no final state in which a network element, through its internal clock, is the clock source for all other network elements (isolated operation). In this case, all network elements switch to the inter-nal clock.
• Ring structuresWithin network sections with external clock masters and external reserve clock sources, no structures in which the clock synchronization is signaled by clock control bits in a closed ring must be set up. This includes also rings with two points.
• Peripheral sections of networkPeripheral sections with only one external clock source must not be configured with clock control bits.
• Backup of clock sources by protection pathIf a clock is transmitted from a clock source to a point and all participating 2-Mbit/s data streams are configured with clock control bits, it is impossible to transmit the clock on a protection path with clock control bits.
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5 Operation
5.1 Network ManagementFig. 5.1 illustrates the basic network management structure for the control and monitor-ing of the FMX2R3.2.
Fig. 5.1 Network Management of FMX2R3.2 (Example)
If the operation system is set up as a multiuser system, the client PC is linked to theserver PC via a LAN. The server PC is connected via the SISA-DCN (Data ConnectionNetwork) to the QD2 interface on the highest SISA concentrator in the SISA hierarchy(e.g. OSU, SISAK, SUE). The AccessIntegrator (ACI) is used to manage all the networkelements which are subordinate to this SISA concentrator in the SISA hierarchy.
In the case of a single user system, a single PC - which incorporates both the server andclient functions - is linked via the DCN to the QD2 interface on the AN.
In addition, for some of the operating tasks (primarily commissioning and maintenance)it is possible to use an LCT. Using a connecting cable for F-interfaces, this is connectedto the F-interface of the highest SISA concentrator in the SISA hierarchy, or directly tothe appropriate F-interface on the system module.
Server 2Server 1
Client 1 Client 2 Client n
Windows domains
QD2RS 485
FRS 422
LAN
ACI
NT NT
FMX2R3.1
FMX2R3.1
FMX2R3.1
FMX2R3.1
FMX2R3.1
FMX2R3.1
Access station
Station inthe ring networkwith branch
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5.2 SISA Communication NetworkThe SISA communication network (DCN) enables centralized operation and mainte-nance of the FMX2R3.2 network.
The SISA network has a uniform basic pattern and possesses a serial data bus, to whicha maximum of 30 subscribers can be connected, see Fig. 5.2. Here, one subscriber functions as a master, whilst the others are assigned to him asslaves. By means of the cascading of this basic pattern, hierarchically-arranged net-works with up to 10 levels can be created. Generally speaking, data traffic moves in bothtransport directions.
For access to the individual network elements, virtual SISA concentrators (SISA-V) areimplemented. They simulate the logical tree structure within the Access Networks (AN),thus enabling selective information exchange with the individual NEs, as well as withtheir subordinate units.
Fig. 5.2 SISA Structure of FMX2R3.2 Network
(1) (30)
(30)(1)
(30)
OS
SISA-V
SISA-V SISA-V NE/SISA-V
SISA-V NE
NE
(1) OSU
SISA-V
(30) x (≤ 30)
SISA-V
NE
NE/SISA-V
(1) OSU
1 ... m
RS485
Plane 5
Plane (n − 1)
Plane n (≤ 10)
(Addr. 1-1)
(Addr. 1-1-3-2)Plane 4
Plane 3
Plane 2
Plane 1
NE
(3) SUE
SISA-V(Addr. 1-1-3)
(1) OSU (2) CUD(1) SUE
SISA-V
NE(Addr. 1-1-3-2-2)
(2) FMX2R3
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To this end, the network elements have the following properties:• Each NE has a specific TMN address.• This address is set with the help of backplane coding (effected by plug-in place) or
via DIL address switches (e.g. terminal panel or slide-in unit).• In the case of a faulty connection to the OS, the NEs can also be operated via the
F interface of SISA concentrators.• The NE default values are so set, that upon commissioning, a connection to the hi-
erarchically superordinate TMN component will always be established.• The NE automatically recognizes interface and bit rate, and adjusts itself in line with
these.
Since the individual NEs, whether related to the plug-in unit or the system as a whole,can exist in multiple form, identification calls for the use of a structured SISA address,see Fig. 5.2. In information exchanges FG conforms to second to the last, and FE thelast position of the SISA address, see Fig. 5.3.
Fig. 5.3 Example of a FMX2R3 Address
In general all QD2 addresses must always be unique since otherwise address collisionsoccur.
5.3 Access to MultiplexerThe multiplexer, including the various line cards, forms the SISA network elementFMX2R3. TMN access to the FMX2R3 is via the QD2 slave interface of the central unit.The network is addressed by backplane coding, with five bits for the CUD central unit.
The multiplexer and other NEs in the shelves SNUS and FMX2S are operated and mon-itored directly from the SUE supervision unit (-B1). The SISA addresses of the shelvescan be set, to guarantee unique addresses for the NEs. The QD2 bus inside the shelvesis switched to the QD2 master port of the SUE (stand-alone operation of the shelf), seeFig. 5.4.
The multiplexer in the shelf MXS19C is operated from the SUE supervision unit (-A2).All QD2 cables are to connect external.
In the ONU 20 FTTO, the multiplexer is operated and monitored via the built insupervision unit COSU.
Network termination units which are installed directly on the subscriber’s premises canbe remotely controlled via the multiplexer. The control and monitoring information istransmitted, e.g., in the D channel of the Uk0 interface of the IUL82C or IUL84C line card.
SISA address Sub address
1 1 3 2- - - : 120 - 01 CUD:
SISA-V(1. shelf, SUE)
FMX2R3(1. shelf)
OS-Port
SISA-V(1. shelf, CUD)
FG-No. FE
2-
OSU
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Fig. 5.4 Operation of System Modules in Standalone Operation of SNUS (Example)
The slave ports of a QD2 element synchronize automatically with their master data sig-nal and for their part use this clock pulse to send the responses. This is also the case ifthey are operated in a V.11 point-to-point connection. The slave ports have a T interface(bypass function) which switches the signal which is received from the master to otherslaves, and in the reverse direction switches the signal which is received from the post-connected slaves to the master. In this way the number of SISA hierarchical levels canbe reduced. For this application the bit rate is however limited to 9.6 kbit/s.
NE ASA32
LCTF
SISA-VLMX/V2
SUE
QD2 slave 1RS485/RS232
V.28
QD2 slave 2
Remote facilities
Internal QD2 bus
SISA-V
RS485primary redundant
CMXC
SISA-V
FMX2R3.2 SMX1/4c
SISA-V
Internal QD2 bus
OTSU2M
SISA-V
LT2ME1LTO/LT
SISA-V
(Uk0)D chan.
QD2-M
LTCOH/LTEC
C
NTU
T port (QD2 slave 1) to other NEsbit rate 9.6 kbit/s
LTO/NTLTCOH/NT
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5.4 DCN StructureThe control and supervision information is exchanged between the various locations to-gether with the transmission signal. For this reason the DCN structure for the operationand supervision of the systems is produced by the supervision structure of the networkused and ring, star and line structures must also be considered for the DCN.
DCN transmission is undertaken via specific DCN channels with bit rates of up to64 kbit/s.The following channels are available for the relevant shelves:
The interfaces of the DCN channels are connected directly via special cables to the QD2ports of a SISA concentrator. A switch is installed in the ONU 20 FTTO for selecting theDCN channel.
The following modules in the following housings are available as SISA concentrators:• SISA-GK/E in its own housing
This SISA concentrator consists of a slave port that is designed for the Ethernet.• SISAK in an MXS19C Shelf• OSU
– in a COMPS(2) Shelf– in an MPS Shelf– 6 x OSU in a OSU-R Shelf
The OSU is preferably used where a number of master ports are needed.• COSU in the ONU 20 FTTO.
OSU-R, MPS and COMPS(2) Shelf are described in user manual UMN Infrastructure(FastLink) SIEMENS Ordering No. A50010-A3-K419-*-7619.
DCN channel Shelf Bit rate
SNUS FMX2S MXS19C ONU20
FTTO
Overhead of the SMX1/4c
V.11 in direction east
V.11 in direction west
2 x
2 x
64 kbit/s
64 kbit/s
ECC 1 and 2 of the CMXC 2 x 64 kbit/s synchronous (with clock)
for connection to master port or for
connection to slave port of the
OSU if the T port is to operate syn-
chronously
ECC 3 and 4 of the CMXC 2 x 9.6 kbit/s or 64 kbit/s asynchro-
nous for connection to slave port
or for connecting the T port of the
OSU
ECC of the CUD 1 x 2 x 2 x 1 x 64 kbit/s
SUE T-port 2 x 2 x 2 x 9.6 kbit/s
OH64 of LTx 1 x 2 x per LTx 1 x 9.6 kbit/s asynchronous
Tab. 5.1 DCN Channels for Remote Operation of the FMX2R3.2
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5.5 Management in an SDH RingFor management in an SDH ring the following must be considered, see Fig. 5.1:• The access station
– Without DCN protection– With DCN protection
With DCN protection the DCN information is transmitted via different paths.– Use of a management system– Use of two management systems
The management systems are located at different stations in the network• Decoupling of the DCN information in further stations in the SDH ring
– Without DCN protection– With DCN protection– Use of a management system– Use of two management systems
• Decoupling of the DCN information in further stations in the ring with branch to line networks.
For transmission of the DCN information to the individual stations in the SDH ring theSDH overhead (V.11) is generally preferred. If this is not possible, the ECC channels ofthe CMXC are to be used. If this too is not possible, the ECC channel of the CUD is rec-ommended.
If a connection between the ECC of the CMXC and a master port of supervision unitOSU is established, the ECC should be operated synchronously (64 kbit/s). The clocklines should be wired for this purpose.
If a slave of the OSU is connected to the ECC, the ECC can be operated asynchronously(64 kbit/s) and the slave port of the OSU can be operated in bus mode.
With all these variants there is provision for transmission of the DCN information at 64kbit/s. The intention here is to have as few network elements as possible between thetopmost SISA concentrator and the remote network elements and thus enable perma-nently stable QD2 connections to be used.
5.5.1 SDH OverheadIf the OSU is used to transmit the data via the SDH overhead, a DCN protection is pos-sible independently of an existing payload protection.
The DCN information is transmitted in both directions (West and East) in the SDH ringvia master port 1 and 2 of the OSU in the access station. Slave ports 1 and 2 of the slaveOSUs in the other stations in the SDH ring, except for the last slave in each case beforethe ring closes, will be operated with the T port function. With the T ports there shouldbe strict adherence to the up and down direction. The clock lines of the slave ports withT port function must be wired. For DCN protection the slave OSUs must be switched toprotection mode via a switch on the unit. In this mode the OSUs can detect that they arebeing polled by 2 masters. Only one master request is ever answered.
DCN protection can relate exclusively to the QD2 network, but can also include the man-agement system. It is also possible to create a protection structure in branches or sub-rings.
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Fig. 5.5 DCN Transport via Overhead in an SDH Ring with One Management System
QD2-S 1OSU
QD2-M 1 QD2-M 2
QD
2-S
1Q
D2-
S 2 O
SU
QD
2-M
SMX1/4c
V.11 V.11
West EastSTM-1/STM-4STM-1/STM-4
updo
wn
updo
wnS
MX
1/4c
V.1
1V
.11
Eas
tw
est
SM
-1/S
TM
-4S
TM
-1/S
TM
-4
V.1
1
QD
2-S
1Q
D2-
S 2O
SU
QD
2-M
updo
wn
updo
wn S
MX
1/4c
V.1
1V
.11
Eas
tw
est
ST
M-1
/ST
M-4
ST
M-1
/ST
M-4
V.1
1
QD2-S 1QD2-S 2
OSU QD2-M
updownup down
SMX1/4c
V.11V.11EastWest
STM-1/STM-4 STM-1/STM-4
V.11 V.11
Access station
NMS
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If two management systems are to be used, this can be done in the way shown in thediagram below:
Fig. 5.6 DCN Transport via Overhead in an SDH Ring with Two Management Systems
Both management systems will be operated fully independently of one another.
5.5.2 Access via the ECCDCN access is via a supervision unit OSU. The cable for the DCN channel is connecteddirectly to the OSU and to a synchronous ECC port of the CMXC. On commissioning adigital point-to-multipoint circuit is created for the ECC of the CMXC. The point is formedby the ECC. The multipoints are switched in the direction of the SDH ring. Each remotestation in the ring represents a multipoint. The ECC occupies one 64-kbit/s time slot inthe 2-Mbit/s signal in each case. DCN protection is guaranteed by 1+1-SNC/I protectionswitching (Subnetwork Path Protection Connection) of the SMX1/4c.
Fig. 5.7 DCN Access via ECC in an SDH Ringwith One Management System
QD2-S 2QD2-S 1
OSU QD2-M
updownup down
SMX1/4c
V.11 V.11
QD2-S 2QD2-S 1
OSU QD2-M
updownup down
SMX1/4c
V.11V.11V.11 V.11
QD2-S 2QD2-S 1
OSU QD2-M
updownup down
SMX1/4c
V.11V.11
NMS 1 NMS 2
STM-1/STM-4
STM-1/STM-4
Internal DCN structuresee Section 5.3
E1 E1 E1 E1
E1 E1 E1 E1 E1
ECC 1
CMXC
SMX1/4c
STM1/STM1/
E1
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4QD2-S 1 QD2-S 2 OSU
T port
QD2-M 1 QD2-M 3QD2-M 2
V.11
64 kbit/s,
E1 with ECC
STM4STM4
P P.-to-M.
NMS
64 kbit/s, synchronous (with clock at the slave)V.11
asynchronous or synchronous
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When only one management system is connected, DCN path protection can also be cre-ated via two ECC ports of the CMXC, see Fig. 5.8.
Fig. 5.8 DCN Access via ECC in an SDH Ring with Redundant Transmission Path
The structure in Fig. 5.9 can be used for two management systems with separate paths.Within the SDH ring the two paths are protected via the 1+1-SNC/I-protection switchingof the SMX1/4c.
Fig. 5.9 DCN Access via ECC in an SDH Ringwith Two Management Systems
5.5.3 DCN Decoupling via ECCThe DCN information is transmitted via the ECC to the SNUS in point-to-point mode.The DCN information in the SNUS can be decoupled in both the CMXC and via theCUD. The CMXC possesses 4 ECC ports, of which port 1 is used in preference in thiscase and is connected to the QD2 slave port 1 of supervision unit SUE.
Internal DCN structuresee Section 5.3
E1 E1 E1 E1
ECC 1
CMXC
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
E1 (port B)
NMS64 kbit/s, asynchronousV.11
E1
64 kbit/s,synchronous,
E1 (port A)
(TS a) (TS b)with ECC with ECC
V.11
64 kbit/s,synchronous, V.11
E1 East
Master
TS b:WestTS a:
Slave
Trans-mission
equipment
E1
Trans-mission
equipmentMaster
Slave
Bus mode
Internal DCN structuresee Section 5.3
E1 E1 E1
E1 E1 E1 E1
ECC 1
CMXC
SMX1/4cSTM1/STM1/
E1
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4QD2-S 1 QD2-S 2 OSU
T port Bus mode
QD2-M 1 QD2-M 3QD2-M 2
V.1164 kbit/s, asynchronous
E1 with ECC
STM4STM4
PP.-to-M.
Local NMS64 kbit/s, synchronous (with clock at the slave)V.11
from the remote NMS
64 kbit/s, synchronous or asynchronous, V.11
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Fig. 5.10 DCN Decoupling via ECC in an SDH Ring
For applications with redundant management systems the configuration to be realizedis shown in Fig. 5.11.
Fig. 5.11 DCN Decoupling via ECC in an SDH Ringwith Two Management Systems
Internal DCN structuresee Section 5.3
E1 E1 E1 E1
E1 E1 E1 E1 E1
ECC 1
CMXC
SMX1/4c
STM1/STM4STM1/STM4
2 × PU16
CUC
1 32
E1
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1SUE
QD2-M 1 QD2-M 2
V.1164 kbit/s, asynchronous
E1 with ECC
QD2-S 2
Bus mode
Internal DCN structuresee Section 5.3
E1 E1 E1 E1
E1 E1 E1 E1 E1
ECC 1
CMXC
SMX1/4cSTM1/STM4STM1/STM4
2 × PU16
CUC
1 32
E1
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
V.1164 kbit/s, asynchronous
E1 with ECC ECCchannel 2
ECCchannel 1
Bus mode
asynchronous, 64 kbit/s,
V.11
NMS 1 NMS 2
Bus mode
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The DCN information can be decoupled via ECC with redundant transmission path asshown in Fig. 5.12 below:
Fig. 5.12 DCN Decoupling via ECC in an SDH Ringwith Redundant Transmission Path
E1
ECC 1
CMXC
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
V.11
64 kbit/s
E1 (Port x)
Transmission
E1
with 2 x ECC
synchr.
E1
E1
Internal DCN structuresee Section 5.3
equipment 1Transmissionequipment 2
T-P. T-P.
East West
TS aTS b
TS b TS a
E1 (Port y)with 2 x ECC
TS a and TS b TS a and TS b
1)1)
TS b:SlaveMaster 1)
MasterSlave
TS a: TS b:Slave 1)Master
MasterSlave
TS a:
1) The end points of the ring may not be closed. Therefore the following are omittedat endpoint 1 connection ECC 4 - QD2-S 2 (T port) and at endpoint 2 connection ECC 3 and QD2-S 1 (T port).
V.11
64 kbit/s asynchr.
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Fig. 5.13 shows the DCN decoupling in the SNUS with 2-Mbit/s line terminations (LTx)via which further units in line structures are connected. If in the CMXC the conferencecircuit is used for the ECC, this configuration can also be used for star structures. Theconfiguration shown supports DCN protection in the line networks too. DCN transmis-sion of two network management systems via two separate DCN paths is not supported.
This structure only makes sense if access is protected via SDH protection (1+1-SNC/I-protection of the SMX1/4c).
Fig. 5.13 DCN Decoupling via ECC in an SDH Ringwith Branch to Line Networks
Internal DCN structuresee Section 5.3
To line networks
E1 E1 E1 E1
E1 E1 E1 E1 E1
ECC 1
CMXC
SMX1/4cSTM1/STM1/
2 × PU16
CUC
1 32
E1
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
V.11
64 kbit/s
E1
STM4 STM4
LTx LTx LTx LTx LTx
E1 E1E1 E1 E1
with ECC
synchr.
V.11
64 kbit/s synchr.
Bus mode
V.11
64 kbit/s synchr.
V.11
64 kbit/s asynchr.
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Fig. 5.14 shows DCN decoupling via the ECC when line networks are branched froman SDH ring and for DCN protection a redundant management system is used.
Fig. 5.14 DCN Decoupling via ECC in an SDH Ring with Branch to Line Networks, Two Management Systems
E1 E1 E1 E1
E1 E1 E1 E1 E1
ECC 1
CMXC
SMX1/4cSTM1/STM1/
E1
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
V.11
64 kbit/s
ECC
STM4 STM4
LTx LTx LTx LTx LTx
E1 E1E1 E1 E1
To line networks
channel 1
asynchr.
V.11
64 kbit/s synchr.
P
P.-to-M.
Bus mode
V.11
64 kbit/s synchr.
NMS 1 NMS 2
V.11
64 kbit/s asynchr.
ECC channel 2
Bus mode
Internal DCN structuresee Section 5.3
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5.5.4 Node in an SDH RingThe branch from an SDH network is made by decoupling a 64-kbit/s channel of an E1signal. This channel is routed to the point of a point-to-multipoint conference. The mul-tipoints direct the DCN channel via E1 signals to the next network elements and theOSU at the node on the same hierarchy level. Slave port 1 of the OSU (in bus mode) isaccessed via the asynchronous ECC. For redundancy this part can be completely du-plicated.
The master ports of the OSU control the DCN transport of the underlying levels via oneor more conferences.
Fig. 5.15 DCN Decoupling via ECC in an SDH Ring at the Node
Internal DCN structuresee Section 5.3
To line networks
E1 E1 E1 E1
E1 E1 E1 E1 E1
ECC 1 CMXC
SMX1/4cSTM1/STM1/
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
V.11
64 kbit/s
E1
STM4 STM4
LTx LTx LTx
E1E1 E1
with ECC
asynchr.
V.11
64 kbit/s synchr.
PP.-to-M.PP
E1 E1
E1 E1 E1
V.11
64 kbit/s asynchr.
Bus mode Bus mode
V.11
64 kbit/s synchr.
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5.6 Management in a Line Network
5.6.1 Access of the Network Management SystemThe DCN is accessed via an SNUS at the end of a line network. DCN path protectioncan be established if only one management system is used, see Fig. 5.16.
Fig. 5.16 DCN Access via ECC in a Line Networkwith DCN Protection
Applications with two management systems require separate DCN paths. The two DCNpaths cannot be protected additionally. Fig. 5.17 shows the structure needed for bothmanagement systems.
Fig. 5.17 DCN Access via ECC in a Line Network with Two Management Systems
Internal DCN structuresee Section 5.3
LTx LTx LTx
E1 E1 E1
DCNLTx LTx LTx
E1 E1 E1
E1 E1 E1 E1
ECC 1
CMXC
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
E1
NMS64 kbit/s, asynchronousV.11
E1
E1ECC chann. 1 ECC chan.2
protection-path
64 kbit/s, synchronous, V.11
64 kbit/s, synchronous, V.11
Bus mode
Internal DCN structuresee Section 5.3
LTx LTx LTx
E1 E1 E1
Second
LTx LTx LTx
E1 E1 E1
E1 E1 E1 E1
ECC 1
CMXC
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4QD2-S 1 QD2-S 2 OSU
T port Bus mode
QD2-M 1 QD2-M 3QD2-M 2
Local NMS 164 kbit/s, synchronous (with clock at the slave)V.11
E1
64 kbit/s, asynchronousV.11from the remote NMS 2
E1E1ECC channel 1 ECC chan. 2
DCN path
64 kbit/s, synchronousor asynchronous, V.11
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5.6.2 DCN Decoupling via ECC in a Line NetworkIf no other management system is used, the DCN information is decoupled in the sameway as in ring structures, see Fig. 5.12. Fig. 5.18 shows the configuration to be estab-lished for applications with a redundant management system.
Fig. 5.18 DCN Decoupling via ECC in a Line Networkor Star Network with Two Management Systems
5.6.3 DCN Decoupling in the FMX2S in the Line NetworkThe DCN information should preferably be decoupled via the ECC channel of the CUD,see Section 5.3.
Internal DCN structuresee Section 5.3
E1 E1 E1
ECC 1
CMXC
RS48564 kbit/s, asynchronous
ECC 2 ECC 3 ECC 4
QD2-S 1 QD2-S 2 OSU
QD2-M 1 QD2-M 3QD2-M 2
V.11
64 kbit/s
E1
LTx LTx
E1 E1
DCN path for 2. NMS
with ECC
asynchr.
LTx LTx
E1 E1
E1
P P
P.-to-M. P.-to-M.
Bus modeV.11
64 kbit/s asynchr.
Bus mode
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5.7 DCN Structures with MXS19C
5.7.1 ECC Channel (64 kbit/s or 9.6 kbit/s)On the local side there is a point-to-point connection between the master port of theSISAK unit and the ECC interface of central unit CUD. The ECC occupies one time slotin the 2-Mbit/s signal. The transmission rate 64 kbit/s or 9.6 kbit/s is set at the masterport. For synchronous 64-kbit/s transmission the operating modes of synchronous onthe local side and asynchronous on the remote side are to be selected. The control in-formation is transmitted on the remote side via the ECC interface of the CUD to the slaveport of the SUE.
Fig. 5.19 ECC Channel (64 kbit/s or 9.6 kbit/s)
Fig. 5.20 ECC in the Central Station
CUD
.QD2-S
CUD
QD2-S
CUD
QD2-M 1
QD2-S
SUE
LCQD2-S
QD2-S
CUD
QD2-S
SISAK
QD2-M 1
64 kbit/s
.
LC
LC
LC
LC
LC
LC
LC
QD2-S
CUD
QD2-M 1
QD2-S
SUE
LC LC
E1A E1B
F19,2 kbit/s
64 kbit/s
2 Mbit/s 2 Mbit/s
ECC
ECCECC
F19,2 kbit/s
QD2-S
SUE
QD2-M 1
19,2 kbit/sF
64 kbit/sor 9,6 kbit/s
64 kbit/s or 9,6 kbit/s
64 kbit/s or 9,6 kbit/s
64 kbit/s or 9,6 kbit/s
64 kbit/s
NMS
Central stationLine networkRemote station
1) Internal connection in the MXS19C via switch
1) 1)1) 1) 1)
SUE CUD
2)
SISAK
ECC
QD2Mout_a1QD2Mout_b1QD2Min_a1QD2Min_b1
14b14a
12b12a
SD1inaSD1inb
SD1outaSD1outb
4c4b
6c6b
MD1inRaMD1inRbMD1outRaMD1outRb
20c20b22c22b
TBTA
RBRA
22a20a
4a2a
X101 X118X118 X110
22b22a
20b20a
X101 1)
1) There is an internal connection inside the MXS19C.2) To subordinate station
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Fig. 5.21 ECC in the Line Network and in the Remote Station
5.7.2 Overhead Channel (9.6 kbit/s)When the overhead channel of a line termination unit (LTx) is used as a transport chan-nel the data is transmitted at 9.6 kbit/s using oversampling. On the local side there is apoint-to-point connection between master port of unit SISAK and the overhead channelof the line termination unit.
On the remote side the overhead signal of the line termination unit will be passed to theQD2 slave port of the SUE.
Fig. 5.22 Overhead Channel (9.6 kbit/s)
SUE CUD
2)ECCTBTA
RBRA
22a20a
4a2a
X101 X110
22b22a
20b20a
X1011)
1) There is an internal connection inside the MXS19C.2) From superordinate station
QD2Sin_b1QD2Sin_a1QD2Sout_b1QD2Sout_a1
2a2b
4a4b
.
2 Mbit/s
QD2-S
CUD
QD2-S
CUD
OH
LCQD2-S
CUD
QD2-S
CUD
OHOverhead
QD2-S
LC
LC
LC
LC
LC
LC
LC
2 Mbit/s
Overhead
.
QD2-S
CUD
.
OH
LC LC
OH
QD2-S
E1A E1B
SISAK
QD2-S
QD2-M
19,2 kbit/s FQD2-S1
QD2-M1SUE
64 kbit/s
9,6 kbit/s
.64 kbit/s
64 kbit/s
...SISAK
QD2-S
QD2-M
19,2 kbit/s FQD2-S1
QD2-M1SUE
64 kbit/s
9,6 kbit/s
....19,2 kbit/s
FQD2-S1
QD2-M1SUE
9,6 kbit/s
1)1)1)
9,6 kbit/s
LTx(LT)
LTx(NT)
LTx(LT)
LTx(NT)
Central stationLine networkRemote station
1) Internal connection in the MXS19C via switch
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Fig. 5.23 Overhead Channel in the Central Station with LTO
Fig. 5.24 Overhead Channel in the Line Network with LTO
SUESISAK
QD2Min_b1QD2Min_a1QD2Mout_b1QD2Mout_a1
12a12b
14a14b
SD1outaSD1outb
SD1inaSD1inb
6c6b4c4b
X101X118 X118
To the QD2 bus1)
1) There is an internal connection inside the MXS19C.2) To subordinate station
MD1outRaMD1outRb
MD1inRaMD1inRb
22c22b
20c20b
3)
3) Only the OH channel of one LTO is allowed to be connected
LTO/LT
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
2)
LTO/LT
O64in-bO64in-aO64out-bO64out-a
15b10b
15a10a
2)
LTO/LT
O64in-bO64in-aO64out-bO64out-a
11b27b
11a25b
2)
SlotLC/LTx
Slot202
Slot 203
X101
X101
1) From superordinate station2) To subordinate station
SISAK
SD1outaSD1outb
SD1inaSD1inb
6c6b4c4b
X118 X118
SUE
QD2Min_b1QD2Min_a1
QD2Mout_b1QD2Mout_a1
12a12b14a14b
X101X101
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
LTO/LT
2)
SlotLC/LTx
MD1outRaMD1outRb
MD1inRaMD1inRb
22c22b
20c20b
QD2Sout_b1QD2Sout_a1
QD2Sin_b1QD2Sin_a1
4a4b
2a2b
3) Only the OH channel of one LTO is allowed to be connected
3)3)LTO/LT
O64in-bO64in-aO64out-bO64out-a
15b10b
15a10a
2)
LTO/LT
O64in-bO64in-aO64out-bO64out-a
11b27b
11a25b
2)
Slot202
Slot 203
X101
X101
LTO/NT
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
1)
LTO/NT
O64in-bO64in-aO64out-bO64out-a
1)
LTO/NT
O64in-bO64in-aO64out-bO64out-a
1)
Slot202
Slot203
X101
X101
Slot LC/LTx
15b10b
15a10a
11b27b
11a25b
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Fig. 5.25 Overhead Channel in the Remote Station with LTO
Fig. 5.26 Overhead Channel in the Central Station with LT2ME1
SUEX101
1) From superordinate station
QD2Sout_b1QD2Sout_a1
QD2Sin_b1QD2Sin_a1
4a4b
2a2b
2) Only the OH channel of one LTO is allowed to be connected
2)
LTO/NT
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
1)
LTO/NT
O64in-bO64in-aO64out-bO64out-a
1)
LTO/NT
O64in-bO64in-aO64out-bO64out-a
1)
X101
X101
Slot 202
Slot203
SlotLC/LTx
15b10b
15a10a
11b27b
11a25b
SUESISAK
QD2Min_b1QD2Min_a1QD2Mout_b1QD2Mout_a1
12a12b
14a14b
SD1outaSD1outb
SD1inaSD1inb
6c6b4c4b
X101X118 X118
To the QD2 bus1)
1) There is an internal connection inside the MXS19C.2) To subordinate station
MD1outRaMD1outRb
MD1inRaMD1inRb
22c22b20c20b
3) Only the OH channel of one LT2ME1 is allowed to be connected
3)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
2)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
15b10b
15a10a
2)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
11b27b
11a25b
2)
SlotLC/LTx
Slot202
Slot 203
X101
X101
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Fig. 5.27 Overhead Channel in the Line Network with LT2ME1
Fig. 5.28 Overhead Channel in the Remote Station with LT2ME1
1) From superordinate station2) To subordinate station
SISAK
SD1outaSD1outb
SD1inaSD1inb
6c6b4c4b
X118 X118
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
LT2ME1
1)
SUE
QD2Min_b1QD2Min_a1
QD2Mout_b1QD2Mout_a1
12a12b14a14b
X101X101
O64in-bO64in-aO64out-bO64out-a
LT2ME1
1)
O64in-bO64in-aO64out-bO64out-a
LT2ME1
1)
Slot202
Slot203
X101
X101
Slot LC/LTx
15b10b
15a10a
11b27b
11a25b
MD1outRaMD1outRb
MD1inRaMD1inRb
22c22b20c20b
QD2Sout_b1QD2Sout_a1QD2Sin_b1QD2Sin_a1
4a4b
2a2b
3) Only the OH channel of one LT2ME1 is allowed to be connected
3)
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
LT2ME1
2)
SlotLC/LTx
3)LT2ME1
O64in-bO64in-aO64out-bO64out-a
15b10b
15a10a
2)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
11b27b
11a25b
2)
Slot202
X101
X101
SUEX101
1) From superordinate station
QD2Sout_b1QD2Sout_a1QD2Sin_b1QD2Sin_a1
4a4b
2a2b
2) Only the OH channel of one LT2ME1 is allowed to be connected
2)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
14c12c
14a12a
1)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
1)
LT2ME1
O64in-bO64in-aO64out-bO64out-a
1)
X101
X101
Slot 202
Slot203
SlotLC/LTx
15b10b
15a10a
11b27b
11a25b
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5.8 Software ManagementThe software management of the AccessIntegrator supports the following operationtasks:• APS Management• Backup and restore of network element data.
The functions of the software management are described in detail in OMN AccessInte-grator. The data management and the memory structure of the FMX2R3.2 are describedin this section.
5.8.1 Memory StructureThe entire software (SW) and firmware (FW) and all data of the network elements arestored in non-volatile memories of the NEs. Additionally backup versions are stored inthe ACI for restoring the configuration in the event of failure.
To administer the software and data each of the plug-in units has a processor compo-nent consisting of the microcontroller and various memory chips (FEPROM, EEPROM,RAM). The microcontroller controls the internal functional sequences on the individualplug-in units in each case. The memory chips are used for SW and data saving.
FW runs in FEPROMs and can only be changed by replacing these components.
Units with loadable SW are equipped with volatile memory (RAM) and non-volatile mem-ory (FEPROM, EEPROM). Software and data for these units can be loaded from theLCT or centrally from the OS (SW download). The RAM contains the running SW and isloaded from FEPROM by the bootstrap program. The bootstrap program itself is storedin FEPROM or PROM. The line cards (LCs) obtain their bootstrap program, which is alsostored in the RAM of these units.
The FEPROM contains that subset of RAM data which has to survive recovery and pow-er failure, so called semipermanent data. These data are determined during start-up bythe unit itself (e.g. NE address setable via binary switch, HW configuration of the NE) orentered via F/QD2 interface as configuration data. The RAM contains data which are notstored in FEPROM, so called transient data (e.g. call processing data).
In addition, the level data are stored in non-volatile memories, which contain the manu-facturer data of each plug-in unit, e.g. name of plug-in unit, product number, device num-ber, software version. These data can be requested via the operation manual.
5.8.2 Data ManagementThe software download requires a bootstrap. The bootstrap contains the boot SW andall functions necessary for the process of SW loading (local and remote SW download).With help of the boot software the NEs of the system modules report their address to theOS or LCT and are now displayed on the screen. The software download can be initiatedand loads the SW to the FEPROM of central units and supervision units. If the SW in theFEPROM are corrupted you get an alarm message PNV (program not valid), otherwisethe SW is unpacked and loaded into the RAM of that units and the associated line cards(LCs), see Fig. 5.29.In case of errored data in the RAM an automatic reloading fromFEPROM to RAM is performed.
The data of system modules (e. g. configuration, SW version) are kept as non-volatiledata in the corresponding central units and supervision units and can be checked by theACI or LCT. So the central units kept data for the line cards.
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In case of SW update, the actual SW version goes on working in RAM. The new SWversion is loaded into the RAM overwriting the current SW version. If there is a distur-bance during loading, the current SW version on the FEPROM will not longer be avail-able. The plug-in unit cannot be booted. Loading must be repeated. A reset must alwaysbe done when a new SW has been loaded so that the plug-in unit can boot.
Line cards of the same type can be replaced during operation and are then loaded au-tomatically with data stored in the plug-in unit.
Line cards of different types which are exchanged during running system modules, canresult in the following failure messages:• Errored SW, if there is no SW for that type stored in Central Unit• Errored configuration data (e. g. ISDN data cannot be loaded to ports).
These errors are not affecting other line cards. The errors can be cleared by softwaredownload or new configuration of the data.
Fig. 5.29 Software Download
5.9 LoopsThe following loops can be switched for test purposes using the operation program:• Local loop
Local loop on the MUX side; in this case, an AIS signal is output via E1out• Remote loop
Remote loop on the external side; in this case, the channels on the F2 side of the multiplexer are blocked.
Bootstrap(write protected)
Buffer storefor SW and data
FEPROM
SW download/update
SW, data
Boot
SW, data
RAM
Boot
Bootstrap Operation SW
RAM/EEPROM
Start SW
Start SW
CUD,
SUE
LCs
RESET(HW/SW)
RESET(HW/SW)
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6 Product Overview
Designation Product number Dimensionsin mm
W × H × D
Weightin kg
Shelves, ModulesFMX2S S42023-A862-A1 535 × 400 × 240 10
(Dead-weight)
SNUS S42023-A863-A1 535 × 400 × 240 10(Dead-weight)
MXS19C S42023-A799-C1 483 × 264 × 190 4.5(Dead-weight)
ONU 30 FTTB S42022-A768-B1 440 × 535 × 260 20Power supply for ONU 30 FTTB S42023-A910-A6 142 × 129 × 225 0.9
ONU 20 FTTO S42022-A768-B5 370 × 165 × 247 7Power supply for ONU 20 FTTO(with battery backup)
V39113-Z5270-A610 170 × 57 × 108 0.5
Over-voltage protection 20 A for CE V39118-Z6004-A62Terminal panels of ONU 20 FTTO:
Central Terminal panel(9 pin Western jack)
S42024-A1867-A1
Central Terminal panel(8 pin Sub-D-jack)
S42024-A1867-A2
Central Terminal panel(coax jacks)
S42024-A1867-A3
LC terminal panel Ethernet S42024-A1867-A4LC terminal panel UNI1 S42024-A1867-A18LC terminal panel for UAC68 S42024-A1867-A16LC terminal panel for CPF2 S42024-A1867-A17LC terminal panel for I8S0P S42024-A1867-A19LC terminal panel for CM64/2 S42024-A1867-A20LC terminal panel for DSC104Cand DSC6-nx64C S42024-A1867-A21
S0 power supply (optional for I8S0P) V39113-Z5240-A680V.24 adapter cable (25-pin Sub-D) S42022-A768-S56OF patch cord (Single mode-multi mode) C39195-Z113-C603LCT cable (universal) S42023-A877-S100
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Plug-in unitsADM1eAdd/drop multiplexer2 × STM-1 (electrical), 120 Ω
DMM: 3366000648382 35 × 234 × 160 0.5
ADM1oAdd/drop multiplexer2 × STM-1 (optical), short haul, 75 Ω
DMM: 3344AAD128342 35 × 234 × 160 0.6
ADM1oAdd/drop multiplexer2 × STM-1 (optical), short haul, 120 Ω
DMM: 3344AAD148382 35 × 234 × 160 0.6
ADM1oAdd/drop multiplexer2 × STM-1 (optical), long haul, 75 Ω
DMM: 3344BBD128342 35 × 234 × 160 0.6
ADM1oAdd/drop multiplexer2 × STM-1 (optical), long haul, 120 Ω
DMM: 3344BBD148382 35 × 234 × 160 0.6
ADM4Add/drop multiplexer2 × STM-4 (optical), short haul, 120 Ω
DMM: 3644AAD148382 35 × 234 × 160 0.6
ADM4Add/drop multiplexer2 × STM-4 (optical), long haul, 120 Ω
DMM: 3644BBD148382,DMM: 3644CCD148382
35 × 234 × 160 0.6
BECBus extension unit
S42024-A1878-A1 20 × 234 × 160 0.3
CM64/2Channel multiplexer
S42024-A1763-A1 20 × 234 × 160 0.4
COSUSupervision unit of ONU 20
S42024-A1866-B1 20 × 220 × 120 0.4
Designation Product number Dimensionsin mm
W × H × D
Weightin kg
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CPF2 (basis unit)Digital signal channel
S22546-A5100-A1 20 × 234 × 160 0.2
CPF2 (modules):CIM-64V24Module V.24
S22546-A5110-A1 15 × 83 × 65 0.03
CIM-n× 64V35Module V.35
S22546-A5130-A1 15 × 83 × 65 0.02
CIM-n× 64V36Module V.36
S22546-A5140-A1 15 × 83 × 65 0.02
CIM-n× 64X21Module X.21
S22546-A5120-A1 15 × 83 × 65 0.03
CIM-n× 64EModule Ethernet
S42025-A1415-A1 15 × 83 × 65 0,03
CUCCentral unit in CMXC
S42024-A1899-B1 20 × 234 × 160 0.3
CUDCentral unit in FMX2R3.2
S42024-A1851-D1 20 × 234 × 160 0.4
DSC6-n× 64CDigital signal channel
S42024-A1767-C1 20 × 234 × 160 0.4
DSC104CDigital signal channel
S42024-A1738-C1 20 × 234 × 160 0.4
FAMFan and Alarm Module
S42024-A1840-A3 20 × 105 × 160 0,4
I4UK2NTPISDN line card 2B1Q
S42024-A1761-A4 20 × 234 × 160 0.4
I4UK4NTPISDN line card 4B3T
S42024-A1762-A4 20 × 234 × 160 0.4
I8S0PISDN line card S0
S42024-A1870-B1 20 × 234 × 160 0.4
IUL82CWith power contact protection
S42024-A1838-C1 20 × 234 × 160 0.4
Designation Product number Dimensionsin mm
W × H × D
Weightin kg
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IUL84CISDN line card 4B3T
S42024-A1838-C2 20 × 234 × 160 0.4
LLA102/104CLeased line analog 2-wire/4-wire
S42024-A1810-B1 20 × 234 × 160 0.4
LTO/LTLine terminating unit 2× 2 Mbit/s,exchange side, medium power
S42024-A1799-C202 25 × 234 × 160 0.3
LTO/NTLine terminating unit 2× 2 Mbit/s,Subscriber side, medium power
S42024-A1799-C302 25 × 234 × 160 0.3
LT2ME1 (basis unit)Line terminating 2-Mbit/s
S42024-A1913-B1 25 × 234 × 160 0.2
LT2ME1 (modules):Uk2mPUk2 with remote power feeding
S42025-A1410-A1 15 × 83 × 137 0.1
G.703shG.703 module, short haul
S42025-A1414-A1 15 × 83 × 137 0.04
SDSLop2-wire SHDSL without remote power feeding
S42024-A304-A1 15 × 83 × 137 0.04
SDSLmp2-wire SHDSL with remote power feeding
S42024-A304-A2 15 × 83 × 137 0.04
SDSL4op4-wire SHDSL without remote power feeding
S42024-A315-A1 15 × 83 × 137 0,04
T4Clock module T4, only with SDSL4op
S42024-A316-A1 15 × 83 × 137 0,04
Ethernet modulewith one 10/100Base-T interface
S42025-A1415-A2 15 × 83 × 137 0,04
MSUESupervision unit ONU 30 FTTB
S42024-A1841-A2 20 × 234 × 160 0,4
OTSU2MOptical terminal supervision unit
S42024-C3231-C1041) 20 × 234 × 160 0.5
PSDPower supply unit in SMX1/4c
S42024-A1901-B1 35 × 234 × 160 0.7
PU162-Mbit/s interface unit
S42024-A1900-A1 15 × 234 × 160 0.3
1) Without F interfaces
Designation Product number Dimensionsin mm
W × H × D
Weightin kg
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SEM106CE&M subscriber converter, 2-wire
S42024-A1737-B1 20 × 234 × 160 0.6
SEM108HCE&M subscriber converter, 2-wire
S42024-A1737-B2 20 × 234 × 160 0.6
SISAKSISA Concentrator
S42024-A1781-A1 20 × 234 × 160 0,6
SLB62Subscriber converter, local battery
S42024-A1760-A1 20 × 234 × 160 0.6
SLX102Subscriber converter, exchange side
S42024-A1809-C11 20 × 234 × 160 0.6
SLX102ESubscriber converter, exchange side
S42024-A1809-A12-A13-A14
20 × 234 × 160 0.6
SUESupervision unit for shelves
S42024-A1857-B1 20 × 234 × 160 0.5
SUB102Subscriber converter, subscriber side
S42024-A1804-C1 20 × 234 × 160 0.6
TC1E3Tributary extender unit1 × 34 Mbit/s
DMM: 331502102 15 × 234 × 160 0.4
TC21E1Tributary extender unit 21 × 2 Mbit/s, 120 Ω
DMM: 331201104 15 × 234 × 160 0.4
TC21E1RExtension unit with retiming21 × 2 Mbit/s, 120 Ω
DMM: 331201105 15 × 234 × 160 0.4
UAC68Universal line card
S42024-A1898-A1 20 × 234 × 160 0.3
Designation Product number Dimensionsin mm
W × H × D
Weightin kg
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7 AbbreviationsACI Management System AccessIntegrator Managementsystem AccessIntegrator ADPCM Adaptive Difference Pulse Code Modulation Adaptive Differenz Puls Code Modulation AIS Alarm Indication Signal Dauer 1 Alzst Alarm state Alarmzustand APS Application Software Applikationssoftware BER Bit Error Rate Bitfehlerhäufigkeit CAMS CAM Shelf Baugruppenträger für CAM CAS Channel Assigned Signaling Kanalzugehörige Signalisierung CC Crossconnections CIM Customer Interface Module Schnittstellenmodul CMXC Crossconnect Multiplexer Compact Crossconnectmultiplexer kompakt COMPS2 Central FastLink Measurement and Power
SupplyFastLink Zentralshelf
CPF Line Card (channel processor card for fast data)
Kanalkarte, Datenanschlusskarte
CRC Cyclic Redundancy Check Zyklische Redundanzprüfung CUD Central Unit Drop/Insert Abzweigzentraleinschub DCE Data Circuit Equipment Datenübertragungseinrichtung (DÜE) DCN Data Communication Network SISA-Datennetzwerk DDF Digital Distribution Frame 2-Mbit/s-Verteiler DEE Data Terminal Equipment (DTE) Datenendeinrichtung DIMX Drop/Insert Multiplexer Abzweigmultiplexer DMA Direct Memory Access Direktspeicherzugriff DSC Digital Signaling Unit Digitalsignalkanal DTE Data Terminal Equipment Datenendeinrichtung (DEE) DÜE Data Transmission Equipment Datenübertragungseinrichtung E&M Earth and Minus ECC Embedded Control Channel Integrierter Steuerkanal EEPROM Electrically Erasable Programmable Read-
Only MemoryElektrisch löschbarer programmierbarer Festw-ertspeicher
EMC Electromagnetic Compatibility Elektromagnetische Verträglichkeit ESD Electro Static Device Elektrostatisch gefährdete Baugruppe ETSI European Telecommunications Standards
InstituteEuropäisches Normungsinstitut für die Fernmelde-technik
FA Foreign Connection Fremdanschaltung FAM Fan and Alarming Module Lüfter- und Alarmierungsbaugruppe FEPROM Partially Alterable Several Times Read Only
MemoryNur teilweise mehrmals beschreibbarer Festw-ertspeicher
FMX Flexible Multiplexer Flexibler Multiplexer FMX2R3.2 Flexible Multiplexer (Second Generation)
Release 3.2Flexibler Multiplexer (2. Generation) Release 3.2
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FMX2S FMX2 Shelf Baugruppenträger für FMX2 FMX2V2 Flexible Multiplexer (Second Generation)
Release 2Flexibler Multiplexer (2. Generation) Release 2
FO Fibre Optical Optische Faser FPGA Field Programmable Gate Array anwenderprogrammierbarer Baustein FTTO Fiber to the Office FW Firmware GB Motherboard Grundbaugruppe HDB3 High Density Bipolar of Order 3 HDLC High Level Data Link Control Datenübertragungsprotokoll HW Hardware IF Interface Schnittstelle ISDN Integrated Services Digital Network Diensteintegrierendes digitales Nachrichtennetz ITU International Telecommunication Union Internationale Fernmeldeunion KP Channel in Service Kanal im Prüfzustand LAN Local Area Network Lokales Netz LC Line Card Kanaleinschub LCT Local Craft Terminal Lokales Bedienterminal LL Leased Lines Festverbindungen LOC Loss of Clock Taktausfall LOF Loss of Frame Rahmensynchronverlust LOS Loss of Signal Synchronausfall LT Line Termination Leitungsabschluss LTx 2-Mbits Line Termination Unit 2-Mbit/s-Leitungsendeinschub MDF Main Distribution Frame Hauptverteilerrahmen MTA Metallic Test Access MUX Multiplexer Multiplexer MXS19C 19-inch Multiplex Shelf 19-Zoll-Multiplexeinsatz NE Network Element Netzelement NMS Network Management System Netzmanagementsystem NT Network Termination Netzabschluss NTBA Network Termination Basic Access Netzabschlussgerät NTU Network Termination Unit Netzabschlussgerät ODF Optical Distribution Frame Passiver Optischer Verteiler OF Optical Fiber Glasfaser OH Overhead Channel Overheadkanal OMIX Open Module Interface for xDSL einheitliche Modulschnittstelle für xDSL ONU Optical Network Unit Teilnehmernahe Einrichtung OS Operation System Betriebssystem OSU Operation and Supervision Unit from
FastLinkBedienungs- und Überwachungseinschub von FastLink
OVP Over-Voltage Protection Überspannungsschutz
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P-APS Partial APS Teil-APS PCB Printed Circuit Board Leiterplatte PCI Peripheral Core Interface Periphere Schnittstelle PCM Pulse Code Modulation Puls Code Modulation PNV Program not valid Programm-Datei ungültig POTS Plain Old Telephone Service Konventioneller Fernsprechdienst PROM Programmable Read-Only Memory Programmierbarer Festwertspeicher QD2 Network Management Protocol Netzmanagement-Protokoll QD2-M QD2-Masterport QD2-Masterschnittstelle QD2-S QD2-Slaveport QD2-Slaveschnittstelle RAM Random-Access Memory Direktzugriffsspeicher (Hauptspeicher) RTU Remote Test Equipment Fernes Messgerät S-APS System APS System-APS SDH Synchronous Digital Hierarchy Synchrone Digital-Hierarchie SHDSL Symmetric High-Bit Rate Digital Subscriber
Line SISA Supervisory and Information System for Lo-
cal AreasSteuer- und Überwachungssystem für Übertragung-snetze
SISA-K SISA Concentrator SISA-Konzentrator SISA-V Virtual SISA Concentrator Virtueller SISA-Konzentrator SNC Synchronous Network Connection SNMP Simple Network Management Protocol Einfaches Netzverwaltungsprotokoll SNUS Service Network Unit Shelf Baugruppenträger für universelle Dienste SW Software SYN Synchronization Synchronisation TDM Time Division Multiplexer Zeitmultiplexsystem TE Terminal Equipment Endgerät TM Transmission Module Übertragungsmodul TMN Telecommunication Management Network TMX Terminal Multiplexer Terminalmultiplexer TS Time Slot Zeitschlitz TU Tributary Unit of SMX1/4c Einschub Tributary des SMX1/4c VSt Exchange Vermittlungsstelle
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