formal equivalence checking

Formal Equivalence Checking

Virendra Singh Associate Professor

Computer Architecture and Dependable Systems Lab Dept. of Electrical Engineering

Indian Institute of Technology Bombay, Mumbai [email protected]

EE 709: Testing & Verification of VLSI Circuits

Lecture – 6 (Jan 17, 2012)

System level

SoC Verification

• System-on-Chip (SOC) design

• Increase of design complexity

• Move to higher levels of abstraction

1E0

1E1

1E2

1E3

1E4

1E5

1E6

1E7

Number of components Level

Gate

RTL

Algorithm

Transistor

Abstr

action

Accura

cy

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System-on-Chip (SoC) design

• Specification to architecture and down to implementation

• Behavior (functional) to structure – System level: system specification to system architecture – RT/IS level: component behavior to component micro-

architecture

Specification

+ constraints

Memory

Memory

µProcessor

Interface

Comp. IP

Bus

Interface

Interface

Interface

Custom HW

System architecture

+ estimates

Processors

IPs

Memories

Busses

RTL/IS Implementation

+ results

Registers

ALUs/FUs

Memories

Gates

Mem RF State

Control

ALU

Datapath

PC

Control Pipeline

State

IF FSM

State

IF FSM IP Netlist

RAM

IR

Memory

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13%

15%

16%

17%

17%

17%

26%

32%

32%

51%

0% 10% 20% 30% 40% 50% 60%

Delay Calculation

Synthesis

Static Timing Analysis

Design Rule Checking

System on Chip

Parasitic Extraction

Post Layout Optimization

Place & Route

Design Creation

Simulation/Design Verification

Bottlenecks in Design Cycles: Survey of 545 engineers by EETIMES 2000

Verification challenge

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System-level design & verification

Remove as many bugs as possible in the earlier stages

Do not introduce new design errors when refining designs

Formal verification in system-level designs:

Property checking and equivalence checking

System-level

RTL

Transistor level

Bugs fix time Cost due to the delay/late time-to-market

revenue loss

3 minutes delay

3 days delay

3 weeks delay

5

Spec

Formal verification • “Prove” the correctness of designs

– Both design and spec must be represented with mathematical models

– Mathematical reasoning

– Equivalent to “all cases” simulations

• Possible mathematical models – Boolean function (Propositional logic)

• How to represent and manipulate on computers

– First-order logic

• Need to represent “high level” designs

– Higher-order logic

• Theorem proving = Interactive method

• Front-end is also very important – Often, it determines the total performance of the

tools

Mathematical models

Design

Front-end tool

Verification engines

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Spec

Backgrounds technology in formal verification

• Methods for reasoning about mathematical models – Boolean function (Propositional logic)

• SAT (Satisfiability checker)

• BDD (Binary Decision Diagrams)

– First-order logic

• Logic of uninterpreted functions with equality

– Higher-order logic

• Theorem proving = Interactive method

Mathematical models

Design

Front-end tool

Verification engines

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8


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• Equivalence checking can be applied at or across various levels

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CEC in Practice

Key observation: The circuit being verified usually have a number of internal equivalent functions

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a

b

c

a

b

c

f = ab + c

F’ = (a+ c)(b+c)

a b c f

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

Canonical Forms

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Complexity

Efficiency of the conversion to canonical form

Memory requirement

Efficiency of the comparison of two representation of the canonical form

Efficiency to generate the counter example in case of a miscompare

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A T 0

A

C

B O 1

T 1

T 2

B C

O 2 3

Diff 1

1

0 0

1

1 1

1

1

1

0

• Satisfiability Formulation

– Search for input assignment giving different outputs

• Branch & Bound

– Assign input(s)

– Propagate forced values

– Backtrack when cannot succeed

• Challenge

– Must prove all assignments fail

• Co-NP complete problem

– Typically explore significant fraction of inputs

– Exponential time complexity

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Canonical form representation is only suitable

DNF and CNF are not suitable

BDD is most popular canonical form

graphical representation of boolean function

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BDD is canonical form of representation

Shanon’s expansion theorem

f(x1, x2, ….xi, ……xn) =

xi.f(x1, x2, … ,xi=1, ……xn) +

xi’. f(x1, x2, … ,xi=0, ……xn)

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f(x1, x2, … ,xi=1, ……xn)

xi

f(x1, x2, … ,xi=1, ……xn)

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Binary Decision Diagram

• Generate Complete Representation of Circuit Function – Compact, canonical form

Functions equal if and only if representations identical

Never enumerate explicit function values

Exploit structure & regularity of circuit functions

A

C

B

O1

T1

T2

A

BC

O2

T3

b

0 1

c

a

b

0 1

c

a

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Decision Structures

Truth Table Decision Tree

Vertex represents decision

Follow green (dashed) line for value 0

Follow red (solid) line for value 1

Function value determined by leaf value.

0 0

x3

0 1

x3

x2

0 1

x3

0 1

x3

x2

x100001111

00110011

01010101

00010101

x1 x2 x3 f

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Variable Ordering

Assign arbitrary total ordering to variables

e.g., x1 < x2 < x3

Variables must appear in ascending order along all paths

OK Not OK

Properties

No conflicting variable assignments along path

Simplifies manipulation

x1

x2

x3

x1

x3

x3

x2

x1

x1

x1

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Reduction Rule #1

Merge equivalent leaves

a a

0 0

x3

0 1

x3

x2

0 1

x3

0 1

x3

x2

x1

x3 x3

x2

x3

0 1

x3

x2

x1

a

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Reduction Rule #2

y

x

z

x

Merge isomorphic nodes

x3 x3

x2

x3

0 1

x3

x2

x1

x3

x2

0 1

x3

x2

x1

y

x

z

x

y

x

z

x

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Reduction Rule #3

x3

x2

0 1

x3

x2

x1

Eliminate Redundant Tests

y

x

y

x2

0 1

x3

x1

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Example OBDD

Initial Graph Reduced Graph

• Canonical representation of Boolean function

For given variable ordering

Two functions equivalent if and only if graphs isomorphic

o Can be tested in linear time

Desirable property: simplest form is canonical.

x2

0 1

x3

x1 (x1+x2)·x3

0 0

x3

0 1

x3

x2

0 1

x3

0 1

x3

x2

x1

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Example Functions

Constants

Unique unsatisfiable function

Unique tautology 1

0

Variable

Treat variable as function

0 1

x

Odd Parity

Linear representation

x2

x3

x4

10

x4

x3

x2

x1

Typical Function

x2

0 1

x4

x1 (x1 x2 ) x4

No vertex labeled x3

independent of x3

Many subgraphs shared

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Representing Circuit Functions

b3 b3

a3

Cout

b3

b2 b2

a2

b2 b2

a2

b3

a3

S3

b2

b1 b1

a1

b1 b1

a1

b2

a2

S2

b1

a0 a0

b1

a1

S1

b0

10

b0

a0

S0

• Functions

– All outputs of 4-bit adder

– Functions of data inputs

A

B

Cout

S

ADD

• Shared Representation

– Graph with multiple roots

– 31 nodes for 4-bit adder

– 571 nodes for 64-bit adder

Linear growth

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Effect of Variable Ordering

Good Ordering Bad Ordering

Linear Growth

0

b3

a3

b2

a2

1

b1

a1

Exponential Growth

a3 a3

a2

b1 b1

a3

b2

b1

0

b3

b2

1

b1

a3

a2

a1

)33

()22

()11

( bababa

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Selecting Good Variable Ordering

• Intractable Problem

Even when problem represented as OBDD

i.e., to find optimum improvement to current ordering

• Application-Based Heuristics

Exploit characteristics of application

e.g., Ordering for functions of combinational circuit

Traverse circuit graph depth-first from outputs to inputs

Assign variables to primary inputs in order encountered

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Selecting Good Variable Ordering

Static Ordering

Fan In Heuristic

Weight Heuristic

Dynamic Ordering

Variable Swap

Window Permutation

Sifting

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b 1 b 1

b 2 b 2 b 2 b 2

e f g h

i j

b 1 b 1

b 2

b 1

b 2

b 1

e f

g h i j

Swapping Adjacent Variables

Localized Effect

Add / delete / alter only nodes labeled by swapping variables

Do not change any incoming pointers

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Dynamic Variable Reordering

Richard Rudell, Synopsys

Periodically Attempt to Improve Ordering for All BDDs

Part of garbage collection

Move each variable through ordering to find its best location

Has Proved Very Successful

Time consuming but effective

Especially for sequential circuit analysis

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a3

b2 b2

a3

a2

a3

b1

b2

0

b3

b1

1

b2

a3

a2

a1

a3

b2

b3

b2

a3

a2

a3

b2

0

b1

b3

1

b2

a3

a2

a1

a2

a3

b1

b2

0

b3

b2

a3

1

b1

a2

a1

a3

b2

0

b3

b2

a3

a2

1

b1

a1

• • • a3

b2

0

b3

b2

a3

a2

1

a1

b1

Best

Choices

Dynamic Reordering By Sifting

Choose candidate variable

Try all positions in variable ordering

Repeatedly swap with adjacent variable

Move to best position found

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ROBDD sizes & variable ordering

• Bad News – Finding optimal variable ordering NP-Hard

– Some functions have exponential BDD size for all orders e.g. multiplier

• Good News – Many functions/tasks have reasonable size ROBDDs

– Algorithms remain practical up to 500,000 node OBDDs

– Heuristic ordering methods generally satisfactory

• What works in Practice – Application-specific heuristics e.g. DFS-based ordering for

combinational circuits

– Dynamic ordering based on variable sifting (R. Rudell)

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Thank you

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formal equivalence checking

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