FPGA/ CPLD LABEXPERIMENT 18AIM : To design and simulate given problem using Verilog HDL.EDA TOOL USED : Xilinx ISE 8.1iMETHODOLOGY : Find the sequence in the given flow diagram and simulate the sequence detector using that sequence.

Fig 16.1 State Diagram of Sequence DetectorSequence detection is the act of recognizing a predefined series of inputs. A sequence detector can be of two types: one is overlapping and other is non-overlapping. In overlapping the part of sequences detected in the previous sequence can be used for future sequence detection but in non-overlapping cannot be used. The state diagram represents a sequence detector for serial input x given by the sequence of 1s and 0s 101001. The output of the non-overlapping sequence detector designed is a single bit z which goes to 1 when the entire sequence is detected. Else it remains 0.State Table:ClkPresent StateNext StateOutput

QX=0X = 1Z=0Z=1

00000000100

00101000100

01000001100

01110000100

10010100100

10100000001

Table 16.1- State table of Sequence DetectorVERILOG CODE : module seq3(x, clk, Q, z);input x,clk;output reg Q,z;initial begin Q