ForSpec vs. Accellera Requirements

Roy ArmoniIntel

roy.armoni@intel.com

R.A. November 2001

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Status of ForSpec Development

ForSpec 1.0 is the dialect of ForSpec that has been donated to Accellera.

Collaboration of Intel with Synopsys, Co-Design and Verisity led to ForSpec 2.0 dialect. Main objectives of this design:

Be compatible with Verilog and Superlog to allow natural embedding of ForSpec within Verilog/Superlog files.

Meet the requirements set by Accellera. Ongoing definition work with Verisity on the incorporation

of Forspec 2.0 in temporal-e.

R.A. November 2001

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Overall Picture (Summery First)

ForSpec 1.0 meets all Accellera requirements, excluding the following three:

R2a – binding to Verilog Boolean expressions. R20a – && between regular expressions. R37a – Abstract clocks – end of sequential event.

ForSpec 2.0 meets ALL Accellera requirements. Details in the sequel.

R.A. November 2001

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R2a – Verilog Syntax

In ForSpec 2.0, the Boolean expression layer has been replaced by Verilog expressions.

On top of them, we added (from ForSpec 1.0):past, future, posedge, negedge, edge, clock,same, mutex, strong_mutex. future is the new name for the prime operator. Posedge, negedge and edge correspond to b_rise, b_fall

and b_change, respectively.

Also, regular operator’s syntax (of *,?,+,{n},{n,m}) has been changed to *[n..m] to allow embedding within Verilog and Superlog.

R.A. November 2001

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R20a – AND between REs

We have added AND to REs. The exact semantics was borrowed from TXP of Synopsys. In terms of regular languages, we defined:L(e1 && e2) =

{ (w1&&u1 … wm&&um wm+1 … wn) :

mn, (w1 … wn)L(e1), (u1 … um)L(e2) }

{ (w1&&u1 … wn&&un un+1 … um) :

nm, (w1 … wn)L(e1), (u1 … um)L(e2) } This operator is compatible with Boolean AND:

,i,c,a,r |= e1 && e2 if ,i,c,a,r |= e1 and ,i,c,a,r |= e2. It is not the same operator as Sugar’s &&. Intel is willing to

add an additional operator similar to Sugar’s if required by the committee.

R.A. November 2001

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R37a – end of events as clocks

We added the operator ended(e) that takes an extended regular event as parameter and returns a Boolean. Its semantics is:,j,c,a,r |= ended(e) ifthere exists ij s.t. ,i,j,c,a,r | e

Any Boolean expression may be used as a clock.

Byproduct: Latched end-of-event is also defined by the template:

matched(e): ended(e)&&CLOCK || ended(ended(e)&&!CLOCK #1 any);