FPGA-accelerator Attractor Computation of Scale Free Gene Regulatory Networks

Ricardo Ferreira, Julio Vendramini

Departamento de Informática,

Universidade Federal de Viçosa, Brazil

ricardo@ufv.br

FPL 201020th Field Programmable Logic Conference31 Aug 2 Sept – Milan, Italy

Contents• Basic Concepts

– Gene Regulatory Networks and Scale Free Networks

• Problem– Attractor Computation

• Contributions– FPGA-accelerator– Architecture Node Framework– Dynamic Interconnections

• Results and Conclusions

Gene Regulatory Networks

• Dynamic Model of System Behaviour• Applications

– Cell differentiation and Evolution– Drug design process

• Perturbations– Robust – Adaptable

Gene Regulatory Networks

• Dynamic Model of System Behaviour• Applications

– Cell differentiation and Evolution– Drug design process

• Perturbations

–Robust – Adaptable

Cell A Cell A

Gene Regulatory Networks

• Dynamic Model of System Behaviour• Applications

– Cell differentiation and Evolution– Drug design process

• Perturbations– Robust

–AdaptableCell A Cell A1

Gene Regulatory Networks● Models

– Ordinary Differential Equations, Bayesian Networks, Petri Nets, .....

– Boolean Networks [Kauffman, 69], “The Origins of

Orders: Self Organization and Selection of Evolution” [Kauffman, 93]

Random Graph, where each Node: Gene (1 or 0) K neighbours; Random Boolean function

Network TopologyRandom Scale Free Hierarchical

Network TopologyRandom Scale Free Hierarchical

Internet, citations, social networks.....•Science [Barabásie e Albert, 1999]•Nature - [Watts e Strogatz, 1998]

Kauffman

Scale FreeRandom Scale Free Hierarchical

Scale Free Gene regulatory networks•[Aldana, 2003], [Irons, 2006],[Iguchi,2007]

Yeast protein Interaction Network

Network Attractors ● Network State = All node states● Network Dynamics

– State Evolution;– System converges to stable cycles, called

attractors

Network

Network state

Network Attractors ● Network State = All node states● Network Dynamics

– State Evolution;– System converges to stable cycles, called

attractors

Network One Step on Time

Network Attractors ● Network State = All node states● Network Dynamics

– State Evolution;– System converges to stable cycles, called

attractors

Network Attractor or cycle

Attractors● Cycles - Biological

– Could be observed (experiments)– Cell type

●Example:

State Diagram of Network

network

Attractor Complexity● Large State Space 2gene

– 2100 ~ 10 27 states...– NP-Hard

●Example:

State Diagram of Network

network

gene

3 genes → 8 states

State transition =All nodes and edgesMust be visited

Attractor Computation

●Synchronous model●Two Simulation instances: S

0 and S

1

Network State diagram

One stepTwoSteps

Attractor Computation

●Synchronous model●Two Simulation instances: S

0 and S

1

Network State diagram

One stepTwoSteps

Sequential Algorithm

● For each step– Visit all nodes and all edges O( N + E )

Network State diagram

Sequential Algorithm

● Several steps to find an attractor....

Network State diagram

Sequential Algorithm Complexity

● O( (T+C) steps ) = O( (T+C) * (N+E))– Where C = cycle size, T = transient size

Network State diagram

Our Approach: Parallel Step Computation O(1)

One clock cycle to visit all Nodes and all Edges

Simulation Based Model

• 100 genes, 2100 states– Impossible to visit all state space

• Generate a large number of random networks and sample

BiologicalKnowledge

models

Revise Models(topologies,

Boolean functions....)

MapNetwork

Initial statesimulate

Simulation Based Model

• 100 genes, 2100 states– Impossible to visit all state space

• Generate a large number of random networks and sample

BiologicalKnowledge

models

Revise Models(topologies,

Boolean functions....)

MapNetwork

Initial statesimulate

GenerateNetworks

10 000 Randomnetworks

1000Initialstates

Previous Approaches on FPGA

NetworkGeneration

SíntesePlace & Route

para FPGA

SynthesisPlace & Route

FPGA

SíntesePlace & Route

para FPGAFPGA

Configuration

SíntesePlace & Route

para FPGAExecution

TimeConsuming > Configuration Execution

Time Time.

[Zerarka, 2004], [Pournara, 2005]Synthesis Time is not reported

Minutes, hours μs

Map NetworkOn FPGA

Our Approach

NetworkGeneration

Size N

SíntesePlace & Route

para FPGA

SynthesisPlace & Route

FPGA

FPGAConfiguration

ArchitectureFramework

Map GenericFree ScaleNetwork

interconnections

NodeVhdl generator

Dynamic Reconfiguration

To generate severalnetworks

Our Approach

NetworkGeneration

Size N

SíntesePlace & Route

para FPGA

SynthesisPlace & Route

FPGA

FPGAConfiguration

ArchitectureFramework

Map GenericFree ScaleNetwork

interconnections

SynthesisOnce !

Proposed Architecture Framework

ArchitectureFramework

interconnections

Each node isMapped on

Process Element (PE)Which implement a

FSM

S0

S1

FSM

Receive data fromThe neighbour

Compute new state

We propose Dynamic InterconnectionsMultistage Interconnection

O( N log2 N)

Edges are mapped

networkmappednetwork

Change configuration

New Network remapped

network

Generate a new randomNetwork

reconfigure Multistage

Generation and Simulation

Newnetwork

DynamicInterconnection

Network

V1

V2

Vn

Several Networks are generated

FPGA

NewConfig.

returnAttractor

size

InitialStates

Scale Free Networks and Architecture

Scale Free Networks and Architecture

Scale Free PE architecture

Network PE Size Distribuition

Size 1 2 4 8 16 32

100 49 28 11 12

200 98 57 25 15 5

300 176 44 30 30 15 5

400 248 80 30 30 8 5

Large numberOf poorly connected

Few number ofStrongly connected

Generic PE distribution

Few number ofStrongly connected

Each random Scale Free

Has different PEdistribution

Scalable Architecture

Network PE Size Distribuition FPGA

Size 1 2 4 8 16 32 Occupancy

100 49 28 11 12 4.4%

200 98 57 25 15 5 9.5%

300 176 44 30 30 15 5 10.9%

400 248 80 30 30 8 5 12.2%

Double Size

CPU and FPGA Execution Time

Network sub- CPU FPGA

size edges steps (ms) (μs) speed-up

100 933 5 8.12 13 706

200 2331 7 55.9 43 1300

300 4285 14 104.4 98 1128

400 4816 19 69.0 70 976

3 order of magnitude

10.000 networks + 100 Initial states → 27 hours 10.000 networks + 100

Initial states → 2 minutes

Dynamic Interconnection Size and configuration bits

Multistage FPGA memories

Size LUTs occupancy (max. 416)

128 1015 0.6% 14

256 1777 1.2% 32

512 4065 2.3% 72

1024 8447 5.6% 160

O(n log2 n)

ConfigurationBits

Up to 512 differentconfigurations

Conclusions

• FPGA acellerators• Bioinformatics – Large amount of Data

and parallelism• Proposed Implementation

– Speed up : 2-3 Order of Magnitude– Dynamic Interconnection Reconfiguration – Real World: 100-2000 nodes

• Suitable for FPGA Technology

Conclusions

• Model Scale Free Network on FPGA• FPGA Embedded Memories

– Reduce space of reconfiguration bits

• Multistage Interconnection– Dynamic

– O(n Log2 n)

• Generic Architecture Framework– FSM computation → nodes– Multistage → edges

Future Works

• Exploration of Gene Regulatory Networks– Boolean Functions– Topologies– Probabilistic Models

• Generic Architecture– Nodes + Dynamic Edges– Model others Cellular Automata Problems