fpga implementation of image watermarking using …
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Turkish Journal of Physiotherapy and Rehabilitation; 32(2)
ISSN 2651-4451 | e-ISSN 2651-446X
www.turkjphysiotherrehabil.org 3403
FPGA IMPLEMENTATION OF IMAGE WATERMARKING USING XILINX
SYSTEM GENERATOR
Garima Gupta1, Vijay Kumar Gupta2, Mahesh Chandra3 1, 2Department of ECE, Inderprastha, Engineering College Ghaziabad
3School of ECE, REVA University Bengaluru
ABSTRACT
In this paper, co-hardware simulation of Image Watermarking has been performed using Xilinx System Gen-
erator and VIRTEX 6 target device on ML605 FPGA Board. In Watermarking, valuable information can be
hidden in the set of digital media by modifying the graphic contents. Here, Watermarking is performed in DWT
domain after scaling of watermark data. Watermarking is implemented in MATLAB Simulink with Xilinx
System Generator toolbox. Then, Co-hardware simulation is performed using VIRTEX 6 device on ML605
Board. The visual results of both simulation and Co- hardware simulation models are achieved and it is ob-
served that the Co- hardware simulation results are better. The device utilization during the implementation of
Co-hardware simulation of watermarking process on ML605 Board is compared with the implementation on
LX240 Board. The ML605 implementation shows a requirement of smaller number of components as com-
pared to other researchers work.
Keywords: Image Watermarking, DWT, Scaling, Xilinx System Generator(XSG), Co-hardware Simulation
I. INTRODUCTION
In this paper, hardware co-simulation of image watermarking is performed using MATLAB and Xilinx System
Generator on ML605 board with Virtex 6 as the target device. Hardware setup is implemented using either DSP’s
or FPGA’s. Since design flexibility with FPGA is more than DSP, it is more feasible to implement such system
with FPGA for optimized performance as discussed[1] by Ana Toledo Moreo et al.
Roy, Li and Shoshan[2] have done hardware implementation of the Digital Watermarking system for compressed
video authentication. The authors worked on the real-time implementation of invisible watermarking using FPGA.
Karthigaikumar, Anumol and Baskaran[3] as well as Korrapati, Nelakudit and Mandhala[4] worked on watermark-
ing using Simulink block in MATLAB and then the algorithm is converted into Hardware Description Language
(HDL) using Xilinx System Generator tool. The algorithm is prototyped in Virtex-6 (vsx315tff1156-2) FPGA.
Joshi, Mishra and Patrikar [5] worked on real time implementation of Digital Watermarking for Image and Video.
They made hardware implementation of digital watermarking using DCT domain. Bhaisare et al. [6] implemented
real time method for watermarking system. They embed invisible, semi fragile watermark information into com-
pressed video streams using DCT. Also, Hajjaji, Mohamed Ali, et al. [7] worked on Xilinx System Generator and
they used HAAR DWT for watermarking. This model was implemented on ML507 Evaluation Platform which is
based on the Virtex-5 FPGA using Xilinx System Generator tool. Saidaniet al. [8] worked on the co-hardware
simulation for video watermarking. The design was implemented using a Spartan3 device (3S200PQ208) then a
Virtex-II Pro (xc2vp7- 6ff672). Shivdeep, Ghosh and Rahaman [9] performed FPGA and ASIC implementation of
color image watermarking. The use of pseudo noise code enhances the security of watermarking scheme. Xilinx
Spartan 3E FPGA kit with XC3S500E device is used for performing the task. Xilinx ISE 14.7 project navigator
along with XST synthesis tool and ISim simulator are used for interfacing, RTL synthesis and simulation, respec-
tively. Pexaras, Karybali and Kalligero [10]presented image and video watermarking schemes for low-cost appli-
cations. They presented FPGA implementation of robust invisible watermarking using spatial domain. In this
method, area calculated for blocks consumption is small as compared to existing methods as shown by the authors.
Turkish Journal of Physiotherapy and Rehabilitation; 32(2)
ISSN 2651-4451 | e-ISSN 2651-446X
www.turkjphysiotherrehabil.org 3404
With the development of technology, efficient and rapid prototyping systems have emerged in current scenario.
These systems require a development environment targeting the hardware design platform. Creating specialized
hardware would greatly reduce the time consumed by these processes. Simulink in MATLAB is an environment
for modeling and simulation. This paper presents a work where watermarking is first modeled and simulated on
MATLAB-Simulink environment on XSG tool and afterword co-simulation is done on ML605 board as shown in
Fig. 1. System Generator is a design tool based on MATLAB-Simulink. Xilinx is a family member of the System
Generator tool. The tool provides high-level generalizations that are automatically amassed into an FPGA at the
push of a button. The Xilinx Integrated Software Environment (ISE) is a powerful design environment that is
working in the background while implementing System Generator blocks.
When XSG is configured with MATLAB, it activates Xilinx block set library to appear in MATLAB-Simulink
environment. With the help of Simulink and Xilinx block set, model is designed and successfully run; a net list is
automatically generated for the given model. Then schematic representation of our synthesized source file can be
displayed with the help of RTL view. This schematic shows a representation of the pre-optimized design in terms
of standard symbols such as multipliers, counters, adders, AND gates, and OR gates that are independent of the
targeted Xilinx device. This schematic also calculates the actual resource utilization for the designed model. Then
mapping of synthesize design to physical resource of the target device is done to create implemented design. In this
paper, hardware implementation of image watermarking is presented on ML605 Board.
II. PRELIMINARY
2.1 Low Pass Filter and High Pass Filter
For 2-D DWT implementation, the image is first converted into four sub bands- LL, LH, HL and HH. This fre-
quency wise decomposition separates the image into high frequency and low frequency components. Frequency
components are separated by using high pass and low pass filters. Fig. 2 shows the 2-D decomposition of input
image. Here, g0[n] is low pass filter and h0[n] is high pass filter representation. After down sampling four compo-
nents (LL, LH, HL and HH) are obtained as shown in Fig. 2. Xilinx FIR Compiler 5.0 of XSG has been used to
design LPF and HPF which are further used to convert the image into four sub- bands LL, LH, HL, HH as shown
in Fig 2. The FDA Toolbox is used to define the filter order and coefficients for FIR compiler as shown in Fig 3.
Having proper parameter settings of FDA Toolbox and Xilinx FIR Compiler 5.0 block, filter coefficients are auto-
matically added from FDA Toolbox in both LPF and HPF filters designed with FIR Compiler as shown in Fig. 4.
Coefficients for LPF and HPF are shown in Fig. 5. This figure shows four tables of filter coefficients- two for
embedding and two for extraction. The output of the filters is displayed using spectrum scope.
Algorithm Developed
Bit Stream
Code Generation
Xilinx System Generator Model
RTL View
Download to FPGA
Figure 1: Design Methodology with Xilinx System Generator
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ISSN 2651-4451 | e-ISSN 2651-446X
www.turkjphysiotherrehabil.org 3405
III. METHODOLOGY
3.1 Watermark Embedding
The DWT based image watermark embedding method is used in experiment. Both input and watermark images are
either black and white image or color image. Fig. 6 shows the block diagram for watermark embedding and Fig. 7
shows the XSG implementation for watermark embedding. After this model is simulated in MATLAB-Simulink
environment. Net list is generated and then configured for hardware co-simulation. Steps for watermark embedding
are as follows-
Step 1: Both host and watermark images are read in MATLAB-Simulink environment and pre-processing is applied
on them. Here Pepper image is considered as host and Leena as the watermark image. Host, watermark images are
color image, gray scale images respectively.
Step 2: Further pre-processing like red component selection from host image, resizing, 2D to 1D conversion, frame
conversion and buffering are done before passing the images to the XSG model as input.
Step 3: InXSG model, 2-D DWT of both host and watermark image is first calculated. Four components after DWT
of host image are 𝐿𝐿ℎ, 𝐿𝐻ℎ, 𝐻𝐿ℎand 𝐻𝐻ℎ. Four components after DWT of watermark image
are 𝐿𝐿𝑤, 𝐿𝐻𝑤, 𝐻𝐿𝑤and 𝐻𝐻𝑤.
Step 4: Each component of watermark image (𝐿𝐿𝑤, 𝐿𝐻𝑤, 𝐻𝐿𝑤 and 𝐻𝐻𝑤) is scaled separately with a scaling factor
before embedding with host image.
Step 5: Scaled components with a scaling factor αof watermark image are embedded with components of the host
image according to the Eqn.1, Eqn.2, Eqn. 3 and Eqn.4 as given below:
𝐿𝐿 = 𝐿𝐿ℎ + α ∗ 𝐿𝐿𝑤 (1)
𝐿𝐻 = 𝐿𝐻ℎ + α ∗ 𝐿𝐻𝑤 (2)
Figure 2: 2-D Decomposition Routine
go[n]
ho[n] Time
domain
Signal x[n]
go[n]
ho[n]
go[n]
ho[n]
LL
LH
HL
HH
↓2
↓2 ↓2
↓2
↓2
↓2
Figure 3: FDA Tool for Filter Designing Figure 4: LPF and HPF using Xilinx
Turkish Journal of Physiotherapy and Rehabilitation; 32(2)
ISSN 2651-4451 | e-ISSN 2651-446X
www.turkjphysiotherrehabil.org 3406
𝐻𝐿 = 𝐻𝐿ℎ + α ∗ 𝐻𝐿𝑤 (3)
𝐻𝐻 = 𝐻𝐻ℎ + α ∗ 𝐻𝐻𝑤 (4)
Step 6: By applying inverse DWT to the new values of 𝐿𝐿, 𝐿𝐻, 𝐻𝐿 and HH the watermarked image is formed.
Fig. 8 shows Co-hardware simulation of embedding system. Co-hardware simulation of embedding system is gen-
erated, and inputs-outputs are connected to the generated model.
Figure 5: Filter coefficients
(a) LPF Coefficients for Embedding (b) LPF Coefficients for Extraction
(c) HPF Coefficients for Embedding (d) HPF Coefficients for Extraction
(a) (b)
(c) (d)
E
IDWT
Host Image
Watermark Image DWT
DWT LHh
LLh
HLh
HHh
LLw
LHw
HLw
HHw
E
E
E
Watermarked
image
S
s
s
s
Figure 6: Block Diagram for Watermark Embedding with Host (Pepper Image) and Watermark (Leena Image)
Turkish Journal of Physiotherapy and Rehabilitation; 32(2)
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3.2 Watermark Extraction
Watermark extraction gives back the embedded watermark. Hence the embedding steps in the reverse direction
need to apply to get back embedded watermark.
Step 1: Watermarked image is taken as an input of the extraction system. Pre-processing operations like-resizing,
2D to 1D conversion are applied at the time of embedding.
Step 2: DWT is applied on the watermarked image to get LL, LH, HL and HH sub-bands.
Step 3:As, 𝑊𝑎𝑡𝑒𝑟𝑚𝑎𝑟𝑘𝑒𝑑 𝑖𝑚𝑎𝑔𝑒 = ℎ𝑜𝑠𝑡 𝑖𝑚𝑎𝑔𝑒 + 𝛼 ∗ 𝑤𝑎𝑡𝑒𝑟𝑚𝑎𝑟𝑘 𝑖𝑚𝑎𝑔𝑒
Therefore, 𝑊𝑎𝑡𝑒𝑟𝑚𝑎𝑟𝑘 𝑖𝑚𝑎𝑔𝑒 = (𝑊𝑎𝑡𝑒𝑟𝑚𝑎𝑟𝑘𝑒𝑑 𝑖𝑚𝑎𝑔𝑒 – ℎ𝑜𝑠𝑡 𝑖𝑚𝑎𝑔𝑒)/ 𝛼
Where 𝛼=scaling factor. The value of α can be chosen randomly, but it is kept same both at the time of embedding
and extraction.
Step 4: The extracted watermark is compared with the original watermark for its similarity. More similar will be
the extracted watermark to the original watermark, better will be the results.
Fig.9 shows block diagram of watermark extraction. Input watermarked image is called from MATLAB workspace.
Host image is Pepper image that is connected as another input of extraction system. After applying DWT to both
the watermark and host image, host image sub-bands and watermarked image sub-bands are obtained. Host sub-
bands are subtracted from watermarked sub-bands and then inverse scaling is applied. At the output, four sub-bands
of watermark are obtained and when IDWT is applied to these sub-bands, watermark image is obtained. Fig.10
shows the implementation of extraction system using XSG. Fig.11 shows Co-hardware simulation model of ex-
traction system.
Figure 7: Embedding Model using XSG
Figure 8: Co-hardware Simulation of Watermark
Embedding System
Turkish Journal of Physiotherapy and Rehabilitation; 32(2)
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IV. RESULTS AND DISCUSSION
Models for watermark embedding and extraction shown in Fig. 7 and Fig. 10 are implemented. In this section, the
results of these models for only simulation and hardware co-simulations are presented, compared, and discussed.
Higher similarity between watermarked image and host image is observed. In this implementation, host image and
watermark image are Pepper image and Leena image, respectively.
Figure 10: Extraction Model using XSG
Figure 11: Co-hardware Simulation of Watermark Extraction System
Sub
ID
W
T
Watermarked
image
Host
Image
DWT
DWT LH
LL
HL
HH
LLh
LHh
HLh
HHh
Sub
Sub
Sub
Waterma
rk image
1/s
Figure 9: Block Diagram for Extracting Watermark
1/s
1/s
1/s
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4.1 Hardware Co-Simulation results
Embedding and extraction system is simulated through XSG and then interfacing of XSG with ML605 kit provides
results after co-simulation.
4.1.1 Watermark Embedding
Results for Simulation only through Simulink and Hardware Co-simulations on ML605 board with target device
Virtex 6 FPGA are shown in Table-1. Here peppers image and Leena image are used as host and watermark images
respectively shown in Fig. 13. Four different sub-bands of watermarked image LL, LH, HL and HH, are shown in
Table-1. Here, Scaling Factor is taken as 0.2. It is also observed from Table-1that Hardware Co-simulations results
are better than simulation results.
Table-1: Co-hardware simulation results of four sub-bands at the time of embedding (α=0.2)
S. No. Sub- bands Host Sub-bands Watermark Sub-bands Watermarked Sub- bands
1. LL
2. LH
3. HL
4. HH
Figure 13: Host Image (Peppers) and Watermark Image (Leena)
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Table 2: Visual comparison between Simulink results and hardware Co-simulation results
S. No. Name of
Sub- band Image through Simulink
Image through Hardware Co-Simula-
tion
1. LL
2. LH
3. HL
4. HH
4.1.2 Watermark Extraction
With the help of four sub-bands of watermarked image and host image, watermark image is again recovered in the
extraction stage. All the four parts of extracted watermark are combined back to give an extracted watermark.
Extracted watermark is same as embedded one. The watermark extracted and obtained through matrix viewer is
shown in Fig. 14.
4.2 Design Summary and Device Utility for Embedding Process
Fig. 15 shows actual device utilization for embedding process. As RTL view represents the design using Macro
blocks. Device utility show how much gates, registers, Look up Tables (LUTs), Flip flops (FFs),Input Output
Blocks (IOBs) and RAMs has been utilized for the purpose of designing.
Figure 14: Extracted Watermark
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Table-3 shows the comparison of this scheme with schemes [11-16] in terms of device utilization. Authors imple-
mented the system using virtex-6 LX240T board and XSG.Table-3 proves the effectiveness of implemented scheme
for slice register and flip-flop utilization as compared to the other schemes. Here utilization is 0% for register and
flip flop whereas utilization is 1% [4]. However bonded utilization is 21% in the implemented system.
Research Work Design Type Pro-
cessing
Domain
Watermark
Type
Area (Logic
blocks or
mm2)/Bonded
I/O
No. of
slice
Regis-
ters
No. of flip flops
(Mohanty , Kumara
and Sridhara)
FPGA (Xil-
inx Virtex-II)
Spatial Invisible
Robust
- - -
(Ghosh and Sudip) FPGA (Xil-
inx Virtex-II
Pro)
Spatial Invisible
Robust
1669 LUTs 959 896
(Maitya and Maity) FPGA (Xil-
inx Spartan-
3E)
Spatial Reversible 11291 LUTs 9881 9347
(Mohanty,
Ranganathan and
Namballa)
ASIC
(0.35µ)
Spatial Invisible
Robust/
Fragile
- - -
(Mohanty,
Ranganathan and
Balakrishnan)
ASIC
(0.25µ)
DCT Invisible
Robust
16.2 - -
(Shivdeep, Ghosh
and Rahaman)
FPGA Spatial
(PN se-
quence)
Invisible 20 IOBs 195 188
(Korrapati,
Nelakudit and
Mandhala)
FPGA - Invisible 50 IOBs 16 156
Presented Method FPGA DWT Invisible 129 IOBs 1 0
Table 3: Comparison of presented scheme with existing scheme
V. CONCLUSION
In this paper a method for hardware implementation of image watermarking is presented. Results obtained after
hardware simulation are satisfactory and better than existing methods in terms of hardware utilization. In future,
this method can be used for implementation of online videos using watermarking. Further, this method can be
improved by introducing more robustness and higher security. Still, lot of scope exist to improve robustness for
real time implementation of watermarking.
Figure 15: Device utility for Embedding Process
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