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Proceedings of ICSP '98

FPGA Implementation of a Multilayer PerceptronNeural Network using VHDLYamina TARIGHT,Michel HUBIN

Laboratoire Perception Systemes et Information (PSI-LCIA),INSA de Rouen, Place E Blonde1 BP 08

F-76 13 1 Mont Saint Aignan, France

Abstract:Our aim is how to use the run-time reconfiguration abilityof SRAM-based FPGA circuits in order to implementartificial multilayer neural networks which are needed toprncess, in real-time, non linear data obtained from a setof microchemical sensors. So we propose, in this paper,

' an innova tive alternative to ASICs and/or mu ltiprocessorsbased architectures.

1. Introduction:There are many real time applications, which require alow-cost, miniaturized and automatic system used forclassification and recognition. Frequently such a device isorganized around several sensors providing complex datathat only an artificial neural network will be able tointerpret.In this frame, the development of electronic noses, whichoperate upon a similar, but simplified, principle as thehuman olfactoq system, represents an alternative to theclassical physico-chemical analytical technique. It hasmany potential applications, as it allows quantitative andqualitative analysis of gaseous mixtures in differentdomains such as food-processing industry, security andair pollution evaluation. The prototypes of electronicnoses seen in the literature [l] [2 ] are composed of a setof a temperature sensor, a humidity sensor and chemicalmicrosensors (semiconductor ones based upon tin oxidesensing layer). These sensors present some advantagessuch as low cost, sensitivity and response time but theirlack of selectivity [3] is resolved by means of a neuralnetwork computing involving two steps: learning andrecognition.The ANN used in these prototypes are always on parallelalgorithm software based and simulated on computers.

Because of the real time, miniaturization and powerconstraints impo sed by som e specific applications like th esupervision of the atmosph eric pollution in urban sites 141we consider a hardware implementation of such ANNs.Very few neural devices are referring to a hardwareimplementation as parallel neural structures are veryexpensive to realize in terms of design time and siliconsurface used in ASIC technology and they also present anevident economic risk because of the fixed architecturalconcept of such a type of component. An alternative ispossible: the use of SRAM field programmable gatearrays (FPGA) which allows the design of cost effectivecircuits using the dynamic reconfiguration ability of suchcomponents.In this paper, using our experience in the design ofFPGA, we will describe our original approach and theproposed solution for the hardware implementation of amultilayer perceptron (MLP) specifically dedicated to thereal time application following of the air pollution [4]SensorArray

UFigure 1. Schematic diagram of an Electronic nose

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2. MLP etection and clrwifKationA. algorithmTh e MLP consists of various layers: an input and outputones between which lie one or several hidden ones whoseoutputs are not observable. These layers are based uponsome processing unit (neurons) interconnected by meansof feed-forward pondered lin ks (figure 2).

Figure 2, Multilayer perceptron neural networkAll these processing units carry out the same operation(figure 3): i.e. the sum of their weighed inputs (equation1). Then they apply the result to a non-linear functionnamed a ctivation function and generally based upon thesigmoid function (equation 2).

Figure 3. Structure of the neuron

i1

l + e - x (2 )4=where y, is the output of the processing unit jw, the synaptic weight coefficient of the i-thinput of the processing unit jb, is the bias

Th e MLP processing is based on two seq uential steps:

learning and recognition whichconsequently could be treated separately.+ learningIn reality, during the learning process, the networkadjusts its parameters, the synaptic weights, in responseto a stimulus input so that its actual output responseconverges to the desired output. At this level the synapticweights of each processing unit are dynamically m odifiedto reach a defined error level according to anoptimization criteria called learning algorithm (forexample backpropagation algorithm) in order to iden*the best architecture with a given number of cells for aallow specific problem. When the actual output responseis the same as the desired one, the network has completedthe learning phase.Then the optimized structure is known, i.e.:0 number of inputs0 number of outputsnumber of layers0 synapticweights0 transfer function+ recognition:Th e MLP doesnt give only the desired outputscorresponding to known inputs, but also the mainplausible outputs for any set of inp uts using the equation(1) with the w, evaluated during the learning phase.B. Looked-infiocess:For our system, the learning phase is obtained by m eansof an algorithmic simulation made on a computer inorder to identify the synaptic weights and the bestarchitecture of the network. Then the hardwareimplementation may be considered.We must take into account some hardware constraints.The optimized software solution leads generally to buildextremely complex circuits depending on the size of thedata. In order to develop realistic devices with aconvenient accuracy and a reasonable hardware size, on emust redefine the resolution of the coefficients and of thecalculus. So the optimization of the architecture and thereduction of the number of configurable logic blocks(CLB) used in the FPGA circuit implicate the bestaccuracy obtained during the learning phase.On account of all these c onsiderations, we determine thearithmetic typeused (floating point or not) and the size ofthe processed data (in bits).A good compromise between accuracy and complexity ofthe processing units allows to obtain a low cost effectivedevice (in terms of CLB in FPGA circuits, andconsequen tly in term of silicon area in derivative ASICs.

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3. FPGA Implementation:A. synthesis tool:Actually, the synthesis tools allow the use of P G Aresources with schematics entrance as well as analgorithmic one. The algorithmic design is written withVHDL (Very High-speed Integrated Circuits HardwareDescription Language) [ 5 ] . This language permits thedesign of complex circuits with a structural description(data low type) or a behavioral one.The synthesis software (Viewsynthesis of ViewLogicCompany) leads from a VHDL program, and aftercompilation, to an XNF (Xilinx Netlist F orma t) file usedby the Xilinx tool, and the co rrespond ing schematics bymeans of prim itives and X -Bloc components with a logicoptimization . The functional simulation insures of thefunctionality of the design before the routing phase of theFPGA (figure 4).

c "T:F*tFunctional Shulatjun

I 6Techmbgy Mapping-1

+ Neuron Architecture:The structural description of a neuron with VHDL allowsduring the compiling step to spec@ generically somecharacteristics like the input numbers and the data size,and even to modify the typeof some arithmetic operatorslike the adder or the multiplier and eventually theactivation function unit if one wants to modlfy theactivation function.The neuron computes the product of its inputs, which aresaved in RAM with the correspo nding synaptic weights,which are memorized in an EEPROM, nd then theresults are added. The result is presented to a comparisonunit designed to represent an appropriate sigmoidfunction. Then the output of this comparison unit is usedas a con troller for a m ultiplexing unit, wh ich delivers they output of the neuron (figure 5 )

B. Architecture:Th e MLP architecture, as shown on figure 2, is iterativeand mainly connected and requires, a priori, (i*j)connections between 2 layers of i and j neurons. A n ullsynaptic weight is applied to the non existent link. Thisleads us to imagine the building of a complete networkbut only with one layer at a time and to use the propertyof dynamic reconfiguration of the FPGA alone processwhich insures the possibility to implement the design ona single FPGA circuit.

ACTNATIONRMCTION

FEPROM

RAM

U UFigure 5. Neural processo r architecture

+ Layer ArchitectureIn the same m anner the structural VHDL description of alayer allows during the co mpilation phase to dete rminethe number of neurons on this layer, which gives thepossibility to synthesize layers with any number ofneurons. (Figure 6)

U u uFigure 6. Layer architecture

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+ Network Architecture:The ability to exploit the run-time reconfiguration of theFPGA circuit leads us to take advantage of 2 RAMS (1 )and (2) in order to process the output data of the neuronlayer ( i - I ) by the following layer (i).1. Conclusion:Th e use of run-time reconfiguration of the FPGA of theXilins company will allow us to develop and implementsome different algorithms on th e same circuit but notuseful at the same time.Moreover. the implementation of the different blocksshown above permits the evaluation and the validation ofthe architecture proposed for a specific problem.5. References:[ 1 J.W.Gardncr. H.V.Shurmer and T .T.Tan. Applicationof an electronic nose to the discrimination of coffees.Sen.cor.ynnd ..Icluatnr.sU. 6 ( 1992) 7 1-75.

[2] J.Mizsei. V .Lantto, Air pollution monitoring with asemiconductor gas sensor array system, Sensors andActuators B. 6 (1992) 223-227.[3] GNiebling. Identification of gases with classicalpattern-recognition methods and artificial neuralnetworks, Sensors and .Ictuators B, 18-19 (1994) 259-263.141 M.Hubin. Y.Taright. S.Lee, Multisensor SmartMicrosystem for the Supervision of AccidentalAtmospheric Pollution, 8th International Congress fo rSensor , Trnnshicers C% systems, .\'urnberg, (1997) Vol 2.129-133.[ 5 ] J.R.Armstrong. F.Gai1 Gray. Structured Logic Designlvith VHDL PTR Prentice Hall.[6 ] XILINX. The programmable Gate .Irrgv Data Book.1995.

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