fpga pinout - how to define pins for fpga

FPGA Pinout

How to pinout the FPGA for Success

By FPGA Central

© FPGACentral.com – World’s 1st FPGA Portal

Selecting The Right FPGA

In this presentation we will review various factors that effect the device selection of

a FPGA or CPLD in a project.


Overview

Selecting the right device is very important and can impact your overall success of the project, including:– Technical feasibility

• A technical roadblock can jeopardize the entire project

– Schedule– Cost

• Design Cost (Time, Tools, IP)• Per device cost

It is important to look at these much before the design starts.


Know what you want

• What external interfaces you need ?– PCIe, I2C, SPI4.2, Interlaken etc

• How many pins do you need ?– Single ended, Differential, Serdes

• What IO standards are required ?– LVCMOS 2.5V, HSTL I, LVDS etc

• What functionality you want to achieve ?• What frequency you need to run the design?


Specify The Requirements

• Group the requirements into the following:– # of LUTs/LE , FF, DSP Block, RAM bits– # of IOs for each voltage level

• 3.3v, 2.5v, 1.8v etc

– # of Clock pins, PLL/DLL/DCM , Clock Buffers (regional or global) required

– Hard macro requirements• Hard macros like PCIe, Ethernet MAC, Serdes,

Processors etc are getting popular. Find out if you require to use any of these (separate must from nice to have)


Know The Vendors

• Xilinx, Altera, Lattice, Actel are few major FPGA vendors with Xilinx & Altera having 85% of the market share

• Many other vendors including startups like SiliconBlue should not be ignored

• A complete list of various FPGA vendors can be found at– http://www.fpgacentral.com/vendor/directory?filter0=3


Know The Devices

• Spend time to learn about the vendor devices. • FPGA vendors usually provide a Device Product

Table which provides the capability of each device that they offer. Usually:– # of LUT/LEs, FF, Serdes, User IO, RAM bits– Package types & Size

• It is recommended to go with the latest released product (As it will be supported longest)


Device Product Table

• Some of these tables are located at– http://www.xilinx.com/publications/prod_mktg/Virtex6_Product_Table.pdf – http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/overview/stxiv-overview.html– http://www.latticesemi.com/products/fpga/ecp3/index.cfm


FPGA Central offers FREE service to help you in selecting a device. If you would like support in selecting the right FPGA

contact us via http://www.fpgacentral.com/find

Isolate Devices

• Based on the requirements gathered, isolate anywhere between 2 to 4 devices

• Quick tips:– Keep room for future expansion (aka feature

crap), bug fixes– Keep the utilization under 80%. Having a full

FPGA makes meeting timing much more challenging


Compare Devices… 1

• Once you have isolated few devices, compare them based on:– Resource utilization (LE, FF, RAM, IO, hard Macro

etc)– # of IO banks available vs # of various voltage level

required– Frequency of operation– Power

• vendors provide tools to measure power – usually excel tools

– Package size Vs Amount of space on the board


Compare Devices… 2

– Cost • TIP: Cost varies based on speed grades and quantity so

negotiate with the vendor

– IP available (either via FPGA vendor or 3rd party) and the cost associated

• Using pre-validated IPs makes the design time shorter and reduces risks/un-know in the design

• TIP– Ask for characterization data for critical

interfaces and IPs.


Select Device

Now you should be able to choose a device based on above criteria. Some times you will have a clear winner over the other. But many times you would find more then one solution which is best for you. In those cases, choose the device and vendor which you are most comfortable with.


Further considerations

• You should also consider the following criteria:– Support (Silicon & IP)– EDA Tools support– Configuration PROM and programming times– Option to migrate to smaller or bigger die (in case you

need less logic or more). – ECC or Parity protection on RAMs– SEU – Single Event Upset (Defines MTBF)– Number of power supply required (usually multiple)– What devices/IP your team have worked on in the

past


www.fpgaCentral.com World’s 1st FPGA Portal

Thank You&

Good Luck Choosing the Device

Go to www.fpgacentral.com/find to get FREE help Selecting the right Device/ IP

fpga pinout - how to define pins for fpga

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