fpga verification in uk & ireland compared to europe as a ... · fpga verification in uk &...

FPGA Verification in UK & Ireland compared to Europe as a whole.

Highlighted Results of NMI FPGA Usage Survey and Mentor Graphics/Wilson Survey

Verification Futures Conference, UK

4th February, 2016

Doug Amos Mentor Graphics, on behalf of NMI

Survey Focus

• Chart usage, methods and challenges of FPGA designer in UK and Ireland – Identify region-specific strengths and needs

– Detect changes since 2014 survey

– Inform immediate activity of NMI FPGA Network

• Provide valuable information to NMI Members – If including these results in your own work, please

include the citation . . . “Source: NMI FPGA Usage Survey 2015”

• Not a market share survey

Survey Methodology

• By NMI, with assistance of FPGA Frontrunners Forum and inputs from Mentor Graphics and FirstEDA

• Held online during October 2015

– Hosted at www.surveymonkey.com/s/NMIFPGA15

– Survey prize draw at FPGA Frontrunners Forum Nov 8th

• Publicised by NMI and FPGA eco-system partners Altera, FirstEDA, Mentor Graphics, New Electronics and Silica

http://www.surveymonkey.com/s/NMIFPGA15

Survey Questions

• Where possible, questions were open-ended allowing free-form answers but requiring manual interpretation for some analyses

• 23 questions grouped into 5 sections . . . – “Your Typical Programmable Technology” (7)

– “IP and Design Entry” (4)

– “Verifying and Debugging your FPGA Designs” (5)

– “Your Design Tasks and Challenges” (4)

– “Some Final Feedback on FPGA Usage” (3)

Response Demographics

Validating Responses

• 168 total survey starts

– Of which 14 discarded as invalid (e.g. not in region)

• 135 fully completed, including contact details

– Answers from anonymous respondents included

– Questions earlier in survey have most data-points

• Responses filtered to remove irrelevant answers (e.g. “we do not use FPGAs”)

– Yielding average of 145 data-points per question

• Worldwide study conducted in four phases

• North America, Europe, Japan, Rest of World

• Sample frame consisted of 1886 participants

• 3.3x larger than our 2012 study

• 9.4x larger than the 2004 Collett study

• Confidence interval 95%

• ±2.19% Margin of Error

Wilson Research Group Study Background

H Foster, UK Frontrunners Forum, Nov 2015 8 © Mentor Graphics Corporation, all rights reserved.

First-level Analysis

. . . and correlation with Wilson/Mentor findings for Europe

“Which FPGAs or other programmable devices does your team typically use?”

Open-ended Answers, 154 Responses

Open answer • Often only vendor name given • Sometimes generic device family (e.g. Spartan) or generation (e.g. Stratix V) • 2014 scored scaled to 2015 total

“Which application areas does your team design FPGAs or programmable devices?”

Multi-choice Answer, 154 Responses

No

. of

Res

po

nd

ents

Se

lect

ing

“How much engineering resource was required on your team’s latest FPGA project?”

Single-choice Answer, 136 Responses in 2014, 154 responses in 2015

Number of Peak FPGA Engineers Increasing

Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

4.0 4.4 3.7

2.6

3.8

2.0

0

2

4

6

8

10

World 2012 World 2014 Europe 2014

FP

GA

Mean

Peak N

um

ber

of

En

gin

eers

Verification Engineers

Design Engineers

4.9% CAGR for FPGA design engineers

20.9% CAGR for FPGA verification engineers


What % of FPGA project time do you estimate is spent on the following tasks?

Answers totalling 100%, 120 Responses

“What % of FPGA project time do you estimate is spent on the following tasks?”

Multi-choice Answers, 125 Responses

Verification Consumes Majority of Project Time

0%

5%

10%

15%

20%

25%

30%

<21% 21%-30% 31%-40% 41%-50% 51%-60% 61%-70% 71%-80% >80%

Stu

dy P

art

icip

an

ts

Percentage of Project Time Spent in Verification

World ASIC/IC 2014

World FPGA 2014

Europe 2014

World ASIC: Average 57%

World FPGA: Average 46%

Europe FPGA: Average 46%



“Which tasks are the most CHALLENGING (select up to THREE)?


No

. of

Res

po

nd

ents

Sel

ecti

ng

Estimate how often non-trivial bugs require remedial action after your team's

FPGA designs begin production


How (if at all) does your team use the FPGA's ability to be updated post-production?


Flaws Contributing to FPGA Rework


* Multiple answers possible

0%

10%

20%

30%

40%

50%

60%

LOGIC OR FUNCTIONAL CLOCKING

Des

ign

Pro

jec

ts

Trends in Types of Flaws Resulting in FPGA Rework

2012

2014


“How does your team typically verify FPGA designs? (Please select all that apply)”


No

. of

Res

po

nd

ents

Se

lect

ing

= Teams working to Safety standard (e.g. DO-254)

FPGA Assertion Language Adoption



0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

Accellera OpenVerification Library

(OVL)

SystemVerilogAssertions (SVA)

PSL Other

Des

ign

Pro

jec

ts

Assertion Languages and Libraries

World 2012

World 2014

Europe 2014


FPGA Verification Technique Trends


0% 10% 20% 30% 40% 50% 60% 70%

Constrained-Random Simulation

Functional coverage

Assertions

Code coverage

Designs

World 2012

World 2014

Europe 2014


FPGA Verification Language Adoption Trends



0%

10%

20%

30%

40%

50%

60%

70%

80%

Des

ign

Pro

jec

ts

Languages Used for Verification (Testbenches)

World 2012

World 2014

Europe 2014


FPGA Testbench Methodology Adoption Trends



0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

AccelleraUVM

OVM MentorAVM

SynopsysVMM

SynopsysRVM

CadenceeRM

CadenceURM

None/Other

De

sig

ns

Methodologies and Testbench Base-Class Libraries

World 2012

World 2014

Europe 2014


Which of these hardware VERIFICATION languages does your team regularly use?


Survey Prize Draw Winner

Paul Sweeney, Hitachi Data systems Paul won an Apple IPad Pro and NMI made a donation on Paul’s behalf to his chosen charity, Save The Children. Draw made by random number generation in presence of FPGA Frontrunners Forum, meeting at Mentor Graphics, Newbury on 8th November, 2015

Observations

• Is FPGA productivity falling?

• Verification is a major part of project effort

• Delayed and fragmented adoption of advanced verification language and methodology

• Some growth in Assertion-Based Verification

• Europe under-resourced for FPGA verification

• Watch for NMI FPGA Network activity based on these findings

Thank You For Your Support

If including these results in your own work, please include the citation . . . “Source: NMI FPGA Usage Survey 2015”

[email protected] [email protected]

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