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應用系統晶片設計實驗室 Applied System IC Design Lab / 45 FPGA雛型設計(1)-Verilog 簡介 Shin-Chi Lai, Assistant Professor Dept. of CSIE, Nan Hua University From 2013/09 to 2014/01. 2013/9/8 1

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Page 1: FPGA雛型設計(1)-Verilog 簡介 - nhu

應用系統晶片設計實驗室

Applied System IC Design Lab / 45

FPGA雛型設計(1)-Verilog 簡介

Shin-Chi Lai, Assistant Professor

Dept. of CSIE, Nan Hua University

From 2013/09 to 2014/01.

2013/9/8

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Outline

• Ch1: Verilog簡介

• Ch2: Verilog 設計結構

• Ch3-Ch5: 閘層描述

• Ch4: 資料流描述

• Ch5: 行為描述

• Ch6: 邏輯電路、狀態機

• Ch7: LED & 7s LED應用

• Ch8: SW & Matrix LED

• Ch9: Nios2 Processor

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

數位IC設計概念 DIGITAL IC DESIGN CONCEPT

Verilog Coding Introduction

Part I:

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Hardware Implementation

• An Algorithm is to solve some specific problems, and can be implemented by FPGA or ASICs.

• Methodology of Hardware Realization

– One processor + a suitable software program (flexibility);

– Dedicated hardware circuits (fast and small);

– Some hardware accelerators + software programs (can be applied to solve more complex problems) ;

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

One processor with software programs

• Processor Type

– Pentium IV + windows + c or java

• More high-level program language

– TI-DSP + c or asm

– ARM + c or asm

– Nios2 + c

– MCU (8051) + c or asm

• Low-level program language

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Dedicated hardware circuits

• Old_PCBs

– TTL, SSI, MSI, VLSI chips and wires.

• New_PCBs

– Some devices, application specific integrated circuit-ASIC, wires.

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Some hardware accelerator + software programs

• System on a board

– Memory, processor, ASIC, I/O, and other devices.

• System on a chip

– Current and future work RSIC-ARM.

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Digital System

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Circuit

• Transistor

• Gate (1 gate = 2 to 14 transistor) – A combination of interacting transistor.

• Circuit – A combination of interacting gates designed to

accomplish a specific logical function.

• IC (Integrated Circuit)

• System -> PCB ( printed circuit board)

• SoC (system on a chip)

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Transistor

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

MOS電晶體示意圖

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Constructing Gate

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

IC Design ( with COMS )

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Applied System IC Design Lab / 45

Design Entry for VLSI System

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Hierarchical Components in PCB

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

IC Industry in Taiwan

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Historical Perspective

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Applied System IC Design Lab / 45

積體電路的分類

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

SIA Roadmap 1997

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Circuit Design Process

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Applied System IC Design Lab / 45

IC Design Flow

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Full Custom Design

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Semi Custom Design

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Applied System IC Design Lab / 45

Standard Cell

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Applied System IC Design Lab / 45

Synthesis Flow of Semi Custom design(1/2)

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Applied System IC Design Lab / 45

Synthesis Flow of Semi Custom design(2/2)

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Applied System IC Design Lab / 45

Synthesis (1/3)

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Synthesis (2/3)

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Applied System IC Design Lab / 45

Synthesis (3/3)

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Applied System IC Design Lab / 45

程式設計提醒 CODING REMINDER

Verilog Coding Introduction

Part II:

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Verilog Coding注意事項(1/3)

1. 保持一行指令一行說明。

2. 每一行指令不可太長，需低於80字元。

3. 說 明 輸 出 / 入 訊 號 之 安 排 依 序 為 ： (Input) -> (Output) -> (Clock) -> (Reset) -> (Enable) -> (Address bus) -> (Data bus)。

4. 例證元件(Instantiation)命名，在對映訊號連接時，最好選擇依名稱(By-name)對映，而不要使用順序式(In-order)方式。

5. 使用參數時，大寫表常數，以小寫表連接信號變數。

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Verilog Coding注意事項(2/3)

6. 匯流排長度之宣告，習慣性由大至小排列 (例: [15:0])，而不是由小到大排列(例: [0:15])。

7. 運算式中所使用之資料應為固定長度。

8. 使用敘述指令時，必須了解其可否合成。

9. 使用內建元件時，務必使用通用型元件，避開機器相關(Machine dependent)之元建。

10.避免使用非同步邏輯。

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Applied System IC Design Lab / 45

Verilog Coding注意事項(3/3)

11.對電路中之循序邏輯電路，避免混合使用正緣與負緣觸發暫存器。

12.對同一變數，不要做重覆之指定。

13.將設計完成之各種IP電路存於元件庫中，建立重複使用觀念。

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Verilog基本觀念

• 運算子(Operator)

• 註解說明(Comment)

• 空格(White Space)

• 數字(Number)

• 字串(String)

• 識別字(Identifier)

• 關鍵字(Keyword)

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Applied System IC Design Lab / 45

運算子(Operator)

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• 運算子與運算元

– Ex: Z = X + Y

• 分別有三:

–單一運算子

–雙重運算子

–三重運算子

Y=~ X; W=X | Y; Z=W ? X : Y;

Case # X Y W Z

1

1

2

2

2

3

3

3

3

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

註解說明(Comment)與空格(Space)

• 若給定之數字之最大位數為x或z時，合成工具會將此數字較高位元補滿x或Z。

• 註解的使用方式:

– // 本方式為單行程式註解…

– /* 本方式為多行 程式註解…*/

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數字(Number)(1/2)

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• Ex: 8’hfc // 8位元長度的16進位數字

16’d2048 // 16位元長度的10進位數字

12’o2347 // 12位元長度的8進位數字

4’b0101 // 4位元長度的2進位數字

8’h3z // …，且最低4位元為高阻抗

4’b0x10 // …，且第2位元為unknown

12’ox732 // …，且最高3位元為高阻抗

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

/* __________________________*/

數字(Number)(2/2)

• x與z其設定之位元表示:

–若給定數字之最大位數為x或z時，合成工具會將此數字較高位元補滿x或z。

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字串(String)

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識別字(Identifier) &關鍵字(Keyword)

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系統顯示(1/2)

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系統顯示(2/2)

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Applied System IC Design Lab / 45

參考資料

• 授課講義下載 – http://ppt.cc/VpGz

• 參考書目 – YC-FPGA / 允成科技有限公司 (搭配實驗模組) – Verilog FPGA 晶片設計 / 杜灶生(全華圖書) – 硬體描述語言數位電路設計實務 / 鄭信源(儒林圖書)

• 有用的網路資源 – Altera DE2-70 platform:

http://www.cnblogs.com/oomusou/category/110932.html – Nios II Processor:

http://www.cnblogs.com/oomusou/category/106931.html – ModelSim:

http://www.cnblogs.com/oomusou/category/109368.html

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http://ppt.cc/VpGz
http://ppt.cc/VpGz
http://www.cnblogs.com/oomusou/category/110932.html
http://www.cnblogs.com/oomusou/category/110932.html
http://www.cnblogs.com/oomusou/category/106931.html
http://www.cnblogs.com/oomusou/category/106931.html
http://www.cnblogs.com/oomusou/category/109368.html
http://www.cnblogs.com/oomusou/category/109368.html
http://www.cnblogs.com/oomusou/category/109368.html
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Q & A

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應用系統晶片設計實驗室

Applied System IC Design Lab / 45

Thanks for your attention!!!

* ^_________^ *

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