free softcores, tools and tool chains · 2020. 4. 28. · free softcores, tools and tool chains the...

Free Softcores, Tools and Tool Chains

The OpenRISC Experience

Jeremy Bennett, Embecosm

Copyright © 2014 Embecosm and University of Bristol Freely available under a Creative Commons license

What is “Free”

Free, as in “not paid for” Free, as in “freedom”

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Open Source Cores

OpenRISC 1000 LEON

LM32 OpenSPARC


OpenCores OpenRISC 1000


Lattice Semiconductor LM32


Gaisler Aeroflex LEON


Oracle OpenSPARC


Applications Using Open Softcores

Samsung SDP1001 and SDP 1002 set top box controllers

NXP/Jennic JN5148 ultra-low power Zigbee transceiver

NASA TechEdSat EADS Astrium Spacecraft controller on a chip


Software Support

OpenRISC LM32 LEON3 OpenSPARC

Simulators ISSVerilatorEDA simulatorsQEMU

ISS?EDA simulatorsQEMU

Fast cycle trueEDA simulators(QEMU)

IA simulatorEDA simulators(QEMU)

CompilerToolchains

GCC 4.8LLVM 3.3

GCC 4.8 GCC 4.4.2 Sun Studio 12

Unix Linux 3.11 Linux? Linux 2.6.21.1 GentooUbuntuFreeBSDOpenSolaris

RTOS RTEMSFreeRTOSeCos

uC/OS-IIulTRON

RTEMSRTLinuxPikeOSeCosVxWorksLynxOS

?


Licensing

● OpenRISC– LGPL v3– Mozilla derivative (mor1kx)

● LEON3– GPL or private commercial

● LM32– “Free” IP core license

● OpenSPARC– GPL


Modern Licensing Alternatives

● Solderpad Hardware License– Apache based, permissive– copyright based

● CERN OHL 1.2– weak copyleft– copyright based

● TAPR OHL– strong copyleft– patent oriented


Business Models

● Pros– no license fees or royalties– access to open source community effort– increasing commercial support available

● Cons– you have responsibility for verification– beware IP infringement

● Summary– use where processor is not the product USP


Overview of OpenCores

Founded by Damjan Lampret

1999 2007 2011

OpenRISC 1000 developed

OpenRISC 1000 commercial deployment

Primary support Flextronics Owned by ORSoC AB

203,202 registered users reported as of 6 February 2014

1,150 projects as of 6 February 2014

203,202 registered users reported as of 6 February 2014

1,150 projects as of 6 February 2014

Web: www.opencores.org and www.openrisc.netIRC: freenode.net, channel #opencores

Web: www.opencores.org and www.openrisc.netIRC: freenode.net, channel #opencores

http://www.opencores.org/

http://www.opencores.org/


The OpenRISC 1000 Project

● Objective to develop a family of open source RISC designs– 32 and 64-bit architectures– floating point support– vector operation support

● Key features– fully free and open source– linear address space– register-to-register ALU operations– two addressing modes– delayed branches– Harvard or Stanford memory MMU/cache architecture– fast context switch

● Looks rather like MIPS or DLX


The OpenRISC 1200

OpenRISC 1200

PowerMgmt

DebugUnit

TickTimer

PIC

CPU

InstMMU

InstCache

DataMMU

DataCache

JTAG

WishBone

WishBone

ALU

● 32-bit Harvard RISC architecture– MIPS/DLX like instruction set– first in OpenRISC 1000 family– originally developed 1999-2001

● Open source under the– GNU Lesser General Public License– allows reuse as a component

● Configurable design– caches and MMUs optional– core instruction set

● Source code Verilog 2001– approx 32k lines of code

● Full GNU tool chain and Linux port– various RTOS ported as well


OR1200 Simulation Models

● Or1ksim: golden reference ISS

– instruction accurate model● traditional interpreting instruction set simulator, 2-5 MIPS● C and SystemC variants

– use standalone, as GDB remote target or as library

– DejaGnu regression test suite with 2,539 tests

● Verilator cycle accurate model from the Verilog RTL– 130kHz in C++ or SystemC

– can be used as GDB target

● Icarus Verilog event driven simulation– 1.4kHz

– 50x slower than commercial alternatives

– can be used as GDB target


OR1200 Verification1999-2010

● Test bench and DUT simulated using Icarus Verilog– Open source event driven simulator– Approximately 20-50 times slower than NC/VCS/ModelSim– 1.4kHz on a basic Core2 Duo

● Test by running programs in C and assembler– 13 different test programs

● Limitations– not exhaustive– no coverage metrics– not consistent with the golden reference model

Needs ImprovementNeeds Improvement


OVM Verification of the OR1200

● MSc by Waqas Ahmed, KTH, Stockholm● Criteria

– does PC update correctly?– does status update correctly?– does exception save context correctly?– is data stored to the correct memory address?– are results stored correctly in registers?

● Compare behavior of RTL against Or1ksim– constrained random generation of scenarios

● Provide SystemVerilog wrappers– for Or1ksim use DPI to SystemC interface

● Results:– l.jr/l.jalr to unaligned address– l.addic and l.lws missing in DUV– l.macrc/l.ror/l.rori missing from Or1ksim– 20 instructions had errors– most coverage targets achieved


GNU Tool Chain Regression Testing

● A suite of tests developed during the life of these projects– test corner cases that have been bugs in the past– run under DejaGNU control– use the same interface as GDB to drive the target

● Very large test suites– GNU C compiler: approx 100,000 tests– GNU C++ compiler: approx 25,000 tests– GNU C++ library: approx 3,000 tests– GNU Debugger: approx 10,000 tests

● Use the unified SystemC debug interface for comparative testing– Or1ksim as golden reference– Verilator model from RTL as DUV


Comparative Regression Testingof the OpenRISC 1200

=== gcc Summary ===

# of expected passes 52753# of unexpected failures 152# of expected failures 77# of unresolved testcases 122# of unsupported tests 716

=== gcc Summary ===

# of expected passes 52677# of unexpected failures 228# of expected failures 77# of unresolved testcases 122# of unsupported tests 716

Golden SystemC TLM Model Verilator SystemC RTL Model

● We can identify two types of problem– tests which fail due to timing out with RTL, but not due to slower model– tests which give a different result with RTL

● These are candidates for possible RTL errors● All now fixed

– result: a better processor design


The Future for OpenRISC

The OpenRISC 2000 project has started...


The Future


Summary

● There are several well established free softcores.● Many commercial deployments.● Good tool and software support.● Good community support.● Commercial support is available.● The risks are well understood and mitigated.● There is no reason not to use one.


Thank you

www.embecosm.com

http://www.embecosm.com/


MAGEEC

MAchine Guided Energy Efficient Compilation

Jeremy Bennett, Embecosm


The Headlines


What Has Changed?

Ericsson T65– released 2001– Li-Ion 720 mAh– standby 300 h– talk time 11 h– includes talk/standby prediction

Sony Ericsson Xperia X10 mini– released 2010– Li-polymer 930 mAh– standby up to 285 h (3G) / 360 h (2G)– talk time up to 4 h (2G) / 3.5 h (3G)


All Computers Large and Small


Some Mathematics

Energy = Power x Time

Power = Energy ÷ Time

or


Hardware Engineers are Very GoodDynamic Voltage and Frequency Scaling

Dynamic energy lossP ∝ V 2R.f and f ∝ VP ∝ f 3

E = P.t and t = 1/fE ∝ f 2 and E ∝ V 2

Static energy lossP = V 2R and f ∝ VP ∝ f 2

E = P.t and t = 1/fE ∝ f and E ∝ V

Turn off circuits that are not being used: clock gating

Atmel AVR ATxmega256 @3.0V and 2MHz: Idle current 290μAAtmel AVR ATxmega256 @1.8V and 32kHz: Idle current 4μA


Improving Battery Life

Layout

Gate

RTL synthesis

Architecture

ISA

Programming language

Compiler

Application

0 50 100 150 200 250 300

Relative battery lifeBased on Bennett & Eder, 2011

Speculation!


Do Compilers Affect Energy?

Identifying Compiler Options to Minimize Energy Consumption for Embedded PlatformsJames Pallister; Simon J. Hollis; Jeremy BennettThe Computer Journal 2013; doi: 10.1093/comjnl/bxt129http://comjnl.oxfordjournals.org/cgi/reprint/bxt129?ijkey=aA4RYlYQLNVgkE3

◾ Initial research in 2012 by Embecosm and Bristol University

◾ Now published open access in a peer-reviewed journal

http://comjnl.oxfordjournals.org/cgi/reprint/bxt129?ijkey=aA4RYlYQLNVgkE3&keytype=ref


What is MAGEEC?

Today we optimize for speed or space

What if we could optimize for energy usage?


MAchine Guided Energy Efficient Compilation

Research into modeling energy usage

Research into feedback directed optimization

Energy measurement


What's New?

Objective is energy optimization

Generic framework: GCC and LLVM initially

Energy measured not modeled

Working system, not research prototype


A Free and Open SourceEnergy Measurement System

mageec.org/wiki/Power_Sensing_Board

http://mageec.org/wiki/Power_Sensing_Board


BEEBS

● A free and open source benchmark suite for embedded systems– expose different energy consumption characteristics– one benchmark can't trigger all optimisations– broad categories to be considered– integer, floating point, branch frequency, memory bandwidth

The Bristol/Embecosm Embedded Benchmark Suite


Get Involved

● MAGEEC– website: http://mageec.org/– wiki: http://mageec.org/wiki/MAGEEC– mailing list: http://mageec.org/cgi-bin/mailman/listinfo/mageec

● EACOF: https://github.com/eacof/eacof● ENTRA: http://entraproject.eu/

● University of Bristol– PhD, summer projects, secondments, industrial collaborators.– EACO initiative: http://www.cs.bris.ac.uk/Research/Micro/eaco.jsp.

● Embecosm: now hiring

http://mageec.org/

http://mageec.org/wiki/MAGEEC

http://mageec.org/cgi-bin/mailman/listinfo/mageec

https://github.com/eacof/eacof

http://entraproject.eu/

http://www.cs.bris.ac.uk/Research/Micro/eaco.jsp


Thank you

www.embecosm.com

http://www.embecosm.com/

free softcores, tools and tool chains · 2020. 4. 28. · free softcores, tools and tool chains the...

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