TM

October 2013

TM 2

• Memory Organization & Operation

• DDR3 Features & Capabilities

• Initialization & Register Configurations

• Common Issues – Hardware and Software

• DDR Validation Tool

3 TM

S D

G

Cbit Ccol

Row (word) line

Column (bit) line

“1” => Vcc

“0” => Gnd

Vcc/2

“precharged” to Vcc/2

Storage

Capacitor Parasitic Line

Capacitance

Access

Transistor

4 TM

RO

W A

DD

RE

SS

DE

CO

DE

R

SENSE AMPS & WRITE DRIVERS

COLUMN ADDRESS DECODER

W0

B0

W1

W2

B1 B2 B3 B4 B5 B6 B7

5 TM

• Multiple arrays organized into banks

• Multiple banks per memory device

− DDR1 – 4 banks, 2 bank address (BA) bits

− DDR2 & DDR3– 4 or 8 banks, 2 or 3 bank address (BA) bits

− Can have one active row in each bank at any given time

• Concurrency

− Can be opening or precharging a row in one bank while accessing another bank

• May be referred to as “internal”, “logical” or “sub-” banks

Bank 0

Row 0

Row 1

Row 3

Row 2

Bank 1 Bank 2 Bank 3

Row

Buffers

Row …

6 TM

• A requested row is

ACTIVATED and made

accessible through the

bank’s row buffer

• READ or WRITE is

issued to the active row

• The row is

PRECHARGED and is

no longer accessible

through the bank’s row

buffer

Bank 0 Bank 1 Bank 2 Bank 3

Row 0

Row 1

Row 3

Row 2

Row

Buffers

Row …

Bank 0 Bank 1 Bank 2 Bank 3

Row 0

Row 1

Row 3

Row 2

Row

Buffers

Row …

Bank 0 Bank 1 Bank 2 Bank 3

Row 0

Row 1

Row 3

Row 2

Row

Buffers

Row …

7 TM

Command /CS /RAS /CAS /WE ADDR

NOP H X X X X

NOP L H H H X

ACTIVE L L H H BA, Row

READ L H L H BA, Col

WRITE L H L L BA, Col

PRECHARGE L L H L BA

PRECHARGE ALL L L H L A[10]

REFRESH L L L H X

LOAD MODE REGISTER L L L L Bank,

OpCode

8 TM

Trcd (ACTTORW ) = 4 clk

Tck = 3.75 ns

Tccd = 2 clk Trtp (RD_TO_PRE) = 2 clk

BA, ROW BA, COL BA, COL BA

ACTIVE READ READ PRECHARGE

CASLAT = 4 clk

D0 D1 D2 D3 D0 D1 D2 D3

Trp (PRETOACT) = 4 clk

Mem Clk

/CS

/RAS

/CAS

/WE

Address

DQS

DQ

9 TM

Without Dynamic ODT

With Dynamic ODT

Significant improvement

of write signal integrity

with dynamic ODT

Write to slot 1

Write to slot 2

10 TM

Controller

VTT Fly by routing of clk, command and ctrl

DDR3 UDIMM

Controller

VTT Fly by routing of clk, command and ctrl

DDR3 RDIMM

VTT

11 TM

• Prevents Illegal

commands and/or

unwanted states

• Resets all state

information

• No power-down required

• Destructive to data

contents

• Independent of Memory

controller

• Good reference: Micron

Technical note TN41-07

12 TM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Sent during the Active command

Sent during the read/write command

8GB 2GB 64k 8k 8

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

O Byte order in a 64-bit data bus width, 8 bytes R Row order in a 15-bit row DRAM, 32k rows

C Column order in a 10-bit column DRAM, 1k columns S Chip select order in a memory controller w/ 4 CS

B Bank order in a 3-bit bank DRAM, 8 banks M Memory controller order in a part with 2 MC

M 0

S 1

S 0

R 14

R 13

R 12

R 11

R 10

R 9

R 8

R 7

R 6

R 5

R 4

R 3

R 2

R 1

R 0

B 2

B 1

B 0

C 9

C 8

C 7

C 6

C 5

C 4

C 3

C 2

C 1

C 0

O 2

O 1

O 0

M 0

S 1

S 0

R 14

R 13

R 12

R 11

R 10

R 9

R 8

R 7

R 6

R 5

R 4

R 3

R 2

R 1

R 0

B 2

B 1

B 0

C 9

C 8

C 7

C 6

C 5

C 4

C 3

C 2

C 1

C 0

O 2

O 1

O 0

13 TM

• Micron MT47H32M8

• 32M x 8 (8M x 8 x 4 banks)

• 256 Mbits total

• 13-bit row address

− 8K rows

• 10-bit column address

− 1K bits/row (8K total when you take

into account the x8 width)

• 2-bit bank address

• Data bus: DQ, DQS, /DQS, DM

• ADD bus: A, BA, /CS, /RAS, /CAS,

/WE, ODT, CKE, CK, /CK

32M x 8

256 Mb13

2

8ADDR

BANK ADDR

DATA

DATA

STROBE(S)

DATA

MASK

ODT

/CS

/RAS

/CAS

/WE

CKE

CK

/CK

A[12:0]

BA[1:0]

Command

Bus

CK

DQ[7:0]

DQS

/DQS

DM

ODT

DATA bus

ADD bus

14 TM

• Micron MT9HTF3272A

• 9 each 32M x 8 memory devices

• 32M x 72 overall

• 256 MB total, Single “rank”

• 9 “byte lanes” – ECC is just a data lane

for “check bits” to/from DDR controller

Two Signal Bus

• 1- Address, command, control, and

clock signals are shared among all 9

DRAM devices

• 2- Data, strobe, data mask not shared

32M x 8

/CS

/RAS

/CAS

/WE

CKE

CK

/CK

A[12:0]

BA[1:0]

DQ[7:0]

DQS

/DQS

DM

ODT

32M x 8

/CS

/RAS

/CAS

/WE

CKE

CK

/CK

A[12:0]

BA[1:0]

DQ[7:0]

DQS

/DQS

ODT

MDQ[0:7], MDQS0, MDM0

MDQ[48:55], MDQS6, MDM6

MDQ[8:15], MDQS1, MDM1

MDQ[16:23], MDQS2, MDM2

MDQ[24:31 MDQS3, MDM3

MDQ[32:39], MDQS4, MDM4

MDQ[40:47], MDQS5, MDM5

MDQ[56:31], MDQS7, MDM7

ECC[0:7], MDQS8, MDM8

/CSn ODTn

DM

15 TM

• Write leveling used to add delay

to each strobe/data line.

Freescale

Chip

Address,

Command

& Clock Bus

Data Lanes

Write leveling sequence during the initialization process will determine the

appropriate delays to each strobe/data byte lane and add this delay for every

write cycle.

16 TM

• Automatic CAS to preamble calibration

• Data strobe to data skew adjustment

Freescale

Chip

Address,

Command

& Clock Bus

Data Lanes

Instead of JEDEC’s MPR method, Freescale controllers use a proprietary method of read

adjust method. Auto CPO will provide the expected arrival time of preamble for each

strobe line of each byte lane during the read cycle to adjust for the delays cased by the

fly-by topology.

17 TM

• Supports JEDEC standard x8, x16 DDR3 devices

• Memory device densities up to 8Gb

• Data rates up to 2133MT/s for DDR3

• Up to four physical ranks (chip selects)

• Physical rank sizes up to 8GB, total memory up to 32GB per

controller

• Physical rank interleaving between 2 or 4 chip selects

• Memory controller interleaving when more than 1 controllers are

available

• Unbuffered or registered DIMMs supported

18 TM

• Up to 32 open pages

− Open row table

− Amount of time rows stay open is programmable

• Auto-precharge, globally or by chip select

• Self-refresh

• Up to 8 posted refreshes

• Automatic or software controlled memory device initialization

• ECC: 1-bit error correction, 2-bit error detection, detection of all errors within a nibble

• ECC error injection

• Read-modify-write for sub-doubleword writes when using ECC

• Automatic data initialization for ECC

• Dynamic power management

19 TM

• DDR3L (1.35V) is a low voltage version of the DDR3 (1.5V).

• DDR3L meet the exact same functional and timing

specifications of DDR3.

• VIH/VIL differences are compensated by corresponding

derating values to Vref resulting no change in AC timing, and

timing budget calculation.

• Example QorIQ products supporting DDR3L:

− P1023, P1017, P1010, P1014, P2040, P3041, P5020, T1040,

T4240

TM 20

• DDR Common Issues

− DDR3 initialization flow

− HW pitfalls

− DDR3 reset timing

− Typical boot-time issues for DDR3

− DDRV tool tips

− DDRv Walkthrough

21 TM

Power-up

DDR

Reset

DDR

CTRL

INIT

Chip selects

enabled and

DDR clocks

begin

Asserted at

least 200us

Stable

CLKS CKE = HIGH

DRAMs

Initialized

Mode Register

Commands Issued

ZQ

Calibration

Write

Leveling

Read

Adjust

Controller

Started

MEM_EN =1

Automatic CAS-to-Preamble

(aka Read Leveling)….

Plus Data-to-Strobe adjustment

ZQCL Issued (512 clocks)

Also DLL lock time is occurring

Init

Complete Ready for User accesses

Automatically handled

By the controller

Need at

least 500us

from reset

de-assertion

to the

controller

being

enabled.

Timed loop

may be

needed.

22 TM

1. Missing DDR3 Reset control or timing violates JEDEC spec

2. Noisy Vref: Care must be taken to isolate Vref

3. No ECC. Without ECC it is difficult to detect runtime memory errors!

4. Ref Plane: ensure excellent reference plane for all DDR signals

5. Termination missing: Discrete implementations require term on address/command/control/clock.

6. POR Config: Insure correct DDR type is selected—DDR3 or DDR3L

7. Expandability: Hook up unused address lines

8. Incorrect Topology: Use JEDEC routing topologies. For DDR3 fly-by topology should be used.

9. Separate VDDQ/VDDIO : VDDQ and VDDIO are common on DDR DIMM Modules, not on controller.

10. Recommended reading--AN3940 (DDR3/3L)

“Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces”

23 TM

1. Do not release DDR3 and CPU reset at same time!

2. Need to keep DDR3 reset asserted during CPU reset and at least

200uS after CPU reset is released.

3. Delaying DDR3 reset release ensures that all DDR controller I/O

are tri-state--except CKE#, which always is asserted early in CPU

reset.

• Suggest implementation in your system logic.

• Might need to adjust DDR3 reset delay timing to make it longer.

4. In some QorIQ products, HRESET_B can be used to gate DDR3

reset in system logic. HRESET_B output is driven high after CPU

reset is complete. See “Power-On Reset Sequence” in reference

manuals.

− For example P2041, P3041, P4080, P5020, T1040, T4240

24 TM

25 TM

1. U-boot hangs when DDR is accessed

− Check to see if DDR_SDRAM_CFG2[D_INIT] clears

Use a timing loop in SW checking completion.

All memory DDR3 locations will be written after controller has initialized.

− D_INIT not clearing means DDR controller did not complete its initialization process due to a DDR3 issue.

Check that all DDR3 data lanes are responding to read commands.

2. ACE Errors – Autocalibration errors

− ACE can occur with or without D_INIT not clearing.

− Typically caused by DDR controller register programming issues

Create or recheck register settings – can use QorIQ Configuration Suite.

− If register settings seem O.K., but ACE continues, likely a hardware issue

Check to see all DDR3 devices are actually working

Signal integrity issues on Data or Command/Address bus.

TM

27 TM

1. Make sure that COP/JTAG can reset your target via its HRESET line. − Lack of reset control will keep DDRv from overating.

− DDRv will be resetting target many times during testing.

− Make sure that your RCW_SRC can be loaded when COP resets your target. I.E. make sure your RCW flash can still be accessed when COP issues a target reset.

Might have to modify your system logic during memory validation testing.

2. Disable all watch dog timers in your target system − Target reboot will prevent DDRv from operating.

− Does console screen show repeating reboots during testing?

If yes, you still have a WDT still enabled somewhere in your board logic.

3. Boot your target via console to u-boot or kernel prompt—then start DDRv testing. − DDRv will “grab” control of board during testing.

− Console will be unresponsive—this is expected.

− Testing overwrites anything stored in DDR3, so you will have to reboot afterwards.

4. Testing can take time, suggest disabling sleep/hibernate modes on your PC host.

− Will prevent loss of results during testing.

28 TM

DDRv Website: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=P

E_QORIQ_DDRV

License file:

<QCS Install directory>/eclipse/Optimization/license.dat

29 TM

1

Test

stages /

scenarios

Tests to be

executed per

each scenario

Scenario

details

2

HW

Connection

setup

30 TM

1

2

3 4

5

6

7

8

9

10

11

12

13

31 TM

Check the

scenarios to

be tested

Double click

on test to see

its content

1

2

3

Choose

which test to

be executed

and how

many times

32 TM

Test results

per DDR

configuration

33 TM

Optimal DDR

configuration

is bolded

Proceed to

next

validation

step

Tests to be

executed can

be changed

between

executions

34 TM

Optimal

settings

35 TM

• Read DDR configuration from uboot

• => md ffe02000

− ffe02000: 0000003f 00000000 00000000 00000000 ...?............

− ffe02080: 80014202 00000000 00000000 00000000 ..B.............

− ffe02100: 00030000 00110104 6f6b8846 0fa8c8cc ........ok.F....

− ffe02110: c7000008 24401040 00441421 00000000 ....$@.@.D.!....

− ffe02120: 00000000 0c300100 deadbeef 00000000 .....0..........

− ffe02130: 03000000 00000000 00000000 00000000 ................

− ffe02160: 00220001 02401400 00000000 00000000 ."...@..........

− ffe02170: 89080600 8675f608 00000000 00000000 .....u..........

• => md ffe02b00

− ffe02b00: 00000000 00000000 00000000 00000000 ................

− ffe02b10: 00000000 00000000 00000000 00000000 ................

− ffe02b20: 5dc07777 77000000 00000000 00000000 ].www...........

Uboot

values

36 TM

• You need QCS 2.2.1 or later installed. Get it from

www.freescale.com/qcs

• Use Eclipse “Add new software..” Eclipse updater

capability to install DDRV on top of QCS. Use as an update

link:

http://freescale.com/lgfiles/updates/Eclipse/Helios36/DDRValid

ation for installation over QCS installed over Eclipse 3.6 or CW

PA 10

• http://freescale.com/lgfiles/updates/Eclipse/Indigo37/DDRValid

ation for installation over QCS installed over Eclipse 3.7

37 TM

• Books:

− DRAM Circuit Design: A Tutorial, Brent Keeth and R. Jacob Baker, IEEE Press, 2001

• Freescale AppNotes: − AN2582 Hardware and Layout Design Considerations for DDR Memory Interfaces

− AN2910 Hardware and Layout Design Considerations for DDR2 Memory Interfaces

− AN2583 Programming the PowerQUICCIII / PowerQUICCII Pro DDR SDRAM Controller

− AN3369 PowerQUICC DDR2 SDRAM Controller Register Setting Considerations

− AN3939 PQ & QorIQ Interleaving

− AN3940 Layout Design Considerations for DDR3 Memory Interface

− AN4039 PowerQUICC DDR3 SDRAM Controller Register Setting Considerations

− https://www.freescale.com/cgi/go/NPD_biweeklytraining

• Micron AppNotes:

− TN-46-05 General DDR SDRAM Functionality

− TN-47-02 DDR2 Offers New Features and Functionality

− TN-47-01 DDR2 Design Guide

− TN-41-07 DDR3 Power-Up, Initialization, and Reset

− TN-41-08 DDR3 Design Guide

• JEDEC Specs:

− JESD79E Double Data Rate (DDR) SDRAM Specification

− JESD79-2F DDR2 SDRAM Specification

− JESD79-3F DDR3 SDRAM Specification

• TOOLS:

− QCS DDRV tool

TM

39 TM

VT

T

Fly

by r

ou

tin

g

Controller

VT

T

Fly

by r

ou

tin

g

A B

D

E

Recommended:

1. A = D

2. B = E

3. A = address,

commands,

controls, and

clocks signal

trace lengths.

4. D = Data,

strobes, and

masks signal

trace lengths.

Pin on Package

Pin on DIMM connector

40 TM

• The RZQ resistor is connected between the DDR3 memory and ground

− Value = 240 Ohm +/- 1%

− Permits driver and ODT calibration

• Easier and more accepted than DDR2’s (optional) OCD method.

• Our controllers support both ZQ calibration commands

− ZQCL – used during initialization (..takes longer)

− ZQCS – used during normal operation (…periodic and takes less time)

41 TM

• FSL DDR3 memory controller supports address mirroring

• This option is only available for dual ranked DIMM

Non-Mirrored Mirrored

42 TM

• Root cause of observed failures:

− Incorrect register setting

− Board changes, layout, power supply

− DRAM changes, die revision or different DRAM vendor used

− Missing erratum implementation

− FPGA firmware changes

− Environment changes

− Missing or incorrect errata workaround implementation

• Step 1 what has changed?

• Step 2 Verify a good register setting, including RCW and LAW registers using the tools.

• Step 3 Scrub the HW layout and schematics, including trace lengths, proper connections and terminations.

TM