2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Front-end FPGAs in the LHCb upgrade

The issues What is known

Work plan

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Why The use of FPGA in and near front end boards

may help in (thoughts inspired by VELO upgrade considerations):

reduce the number of optical links used in the TELL40 boards

Provide an intermediate layer of processing prior to the TELL40 boards (extended BCO tag, chip ID, …)2

Advantages: Reconfigurable May provide an effective way to perform the lowest

level clustering, sorting, extended address/time stamp options

Interface specific detector algorithms to a common back end (TELL40) device

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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The issues

Radiation level expected is a major constrain: for a specific application we need to know: Radiation level expected in the board

location for the planned duration of the data taking

Functionality needed in the FPGA to be adopted

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Starting point: survey of what is known

Sources: Alice Detector Data Link project [200

MB/s @1.6 KRad] “Problems and solutions to the use of

FPGA’s in radiation zone” seminar by Czaba Soos [http://indico.cern.ch/conferenceDisplay.py?confId=39740]

NASA, XILINX… web sites

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Concerns in FPGA performance

Single-Event Upsets (SEUs) Single-Event Transients (SETs) Single-Event Functional Interrupt

(SEFI) Configuration loss Data corruption

Damaging effects (Single Event Gate Rupture, Single Event Latch up)

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Some definitions

SEU: state change due to the charge collected by the circuit sensitive node, if higher than a critical linear energy transfer (LET)

SET: Voltage transient induced by charge deposition propagating through FPGA, latched if arrive at a clock edge, propagation distance decreases as the square of the technology feature size

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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The ALICE DDL Project High speed point to point optical link

designed to interface the readout electronics of the ALICE sub-detectors (except inner tracker) to the DAQ computers in a standard way

Speed 200 MB/s/link Max radiation fluence 3.9x1011 n/cm2,

8x109 p/cm2, 1.5x1011 1 MeV neq/cm2

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Results from Alice DDL Project

Configuration loss measurements for SRAM & flash memory FPGA

= probability that the particle flips a bit cm2/logic cell Radiation tolerant ~1 KRad

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Data corruption measurement

Mitigation techniques can be used to detect/correct data corruption. Error rate is application specific

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A brighter spot: radiation tolerance trend as a function of feature size

Ultra thin oxide features reduced interface trap and oxide trap charge

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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New devices

XILINX: VIRTEX-4QV 300 KRad TID wafer lot

verification XILINX VIRTEX-5 (65 nm) Lots of useful information at

http://www.xilinx.com/esp/aero_def/radiation_effects.htm

ALTERA STRATIX (0.13 μm-0.065 μm), recently 40 nm unveiled (stratix IV)

2/2/2009 Marina Artuso LHCb Electronics Upgrade Meeting

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Plans

Define problem(s): Are there different front end interfaces that

have similar functionality (configuration memory size, register cell size, memory cell size…)

Which are the levels of radiation that we are tackling with (few KRad-several 100 Krad)

Useful mitigation techniques Design demonstrator system & test at

suitable level of irradiation.