functioning hardware from functional specifications€¦ · ibm pl day, november 18, 2014....
TRANSCRIPT
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Functioning Hardwarefrom
Functional Specifications
Stephen A. EdwardsMartha A. Kim
Richard TownsendKuangya Zhai
Lianne Lairmore
Columbia University
IBM PL Day, November 18, 2014
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Where’s my 10 GHz processor?
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Intel CPU Trends
Sutter, The Free Lunch is Over, DDJ 2005. Data: Intel, Wikipedia, K. Olukotun
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The Cray-2: Immersed in FluorinertThe Cray-2: Immersed in Fluorinert
1985 ECL 150 kW1985 ECL 150 kW
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Where’s all that power going?What can we do about it?
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Dally: Calculation Cheap; Communication Costly
64b FPU
0.1mm2
50pJ /op1.5GHz
64b 1mm
Channel25pJ /word
64b Off-Chip
Channel1nJ /word
64bFloatingPoint
20mm
10m
m 2
50pJ
, 4 c
ycle
s
“Chips are powerlimited and mostpower is spentmoving data
Performance =Parallelism
Efficiency =Locality
Bill Dally’s 2009 DAC Keynote, The End of Denial Architecture
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Parallelism for Performance; Locality for Efficiency
Dally: “Single-thread processors arein denial about these two facts”
We needdifferent programming paradigmsanddifferent architectureson which to run them.
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The Future is Wires and Memory
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How best to use all thosetransistors?
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Dark SiliconDark Silicon
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Taylor and Swanson’s Conservation Cores
BB1
BB0
BB2
CFG +
+
*
LD
+ LD LD
+1 <N?
+ + +
ST +
Datapath
Inter-BB State Machine
0.01 mm2 in 45 nm TSMC runs at 1.4 GHz
.V
Synopsys IC Compiler, P&R, CTS
C-core Generation
.V
Code to Stylized Verilog and through a CAD flow.
Custom datapaths, controllers for loop kernels; uses existingmemory hierarchySwanson, Taylor, et al. Conservation Cores. ASPLOS 2010.
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Bacon et al.’s Liquid Metal
Fig. 2. Block level diagram of DES and Lime code snippet
JITting Lime (Java-like, side-effect-free, streaming) to FPGAsHuang, Hormati, Bacon, and Rabbah, Liquid Metal, ECOOP 2008.
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What are we doing about it?
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Functional Programs to FPGAs
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Functional Programs to FPGAs
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Functional Programs to FPGAs
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Functional Programs to FPGAs
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Functional Programs to FPGAs
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Functional Programs to FPGAs
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Functional Programs to FPGAs
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Why Functional Specifications?
I Referentialtransparency/side-effect freedommake formal reasoning aboutprograms vastly easier
I Inherently concurrent andrace-free (Thank Church andRosser). If you want races anddeadlocks, you need to addconstructs.
I Immutable data structures makesit vastly easier to reason aboutmemory in the presence ofconcurrency
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Why FPGAs?
I We do not know the structure offuture memory systemsHomogeneous/Heterogeneous?Levels of Hierarchy?Communication Mechanisms?
I We do not know the architectureof future multi-coresProgrammable in Assembly/C?Single- or multi-threaded?
Use FPGAs as a surrogate. Ultimately too flexible, butrepresentative of the long-term solution.
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The Practical Question
How do we synthesize hardwarefrom pure functional languages
for FPGAs?
Control and datapath are easy; the memory system isinteresting.
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The Type System: Algebraic Data Types
Types are primitive (Boolean, Integer, etc.) or other ADTs:
type ::= Type Primitive type| Constr Type∗ | · · · | Constr Type∗ Tagged union
Examples:
data Intlist = Nil −− Linked list of integers| Cons Int Intlist
data Bintree = Leaf Int −− Binary tree of integers| Branch Bintree Bintree
data Expr = Literal Int −− Arithmetic expression| Var String| Binop Expr Op Expr
data Op = Add | Sub | Mult | Div
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Example: Huffman Decoder in Haskell
data HTree = Branch HTree HTree | Leaf Chardecode :: HTree→ [Bool]→ [Char]decode table str = bit str tablewhere
bit (False:xs) (Branch l _) = bit xs l −− 0: leftbit (True:xs) (Branch _ r) = bit xs r −− 1: rightbit x (Leaf c) = c : bit x table −− leafbit [] _ = [] −− done
1 Leaf8-bit char
9-bit pointer9-bit pointer 0 Branch
1 ConsB12-bit pointer
0 Nil
1 Cons8-bit char10-bit pointer
0 Nil
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Optimizations
Memory
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Optimizations
Memory
Input Output
HTree
SplitMemories
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Optimizations
Memory
Input Output
HTree
In FIFO
Mem
Out FIFO
MemHTree
SplitMemories
Use Streams
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Optimizations
Memory
Input Output
HTree
In FIFO
Mem
Out FIFO
MemHTree
In FIFO
Mem
Out FIFO
MemHTree
SplitMemories
Use Streams
Unroll for locality
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Optimizations
Memory
Input Output
HTree
In FIFO
Mem
Out FIFO
MemHTree
In FIFO
Mem
Out FIFO
MemHTree
In FIFO
Mem
Out FIFO
Mem
HTree Mem
SplitMemories
Use Streams
Unroll for locality
Speculate
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Hardware Synthesis:Semantics-preserving steps to
a low-level dialect
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Removing Recursion: The Fib Example
fib n = case n of1 → 12 → 1n → fib (n−1) + fib (n−2)
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Transform to Continuation-Passing Style
fibk n k = case n of1 → k 12 → k 1n → fibk (n−1) (λn1→
fibk (n−2) (λn2→k (n1 + n2)))
fib n = fibk n (λx→ x)
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Name Lambda Expressions (Lambda Lifting)
fibk n k = case n of1 → k 12 → k 1n → fibk (n−1) (k1 n k)
k1 n k n1 = fibk (n−2) (k2 n1 k)k2 n1 k n2 = k (n1 + n2)k0 x = xfib n = fibk n k0
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Represent Continuations with a Type
data Cont = K0 | K1 Int Cont | K2 Int Cont
fibk n k = case (n,k) of(1, k) → kk k 1(2, k) → kk k 1(n, k) → fibk (n−1) (K1 n k)
kk k a = case (k, a) of((K1 n k), n1)→ fibk (n−2) (K2 n1 k)((K2 n1 k), n2)→ kk k (n1 + n2)(K0, x ) → x
fib n = fibk n K0
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Merge Functions
data Cont = K0 | K1 Int Cont | K2 Int Contdata Call = Fibk Int Cont | KK Cont Int
fibk z = case z of(Fibk 1 k) → fibk (KK k 1)(Fibk 2 k) → fibk (KK k 1)(Fibk n k) → fibk (Fibk (n−1) (K1 n k))
(KK (K1 n k) n1) → fibk (Fibk (n−2) (K2 n1 k))(KK (K2 n1 k) n2)→fibk (KK k (n1 + n2))(KK K0 x ) → x
fib n = fibk (Fibk n K0)
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Add Explicit Memory Operations
load :: CRef→Contstore :: Cont→CRefdata Cont = K0 | K1 Int CRef | K2 Int CRefdata Call = Fibk Int CRef | KK Cont Int
fibk z = case z of(Fibk 1 k) → fibk (KK (load k) 1)(Fibk 2 k) → fibk (KK (load k) 1)(Fibk n k) → fibk (Fibk (n−1) (store (K1 n k)))
(KK (K1 n k) n1) → fibk (Fibk (n−2) (store (K2 n1 k)))(KK (K2 n1 k) n2)→fibk (KK (load k) (n1 + n2))(KK K0 x ) → x
fib n = fibk (Fibk n (store K0))
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Syntax-Directed Translation to Hardware
fib
fibk
load
store
mem
load′
Call
do
wedia
CRef
CRef
Cont
result
n
Cont
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Duplication Can Increase Parallelism
fib 0 = 0fib 1 = 1fib n = fib (n−1) + fib (n−2)
After duplicating functions:
fib 0 = 0fib 1 = 1fib n = fib ′ (n−1) + fib′ ′ (n−2)
fib ′ 0 = 0fib ′ 1 = 1fib ′ n = fib ′ (n−1) + fib′ (n−2)
fib ′ ′ 0 = 0fib ′ ′ 1 = 1fib ′ ′ n = fib ′ ′ (n−1) + fib′ ′ (n−2)
Here, fib’ and fib” may run inparallel.
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Duplication Can Increase Parallelism
fib 0 = 0fib 1 = 1fib n = fib (n−1) + fib (n−2)
After duplicating functions:
fib 0 = 0fib 1 = 1fib n = fib ′ (n−1) + fib′ ′ (n−2)
fib ′ 0 = 0fib ′ 1 = 1fib ′ n = fib ′ (n−1) + fib′ (n−2)
fib ′ ′ 0 = 0fib ′ ′ 1 = 1fib ′ ′ n = fib ′ ′ (n−1) + fib′ ′ (n−2)
Here, fib’ and fib” may run inparallel.
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Unrolling Recursive Data Structures
Original Huffman tree type:
data Htree = Branch Htree HTree | Leaf Char
Unrolled Huffman tree type:
data Htree = Branch Htree′ HTree′ | Leaf Chardata Htree′ = Branch′ Htree′′ HTree′′ | Leaf′ Chardata Htree′′ = Branch′′ Htree HTree | Leaf′ ′ Char
Increases locality: larger data blocks.
A type-aware cache line
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I Dark Silicon is the future: fastertransistors; most must remain off
I Custom accelerators are thefuture; many approaches
I Our project: A Pure FunctionalLanguage to FPGAs
BB1
BB0
BB2
CFG
+
+
*
LD
+ LD LD
+1 <N?
+ + +
ST +
Datapath
Inter-BB State Machine
0.01 mm2 in 45 nm TSMC runs at 1.4 GHz
.V
Synopsys IC Compiler, P&R, CTS
C-core Generation
.V
Code to Stylized Verilog and through a CAD flow.
C et al.
x86 et al.
gcc et al.
abstraction
timetoday
FutureLangu
ages Higher-levellanguages
Future ISAsMorehardware reality
A Functional IR
FPGAs
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I Algebraic Data Types in Hardware
I Optimizations
I Removing recursion
Encoding the Types
Huffman tree nodes: (19 bits)
1 Leaf8-bit char
9-bit pointer9-bit pointer 0 Branch
Boolean input stream: (14 bits)
1 ConsB12-bit pointer
0 Nil
Character output stream: (19 bits)
1 Cons8-bit char10-bit pointer
0 Nil
Optimizations
Memory
Input Output
HTree
In FIFO
Mem
Out FIFO
MemHTree
In FIFO
Mem
Out FIFO
MemHTree
In FIFO
Mem
Out FIFO
Mem
HTree Mem
SplitMemories
Use Streams
Unroll for locality
Speculate
Syntax-Directed Translation to Hardware
fib
fibk
load
store
mem
load′
Call
do
wedia
CRef
CRef
Cont
result
n
Cont