g é rard: the hard man behind the soft core
DESCRIPTION
G é rard: The Hard Man behind the Soft Core. Satnam Singh Microsoft Research, Cambridge UK The University of Birmingham. !. multiple independent multi-ported memories. hard and soft embedded processors. fine-grain parallelism and pipelining. BlockRam Memory Map (.bmm). - PowerPoint PPT PresentationTRANSCRIPT
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Gérard: The Hard Man behind the Soft Core
Satnam SinghMicrosoft Research, Cambridge UK
The University of Birmingham
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!
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multipleindependentmulti-ported
memories
fine-grainparallelism
andpipelining
hard and softembeddedprocessors
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0101110001110001110100111001100100111000111001010110001110001110
New .bit File0101110001110001110100111001100100111000111001010110001110001110
.mem File
DATA2BRAM
0101110001110001110100111001100100111000111001010110001110001110
ELF File
# CPU address space 0xFFFFE000 - 0xFFFFFFFF. ADDRESS_BLOCK dramctlr BUS_BLOCK [0xFFFFF000:0xFFFFFFFF] xrefdes/dramctlr/bram0 [7:0] LOC=RAMB16_X0Y0; xrefdes/dramctlr/bram1 [15:8] LOC=RAMB16_X1Y0; xrefdes/dramctlr/bram2 [23:16] LOC=RAMB16_X2Y0; . . . END_BUS_BLOCK; END_ADDRESS_BLOCK;
BlockRam Memory Map (.bmm)
0101110001110001110100111001100100111000111001010110001110001110
.bit File
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ZBT SSRAM SDRAM
ZBT SSRAMController
SDRAMController
405PPC
On-ChipPeripheral
ROM
High-SpeedPeripheral
On-ChipPeripheral
CoreConnect OPB(On-Chip Peripheral Bus)
OPB
DDRSDRAM
CoreConnect Processor Local Bus (PLB) Arbiter
DDR SDRAMController
External BusController OPB Bridge
OPB BridgeI-Cache PLB
D-Cache PLB
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locksmonitorscondition variablesspin lockspriority inversion
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PLDI 1998
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PLDI 1999
12345
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PLDI 2000
1 2 3 4 50
10
20
30
40
50
60
70
80
Series1Series2
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POPL 1998
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POPL 1999
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POPL 2000
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ray of light
Signal
Lustre
PRET-C
SHIM
Jazz
Esterel
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San Jose, 6 June 2003
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Sylvan Dissoubray
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Gérard wearing Satnam’s ring
Satnam wearing Gérard’s ring
San Jose, 6 June 2003
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Gérard Berry
Synchronous Programming Language Combat Team
Albert Benveniste
NicolasHalbwachs
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Zero delay example: Newtonian Mechanics
Concurrency + DeterminismCalculations are feasible
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Predictable delay examples: sound, light, waves
• Wait long enough, same result as 0-delay !• Zero delay and predictable delay are fully compatible• Constructive semantics is the unification• A theory of causality for reactive systems
• Clocked digital circuits paradigm
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Safe State Machines Esterel code
loop [ await A || await B ] ; emit Oeach R
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Esterel design
void uart_device_driver (){.....} uart.c
VHDL, Verilog -> hardware implementation
C -> software implementation
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Hardware UART
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Software UART
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18/01/2011 31G. Berry, Microsoft Research
Project Structure
Automatic Documentation
ProjectManagement
Executable Specification
Exporter
Debugging & Simulation
Formal Verification
DesignVerification
Sequential Equivalence
check
DUT
Optimized for synthesisDFT-ready
SystemC & RTL flow integration
C / C++ / SystemC Verilog / VHDL
.sc .vhd
Architecture
Design Specification CaptureDesign
FunctionalSpec Verification
Requirements
ArchitectureDiagram (2007)
Editor
Simulator
DesignVerifier
ModelReporter
Code & TestbenchGenerators
Editor
SequentialEquivalence
Checker
IDE
PlayerIDE
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G. Berry, Microsoft Research 18/01/2011 32
SCADE in the Airbus A380
– Flight Control system – Flight Warning system– Electrical Load Management system– Anti Icing system– Braking and Steering system– Cockpit Display system– Part of ATSU (Board / Ground comms)– FADEC (Engine Control)– EIS2 : Specification GUI Cockpit:
– PFD : Primary Flight Display– ND : Navigation Display– EWD : Engine Warning Display– SD : System Display
Flight ControlPrimary & Secondary
Commands
Anti Ice Control Unit
FlightWarningSystem
Braking & Steering Control Unit
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French Synchronous Language Thread Level Remains High
SEVERE:hysteresis
HIGH:deadlock
ELEVATED:priority inversion
GUARDED:non-atomic action
LOW:race condition
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begin…end
procedurestatic final void
forwhile
loop
accept
if then else
case
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present gift then await scream end present
Thank you Stephen Edwards
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present gift then pause; every day do await thanks end every end present
Thank you Stephen Edwards
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abort nothing when bored
Thank you Stephen Edwards
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every day do nothing end every
Thank you Stephen Edwards
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run slowly
Thank you Stephen Edwards
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await falls ; every body do sustain disbelief end every
Thank you Stephen Edwards
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present case legally do run away end present
Thank you Stephen Edwards
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abort task when immediate objection
Thank you Jens Brandt
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abort run slowly || run fastly when sleepy
Thank you Mike Kishinevsky
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trap mouse in every loop do run cheese end every handle hair do run water end trap
Thank you Mike Kishinevsky
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Engine control software programmed in Esterel by non-French speaker
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Kavi Arya, Mumbai, 10 January 2004
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Esterel
present A then emit A end
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QEsterel
present A then emit A end
Thank you Georges Gonthier
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Mike Kishinevsky
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Mike Kishinevsky