Gaining Insight into DDR3/4 and LPDDR3/4

Alan Gosselin

Senior Field Applications Engineer

Digital Verification Tools

April 2015

Agenda – Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

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Insight for DDR2/3/4 and LPDDR/2/3/4 Data Rates

Data Rate (Mb/s)

2015 -

Majority

new

designs

will be in

this

range

DQ capture over 2400Mb/s is particularly challenging

0

500

1000

1500

2000

2500

3000

3500

4000

4500

2013 2014 2015 2016

LPDDR4

LPDDR3

DDR4

DDR3

3

2400 Mb/s

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DDR4 and LPDDR4 Design and Validation Challenges

• Faster data rates and smaller signal swings

• Extreme space constraints

• New protocols with new features require new memory controllers

• Memory controllers must be smarter

• Power management features need to be understood to optimize systems.

• Risk that systems will not behave as designed

Maintaining signal integrity at higher data rates with smaller signal swings is a significant challenge

Insight required to meet challenges

4

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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DDR4 x4/x8 BGA interposer

Soft Touch Pro

Mid-Bus Probing

DDR4 SODIMM Interposer DDR4 DIMM interposer

LPDDR3 POP interposer

Specialty probing from Keysight User designs probing into system under test

Proven LA Probing Techniques for Highest Data Rates

Industry standard interposers = Designed and available!

Follow

Design

guidelines!

Run

simulations!

Joint technical effort to meet specific needs

Aug 6, 2013

MemCon 6

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DDR4 LA Interposers

Ease of connection

Direct connect to U4154B

Low profile - Minimal loading

Support UDIMM or RDIMM

Timing and State analysis

Support DDR Setup Assistant and

DDR Eye Scan

FS2510: DDR4 DIMM interposer

FS2512B: DDR4 1867 SODIMM interposer

FS2510 Proven DDR4 >3.1Gb/s

simultaneous Read and Write capture

with FS1070 conversion kit

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• Designed for DDR4 < and > 2400

• Three flex wings:

• Bend up to 180 deg

• Recommended bend radius of 1.27MM if

flex is bent at rigid portion of interposer

• ZIF doors and GND plane on back

side of wings

• Requires two E5849A DDR4 ZIF cables

DDR4 x4/x8 BGA LA Interposer – W4633A

MemCon

Aug 6, 2013

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Probing Techniques: LA Mid-Bus Probing Keysight DDR Configurator Creator Tool to simplify and ensure:

• Proper labels for SW tools, DDR

triggers and DDR setup

assistant

• Proper scan windows for State

mode

• Proper scan triggers for DDR

Eyescan

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DDR4 x4/x8 BGA Scope Interposer

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Riser

DDR4 BGA interposer

DDR4 DRAM

Note: All signals available at probe points except

power, Vref, RFU

Elevates the interposer for

smaller surface keep-out area

Supports x4/x8 pin-out

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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• Asynchronous to system under test

• High Resolution is most useful >2400Mb/s

Timing modes – See when events happen

• Synchronous to clock from system

• Enables most powerful SW tools

State mode – Follow signal flow – see what happened

• Unique qualified views of all ADD/CMD/DQ/DQS

DDR eye scan mode – eye diagrams

Sept 18, 2012

Insight from Logic Analysis – Multiple Modes & Views

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– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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Bus Level Signal Integrity Insight

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2 modes - multiple views

• Required to set State mode sampling positions

• Rapid Bus level signal integrity insight

Overlay Mode

• Unique qualified scan views

• Simultaneous views of all DQ and DQS

Signal Trace Mode

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Challenge: Eye openings on DDR4 > 3.1Gb/s

Next Steps:

• Take trace to inspect ODT operation

• Cross trigger scope to check for ISI

Eye Scan Insight:

• Potential ODT setting

issue. Threshold of first

bit in burst has less swing

than remainder of burst.

• Could also be ISI

(inter-symbol interference)

• Overdriving DDR4 DRAM

to 1.4V could cause

damage.

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Insight: DDR4 Inter-symbol Interference (ISI)

Symptom: READ Data Corruption on DDR4 1600 system

Next Steps:

• Check for ISI with scope

• Review simulations of

READ data. Look closely

at DRAM drivers and

termination.

Eye Scan Insights:

• DDR4 2400 system looks good, no ISI

• DDR4 1600 system exhibits ISI on READ DQ

and DQS.

Eye Scan Settings: Signal trace mode

DDR4 2400 DDR4 1600

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Challenge: System Signal Integrity

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DDR4 >3.1Gb/s DIMM system

Eye Scan Insight:

• DQS2 has less swing

than other DQS

Next Steps:

• Check DQS2 DRAM

drive strength,

termination and trace

routing

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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State Mode – Logic Analyzer samples once per target clock edge. Similar to DDR

devices.

• Synchronous to CK0 in system under test.

• Requires Tuning to ensure logic analyzer sample is taken when

data is valid. Logic analyzer is unique in ability to adjust sample

position.

• Necessary for Decoders and other tools to operate correctly.

(Timing mode provides undetermined samples during transitions

on the bus and isn’t consistent enough for the tools to operate

reliably.)

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2013 2015

Dat

a R

ate

DDR4 and LPDDR4 Challenges

Data Valid Windows Shrinking

Data Rates Increasing

Signal swing decreasing

Signal integrity variations between systems

Read DDR4 1600 Data valid windows scanned on U4154B logic analyzers with

FS2510 DDR4 DIMM interposer on different DDR4 targets.

Read DDR4 1867

DDR4 3120, 2400 and

1600 eyes were less

than 200mV at the

DDR4 interposer!

Read

DDR4

2400

Read

DDR4

3120

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Insight from Triggering on sequential events at high speeds

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DDR4 > 3.1Gbps Waveforms and Burst Trigger

State waveforms - Rising &

Falling edge samples DQ 7-0

(TZ) in label designates Timing Zoom,

High resolution Timing waveforms

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Challenge: Capturing initialization sequences

• 4M State

Waveform,

initialization

sequence

• Trigger

stores only

valid

commands

and enough

samples

after a

Read or

Write to

capture

data bursts.

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Example: DDR4 >3.1Gb/s Initialization

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Detailed Insight from Capturing System Initialization

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Follow the initialization signal flow of DDR4 3.2Gb/s system

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Decoder output from State mode trace in listing view

Data

Burst

of 16

Active 1 -2

sequence

Data captured

on rising and

falling edges

when over

2.5Gb/s

Row and

Column

address

decoded

LPDDR4 Signal Flow Insight

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Challenge: Functional Compliance Testing

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Compliance and Performance Tools

Compliance Tools

• Post process

• Real time

Performance Analysis

• Provides bus statistic information.

• Provides histogram view on

number of access at a specific

memory address

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Insight for Systems that Don’t Behave as Expected Symptoms of issue:

• Actual write bandwidth on a DDR3 system was much slower than calculated BW.

(Same issue could occur on any DDR or LPDDR system.)

• System performance was unacceptable, the product could not ship.

• Without a trace showing what the system was actually doing, designers were blind to

the cause of the symptom.

• Time to Market slipped away…

• The following trace showed the system beginning to write.

• FPGA designer looked at the trace.

• Immediately saw the root of the problem

- Fixed the issue quickly after seeing the traffic

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What the Designer Saw

1) Started out

streaming

writes (ODT

high)

Something

wrong, ODT

started toggling

– should have

been high >

90% of the time

Zoom in:

See NOP

instead of

streaming

Writes

1 2

2

1

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Validation of Resolution

FPGA code corrected

System Streaming Writes!

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Post-Process Protocol Compliance SW Tool

Post Process runs on logic

analyzer traces

Post Process tool can on

a single trace or run

repetitively and display

compiled results

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Real-Time Protocol Compliance SW Tool Real-Time example:

Trigger on tRCD violation

Write too close to Activate

Real-Time compliance tool

takes logic analyzer traces

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Challenge: Setting up measurements quickly

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Tuning tool – DDR Setup Assistant

Used DDR setup assistant with

10 simple steps to setup State

mode measurements

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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Timing Analysis

This figure illustrates how a logic analyzer samples a sine wave as it crosses

the threshold level.

Sample points are stored in memory and used to reconstruct a squared-off

digital waveform.

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LPDDR4 - Speed change viewed with Timing Zoom

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LPDDR4 Timing Zoom waveform – entering slower speed

Clock

turns on

for 6

cycles

before

CKE

enabled CA, BA, DQ,

and DQS low

unless driven

high

Active 1 -2 sequence

Insight Gained from Logic Analyzer

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Insight Into DDR4 Write Strobe Alignment

DDR4 2400: Timing Zoom high resolution capture

* Shows expected fly by routing effect on DQS on unregistered DIMM.

* DQS W for byte lanes shift right to adjust for DRAM location on DIMM.

Bursts of 8

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Insight: Incorrect DDR4 DQS Write Training

Timing Zoom 256k high resolution trace.

Shows DQS_Write training incorrect for unregistered DIMM.

Bursts of 4

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– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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BGA Interposer with InfiniiSim Physical layout of a board

Memory Controller

DRAM probe

InfiniiMax probe head

InfiniiSim General Purpose 9 Blocks Topology

Memory

Controller DRAM

BGA probe

S2P file

InfiniiMax

probe head

s1p file

Measurement

Simulation

Delay

Save configuration as transfer function file

BLOCK E

BLOCK P

Note: In some cases, channels need to be

modeled for best measurement accuracy.

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InfiniiSim

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Bandwidth/rise time and amplitude improved with InfiniiSim

DDR4 2400

InfiniiSim on

• CLK (ch2)

InfiniiSim off

• CLK (m1)

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InfiniiSim

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Gain more margin on eye diagram with probe correction

tDIVW margin: 141%

vDIVW margin: 106%

tDIVW margin: 196%

vDIVW margin: 111%

InfiniiSim OFF InfiniiSim ON

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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DDR4 Debug Tool

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What can it do?

• Correctly identify

read/write bursts.

• Make pre and post

compliance measurement

with saved traces.

• Collect statistical result

with multi burst

measurement.

• Navigate to measurement

and read/write burst.

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Read and Write Separation with Navigation

Customizable in

Footer 43

• Reports number of

read/write bursts.

• Navigate to each

burst.

• Markers indicate start

and end of burst.

write write

read read read

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Pre and Post compliance measurement

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Statistical Analysis

• Report timing

measurement

results – min,

max, mean.

• No auto-scaling

done on saved

traces to speed

up

measurement

time.

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Measurement results with Navigation

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• Specify number

of bursts to

measure.

• Marks all valid

measurements

in the trace.

• Report number

of measurement.

• Navigate to the

measurement.

• Mark min and

max

measurement

• Mark

measurement

thresholds

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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DDR4 Test Coverage

Customizable in

Footer 47

Electrical Tests

Timing Tests

Clock Tests

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Test Result of tDIVW

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Marker is placed on the

worst case margin

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DDR4 Test Result

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Compliance app reports

the following

information:

1. Worst case value

with screenshot.

2. Multiple trial run

results.

3. Statistical report of

min, max and std

dev.

4. Pass/fail status with

margin.

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HTML Report

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HTML report is presented for reporting

purposes. Provides details of test result

with screenshot of worst case value

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Offline Support for Compliance Testing

Key Features Allows testing on PC (Infiniium

offline software required) and

scope (no live data required)

Supports .h5 and .wfm waveform

format.

Supports DDR3/LPDDR3/DDR4

electrical and timing tests.

Supports testing with .h5

waveform from ADS simulation

tool.

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Offline tool use model with ADS Simulation tool

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Test flow from ADS to DDR Compliance Testing W2351EP DDR4 Compliance Test Bench

Live signal

acquired by

scope

Live signal from DUT Compliance app

performed live on scope

Compliance app

performed offline on PC

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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Complementary Solutions - Logic Analyzer and MSO

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Use complementary solutions to debug faster Features Logic Analyzer MSO (Mixed Signal Oscilloscope)

Simultaneous

View of Digital

and Analog

signals

• Requires an external scope, via View Scope

for up to 4 analog channels

• One box solution with cross

trigger and tight correlation.

• 16 ADD/CMD digital

• 4 DQS/DQ Analog

Functional

validation

Complete View all ADD/CMD/DQ/DQS

• Functional Compliance Tests

• Address/command/control and data validation

Partial view

• 16 command and address

(depending on number of digital

channels connected).

Eye diagram

display

• Qualitative bus level signal integrity insight

• Simultaneous eye diagram displays to view all

signals relative to each other.

• No measurement on eye

• Quantitative measurements

• Parametric Compliance Tests

• Eye height and eye width

measurements

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DDR4 Computer System Design MSO Probing

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Cable to MSO digital input (Address/Command/Control)

DIMM under test

E2677A solder in probe

heads to oscilloscope

(DQS, DQ)

MSO slot interposer

SODIMM MSO Interposer

To MSO

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ViewScope to Study ISI further

Setup logic analyzer

Trigger for bit pattern

that stresses ISI:

• Data bit pattern 00101

• Capture DQS and DQ

with scope

• View scope traces in

logic analyzer display to

correlate functional with

Signal Integrity trace

from scope.

Up to 4 scope channels into LA waveform

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Simple user interface

displays the violations and

simultaneously triggers the

logic analyzer or

oscilloscope at the violation

The DDR Detective® – DDR3, DDR4 and LPDDR3 (LPDDR4 under investigation)

– General Debug

• 512M Trace for Address/Command/Control

• Waveform

• State Listing

• Chart 2D or 3D the trace buffer contents

– Compliance Testing

• Real Time, ALL THE TIME JEDEC Compliance Violation Detection

• Counters can run continuously never missing a cycle

• Trigger on violation and drill down using waveform and state listing

– Performance Analytics

• First of its kind! Large Counters never miss a cycle and can report metrics

continuously for seconds, hours and even days!

• Command Bus Utilization by rank, bank group and bank

• Data Bus Utilization and Bandwidth by rank, bank group and bank

• Page Hit/Miss/Unused

• Multiple Bank Open – how many banks are open at any one time

• Bank Group Analysis – what percentage of consecutive commands go to the

same bank group/different bank group

• Bank Utilization – How long are banks left open

• Power Management – how long spent in self refresh/precharge power

down/Active power down/DLL enable/Idle/Active/Max Power Down

• Bus Mode – Idle/Active/MPR Mode/MRS/VREF Train/Write Level/Power

Management

The DDR Detective®

Four Target Connections Available

BGA

The DDR Detective®

DIMM

SO-DIMM

Midbus (STPro)

– Insight needed for debug and validation challenges

– Probing Solutions for Logic Analyzer and Scope

– Insight from Logic Analysis

• DDR Eye Scan insight

• State Mode Insight

• Timing Mode Insight

– Insight from Oscilloscope

• InfiniiSim

• DDR Debug Tool

• DDR Compliance

– Other Tools

– DDR Solution Overview, Recommendations, & Q&A

Agenda

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Solutions to succeed for DDR4 and LPDDR4

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Broad coverage for DDR4 and LPDDR4 design and test solutions

Physical Layer Simulation with DDR4 specific tools

Physical Layer Compliance Test Measurements and Debug

Functional Compliance Test Measurements and Debug

MSOX91304A Infiniium Series scope

U4154B Logic Analyzer system

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Contact Keysight

Aug 6, 2013

Product Selection and Configuration Assistance,

Education and Training

US phone: 1 800 829-4444 Press # then 2

Hours: 8:00am – 8:00pm ET, Mon - Fri

For more information on Keysight Technologies’ products, applications or

services, please contact your local Keysight office. The complete list is

available at:

www.Keysight.com/find/contactus

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Q & A

63

Page 64

Thank you very

much for your

time and

attention!

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DDR4: Xilinx KCU105 UltraScale Eval Kit

http://www.xilinx.com/products/boards-and-kits/KCU105.htm

Keysight and Xilinx DDR4 demo video: https://www.youtube.com/watch?v=Wr_zcq2KOzA

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Optional Grypper Sockets

– Randy Knudsen

– Sr. Product Market Manager

– HSIO Technologies, LLC

–

– E-mail: randy.knudsen@hsiotech.com

– Office: +1.763.447.6267

– Main: +1.763.447.6260

– Fax: +1.763.416.0174

– Website: www.hsiotech.com

Vendor HSIO

Can be installed on top and/or

bottom of BGA interposer.

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