gallium nitride electronics for cryogenic and high
TRANSCRIPT
Gallium Nitride Electronics for Cryogenic and HighFrequency Applications
by
Qingyun Xie
B.S., Cornell University (2016)
Submitted to the Department of Electrical Engineering and ComputerScience
in partial fulfillment of the requirements for the degree of
Master of Science in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
May 2020
© Massachusetts Institute of Technology 2020. All rights reserved.
Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Department of Electrical Engineering and Computer Science
May 15, 2020
Certified by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tomas Palacios
Professor of Electrical Engineering and Computer ScienceThesis Supervisor
Accepted by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Leslie A. Kolodziejski
Professor of Electrical Engineering and Computer ScienceChair, Department Committee on Graduate Students
2
Gallium Nitride Electronics for Cryogenic and High Frequency
Applications
by
Qingyun Xie
Submitted to the Department of Electrical Engineering and Computer Scienceon May 15, 2020, in partial fulfillment of the
requirements for the degree ofMaster of Science in Electrical Engineering and Computer Science
AbstractCryogenic and high frequency electronics have received renewed attention due to theirapplication in the control and readout electronics of quantum computing systems, amongothers. The potential of AlGaN/GaN HEMTs for cryogenic high frequency application wasexplored. The performance of AlGaN/GaN HEMTs with both conventional gate material(Ni/Au) and superconducting gate material (NbN) was studied at cryogenic temperature.Furthermore, in order to study device-circuit interaction of the devices, a simulation frame-work bridging the device-level and circuit-level was developed. The framework was testedon two device concepts, namely GaN p-channel FETs for complementary logic applicationand the vertical fin transistor for high power RF application.
Thesis Supervisor: Tomas PalaciosTitle: Professor of Electrical Engineering and Computer Science
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Acknowledgments
First and foremost, I would like to express my heartfelt gratitude to my advisor, Prof.
Tomas Palacios, for his mentorship and encouragement throughout the thesis work. His
strong confidence in me, creativity and optimism have been essential in overcoming the
challenges of this research. Furthermore, I am immensely fortunate to have worked with
my lab mates. They include, in alphabetical order, Dr. Ahmad Zubair, Dr. Daniel Piedra,
Elaine D. McVay, Jiadi Zhu, Dr. Jie Hu, John Niroula, Dr. Jori Lemettinen, Joshua A.
Perozek, Mr. Kohei Yoshizawa, Mantian Xue, Marek Hempel, Mengyang Yuan, Miguel
Sanchez Lozano, Nadim Chowdhury, Dr. Nitul Singh Rajput, Pao-Chuan Shih, Dr. Xu
Zhang, Dr. Yuhao Zhang, Dr. Yuxuan Lin, and many more. Special thanks to Dr. Ujwal
Radhakrishna and Dr. Pilsoon Choi.
The experimental part of this work involving superconductors would not have been
made possible without the invaluable advice and support from Prof. Karl K. Berggren and
members of his lab, including Dr. Ilya Charaev, Marco Colangelo and Owen Medeiros.
I gratefully acknowledge Prof. Jesus Grajal de la Fuente (Universidad Politecnica de
Madrid), Prof. Dimitri A. Antoniadis and Prof. Kevin P. O’Brien for the insightful dis-
cussions. Special thanks to Dr. Garrett J. Schlenvogt and Mr. Thomas A. Jokinen of
Silvaco, Inc. for their technical advice and support.
Staff members of the Microsystems Technology Laboratories (MTL), Nano-structures
Laboratory (NSL) and MIT.nano deserve full credit for their dedication in the maintenance,
training and guidance on the use of the micro-fabrication facilities and the computational
server.
Last, but not least, I would like to thank my family for their endless amounts of love.
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Contents
1 Introduction and Motivation 15
1.1 Need for Cryogenic Electronics . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.1 Applications for Cryogenic Electronics . . . . . . . . . . . . . . . 15
1.1.2 Device Technologies for Cryogenic Electronics . . . . . . . . . . . 16
1.1.3 Exploring GaN HEMT as the Device Technology for Cryogenic
Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.4 Advantages of GaN in RF systems and Integration . . . . . . . . . 19
1.1.5 Requirements of the Active Device for LNA Application . . . . . . 21
1.2 Integration of Superconductor and Semiconductor . . . . . . . . . . . . . . 22
1.3 Need for Modeling and Simulation in Device Design . . . . . . . . . . . . 23
1.3.1 Analytical Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.2 TCAD Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.3 Compact Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3.4 Establishing a Holistic Framework from Device-Level to Circuit-
Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2 Fabrication of Superconductor Gate AlGaN/GaN HEMTs 27
2.1 Device Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Choosing the Superconductor . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Fabrication Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2 Device Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.3 Contact Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
2.3.4 Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4 Fabricated Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3 Characterization of Superconductor-Gate AlGaN/GaN HEMTs 37
3.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Device Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.1 Contact Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.2 Channel Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.3 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.4 Critical Temperature Measurement of Superconducting Film . . . . 40
3.3 Optimization of Device Performance . . . . . . . . . . . . . . . . . . . . . 41
3.4 Analysis of Performance of Superconductor Gate AlGaN/GaN HEMTs . . 43
3.4.1 Temperature Dependence of Device Performance . . . . . . . . . . 43
3.4.2 Comparison of Gate Material . . . . . . . . . . . . . . . . . . . . . 47
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Simulation Framework from Device-Level to Circuit-Level 51
4.1 Case I: From Experimental Data to Circuit-Level Application . . . . . . . . 52
4.1.1 Bridging the Gap by using Compact Modeling . . . . . . . . . . . 52
4.1.2 Example: GaN p-FETs for GaN Complementary Logic Circuits . . 53
4.2 Case II: From Exploratory Device Design to Circuit-Level Application . . . 56
4.2.1 Vertical Fin Structure . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.2 Adopting the GaN Vertical Fin Transistor for RF Applications . . . 59
4.2.3 TCAD simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.4 Compact Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2.5 RF Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 Conclusions and Future work 71
5.1 Superconducting Ohmic Contacts to AlGaN/GaN 2DEG . . . . . . . . . . 71
8
5.1.1 Interaction of NbN with AlGaN/GaN quantum well . . . . . . . . . 72
5.2 Integration of Superconductor Gate HEMT into a RF system . . . . . . . . 72
5.3 Simulation Framework from Device-Level to System-Level . . . . . . . . . 73
9
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List of Figures
1-1 Schematic of the quantum computer setup. . . . . . . . . . . . . . . . . . . 17
2-1 Epitaxial structure of an AlGaN/GaN HEMT. . . . . . . . . . . . . . . . . 28
2-2 Ohmic contacts to AlGaN/GaN 2DEG. . . . . . . . . . . . . . . . . . . . . 30
2-3 Mesa created for device isolation. . . . . . . . . . . . . . . . . . . . . . . 31
2-4 Lift-off of NbN film. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2-5 Images of fabricated AlGaN/GaN HEMTs (DC type). . . . . . . . . . . . . 34
2-6 Images of fabricated AlGaN/GaN HEMTs (RF type, short-channel). . . . . 35
3-1 Cryogenic measurement setup of fabricated devices. . . . . . . . . . . . . . 38
3-2 Principle of TLM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3-3 Sheet resistance vs. temperature of deposited NbN film. . . . . . . . . . . . 41
3-4 I-V characteristics of long-channel transistors. . . . . . . . . . . . . . . . . 42
3-5 I-V characteristics of short-channel transistors. . . . . . . . . . . . . . . . 44
3-6 I-V characteristics of the Ni/Au gate device at room and cryogenic temper-
ature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3-7 I-V characteristics of the NbN gate device at room and cryogenic temperature. 46
3-8 I-V Characteristics of the Ni/Au gate and NbN gate devices at room tem-
perature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3-9 I-V Characteristics of the Ni/Au gate and NbN gate devices at cryogenic
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4-1 IV characteristics of a p-GaN gated AlGaN/GaN HEMT together with fit-
ting by MVSG model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11
4-2 GaN CMOS platform on which the p-FET and n-FET are fabricated. . . . . 54
4-3 Fitting of measurement data with MVSG model for (a) n-FET; (b) p-FET. . 55
4-4 Results of DC and transient simulation of GaN CMOS inverter. . . . . . . . 55
4-5 Simplified schematic of the unit cell of the (a) lateral and (b) vertical device
structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4-6 Thermal characteristics of the lateral and vertical structure. . . . . . . . . . 58
4-7 Schematic of the vertical fin device for power application. . . . . . . . . . . 60
4-8 Schematic of the vertical fin device for RF application. . . . . . . . . . . . 60
4-9 Schematic of proposed GaN RF fin transistor, along with flow chart of the
simulation methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4-10 Comparison of experimental measurement and simulations in vertical power
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4-11 DC and thermal performance of the proposed device. . . . . . . . . . . . . 64
4-12 Electron mobility in the fin channel of the vertical RF fin transistor. . . . . . 66
4-13 Analysis of the ON-resistance of the vertical RF fin transistor. . . . . . . . . 66
4-14 RF small-signal simulation of the vertical RF fin transistor. . . . . . . . . . 68
4-15 RF large-signal simulation of the vertical RF fin transistor. . . . . . . . . . 68
12
List of Tables
1.1 Summary of recently reported LNAs fabricated using various device tech-
nologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Summary of key specifications of devices with different gate materials, de-
vice dimensions and operating temperatures. . . . . . . . . . . . . . . . . . 49
4.1 Contributions of each region in the vertical RF fin device to ON-resistance. . 66
4.2 Comparison of specifications for the proposed device and GaN-on-SiC de-
vice. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Chapter 1
Introduction and Motivation
1.1 Need for Cryogenic Electronics
Electronics has become the backbone of modern-day information society, enabling telecom-
munications, storage of information, digital control, sensing and many more applications.
Therefore, electronics systems are required in every possible operating environment, from
room temperature to harsh environments. Most of the electronics devices in cell phones,
laptops and data centers operate at or near room temperature conditions. However, elec-
tronics and device components are required in harsh environment sensing and control, like
oil and gas rigs and space applications [1]. In fact, temperature fluctuation in these systems
have become a concern to the point where temperature compensation has become a critical
issue [2]. This category of electronic devices is collectively known as “extreme temperature
electronics” and warrants special attention.
1.1.1 Applications for Cryogenic Electronics
The roots of low-temperature electronics are traced back to the study of the temperature
dependence of material properties of silicon [3]. Some of the first devices optimized for
cryogenic operation were infrared detectors and superconductivity devices [4]. Since the
1980s, with the aggressive scaling of CMOS technology known as the Moore’s Law, the
low-temperature operation of very large scale integration (VLSI) systems has been studied.
15
It is possible to improve the performance of VLSI systems through cryogenic cooling,
giving rise to the “cryo-computer” [5], [6].
An application area which has recently attracted attention is quantum information sys-
tems, colloquially known as the “quantum computer.” In these systems, the computation
is performed not by logic bits, but by quantum bits (or qubits in short). Until “high-
temperature qubits” become a reality (like the room-temperature logic bit, the transistor),
the qubits would have to be placed in cryogenic environments in order to ensure their fi-
delity.
A schematic of the quantum computer setup is presented in Fig. 1-1 [7]. It is evident
that, simply placing the qubits in the large cryogenic chamber is not sufficient to build a
functional quantum information system. Since current qubits are mostly discrete compo-
nents, highly integrated electronics systems are used to control and readout the qubits [8].
These electronics components must be able to operate robustly at cryogenic temperatures
in the range of 4 K and lower. For example, in the readout part, the weak signals of the
qubits (typically <−100 ˜−120 dBm) must be accurately read with very low noise input
so that their state could be determined. This is when the “HEMT,” more accurately the
HEMT-based LNA, becomes critical to the qubit readout, as highlighted in Fig. 1-1.
1.1.2 Device Technologies for Cryogenic Electronics
A close examination reveals that silicon CMOS or BJT technology is not necessarily suit-
able for operation at cryogenic temperatures.
Silicon, if left undoped, is an intrinsic semiconductor with only ˜1010 /cm3 of holes and
electrons. The key enabler of silicon devices is doping in different regions, which gives rise
to free carriers and interesting physics. In the case of the bipolar junction transistor (BJT),
two back-to-back p-n junctions are formed and the manipulation of these p-n junctions give
an amplification of base current. In the case of the field-effect transistor (FET), also known
as the metal-oxide-semiconductor (MOS) structure, an inversion layer is formed in the bulk
substrate.
However, the ionization of dopants is highly temperature-dependent, following Boltz-
16
10
mK
Qubit
80
0m
K
LPF
Filter
4 K
HEMT
Isolator
HPF
RFDrive
denotes signal attenuator (e.g. 20 dB)
10
mK
80
0m
K
4 K
×
LO
IFRF
60
K
60
K
300 K
DCPump
Readout
Figure 1-1: Schematic of the quantum computer setup, illustrating the electronics compo-nents at each temperature stage [7]. LPF: low-pass filter; HPF: high-pass filter.
17
mann statistics, n(T ) ∝ exp(−∆E/kT ). At cryogenic temperatures, the doped semicon-
ductor suffers from what is known as the “freeze-out” effect. Examining this effect from a
band energy approach, the dopants do not have sufficient thermal energy to dissociate free
carriers into the valence and conduction bands. Degenerate (heavy) doping is required to
overcome this effect, but degenerately doped devices typically lead to other non-idealities
in device characteristics. The characteristics of CMOS technology in cryogenic tempera-
tures has been extensively studied [9].
There are some technologies in which donor freeze-out is inherently prevented. One
example is the hetero-junction bipolar transistor (HBT), with the commonly used material
systems being SiGe, GaAs and InP. The defining feature in the HBT which differentiates it
from the traditional BJT is the hetero-junction in the base region. This gives an additional
exp(∆E/kT ) of carriers, where ∆E is the band gap difference between the hetero-junction.
Active research is being conducted in HBTs for application in quantum systems [10]–[12].
Another technology is the high electron mobility transistor (HEMT), also known as
heterostructure FET (HFET) or modulation-doped FET (MODFET). In these devices, the
channel is not created by inversion as in the case of the MOSFET. In the case of GaAs
HEMTs, a thin layer of delta doping (in degenerate doping levels) provides the carriers
which populate the quantum well channel (in the case of GaAs, near the AlGaAs/GaAs
interface). HEMT structures using delta doping has been shown to work at cryogenic
temperatures [13].
1.1.3 Exploring GaN HEMT as the Device Technology for Cryogenic
Electronics
The AlGaN/GaN HEMT works in a similar way as other HEMTs, in that a high electron
mobility channel (two-dimensional electron gas, 2DEG) is created through the quantum
well at the AlGaN/GaN interface. However, the carriers is not formed by intentional delta
doping. Rather, for reasons explained below, the 2DEG is commonly described as being
“polarization-induced” [14].
Being wurtzite material structures, AlGaN and GaN feature dipoles in their unit cell.
18
The dipole gives rise to spontaneous polarization. Another source of polarization is known
as piezoelectric polarization, where the lattice mismatch between AlGaN and GaN (with
the lattice constant of AlGaN being lower in both a and c directions) creates strain [15].
The main source of the electrons is widely believed to be the surface states on the AlGaN
surface [16].
Therefore, it is significant to study if wide band gap heterostructures, in particular for
AlGaN/GaN which features polarization-induced 2DEG, would be suitable for cryogenic
applications. It may be argued that, the 2DEG in AlGaN/GaN heterostructure is robust at
cryogenic temperature, therefore the operation of the AlGaN/GaN HEMT would not be
significantly affected.
1.1.4 Advantages of GaN in RF systems and Integration
Besides inherent material properties and semiconductor device physics, there are several
practical factors to consider when choosing a semiconductor technology for cryogenic elec-
tronics. One factor is its potential for integration in circuit systems. For example, in the
readout of qubits, a high performance LNA is critical, and this function is typically served
by HBTs or HEMTs. Traditionally, LNAs have been based on SiGe HBTs or narrow band
gap III-V (GaAs, InP) HEMTs. LNAs tailored for cryogenic applications are commercially
available [17]. In particular, SiGe LNAs are capable of being integrated into millimeter-
wave integrated circuits (MMICs) using existing CMOS processes to realize ultra low noise
cryogenic receivers [11].
While traditionally known for its high power performance in power amplifiers, GaN
devices have been increasingly applied in LNAs for high frequency, including W-band and
beyond, operation [18], [19]. These GaN-based LNAs have achieved spectacular noise
figures at such high frequencies, and the numbers will significantly improve at lower fre-
quencies of operation, typically 4-6 GHz for the readout of qubits. A summary of recently
reported LNAs fabriated using various device technologies is provided in Table 1.1.
In addition, the availability of GaN technology has benefited tremendously from being
prevalent in both the light-emitting diode (LED) and electronics fields. The recent years
19
Ref.
ProcessType
Bandw
idth(G
Hz)
Gain
(dB)
TN
(K)/N
F(dB
)P
DC
(mW
)[11]
SiGe
0.13µm
Two-stage
0.1–5>
29.64.3
K20
[20]SiG
e0.13
µmTw
o-stage19–23.5
>20
≤45
K<
0.9[21]
SiGe
0.13µm
One-stage
52–6515.6
1916.3
K[22]
GaA
s0.1
µmT
hree-stage4–12
31.55.3
K8
[23]InP
Three-stage
4–1226
8.1K
12[24]
InPT
hree-stage0.3–14
41.66.3
K3.5
[25]InP
–20-25
–8
K–
[24]InP
Three-stage
16-2832.2
6.3K
3.5[18]
GaN
-SiC0.25
µmT
hree-stage1–25
133.3–4.6
dB900
[26]G
aN-SiC
0.15µm
–0.1–45
>10
1.6–2.5dB
2500[27]
GaN
-SiT
hree-stage22–30
19.5–22.5dB
0.4–1.1dB
210[19]
GaN
-SiCFour-stage
106.5–113.530
7.6dB
–
Table1.1:Sum
mary
ofrecentlyreported
LN
As
fabricatedusing
variousdevice
technologies.
20
has witnessed aggressive efforts by academia and industry to push the GaN technology
to the next levels. Unlike for instance InP substrates, GaN substrates are available in 8-
inch and even 12-inch substrates [28]. This has opened up additional advantages for GaN
technology in terms of cost and scale.
1.1.5 Requirements of the Active Device for LNA Application
As the name suggests, to create high performance low noise amplifiers, the active device
itself must contribute as little noise as possible.
Noise has been studied since the invention of silicon FETs. In particular, noise becomes
an issue at higher frequencies due to increased parasitics. A classic treatment of gate noise
in silicon FETs is available in [29]. Furthermore, since the early days, the impact of noise
sources on amplifier performance has been examined [30].
Later, as HEMTs were being developed in the 1970s and 1980s and being increasingly
used in high frequency operation, several noise models have been proposed for HEMTs.
Here, two models are presented. The Fukui model suggests that
F = 1+K fffT
√gm(Rg +Rs) (1.1)
where F is the noise figure, K f is a fitting parameter based on the quality of channel ma-
terial, f is the frequency of operation, fT is the transition frequency of the transistor, Rg is
the gate resistance, and Rs is the source resistance [31].
Another model, the Pospieszalski model, is slightly more complex but offers insight
into the effect of the noise temperature:
F = 1+2(
ffT
)2 RiTd
RdsTa+
2Ta
ffT
√RiTgTd
Rds+
(ffT
)2 R2i T 2
d
R2ds
(1.2)
where Tg is the gate noise temperature, Td is the drain noise temperature, Ta is the ambient
temperature, Ri is the channel resistance, and Rds is the drain-to-source resistance. The
“common message” which both noise models deliver through Eq. (1.1) and (1.2) is that,
reducing the parasitic resistance is extremely important.
21
The noise characteristics of AlGaN/GaN HEMTs have also been studied in detail [32],
[33]. In particular, high fT and fmax (maximum oscillation frequency) are extremely impor-
tant to reduce noise [33]. Approximate expressions for fT and fmax, two important metrics
of high frequency devices, are presented in Eq. (1.3) and (1.4), respectively [34]:
fT =vsat
2πLg(1.3)
fmax = fT
/2√
Ri +Rs +Rg
Rds+2π fT RgCgd (1.4)
where Lg is the length of the gated channel, Rd is the drain resistance, Cgd is the gate-drain
capacitance.
In summary, at the device-level, to achieve a low noise device, high fT and fmax are ex-
tremely important. This is achieved through low contact resistance Rc, low gate resistance,
and aggressive scaling of transistor (to reduce Lg). One popular method to reduce the gate
resistance, despite the very short channel length, is to use T-shaped gates or mushroom
gates as demonstrated in Si FETs, GaAs HEMTs and GaN HEMTs [34], [35].
In a semiconductor device, the sources of noise include flicker noise (1/f noise), shot
noise, thermal noise and generation/recombination noise. For a HEMT, among these sources
of noise, thermal noise limits the noise performance at high frequencies [13].
1.2 Integration of Superconductor and Semiconductor
Superconductors differ from conventional conductors in that they transport charged carri-
ers without resistance. This typically occurs below a critical temperature, above which the
material behaves as a standard conductor. The widely accepted theory for the origins of
superconductivity is known as the Bardeen-Cooper-Schrieffer (BCS) Theory [36]. Inter-
estingly, John Bardeen was also credited for the invention of the transistor, and therefore it
seems to follow naturally that the pursuit of superconductor-semiconductor integration is
taking place.
The idea of integration of superconductor and semiconductor began in the silicon days
22
[37]. While it possibly started as curiosity-driven research, the key motivations were to im-
prove the current conduction within the semiconductor device. Typically, superconductor
elements are integrated into existing semiconductor devices of various kinds. For example,
for the hot electron transistor (HET), the selection of the base material is critical to the
performance of the device [38]. Among various types of base materials, a superconductor
base was proposed [39].
In this work, the aim is to design high performance devices capable of low noise oper-
ation at high frequency, specifically for cryogenic applications. The introduction of super-
conducting electrodes is expected to lower the noise significantly, according to Eq. (1.1)
and (1.2).
It should be noted that, the generation of noise is inherent to the operation of the semi-
conductor device. Therefore, using superconducting electrodes does not completely re-
move it [40]. Nevertheless, due to the stringent noise requirements of the cryogenic re-
ceiver, any effort to reduce noise should be taken into consideration.
1.3 Need for Modeling and Simulation in Device Design
There are noticeable differences among analytical modeling, compact modeling and FEM
/ TCAD modeling. They represent different levels of abstraction of the fabricated device.
The different aspects of modeling/simulation is elaborated in this section, with an emphasis
on GaN devices, which is the focus of this thesis.
1.3.1 Analytical Modeling
The earliest analytical modeling in the understanding of the transistor came at what is
now known as “long-channel device.” For example, the famous Pao-Sah double integral is
widely known as the first MOSFET theory valid in all regimes of operation [41]. This in-
tegral based on drift-diffusion equations gives the drain current. The classic equations like
the gradual channel approximation (GCA) are well documented in many semiconductor
device textbooks [42], [43].
23
1.3.2 TCAD Simulation
TCAD stands for “technology computer-aided design”, and in the context of device-level
research, typically refers to the simulation of device behavior through the finite-element
method (FEM). Typical TCAD software used in semiconductor device simulation include
Sentaurus and Silvaco. According to the manuals, many physical models could be cap-
tured. For example, for carrier statistics, the Boltzmann or Fermi-Dirac statistics could
be chosen. For carrier generation/recombination, models like Shockley-Reed-Hall could
be used. These models are either based on physics or some empirical fitting, and aim to
accurately describe the operation of the device.
With the sophistication of device design and processing, it is important to accurately
model the effects, including secondary effects which are not conveniently captured by the
analytical model but still play an increasing role in device characteristics. In the case
of AlGaN/GaN HEMT, due to its high power density (reaching continuous wave power
densities of >40 W/mm [44]), large amounts of heat is dissipated. In turn, the large heating
leads to local temperature rise and lowers the carrier mobility due to increased phonon
scattering. A “steady-state” equilibrium is required.
In the case of the elctro-thermal effect and in many other scenarios, a large number
of self-consistent equations must be solved simultaneously. Fortunately, the phenomenal
increase in computing power came to the rescue – numerical solvers have become more
powerful and robust. TCAD software packages take advantage of the increased computa-
tional power to perform finite-element simulations of complicated structures.
As compared to silicon, wide band gap semiconductor devices (like GaN) typically suf-
fer from convergence issues. One major reason is that the wide band gap results in very low
concentrations of minority carriers (in the case of AlGaN/GaN HEMTs, the holes). Hence,
extended precision solvers are often required in the software, which in turn increase the
computational burden. Thankfully, the ability to achieve convergence has greatly improved
in the simulation software as wide band gap devices are increasingly being simulated.
24
1.3.3 Compact Model
A major push factor in the development of compact models is the need for large-scale
integration (of devices) and circuit design. Robust, accurate and relatively simple device
models are required at the circuit-level to facilitate the design of complex circuits.
One of the earliest circuit simulation languages is the Simulation Program with Inte-
grated Circuit Emphasis, more commonly known by its acronym, SPICE [45]. This simu-
lation program, developed at U.C. Berkeley, is capable of handling non-linear DC analysis,
small signal analysis, and non-linear transient analysis.
In the modern day, typically, foundries offer the process design kit (PDK) which con-
tains highly accurate models for each type of device fabricated in that process. The circuit
designer, who specializes in the “tape-out” (and not the device fabrication), uses the device
model to design large-scale circuits using softwares like Cadence Virtuoso and Keysight
Advanced Design System (ADS).
In the case of HEMTs, an early and still widely used model is the Angelov model [46],
[47]. This model is based on a small-signal model. There is even a dedicated study on
performance of cryogenic LNAs using the Angelov model for GaAs [48]. There are some
compact models developed by the manufacturers of GaN devices, such as the Cree model
and the TOM (TriQuint) model [49].
Recently, two models have been listed as the industry-standard models following a
selection process by the Compact Model Coalition (CMC) [50]. The first model is the ASM
(Advanced SPICE Model)-HEMT, a surface potential-based model [51]. The second is the
MIT Virtual Source GaN-FET (MVSG) model [52], a charge-based model. In particular,
for the MVSG model, many parameters in this model are “physics-based,” meaning that
they either come from physical design parameters (e.g. length of gated channel, length
of access regions) or are physically significant values (e.g. carrier injection velocity from
the source, initial low-field mobility). For a research project on device design, it aids the
physics-based understanding of the device, is straightforward to use and has been proven to
be accurate for a number of RF applications including power amplifier, low-noise amplifier,
and amplifier linearity [53]–[55]
25
1.3.4 Establishing a Holistic Framework from Device-Level to Circuit-
Level
As GaN electronic device technology (in particular, AlGaN/GaN HEMTs) become more
mature, these devices are increasingly used in circuits. In order for circuit designers to take
full advantage of the properties of GaN transistors, device-circuit interaction has become
increasingly important [54]. For example, to design a highly linear amplifier, the device
characteristics (in particular, characterization of gm and Cgs that would affect linearity)
would need to be clearly understood. In the context of a device-level research project
where there is higher flexibility in fabricating the device to achieve required specifications,
the device design could be tailored to meet the circuit-level needs, as demonstrated in [55].
A coordinated simulation framework with a seamless flow of data (and human under-
standing) between each level of abstraction would greatly facilitate the device and circuit
co-design process. Furthermore, we are at a stage where each level of abstraction (i.e.
analytical modeling, TCAD simulation, compact model, separately) has been extensively
optimized. This thesis seeks to address the link between TCAD model, compact model and
circuit-level simulation. The aim is to facilitate design of a wide variety of devices and for
them to be applied into circuits.
26
Chapter 2
Fabrication of Superconductor Gate
AlGaN/GaN HEMTs
This chapter presents the fabrication process of the superconductor gate AlGaN/GaN HEMT.
While the fabrication process is derived from that of the conventional AlGaN/GaN HEMT,
the highlight of the proposed device is the superconductor gate, which in this work is made
of NbN. The intention of using a superconductor material for the gate is to reduce the gate
resistance, and therefore increase fmax according to Eq. (1.4).
2.1 Device Structure
The superconductor gate AlGaN/GaN HEMT is similar to a standard AlGaN/GaN HEMT
as shown in Fig. 2-1. The starting substrate is a metal organic chemical vapor deposition
(MOCVD) epitaxially grown AlGaN/GaN on 8-inch Si substrate.
The polarization-induced 2DEG gives rise to the channel which is connected on both
ends by two ohmic contacts, labeled as the drain and source. In the middle of the channel
is a gate (in this case, made of superconductor material), which modulates the channel.
27
GaN
Al0.2Ga0.8N
(a) (b)
Si Substrate
Strain-Compensating Buffer
UID GaN
AlGaN
S G D
Figure 2-1: (a) Illustration of an AlGaN/GaN HEMT showing the epitaxial structure; (b)TEM image of an AlGaN/GaN interface. (Image credit: Dr. J. Lemettinen, Dr. N. S.Rajput)
2.2 Choosing the Superconductor
There exists many types of superconductor materials based on cuprates, oxides, chalco-
genides, borides, nitrides and other material categories [56].
One key metric of a superconductor is its critical temperature (Tc). In fact, the race
for the discovery of high-temperature superconductors has been an active area of research
[57]. For the required application of this work, the critical temperature should be above 4
K, which is the operating temperature of the cryogenic HEMT.
The nitride material system is a truly amazing material system – various nitride com-
pounds give different properties which could be easily integrated together. On one hand,
the AlGaN/GaN material system features a wide band gap and therefore suitable for semi-
conductor devices. On the other hand, transition metal nitrides like TiN and NbN offer
superconducting properties.
The superconducting properties of NbN have been exploited for a variety of device
applications, including hot electron bolometer [58], [59], superconducting nanowire single
photon detector (SNSPD) [60], and superconducting quantum interference device (SQUID)
[61]. High performance devices have been reported. Microwave resonators based on NbN
have also been studied [62], [63].
The integration of NbN and semiconductors has enabled Josephson Junctions, a key
component of superconducting qubit technology [64]. Josephson Junctions based on wide
band gap semiconductors have been demonstrated using NbN/AlN/NbN [65], [66] and
28
NbN/GaN/NbN [67]. In a recent work, the superconducting properties of NbN has been
used to give quantum oscillations in the 2DEG [68]. The NbN was grown underneath the
semiconductor material (AlGaN/GaN), and was used as a source load. A bulk accous-
tic wave (BAW) resonator with epitaxially grown NbN as the electrodes has been pro-
posed[69]. In other cases, the NbN is simply used as a sacrificial layer to release the
AlGaN/GaN semiconductor device structure [70].
Taking advantage of existing progress in other NbN-based superconducting compo-
nents, the choice of NbN as the superconductor material, when integrated with the Al-
GaN/GaN semiconductor material system, opens up numerous possibilities for an all-
nitride platform for superconducting qubits and systems [66].
2.3 Fabrication Process
2.3.1 Ohmic Contacts
In the first step, the ohmic contacts are created, as shown in Fig. 2-2(a). Achieving a good
ohmic contact is extremely important to any semiconductor device, because we wish to
minimize the contact resistance (hence voltage drop) and therefore increase current levels.
In the early days of research in AlGaN/GaN HEMTs, forming an ohmic contact to the
2DEG has been a challenge. This is because the the material system is wide bad gap,
therefore a direct metal contact would form a highly Schottky contact.
Ti (20 nm)/Al (100 nm)/Ni (25 nm)/Au (50 nm) is the commonly used metal stack
in forming ohmic contacts to AlGaN 2DEG [71]. The top view of the metal stack (Au)
immediately after deposition is shown in 2-2(b). The key step in the formation of ohmic
contacts is the rapid thermal annealing (RTA), which in this case is 800 °C for 30 sec in N2
ambient. The RTA allows the metal stack to form an alloy, as shown in 2-2(c). In fact, the
annealing temperature of 800 °C is higher than the metling point of aluminum (660 °C),
therefore the Al would melt and diffuse across the AlGaN barrier.
Increasing the annealing temperature is found not to be of significant use in achieving
ohmic contact to the channel, a similar observation as in other AlGaN/GaN (high Al con-
29
Ohmic contacts(a) (b) (c)
Figure 2-2: (a) Optical image showing ohmic contacts to 2DEG; (b) Top surface of ohmicmetal stack (with Au on top) before alloying; (c) Top surface of ohmic metal stack afteralloying.
tent) devices [72]. At very high annealing temperatures, especially beyond 950 °C, cracks
may form on the sample. This is a problem because of the existing large lattice mismatch
between GaN and Si (if Si substrates are used).
For short-channel devices, electron beam lithography is used to define the ohmic con-
tacts with LSD < 2 µm. The Ti/Al/Ni/Au stack is deposited by electron beam evapora-
tion and patterned by lift-off. Since the stack is relatively thick (˜200 nm), a double-layer
PMMA resist (thickness of ˜550 nm) is used to ensure the lift-off thickness ratio of close
to 1:3.
2.3.2 Device Isolation
Individual devices need to be electrically isolated from each other. The resulting isolated
region is also known as the mesa. There are generally two methods for device isolation,
namely mesa etching and ion implantation. Mesa etching removes the active device layers,
while ion implantation damages the channel in the active device layers for the isolation
regions. In this work, mesa etching was performed using Cl2/BCl3 plasma using Electron
Cyclotron Resonance Reactive Ion Etching (ECR-RIE), due to the convenient plasma etch-
ing facilities available. During the etch process, the ohmic contacts are protected by thick
(˜2 µm) photoresist. Typically, the etch depth is around 120 nm as measured by the atomic
force microscope (AFM). Fig. 2-3(a) shows the mesa created for device isolation. The
etched sidewall of the mesa is shown in Fig. 2-3(b).
30
50 m 20 m
(a) (b)
Figure 2-3: (a) SEM image showing the mesa (islands) created for device isolation; (b) Azoomed-in tilted view showing the etch which is around 120 nm.
2.3.3 Contact Pads
Next, the contact pads consisting of Ni (20 nm)/Au (100 nm) are deposited by electron
beam evaporation and patterned by lift-off. The ohmic contacts are designed to be small
in order to reduce the write time in the electron beam lithography. The large contact pads
facilitate probing, especially for cryogenic probes which are large in size. For the devices
which require RF probing, G-S-G (G: ground; S: signal) pads are used, in the fashion of
co-planar waveguides.
There are a few minor issues which need to be taken care of.
1. There might be issues with the lift-off of large pads. A descum of photoresist using
O2 plasma is required to clean the surface. Furthermore, for RF pads, sometimes the
unwanted metal in small sized corners may not be properly removed.
2. The adhesion of the pads is very important. Therefore, typically a thin Ni or Ti layer
is used below the Au layer.
3. The size of the pads need to be big enough for the probe tips to land. This is important
since the cryogenic probe tips might be larger than the room-temperature small-sized
probe tips. However, for RF pads, the probe pads should not be made excessively
large. Even though this would make it easy to probe, the capacitance between the
signal and ground probe pads would increase and reduce RF performance.
31
2.3.4 Gate
In the last but critical step, the gate is deposited. For the reference devices, Ni (20 nm)/Au
(100 nm) gates are deposited by electron evaporation and patterned by lift-off. 100 nm
gate length features have been obtained using PMMA and development at low tempera-
ture. For smaller resolution and higher contrast, cold development of PMMA at sub-zero
temperatures may be used [73].
For the NbN gate devices, NbN was deposited using DC reactive magnetron sputtering
[74]. A total of 23 nm of NbN was deposited. The sputtering target is Nb, which reacts
with N2 in the ambient to form NbN. Before depositing NbN, O2 plasma treatment was
performed at 50 W for 15 sec at a flow rate of 10 sccm in order to clean the surface.
Other methods are available to deposit NbN, notably, epitaxial growth by MBE. This
method has been demonstrated in other NbN-GaN integration efforts [68], [69]. Since the
NbN is a device top layer in this work, the samples would need to be sent into the MBE
chamber for regrowth, which would be tricky to perform.
In this work, the lift-off technique was used to pattern NbN. Decent lift-off was achieved.
However, since the NbN was sputtered, it could be difficult to lift-off in large area. Fig.
2-4(a) shows the lift-off in a region of the sample.
For patterning the NbN, there are various advantages and disadvantages in using lift-off
and etching. Lift-off is a convenient process requiring only one lithography step. However,
for large area fabrication (beyond piece scale), there might be poor area uniformity for
lift-off. The sample would enter the sputtering chamber with patterned resist. This may
result in contamination of the chamber with organics because some of the resist may be
removed by the sputtered atoms. Better lift-off than the one achieved in Fig. 2-4 could be
achieved with a double-layer resist to create the undercut profile which aids lift-off. For
example the combinations PMMA 495 A4/PMMA 950 A4 or MMA/PMMA may be used.
Furthermore, it was found that the edges of the thin NbN gate (for short-channel devices) is
slightly rougher than that of the Ni/Au gate, as shown in Fig. 2-4(b)–(c). This might affect
the gate modulation of the channel. One possible reason for the increased roughness is due
to the method of deposition of the gate material, where the NbN film is sputtered whereas
32
(c)(b)
(a)
Source(Ti/Al/Ni/Au)
Drain(Ti/Al/Ni/Au)
Source(Ti/Al/Ni/Au)
Drain(Ti/Al/Ni/Au)
Gate (Ni/Au)Gate (NbN)
Gate Pad Gate Pad
65
0 n
m
65
0 n
m
1.4
µm
1.4
µm
Good lift-off with the NbN
film in all except in the gate
region removed
Residual NbN film,
throughout the device,
indicating poor lift-off
Figure 2-4: Effect of lift-off of NbN film. (a) Optical image of a region of the AlGaN/GaNHEMT sample after lift-off of NbN film. Regions of good and poor lift-off are indicated;(b) SEM image of the gate region of a NbN-gated device; (c) SEM image of the gate regionof a Ni/Au-gated device.
Ni/Au film is evaporated.
Etching of NbN could be done using reactive ion etching (RIE) by CF4-based plasma
or XeF2 plasma. The advantage of XeF2 is its high selectivity to GaN and other materials,
but it is tricky to control the etch rate. This is especially relevant for the patterning of small
features like the gate, with one dimension (length of gate) at sub-micron levels for high
frequency RF devices. The problem with CF4-based plasma is that it may lead to undesired
effects (for high performance RF devices) such as depletion of 2DEG and introduction of
traps [75].
In order to avoid the CF4-based plasma coming into direct contact with the AlGaN
surface, a dielectric capable of resisting CF4 etching must be deposited on the AlGaN
surface. For example, Al2O3 may be used. The Al2O3 layer must be patterned and etched
if it is desired that the NbN gate is closer to the channel, resulting in additional processing
steps.
33
Gate
(NbN)
Ohmic Contact
(Ti/Al/Ni/Au)
Probe Pad
(Ni/Au)
50 μm
(a) (b)
Ohmic
Contact
(Ti/Al/Ni/Au)
Gate
(Ni/Au)
Figure 2-5: Fabricated AlGaN/GaN HEMTs. (a) SEM image of a fabricated AlGaN/GaNHEMT (DC type); (b) Optical image of a DC transistor with NbN gate. The alloyed contactis clearly seen in both the SEM and optical images, similar to Fig. 2-2(c). In sub-figure (b),the NbN gate (Lg = 100 µm) is clearly differentiated from the other contacts by its color.
2.4 Fabricated Devices
Several types of devices were fabricated using the process flow. Fig. 2-5 shows two basic
transistors suitable for DC measurements. Fig. 2-5(a) shows the SEM image of a con-
ventional Ni/Au-gated AlGaN/GAN HEMT. A long-channel (Lg = 100 µm) NbN-gated
AlGaN/GaN HEMT is presented in Fig. 2-5(b) to illustrate the NbN gate. For RF mea-
surements, the G-S-G probe pad configuration is required. An example of a short-channel
transistor for RF probing is presented in Fig. 2-6(a). The SEM image of the gate region,
presented in Fig. 2-6(b), indicates that sub-micron gate lengths were achieved.
2.5 Conclusion
In this chapter, the fabrication process flow was presented. Several rounds of optimization
were performed to achieve working short-channel devices. In the next part of this work,
the devices will be characterized.
34
Gate
Drain
SourceSource
Gate
Source
Drain
(a) (b)
Figure 2-6: A fabricated short-channel AlGaN/GaN HEMT suitable for RF G-S-G probing.(a) Optical image of the fabricated transistor, showing the source, drain and gate; (b) SEMimage of the gate region, with the values of the lengths Lg, Lgs, Lgd , Lsd labeled.
35
36
Chapter 3
Characterization of
Superconductor-Gate AlGaN/GaN
HEMTs
In this chapter, the fabricated AlGaN/GaN HEMTs, both the superconductor gate device
and the reference device (standard metal gate), will be characterized, primarily through
electrical I-V measurements.
3.1 Measurement Setup
The measurements were first conducted at room temperature and atmospheric pressure
conditions on the Cascade Microtech Summit 11000 probe station. Since the devices are
intended for cryogenic temperature conditions, measurements were also conducted at cryo-
genic temperature. Fig. 3-1 illustrates the setup. The devices are placed in a vacuum cham-
ber and liquefied helium is used to lower the temperature to ˜4.2 K. The IV characteristics
were measured using Keysight B1500A semiconductor parameter analyzer, which consist
of several source/measure units (SMUs).
37
Semiconductor
Parameter Analyzer
Cryogenic Probe Station
Device Under Test (DUT)
Helium Liquefier
Figure 3-1: Cryogenic measurement setup of fabricated devices. The inset shows a devicewith the RF probes landed on it, as observed through the optical microscope.
3.2 Device Properties
Before the three-terminal device performance is evaluated, it is important to characterize
some important device properties.
3.2.1 Contact Resistance
The transfer length measurement (also known as transmission line measurement, TLM) is
a commonly used method to determine the resistance between the metal contact and the
semiconductor channel, also known as contact resistance. Fig. 3-2 presents the extraction
of various parameters using the TLM. A detailed explanation of the principle of TLM is
available in [76]. The fabricated ohmic contacts typically show a Rc ≈ 0.6 Ω·mm.
3.2.2 Channel Resistance
In the case of lateral transistors like the AlGaN/GaN HEMT, the channel could be thought
of as a thin sheet of charged carriers. A few parameters quantify the properties of this sheet
channel.
38
Figure 3-2: Principle of TLM. (Figure credit: N. Chowdhury)
The sheet density of carriers (ns) could be determined by several methods, including
Hall, TLM and FAT-FET measurements.
The channel sheet resistance is related to mobility and carrier concentration, according
to
Rs =1
qµns(3.1)
The units of sheet resistance is typically given as Ω/.
3.2.3 Mobility
Mobility, defined as µ = v/E, an important parameter in carrier transport. because it gives
the carrier velocity for a given amount of electric field (exerted through applied voltage).
In the long-channel approximation of FETs, the drain current is directly proportional to
mobility, according to
IDS =WL
µCg (VGS−Vth)2 (3.2)
39
The temperature dependence of mobility has been studied since the early days of Al-
GaN/GaN research. There are two different mobilities, namely the mobility in the bulk
GaN and the mobility in the AlGaN/GaN 2DEG. For the mobility in bulk GaN, the mobil-
ity first rises then drops as the temperature is lowered from room temperature to cryogenic
temperature [77], [78]. For the mobility in AlGaN/GaN 2DEG, the mobility value has
increased from room temperature to cryogenic temperature [79], [80]. Since for an Al-
GaN/GaN HEMT, the conduction takes place primarily through the 2DEG and the ohmic
contact directly contacts the 2DEG, the mobility in the 2DEG should be considered, rather
than the mobility in the bulk GaN.
Hall mobility is the mobility of the carriers as measured through the Hall effect, a well
known effect in electromagnetics. For the samples used in the experiment, the measured
Hall sheet resistance is 455 Ω/. The sheet density of electrons ns is 7.94×1012 /cm2.
According to Eq. (3.1), the Hall mobility of electrons is 1730 cm2/V·sec. The values are
obtained through Hall measurement of a van der Pauw structure was conducted at room
temperature and at a magnetic field strength of 0.29 T.
It should be noted that, field effect mobility is another type of mobility which is Unlike
Hall mobility which could be thought of as an exclusively material / channel property, the
field effect mobility is the mobility inferred from the field effect transistor (FET). Long-
channel transistors, colloquially known as FAT-FET (due to the large size of the devices),
are used to determine the field effect mobility. They could be useful too to
3.2.4 Critical Temperature Measurement of Superconducting Film
Critical temperature (Tc) is one of the defining characteristics of a superconductor. In order
to measure the resistance characteristics vs. temperature of the deposited NbN film, an
AlGaN/GaN substrate sample (same as the device substrate) was placed in the chamber
during the deposition. Four-point probe technique was used to measure the resistance of
the sample. The ambient temperature of the sample was lowered by placing the sample in
a helium dewar. The values were converted to sheet resistance according to a geometrical
scaling factor of van der Pauw geometries [81]. The temperature variation of resistance of
40
TC
= 9.6 K
Figure 3-3: Sheet resistance vs. temperature of deposited NbN film measured using fourpoint probe technique.
deposited NbN film is presented in Fig. 3-3. According to Fig. 3-3, Tc ≈ 9.6 °C.
Future improvement in measurement Since the NbN features in the electronic devices
are thin (smallest dimensions are sub-micron), the four point probe technique could be used
to measure the resistance of these narrow-sized features.
3.3 Optimization of Device Performance
In the initial stage, long-channel devices were fabricated to test the process flow. Here,
long-channel devices refer to devices whose features could be defined by conventional UV
lithography, typically with gate lengths of >2 µm. Fig. 3-4 shows the device characteristics
of long-channel devices. These devices confirm that the device structure and fabrication
process flow is working.
In order to achieve good RF performance, the device features, in particular the gate
length, needs to be aggressively scaled, in order to increase the carrier transit frequency.
This is reflected in Eq. (1.3) which defines fT .
In short-channel devices, two lithography steps need to be performed using electron
beam lithography, namely the ohmic contacts and the gate. Several rounds of optimizations
41
Figure 3-4: I-V characteristics of long-channel transistors.
42
were conducted to repeatably achieve short gate lengths (<500 nm) and good performance.
The device performance of some of the short-channel devices fabricated is presented in Fig.
3-5. An ION/IOFF ratio of > 108 was achieved in the reported short channel devices.
In general, with the reduction in channel length, the ON-resistance of the device reduces.
This is evident from the reduction in ON-resistance from 3-4(a), 3-4(c), 3-5(a), 3-5(c), to
3-5(e). The maximum drain current increases to 1.1 A/mm for Lg = 0.3 µm.
3.4 Analysis of Performance of Superconductor Gate Al-
GaN/GaN HEMTs
The IV characteristics of superconductor gate AlGaN/GaN HEMTs were measured in a
vacuum chamber at both room temperature (˜295 K) and liquid helium temperature (˜4.2
K).
3.4.1 Temperature Dependence of Device Performance
The temperature dependence of device performance, specifically at room temperature and
cryogenic temperature, is studied.
A comparison of the I-V characteristics of the Ni/Au gate device is presented in Fig.
3-6. From the output curves (Fig. 3-6(a), (c)), it is observed that the ON-resistance of
the device decreases at cryogenic temperature, along with the drain current levels. From
the transfer curves (Fig. 3-6(b), (d)), it is observed that the gate leakage in the OFF-state
(VGS < Vth) increases at cryogenic temperature, but the switching behavior (VGS ≈ Vth) is
very similar.
A comparison of the I-V characteristics of the NbN gate device is presented in Fig. 3-7.
From the output curves (Fig. 3-7(a), (c)), it is observed that the ON-resistance of the device
decreases at cryogenic temperature, along with the drain current levels. This is similar to
the observation for the Ni/Au gate devices.
There are some interesting differences in the transfer characteristics of the device, as
presented in Fig. 3-7(b), (d)). Firstly, the gate leakage current in the OFF-state decreases
43
Figure 3-5: I-V characteristics of short-channel transistors.
44
Figure 3-6: I-V characteristics of the Ni/Au gate device at room and cryogenic temperature.
45
Figure 3-7: I-V characteristics of the NbN gate device at room and cryogenic temperature.
significantly by ˜2 orders of magnitude. Secondly, the threshold voltage shifts visibly.
There appear to be two turn-ons of the device. The threshold voltage of the first turn-
on shifts negatively, while the threshold voltage of the second turn-on shifts positively.
Focusing the second turn-on, which is the apparent threshold voltage as defined by the
linear IDS-VGS curve, the increase in Vth could partially explain the decrease in drain current
for the same VGS applied. Thirdly, the subthreshold swing (SS) of the device decreases, as
predicted in classical FET theory (diffusion of carriers). It should be noted that, there is a
theoretical limit on the reduction of SS proportional to the characteristic decay of a band
tail [82].
Double turn-on phenomenon It should be noted that in many of the devices, the “dou-
ble turn-on” phenomenon is observed. There are many possible factors leading to this
46
Figure 3-8: I-V Characteristics of the Ni/Au gate and NbN gate devices at room tempera-ture.
phenomenon, including existence of traps, a second channel in the GaN layers etc. There
is also the trivial reason that the devices are measured using RF G-S-G probes, and the two
channels beneath the two gates could have different threshold voltages. C-V measurements
of the devices at room temperature confirm that there is a small degree of trapping effects.
More studies are required to verify the origins of the double turn-on phenomenon.
3.4.2 Comparison of Gate Material
It is insightful to compare the device performance of the proposed device (NbN gate) and
reference gate (Ni/Au gate). In this study, the devices were fabricated on the same type
of substrate (albeit different samples), and the nominal device dimensions were kept the
same.
A comparison of the I-V characteristics of the devices at room temperature is presented
in Fig. 3-8. Devices of the same nominal dimensions are selected for each comparison. At
room temperature, the gate current leakage for the NbN gate device is larger. This is likely
because NbN has a lower workfunction than Ni (˜4.8 eV vs. 5.1 eV) so the Schottky barrier
height is lower. No gate dielectric is applied to these devices. Therefore, the thermionic
emission and diffusion current through the Schottky barrier height is larger.
A comparison of the I-V characteristics of the devices at cryogenic (LHe2) temperature
is presented in Fig. 3-9. The gate current leakage of the NbN gate devices is lower than
47
Figure 3-9: I-V Characteristics of the Ni/Au gate and NbN gate devices at cryogenic tem-perature.
that of the Ni/Au gate devices. At both room and cryogenic temperatures, the threshold
voltage of the NbN gate device is more positive.
A summary of the key specifications of devices with different gate materials, device
dimensions and operating temperatures is presented in Table 3.1.
3.5 Conclusion
In this chapter, NbN-gated AlGaN/GaN HEMTs were systematically characterized and
studied at both room and cryogenic temperature. The performance of the proposed device
was compared against a reference device, the standard AlGaN/GaN HEMT.
Superconductor gate AlGaN/GaN HEMTs were demonstrated though their performance
could be further improved through better device design and optimized fabrication process.
In-depth studies need to be conducted to fully understand their characteristics and trade-
offs. Nevertheless, the demonstration of a HEMT with superconducting gate electrode
opens the possibility of an all-nitride platform for superconducting qubits [66].
48
Dim
ensi
onsa
Out
putC
hara
cter
istic
sTr
ansf
erC
hara
cter
istic
sG
ate
Mat
.L G
(µm
)L S
D(µ
m)
T(K
)I D
,max
(A/m
m)
RO
N(Ω·m
m)
V th
(V)
g m,m
ax(S
/mm
)I D
,ON/
I D,O
FFSS
(mV
/dec
)N
i/Au
0.7
1.5
295
0.87
2.1
−2.9
0.28
6.0×
107
75.0
Ni/A
u1.
02.
029
50.
802.
5−2
.80.
261.
8×
108
75.3
Ni/A
u0.
20.
84.
30.
691.
6−2
.90.
326.
8×
108
23.0
Ni/A
u0.
71.
54.
30.
711.
5−2
.80.
347.
0×
107
28.2
Ni/A
u1.
02.
04.
30.
681.
6−2
.80.
318.
1×
107
30.0
NbN
0.4
1.1
295
0.63
2.6
−1.1
0.29
1.1×
106
144.
8N
bN0.
71.
529
50.
544.
0−1
.00.
231.
0×
106
100.
5N
bN1.
02.
029
50.
523.
1−1
.00.
225.
9×
105
133.
9N
bN0.
20.
84.
30.
522.
2−1
.00.
281.
3×
109
20.9
NbN
0.3
1.0
4.3
0.56
1.6
−0.9
0.30
2.4×
108
15.4
NbN
0.4
1.1
4.3
0.49
2.4
−0.7
0.26
1.1×
109
12.5
NbN
0.7
1.5
4.3
0.42
2.8
−0.7
0.23
1.3×
109
13.2
NbN
1.0
2.0
4.3
0.36
4.5
−0.7
0.19
4.9×
109
13.1
Tabl
e3.
1:Su
mm
ary
ofke
ysp
ecifi
catio
nsof
devi
ces
with
diff
eren
tgat
em
ater
ials
,dev
ice
dim
ensi
ons
and
oper
atin
gte
mpe
ratu
res.
a Ref
ers
tode
sign
(nom
inal
)dim
ensi
ons.
Act
uald
imen
sion
sm
ayva
rysl
ight
lydu
eto
fabr
icat
ion
proc
ess
vari
atio
n.
49
50
Chapter 4
Simulation Framework from
Device-Level to Circuit-Level
In real-world applications, most electronic devices will need to be eventually integrated into
systems to perform useful functions. For example, an AlGaN/GaN HEMT is integrated
into a MMIC PA to perform power amplification. While device-level research is critical
to improving the device performance, an appreciation of the circuit-level application is
equally important. A simulation/modeling framework needs to be established to ensure that
the device-circuit interaction is well studied. This chapter aims to establish a simulation
framework from the device-level to system-level.
Two different cases will be discussed here. In the first case, the simulation framework
begins from existing device-level experimental data. The circuit-level application will be
examined. This case is useful for designers who have developed some device technol-
ogy, and wish to evaluate its potential for circuit-level applications. The example used is
the GaN p-channel FET and its potential for application in a GaN complementary logic
inverter.
The second case is more exploratory. The simulation framework begins from ex-
ploratory device-level research of a novel device design. Through experimentally calibrated
TCAD simulation setup, the device operation and characteristics could be studied in detail.
The design parameters (e.g. device dimensions) could be varied to understand the trade-
offs in device design. In this work, the device will be applied in a single-transistor RF PA
51
in common-source configuration, though the framework could be easily extended to other
circuit-level applications. The example used is the GaN vertical fin RF device, which is a
novel device design. The flow begins from the conception of the device, to its device-level
performance (with a focus on the electro-thermal effects) and amplifier-level performance.
4.1 Case I: From Experimental Data to Circuit-Level Ap-
plication
4.1.1 Bridging the Gap by using Compact Modeling
In realizing an accurate and robust simulation framework from device-level to circuit-level,
the compact model serves as the key link between the two levels of abstraction. Therefore,
it would be informative to examine compact modeling in greater detail.
The MVSG model is a physics-based model which was developed based on the virtual
source concept [52], [83], [84]. Even though the original MVSG model was designed for
AlGaN/GaN HEMTs, the model is versatile enough to capture the behavior of a general
FET.
Typically, DC I-V characteristics are used to fit the model. As with any compact model,
the more raw data available, the more certain that the model would be able to capture
the behavior in different operating conditions. The software Keysight IC-CAP (Integrated
Circuit Characterization and Analysis Program) was used to aid the model fitting [85]. Fig.
4-1 illustrates the fitting of a fabricated p-GaN gated AlGaN/GaN HEMT (also known as
the gate injection transistor GIT). Excellent fit was obtained for a wide voltage range for
both the output and transfer characteristics.
Sometimes, there exists some non-idealities in the device behavior, especially for early
device prototypes in which there is variation in the fabrication process. In this case, fitting
should be done with extra care to ensure that the qualitative trend first fits over the entire
operating range, and then if possible, to achieve a good quantitative fit.
52
0 1 2 3 4 5
VDS
(V)
0
100
200
300
I DS (
mA
/m
m)
Experiment
MVSG Model
(a)
0 1 2 3 4 5
VGS
(V)
0
100
200
300
I DS (
mA
/m
m)
Experiment
MVSG Model
(b)
VGS,max = 5 V
VGS = 0.5 V
VDS,max = 3 V
VDS = 0.5 V
Figure 4-1: IV characteristics of a p-GaN gated AlGaN/GaN HEMT together with fittingby MVSG model.
4.1.2 Example: GaN p-FETs for GaN Complementary Logic Circuits
In recent years, there has been significant advancement in the technology of GaN elec-
tronics. Many semiconductor device is almost never meant to be used discretely – their
potential lies in the integration in circuits. As new types of devices are being developed,
integration becomes a natural option to consider.
AlGaN/GaN HEMTs are n-channel devices and thus far has been used in RF power
amplifiers and as power switches. In the case of power switches, even though they feature
fast switching speed and low switching loss, often the efficiency, size and power density of
a power electronic circuit is dominated by the size of its passive components like inductors
and capacitors [86]. The maximum operating frequency of a discrete GaN transistor is
limited by the inductance between the gate of the transistor and the driver circuit [86], [87].
However, this inductance in the gate loop can be significantly reduced by monolithically
integrating the driver circuit and power transistor on the same chip.
Recently, there has been several demonstrations of GaN-based power ICs [88]–[90].
All these demonstrations are n-type logic only in which the D-mode transistor is used as
the load to the E-mode transistor. The E/D-mode logic suffers from static power dissipation
and reduced voltage swing at the output. GaN complementary logic technology, like its Si
counterpart, consumes zero or negligible static power, reduces the circuit complexity, offers
higher noise immunity and higher linearity.
53
Figure 4-2: GaN CMOS platform on which the p-FET and n-FET are fabricated.
The development GaN complementary circuit technology begins with research into p-
FETs. In recent years, several p-FETs have been demonstrated on various epitaxial struc-
tures [91]–[95]. In Si CMOS technology, aggressive scaling of devices brought about the
improvement in performance of complementary circuit technology. The most scaled p-FET
till date is a self-aligned p-FET [96]. In order to evaluate the potential of this p-FET for
complementary circuit applications, a simulation framework employing the MVSG model
was developed.
Measured DC characteristics of the p-FET and n-FET fabricated on the same GaN
CMOS platform (illustrated in Fig. 4-2) were used in the fitting of the MVSG model. Fig.
4-3 shows that a good fit was obtained with the MVSG model. It should be noted that,
even though the p-FET is also a field effect transistor and therefore modeled by the MVSG
model (which is generally valid for FETs), there are some non-idealities in the p-FET
behavior (or deviations from classical FET behavior) given that this is early experimental
work. Therefore, fitting should be done with extra care to ensure that the qualitative trend
first fits over the entire operating range (in the case of CMOS, from 0 to VDD), and then if
possible, to achieve a good quantitative fit.
The simulation methodology is presented in Fig. 4-4(a). The methodology begins with
the experimental data, and two compact models (for n-FET and p-FET) are developed based
on this data (Fig. 4-3). The compact models will be inserted into the logic circuit. The
54
VDS = 2 V
(a) (b)
Figure 4-3: Fitting of measurement data with MVSG model for (a) n-FET; (b) p-FET.
Experimental Data
Compact Modeling
(MVSG Model)
Logic Circuit
Simulation
(Cadence Virtuoso)
(a)(c) (d)
0 200 400 600
Time [ns]
0
2
4
6
Vo
lta
ge
[V
]
VIN
VOUT
0 100 200
Time [ns]
0
2
4
6
Vo
lta
ge
[V
]
VIN
VOUT
VIN
VDD = 5 V
VOUT
Wp = 250 m
Wn = 25 m
CL = 35 pF+ +
−
−
VO
UT
[V]
I DD
[mA
]
0 1 2 3 4 5
VIN
[V]
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
VDD
=5 V
Voltage Gain=48
at VIN
=0.68 V
(b)
Figure 4-4: (a) Circuit diagram and methodology used in this work to simulate the GaN-based complementary logic inverter. (b) Voltage transfer curve of the GaN-based comple-mentary logic inverter. The n-FET and p-FET have gate widths of 25 µm and 250 µm,respectively. Simulated waveforms showing the (c) fall and (d) rise edge of the output sig-nal from the inverter. The rise/fall time of the input signal is 10 nsec. The fall and risetimes of the output signal are 60 nsec and 301 nsec, respectively.
55
circuit characteristics is simulated using a circuit design simulator like Cadence Virtuoso.
The circuit simulated is a standard complementary logic inverter circuit, as shown in
Fig. 4-4(a). A capacitive load of 35 pF is chosen because it resembles the typical gate input
capacitance, which is the load of the logic inverter in a power driver circuit. The widths of
the n-FET and p-FET are 25 µm and 250 µm, respectively, corresponding to a sizing ratio
of 1:10. The capacitive load, when normalized to the width of the p-FET, is 140 pF/mm,
within the range of typical p-FET loads [97].
The simulated voltage transfer curves for the complementary logic inverter are pre-
sented in Fig. 4-4(b), which shows a maximum voltage gain of 48 V/V at VIN = 0.68 V.
The DC current drawn by the inverter (IDD) has a peak of 0.52 mA at VIN = 0.70 V, which
is the switching point of the inverter. As shown in Fig. 4-4(c)–(d), the fall and rise times of
the circuit are 60 nsec and 301 nsec, respectively. The longer rise time is mainly due to the
high RON of the p-FET.
A few observations could be inferred from the DC gain curve in Fig. 4-4(b). Firstly,
the switching point, which should be ideally at VDD/2, begins at close to 0 V. This is be-
cause the n-FET is marginally E-mode. The simulated inverter behavior closely resembles
the behavior of a reported GaN inverters in which the devices are also marginally E-mode
[91]. This highlights the potential for this simulation to be used in the study of GaN com-
plementary logic circuits. It is interesting to note that, the experimentally demonstrated
inverter fabricated on a similar platform (Fig. 4-2) demonstrated very similar behavior as
predicted in Fig. 4-4(b) [98].
4.2 Case II: From Exploratory Device Design to Circuit-
Level Application
The innovation in device structures never ends: the research community is always seeking
to create novel structures to realize high performance devices or devices for specialized
applications. For this section, the GaN vertical RF fin transistor is used as an example
to develop the simulation framework from the exploratory device design to circuit-level
56
application.
4.2.1 Vertical Fin Structure
Traditionally, AlGaN/GaN HEMTs, like most transistors, are based on the “lateral” or
“planar” structure. The lateral structure takes advantage of the planar bottom-up fabrication
techniques. The defining feature is that the channel (in the case of the AlGaN/GaN HEMT,
the 2DEG) is planar. A simplified schematic of the lateral structure is presented in Fig.
4-5(a).
In vertical structures, as the name suggests, current conduction occurs in the vertical di-
rection. Typically, the source is placed on the top and injects carriers vertically downwards
to the drain located at the bottom (relative to the source). In this case, bulk conduction takes
places through the semiconductor, instead of in the lateral structure where the carriers flow
through only a thin layer of the structure (the lateral channel). The fabrication of vertical
structures in GaN has been made possible thanks to advances in processing techniques of
the material. A simplified schematic of the lateral structure is presented in Fig. 4-5(b).
One immediate benefit which arises as a result of the bulk conduction in the vertical
structure is thermal management in the device. In a high power device, large amounts
of heat is dissipated, primarily through Joule heating, and the raised temperature leads to
various reliability issues. Joule heating is characterized by the current density and electric
field, according to
P = ~J ·~E (4.1)
where P is the power dissipated per unit volume, ~J is the current conduction density (in
current per unit area), and ~E is the electric field density. The power dissipation results in a
local temperature rise.
An illustration is shown in Fig. 4-6. In the self-heating of the lateral device, shown
in Fig. 4-6(a), a sharp peak is found at the channel (near AlGaN/GaN interface), near the
drain-side of the gate edge. This shark peak could lead to various reliability issues.
In the vertical structure, since current conduction occurs more uniformly in the bulk,
the temperature spread across the device structure is more uniform. This is illustrated in
57
GaN
Substrate
Passivation
G G
S
D DGaN
Substrate
Passivation
S G D G S
AlGaN
(a) (b)
Figure 4-5: Simplified schematic of the unit cell of the (a) lateral and (b) vertical devicestructure.
Figure 4-6: Cross-sectional illustration of the thermal characteristics of the (a) lateral and(b) vertical device structure. The thermal profiles are extracted at a DC power dissipationlevel of 570 W/mm2. (c) Comparison of peak temperature rise for both structures.
Fig. 4-6(b). Hence, the maximum temperature rise is less than the lateral structure, for the
same amount of power density which flows through the unit cell of device. This is because
the unit cells in the vertical structure are more closely spaced and therefore power density
is high. For the same power density and same channel lengths (lateral)/channel heights
(vertical), a comparison of the peak temperature rise between lateral and vertical structure
is presented in Fig. 4-6(c).
Various vertical structures have been proposed for GaN-based FETs. An early demon-
strated vertical GaN transistor is the current aperture vertical electron transistor (CAVET)
[99]–[101]. The current is confined to the aperture by the regrowth of p-GaN. Another
method to confine the carriers is by the trench design and regrowth of p-GaN on the trench
surface [102]. In comparison, the vertical fin structure uses a top-down fabrication ap-
proach and eliminates the need for material regrowth [103]. In this thesis, the vertical fin
58
structure will be studied.
In addition to thermal management, the capability of lateral GaN transistors for high
power RF applications is fundamentally limited by, (a) non-uniform heat generation and
high local power density, (b) surface states causing dynamic ON-resistance and current
collapse, (c) high electric field near surface which causes reliability issues, and (d) poor
device linearity which forces circuit designers to back off output power at the expense of
efficiency [104]–[108]. Studies have been conducted to evaluate the RF behavior of various
vertical transistors [109], [110].
4.2.2 Adopting the GaN Vertical Fin Transistor for RF Applications
Current vertical GaN structure focus almost exclusively on power applications, i.e. its
ability to serve as as high voltage blocking switch. Till date, 1200 V breakdown voltage
has been demonstrated in vertical fin power transistors [111]. Given that GaN electronics
is widely used in RF applications, the question naturally follows, could the vertical GaN
transistor find its way in RF applications?
In order to adopt the GaN vertical fin transistor for RF applications, the device structure
of the vertical fin transistor for power applications, illustrated in Fig. 4-7, should first be
examined. There are several device features which may pose a problem and therefore
warrant modification:
1. Large gate-source capacitance, therefore detrimental to high frequency performance
(refer to Eq. (1.3), (1.4))
2. Gate is too long (i.e. large height), therefore the carrier transit time through the gated
region is long (refer to (1.3))
3. Drift region of ˜8 µm is too long, therefore increasing ON-resistance
4. Backside drain and conductive substrate increases loss and is difficult for RF probing
In an effort to address these issues, the structure in Fig. 4-8(a) has been proposed. The
changes include:
59
Figure 4-7: Schematic of the vertical fin device for power application [111]. (Figure credit:Dr. Y. Zhang)
Figure 4-8: (a) Schematic of the vertical fin device for RF application; (b) Simplifiedschematic cross-section of the device showing the different regions. (Figure credit: J.Perozek)
1. Reduced source/gate overlap
2. <100 nm gate for Ka band operation (˜30 GHz)
3. 1.5 µm drift region for 200 V breakdown
4. Top side drain
Fig. 4-8(b) shows a simplified structure of the vertical RF device.
Furthermore, as discussed earlier, thermal management of high power devices is critical
to improving their performance. It is imperative to minimize the thermal resistance between
the channel and the heat sink. Due to the high thermal conductivity of chemical vapor
deposition (CVD)-diamond, GaN lateral devices on CVD-diamond substrate has gained
significant attention in the research community [112]–[115].
In summary, this work proposes a novel device which features the merits of the vertical
device structure and is customized for high power RF applications. Through systematic
60
SiO2
Sourc
eChannel
Drift Region
Drain
Buffer Layer, 40 nm
Drain Contact
Gate
Gate Dielectric
Al2O3 , 10 nm
Source Contact
CVD Diamond Substrate, 100 m
NCD Passivation, 400 nm
Dielectric, 20 nm
Source
height = 400 nm
width = 100 nm
ND = 2×1019 cm-3
Channel
height = 30 nm
width = 100 nm
ND = 6×1016 cm-3
Drift Region
height = 2 m
width = 5 m
N = 3×1017 cm-3D
Drain
height = 900 nm
width = 8 m
ND = 1×1020 cm-3
Width=8 m
Figure 4-9: (a) Schematic cross-section of the proposed GaN RF fin transistor along with allthe device dimensions and doping concentrations; (b) Flow chart of the simulation method-ology employed in this work.
simulation studies, the performance of the proposed device in DC and RF (Class AB) are
evaluated.
4.2.3 TCAD simulation
Given that thermal management is an important aspect of any high power device opera-
tion, the TCAD simulation which is conducted needs to include electro-thermal effects.
This is required to understand the effect of self-heating and impact on device performance.
Electro-thermal simulations have been conducted for various GaN device structures [104],
[105], [116], [117].
Fig. 4-9(a) shows the cross-section of the proposed vertical RF GaN fin transistor
with relevant device dimensions. The structure consists of five different layers: an n+
GaN source layer, an unintentionally doped (UID) GaN channel layer, an n− GaN drift
layer, an n+ GaN drain layer and a CVD diamond layer. Plasma-enhanced chemical vapor
61
deposition (PECVD) grown nano-crystalline diamond (NCD) layer has also been added in
the proposed device as a top-side thermal spreading layer [118]. The current conduction in
the proposed device occurs vertically, and it is confined to vertical fins surrounded by the
gate electrode. The width of the fins is 100 nm to allow for good electrostatic control of
the channel, and also taking into consideration the fabrication process. The gate electrode
is separated from the GaN channel by a high-k gate oxide (Al2O3) of thickness 10 nm.
For a vertical device with good aspect ratio, the breakdown voltage is controlled by the
thickness of the drift region, which for a 200 V breakdown is 2 µm [111]. In this work, a
CVD diamond substrate is used. A reference device using a 6H-SiC substrate and silicon
nitride passivation is also simulated.
Fig. 4-9(b) shows a summary of the methodology of this work which has been exten-
sively calibrated by our group in order to evaluate the RF performance of the proposed
device [52]. An electro-thermal TCAD simulation was performed in Silvaco Atlas [119]
to calculate the static I-V and C-V characteristics which then have been used to develop a
compact model using the industry-standard MIT Virtual Source GaN FET (MVSG) Model
[52]. This compact model was finally used in Keysight Technology’s Advanced Design
System (ADS) [49] to perform RF small- and large-signal simulations.
Our group has been developing GaN-based vertical devices for power electronics appli-
cations [103], [111], [120]. Although the transistors are not optimized for RF applications,
their experimental results are used to benchmark the accuracy of the TCAD simulations.
Fig. 4-10(a) shows the key transfer characteristics of experimental devices (Scanning Elec-
tron Microscopy (SEM) image of which is shown in Fig. 4-10(b)), and the comparison
with the results provided by the TCAD simulations. Excellent agreement between the sim-
ulation results and the experiments is obtained.
In the electro-thermal device simulations, the drift-diffusion carrier transport and lattice
self-heating models were coupled and solved iteratively. The ambient of the device was set
to a fixed temperature of 300 K. Experimental values of thermal conductivity were used and
interfacial thermal resistance (between GaN and substrate) was taken into account [112],
[121]–[123]. A contact resistance of 0.2 Ω·mm is assumed at the source and drain contacts.
The transfer, output and C-V characteristics of the proposed device are presented in
62
Figure 4-10: (a) Comparison of experimental measurement and simulations in verticalpower device (b) SEM cross-section of the measured device [103].
Fig. 4-11(a)–(c), respectively. The proposed device shows a maximum drain current of
4275 kA/cm2 and a RON of 0.81 µΩ·cm2 for a single fin. These values are normalized by
the area of the gated fin channel, as per the convention of vertical fin transistors [103],
[111]. The saturation in current is caused by pinch-off of the channel, as well as the effect
of Joule heating leading to degradation of carrier mobility.
A major advantage of TCAD simulations is that rich amounts of information on the
device operation could be obtained. This is valuable information especially in the ex-
ploratory stage of device design, to understand the device operation, characteristics and
trade-off. Three aspects will be covered, namely the temperature profile, mobility profile
and analysis of ON-resistance.
Temperature profile Fig. 4-11(d) shows the peak temperature rise in the device as a
function of DC power dissipation. In this work, the values of power are normalized by the
width of the gate which is in the direction normal to the plane of Fig. 1(a). According to
Fig. 4-11(d), for every 1 W/mm increase in DC power dissipation, the peak temperature
in the proposed device is increased by ˜7.9 K which is about 7 times smaller than the
GaN lateral RF device on Si substrate [9]. The outstanding thermal performance can be
attributed to three core factors: vertical current conduction which allows for the uniform
heat dissipation, diamond substrate, and NCD top layer. But when compared to vertical fin
RF transistor on SiC substrate the proposed device shows 1.4 times better thermal resistance
(see Fig. 4-11(d)). Lower temperature rise of the proposed device compared to GaN-on-
63
0 5 10 15
VDS
[V]
0
1000
2000
3000
4000
5000
[kA
/cm
2]
I DS
-2 0 2 4 6
VGS
[V]
0
1000
2000
3000
[kA
/cm
2]
I DS
-2 0 2 4
VGS
[V]
0
10
20
30
40
50
CG
G
TCAD
Sim.
MVSG
Model
(a) (b)
(c)
(d)
(e) (f)
[pF
/mm
]
0 10 20
PDC
[W/mm]
0
100
200
300
400
T [
K]
GaN-on-Diamond
GaN-on-SiC
170
170170
180
180
180
180
186
186
186
190
160
170
180
190
200
244
244
250
250
250
260
2602
60
260 266
266
270
230
240
250
260
270
280
GaN-on-Diamond GaN-on-SiC
T [K
]
T [K
]
Figure 4-11: DC and thermal performance of the proposed device. (a) Output character-istics, VGS = 0,2,4,6 V; (b) Transfer characteristics; VDS = 0.1,1,2,3 V; from thesemilog plot of IDS-VGS (not shown here) SS = 81 mV/dec is obtained; (c) Total gate ca-pacitance vs VGS. (d) Maximum temperature rise of structure vs PDC, compared with GaN-on-SiC device. In (a)–(c), the values obtained from MVSG compact model are shown asdiamond shaped red marker and solid line represents TCAD simulation curves. In (a)–(b), IDS is normalized by the cross-sectional area of the fin. In (c)–(d), CGG and PDC arenormalized by the width of the fin (direction normal to the paper); (e)–(f) Temperature dis-tribution of the region near the gate channel at PDC = 20 W/mm, for the proposed deviceand the GaN-on-SiC device, respectively. The dotted lines denote the regions of the device,i.e. the source, channel and drift regions.
64
SiC device makes it more reliable for higher power RF operation. As shown in Fig. 4-
11(e)–(f) for both devices, the maximum temperature rise occurs in the drift region near
the gate channel, corresponding to the region of high electric field and current density.
Mobility profile Since the channel is formed by carrier accumulation (by varying con-
centrations based on distance to gated fin / horizontal direction in Fig. 4-9(a), an explicit
mobility value could not be assumed in this study. Instead, a mobility model based on the-
oretical calculations and calibration with experimental data was used. The mobility model
is divided into two parts, namely the low-field mobility and the high-field mobility. The
low-field mobility µ0 is similar to the Arora model for silicon, and is set to be dependent
on concentration and temperature [124]–[126]. However, in any semiconductor material,
velocity saturation is observed due to increased scattering of carriers at higher velocities.
Therefore, a high-field mobility model is used with the input parameters being the low-
field mobility µ0 and electric field E. A typical Monte Carlo-like model is assumed for
bulk GaN [125]–[127].
Of particular interest is the mobility in the gated fin channel, which is the narrowest
region in the device and which provides physical confinement of vertical current conduc-
tion. The mobility was extracted along the fin of the channel, as shown in Fig. 4-12(a), and
the results are presented in Fig. 4-12(b). In the fin channel, the GaN/dielectric interface
and GaN bulk have a mobility of 47 cm2/V·sec (minimum) and 81 cm2/V·sec (maximum),
respectively. In the drift region, the mobility increases from ˜150 cm2/V·sec (at the fin
channel / drift region interface) to ˜400 cm2/V·sec (near the drain electrode).
Analysis of ON-resistance The significant components of the ON-resistance are drift re-
gion and ohmic contacts [128]. Fig. 4-12 illustrates the method used to extract the ON-
resistance contribution of each region. The approximate contributions of each region are
reported in Table 4.1. The largest contributors to the RON,SD is the drift region (light doping
of 3×1017 /cm3 and thickness of 2 µm), followed by the source/drain electrodes.
65
Dra
in
Dra
in
Source
Fin
Channel
Drift
Region
Drain RegionG
ate
Ga
te
wid
th=
0
(a) (b)
Figure 4-12: Electron mobility in the fin channel of the vertical RF fin transistor: (a) Sim-plified device structure showing the cutline (dashed yellow line); (b) Profile of electronmobility along the cutline. Width of fin channel is 100 nm.
Dra
in
Dra
in
So
urc
eF
in C
ha
nn
el
Drift
Region
Drain Region
Ga
te
Ga
te
Depth = 0
(a)F
in C
ha
nn
el
Dri
ft R
eg
ion
Dra
in R
eg
ionS
ou
rce
Co
nta
ct
(b)
Figure 4-13: Analysis of the ON-resistance of the vertical RF fin transistor: (a) Simpli-fied device structure showing the cutline (dashed yellow line); (b) Profile of local electricpotential (normalized by VDS) along the cutline.
Region Resistance Value (µΩ·cm2) Percentage out of RON,SD (%)Source electrode 0.20 24
Fin channel 0.15 18Drift region 0.27 33Drain region 0.01 1
Drain electrode 0.20 24Total 0.81 100
Table 4.1: Contributions of each region in the vertical RF fin device to ON-resistance.
66
4.2.4 Compact Modeling
In order to bridge the gap between device-level TCAD simulation (of the physical structure)
and circuit-level abstraction, an accurate and robust compact model is required. A MVSG
model was fitted using the simulated DC characteristics of the proposed transistors.
Given that the MVSG model is largely a physics-based model, special care should be
made to ensure that the values fall within reasonable range. Furthermore, since this is a
comparison between the proposed device (GaN-on-diamond) and reference device (GaN-
on-SiC), the same physics-based parameters are used, while thermal-related fitting param-
eters are varied. Excellent fit is obtained, as shown in Fig. 4-11(a)–(c). It is worth noting
here that the parasitic capacitances associated with the device structure were extracted from
TCAD simulations and hence included in the MVSG model simulations. This is evident
from off-state CGG fits in Fig. 4-11(c).
4.2.5 RF Simulation
By taking advantage of the industry-standard MVSG model, RF small-signal and large-
signal simulations were conducted in ADS to evaluate the RF performance of the devices.
Class AB operating condition of VDS = 20 V was used. The results shown in Fig. 4-15
give a maximum current gain cut-off frequency ( fT ) of 94 GHz and maximum power gain
cut-off frequency ( fmax) of 104 GHz for the proposed device.
Finally, the calibrated compact model is used to perform source- and load-pull simula-
tions of the device biased in class-AB operating condition at a center frequency of 30 GHz.
The power sweep simulation results for source/load impedances optimized for power-added
efficiency (PAE) are reported in Fig. 4-15. The device provides a linear gain of 5.0 dB. A
peak PAE of 11.0 % is achieved at an output power of 38.6 W/mm. OIP3 of the proposed
device is found to be 28 dBm. A comparison of DC, thermal and RF performance the
proposed device and GaN-on-SiC device is presented in Table 4.2. It should be noted that
these performance metrics could be further improved with optimizations in device design
and circuit matching.
67
109
1010
1011
Frequency [Hz]
0
10
20
30
40
50GaN-on-Diamond
109
1010
1011
Frequency [Hz]
-10
0
10
20
30
40GaN-on-Diamond
(a) (b)
US
[dB
]
h21
[dB
]Figure 4-14: (a) Mason’s unilateral power gain (US) of the device plotted as a function offrequency gives an estimate of fmax (from the zero-intercept on the frequency axis); (b)Small-signal current gain (h21) vs. frequency plot gives an estimate of fT (from the linearextrapolation at a slope of −20 dB/decade to the frequency axis). It should be noted thatthese simulations take into account our best estimate for the parasitic capacitances of thevertical transistor structure as per TCAD simulation.
(a)
, IM
3 [d
Bm
]P
out[d
Bm
] (b)
0 20 40
Pin
[dBm]
0
10
20
30
40
50P
out
Gain
PAE
Pout
[dB
m],
Ga
in[d
B],
PA
E[%
]
-20 0 20 40
Pin
[dBm]
-100
-50
0
50
Pout
IM3
Figure 4-15: (a) Pout , Gain, and PAE vs. Pin are plotted for the proposed device for a class-AB operating condition at 30 GHz. (b) Pin vs. IM3 power characteristics of the proposeddevice when biased into class-AB.
68
Specification Proposed Device GaN-on-SiCRON [µΩ·cm2] 0.81 0.81Rth [K·mm/W] 7.9 10.7fT [GHz] 94 92fmax [GHz] 104 94Linear Gain [dB] 5.0 3.8Peak PAE [%] 11.0 3.2Pout at Peak PAE [W/mm] 38.6 26.6DC Current at Peak PAE [kA/cm2] 3000 1600OIP3 [dBm] 28 20
Table 4.2: Comparison of specifications for the proposed device and GaN-on-SiC device.
Note on DC-RF dispersion For the purpose of this modeling, DC-RF dispersion was not
considered. The main purpose of this work is to propose a novel device design and evaluate
the maximum potential of vertical fin transistors for applications in a power amplifier.
In general, it has been argued that, compared to lateral HEMTs, the problem of DC-RF
dispersion is less severe in vertical transistors (of various designs) due to the lack of surface
states [129]–[131]. The channel is “buried” inside the bulk GaN device, as compared to
HEMTs where the channel is very close to the AlGaN/GaN interface. Furthermore, in
HEMTs, the strong polarization at the AlGaN/GaN interface will cause electrons to be
trapped at high electric field.
Nevertheless, as with any semiconductor device, trapping effects/dynamic behavior
negatively affects the RF performance of the device. As for the specific type of vertical
device design used in this work, the vertical fin transistor, to the best of the author’s knowl-
edge, there has been limited studies of trapping effects, impact of defects, and reliability
issues of vertical fin transistors [132]–[135]. For example, since bulk current conduction
occurs in the vertical fin transistor, the quality of the material (in terms of threading dislo-
cation density etc.) will play an important role in the trapping effects. This would be an
interesting area for future research.
69
4.3 Conclusion
In this chapter, a simulation framework for the simulation from device-level to circuit-level
was developed. Two scenarios were examined – (a) predicting circuit behavior for a fabri-
cated device; (b) studying the device characteristics of a novel device for RF applications.
Two different circuit applications were examined, namely the logic circuit and RF circuit.
The framework would facilitate the research into novel devices and their application in
circuits, in particular, device-circuit interaction to achieve higher performance systems.
70
Chapter 5
Conclusions and Future work
In this thesis, some experimental and simulation studies of cryogenic and high frequency
GaN devices were presented. While these initial studies show promising results, more
research is undoubtedly needed to push the GaN technology to the next level.
5.1 Superconducting Ohmic Contacts to AlGaN/GaN 2DEG
In this work, the gate electrode was changed from a conventional metal (Ni/Au) to a su-
perconducting material (NbN). A question naturally follows, could superconducting ohmic
contacts (source and drain) be realized? The main benefit would be the reduced contact
resistance which is critical to noise. The widely cited noise models of Eq. (1.1) and (1.2)
reveal that, reducing the gate resistance and the contact resistance is critical to improving
the noise figure of the transistor.
For HEMTs, there has been some previous demonstrations of superconducting elec-
trodes on the GaAs material system [136], [137]. In these demonstrations, a direct contact
was formed between the NbN and the GaAs system. In the case of the AlGaN/GaN ma-
terial system, this is not possible due to the wide band gap (˜3.4 eV for GaN). Therefore,
the method of alloying the Ti/Al/Ni/Au contact stack at high temperature (in this work, 800
°C) has been extensively used.
The effect of annealing NbN at high temperature has been studied [138], [139]. In gen-
eral, exposing NbN to high temperature may lead to a phase change in NbN and therefore
71
damage its superconducting properties.
The second method to achieving ohmic contacts is by ion implantation of donor species
in GaN (e.g. Si) to create regions of n+-GaN for better contact. However, in this method,
the deposited metal would still have to be annealed, albeit at a slightly lower temperature.
The third method is to use regrowth technology to create regions of n+-GaN. Further-
more, polarization-doping may be included using InGaN and this would form a good con-
tact to GaN. A variety of regrowth techniques and related fabrication processes have been
explored to achieve good ohmic contacts to the Ti/Au contact, a commonly used ohmic
metal stack for regrowth [140]. Some lessons could be learned and applied to create a
NbN-based ohmic contact.
5.1.1 Interaction of NbN with AlGaN/GaN quantum well
The interaction of the superconductor and semiconductor remains an interesting problem.
In the case of the most widely used semiconductor, silicon, there has been early studies of
the semiconductor-coupled Josephson junctions [64]. For GaN, there has been some studies
on the semiconductor-superconductor interaction (GaN/NbN) for use in Josephson Junc-
tions [66], [67]. In these works, bulk GaN was used. To the best of the author’s knowledge,
there needs to be more research on the interaction of Nbn with the AlGaN/GaN quantum
well. The AlGaN/GaN heterostructure is different from the GaAs-based heterostructure
because the former features polarization-induced two-dimensional electron gas (2DEG)
while the latter features modulation doping. Using GaN HEMTs with all-superconducting
electrodes as the device, it would be interesting to understand the interaction of NbN with
the 2DEG.
5.2 Integration of Superconductor Gate HEMT into a RF
system
While the emphasis of this thesis work is on device-level research, which involves under-
standing device operation, device design and fabrication, the potential for integration of the
72
device into a low noise amplifier (LNA) would allow us to better understand the device-
level requirements. In this regard, the simulation framework developed for RF and logic
circuits would be extremely useful. Next, a LNA prototype could be fabricated to demon-
strate the possibility of applying the device-level NbN GaN HEMT technology for circuit
applications.
In any RF system, both active and passive components are critical. The active compo-
nent refers to the transistor, while other passive components include inductors, capacitors,
circulators, isolators etc. There has been ongoing work on building superconducting pas-
sive microwave components [62], [63]. The AlGaN/GaN HEMT with superconducting
electrodes could be integrated with these passive components to improve the performance
of the RF system. A larger scale integration on the NbN-GaN platform could also in-
volve other devices which take advantage of superconductivity, like the superconducting
nanowire single-photon detector (SNSPD).
5.3 Simulation Framework from Device-Level to System-
Level
The simulation framework has been established and proven to be effective in understanding
the system-level performance. As in any device, optimizations to the device design and
fabrication is always in progress to achieve higher performance. This could be aided by
the simulation framework. An inference / machine learning algorithm could be applied
to “work backwards,” in other words, receive feedback from the circuit-level and tune
parameters at the device-level. This is aided by the fact that the compact model chosen,
the MVSG model, is physics-based and many parameters correspond directly to physical
parameters. This is unlike models like the Angelov model which, though accurate, is based
on fitting of an electrical small-signal circuit.
In the case of the NbN gate GaN HEMT, the impact of non-idealities on circuit-level
behavior could be studied. For example, upon careful calibration to ensure an accurate
intrinsic transistor model, the effect of the difference in gate resistance and kinetic induc-
73
tance of superconducting components could be studied. The simulation should be done in
context of the application, e.g. a LNA.
74
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