gan-based radiation hardened high-speed dc-dc converter ...€¦ · gan-based radiation hardened...
TRANSCRIPT
Ashwath Hegde(1), Yu Long(2), Esko Mikkola(2), Jennifer Kitchen(1), Phaneendra Bikkina(2), Andrew Levy(2), Lloyd Linder(2)
(1)Arizona State University, (2)Alphacore, Inc.
GaN-Based Radiation Hardened High-Speed DC-DC Converter
Develop reliable, low-mass, small-form factor, radiation-tolerant,high-performance, single-module point-of-load (POL) DC-DC buckconverter(s) that support high particle energy, high radiation orspace applications. It will have not only a direct application to theexisting power conversion system for the large hadron collider(LHC), but also board applications to the DOE’s future medium-power POL converters.
• Robust to radiation and magnetic field tolerant environments.
• Efficiently converts an input voltage of 18V-24V to a regulatedoutput of 1.0V to 3.3V with up to 7A load current.
• Realized within a small form factor for integration within theLHC.
This work has been funded by a Department of Energy SBIR Phase I Contract # DE-SC0015764
Customized rad-hard IC Prototype
• Develop reconfigurable capabilities: frequency selection,dead-time, soft-start adjustment. Upgrade to a customizedoutput air-core inductor to achieve optimal converterefficiency and volume requirement.
• Add function of rad-hard redundancy at system and circuitlevels with techniques such as triplication and voting forboth analog and digital blocks.
• Update the off-chip passive components for control-loopcompensation to a fully on-chip compensation. Improveperformance of non-BJT BGR, on-chip voltage regulationoptions for a stable multiple voltage supply.
• Add protection schemes such as under-voltage lockout(UVLO), over-current protection (OCP), over-temperatureprotection (OTP), output voltage protection, adaptive dead-time control, etc to the next prototype IC tape-out.
• Improve circuit performance, such as sink/source currentcapability and driving transition for output driver, closed-loop response stability and control band-width, efficiencyand conversion ratio for converter, volume and weight foroff-chip passive components.
• Approximate tape-out schedules in 2018 are January/Marchand September. Final testing and assembly should befinished within 2019.
Input Output
epm
enm
VDD
GND
Input Output
ENM_10_0P4_DG_BODY
VDD
GND
epm
mosW = 360
mosL = 0.35
m = 20
mosSeg = 20
mosW = 360
mosL = 0.35
m = 20
mosSeg = 20
mosW = 89
mosL = 0.4
m = 20
mosSeg = 20
mosW = 10.5956
mosL = 0.4203
m = 180
mosSeg = 1
pwlned nlvdnlvd
Conventional
NMOS
Customized
Radhard NMOS
nhvd
Parasitic
Junction
Diodes
• Highly integrated, high switching speed buck convertertopology to achieve a small physical form-factor.
• Optimal division of functionality between Silicon and GaN totake advantage of inherent high current density and highswitching speed of GaN devices for the crucial power stageand the versatility of CMOS to implement the bulk of thecontroller functionality .
• Built-in-self test (BIST) that runs in the background tomeasure loop parameters, diagnose loop components, andestimate remaining lifetime to ensure reliable operation.
• An enclosed layout transistor (ELT) technique and design flowto reduce the total ionized dose (TID) induced leakage[1].
• Innovative CMOS-based gate driver architectures thatdirectly control the converter’s high voltage GaN power stageby employing only thin gate-oxide low-voltage devices tomaintain highest radiation hardening[2].
• On-chip high-efficiency voltage regulation and distributionschemes.
• Accurate Bandgap Reference (BGR) employing CMOS deviceswithout radiation-prone bipolar devices[3].
[1] R. C. Lacoe, “Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology,” IEEE Transaction Nuclear Science, vol. 55, no. 4, Aug. 2008, pp.1903-1925.
[2] F. Faccio, G. Blanchot, et. al, “FEAST2: A radiation and magnetic field tolerant Point-of-Loadbuck DC-DC converter,” 2014 IEEE Radiation Effects Data Workshop (REDW), Paris, France,Jul. 2014.
[3] J. Ramos-Martos, A. Arias-Drake, et al., “Evaluation of the AMS 0.35 um CMOS Technology forUse in Space Applications,” the 4th International Workshop on Analog and Mixed-SignalIntegrated Circuits for Space Applications (AMICSA), Noordwijk, Netherlands, Aug. 2012.
[4] J. Wibben and R. Harjani, “A High-Efficiency DC–DC Converter Using 2 nH IntegratedInductors”, IEEE Journal of Solid State Circuits, vol. 43, no. 4, pp.844-854, Apr. 2008.
[5] A. Hegde, Y. Long and J. Kitchen, “A Comparison of GaN-Based Power Stages for High-Switching Speed Medium-Power Converters,” the 5th Workshop on Wide Bandgap PowerDevices and Applications (WiPDA), Albuquerque, NM, USA, Nov. 2017.
[6] F. Neveu, B. Allard, C. Martin, P. Bevilacqua and F. Voiron “A 100 MHz 91.5% Peak EfficiencyIntegrated Buck Converter With a Three-MOSFET Cascode Bridge,” IEEE Transactions onPower Electronics, vol. 31, no. 6, June 2016, pp.3985-3988.
[7] L. Salem, J. Buckwalter and P. Mercier, “A Recursive House-of-Cards Digital Power AmplifierEmploying a λ/4-less Doherty Power Combiner in 65nm CMOS,” in Proc. of IEEE 42nd EuropeanSolid-State Circuits Conference (ESSCIRC) Conference, Lausanne, Switzerland, Sep. 2016, pp.189-192.
GaN Single Stage
Vout
L1
L2
C1
C3
Vin
R_load
24V
5.4V(Imax 10A)
P1
S1
S2
11
0u
F
350nH
110nH
4.7uF
IL2 VoutVin
GaN Multi-Phase
R_load
24V
5.4V(Imax 10A)
11
0u
F
350nH
110nH
110nH
4.7uF
L1
L2
C1
C3
L3
P2
S4
S3
P1
S1
S2
IL2
IL3
Vout
L1
L2
C1
C3
L3
Vin
GaN Stacked Interleaved
R_load
24V
5.4V(Imax 10A)
P2
S4
S3
11
0u
F
350nH
110nH
110nHC1'
10uF
4.7uF
P1
S1
S2
IL2
IL3
Power Stages Prototype
Three architectures have been selected for the DC-DC buckconverters to evaluate performance of the different powerstages. For comparison purposes, the measured results for eacharchitecture in the figure below are configured as open-loop andthe control signals are provided by function generator.
• Multi-phase architecture has the advantages of high efficiencyat large load at 10A.
• Stacked interleaved architecture[4] reaches best performanceat middle load range at 5A with a duty-cycle independentripple cancelation.
• single-phase stage has a reasonable performance based onthe trade-off between the size, volume and efficiency.
A fully customized ELT-type NMOS low-voltage core transistorlibrary cells including different sizes of primitive cells (p-cell)based on the selected 0.35um CMOS process is developed toassist EDA design flow such as DRC, VLS and PEX process. Theprocedures can be divided into four steps.
• Approximate a standard NMOS W, L and W/L with a Calibreextracted layout view.
• Create a complete DRC and LVS clean cell with all isolationring, body contact and parasitic diodes added, run PEXsimulation if necessary.
• Create a core device cell views with only gate, source anddrain connection kept the last step.
• Create/Update Cadence component description format (CDF)parameters for the core cells created above.
These Figures show the cell views of schematic, symbol and layoutfor a customized ELT NMOS. A buffer with multiplier and isolationrings is generated and verified in pre and post layout simulation.
At circuit level low-voltage 3.3V core MOSFET’s have to be used toprovide 5V gate driver output. A cascoded, or “house-of-card”structure is used to achieve the 5V output swing withoutexceeding the 3.3V VDS break-down voltage[6] [7].
The high-side (HS) or low-side (LS) driver is shown in the figures.The schematic and its simulation waveforms at 2-20 MHzfrequency with 20% duty-cycle validate the functions. The rad-hard layout with 25V isolation rings is shown below.
approx. size: 880 um x 440 um
Figure below on the left is the top-level diagram of the wholecustomized rad-hard driver and controller IC. The I/O LC filters,single-phase GaN power stage, and the passives compensationare off-chip. The circuit on the left pad-frame contains individualblocks for testing, the larger pad-frame on the right is the fullcomplete prototype IC. The final package is 64-lead QFN (9×9).
Design Innovations
Acknowledgements
Motivation
Design Approach
The design in this phase involves three steps.
• A printed circuit board (PCB) prototype design using discretecomponent-of-the-shelf (COTS) driver and controller IC’s hasbeen fabricated and tested in February.
• A fully customized driver IC with conventional analog/digitaldesign techniques has been tape-out with a 0.35um CMOSprocess in April.
• A fully customized single-chip driver and controller ICemployed with various RHBD techniques has been taped outwith a 0.35um CMOS process in July.
Parameter Specifications Unit
Input Voltage 16 - 24 V
Output Voltage 1.0 - 2.7 V
Load Current 5 - 7 A
Overall Efficiency ~ 80 %
Switching Speed > 10 MHz
Temperature range -55 to 125 °C
TID tolerance 3 Mrad
Mean Time to Failure 4e7 @ 150 ºC hours
Efficiency Drop @1Mrad TID < 6 %
Physical Dimensions 38mm x 17mm x 8mm mm
Based on the simulation and measured results in the figures,based on the stringent form-factor requirement, the single-phasestage has been selected for next step development due to itsoptimal trade-off between the size, volume and efficiency[5].
Customized ELT NMOS P-cell Library
5 V
0 V
2.5 V
5 V
0 V
5 V5 V
2.5 V2.5 V
2.5 V
2.5 V
0 V
0 V
Full Tape-out Schematic & Layout
To drive the cascaded output driver, a complementary signal pairwith one swing range of 2.5-5V and the other one of 0-2.5V isneeded. A level shifter also used the radiation tolerant thin gate-oxide low-voltage LDMOS provided in the 0.35um CMOS process.Simulation shows the simulation waveforms with 2-3ns dead-timeat 20 MHz with 20% duty cycle.
VL
VH
VH
VH
VL
VL VL
VH
Isolated HV domain
Common LV domainapprox. size: 420 um x 500 um
Future Developments
References
LC Passive Output
Network
5V BS Supply
5V Supply
High-side
Low-side
Gat
e D
rive
Si
gnal
Ge
ne
rati
on
BIS
T C
ircu
itry
&
Mo
du
lato
r
3.3V Supply
18V Supply
Off-chip Passive Compensation
1.7V Load
Off-chip Passive Module
eGaN Single-PhaseCMOS IC 0.35um Process
Converter Power Stage
Level Shifter
Dead-time BGR
Ramp Generator
Error Amplifier
Type III Compensation
Vout = 1.0-2.7V, Iout,nom = 5 A, Iout,max = 7 A
CLoad RLoad
Vin = 18-24V
LDO2LDO1
Vin Vdrv = 5V Vctl = 3.3V
High-Speed Comparator
HS Driver
LS Driver
5V Domain
3.3V Domain
25V Iso. Domain