garney hub additions

7/26/2019 Garney Hub Additions

http://slidepdf.com/reader/full/garney-hub-additions 1/15

May 16, 2000 1



May 16, 2000 2

USB 2.0Hub Add it ions

John Garney

Hub Working Group ChairIntel Corporation



May 16, 2000 3

Hub Add it ions

Requirements and Architecture

– Additions to USB1.1

Transaction TranslatorBulk/Control Transaction Handling

Isochronous/Interrupt Transaction Handling

Additions to Chapter 11



May 16, 2000 4

Requirements:

Provide high-speed expansion

Isolate full/low-speed from high-speed

–

Avoid lower speed impact on HS, i.e., LS impact on FS

All USB2.0 Hub Ports support HS/FS/LS

Optional: standardized port indicators (LEDs)



May 16, 2000 5

System SW

Client Driver Client Driver

USB 1.1Device

HS Hub

USB 1.1 Hub

USB 1.1Device

HS Device

USB 2.0 HostController

Full/Low Speed

High Speed Only

(2 x 12Mb/sCapacity)

Hub In High Speed Sys tem

Hub provides high-speed expansion (ala 1.1 hub) Hub provides additional classic bus(es)

– Same total number of devices per USB2.0 Host Controller (e.g. 127)

Greater end user value than classic hub

– Performance, expansion and ease of use

Hub is user selected device (not required for all systems)



May 16, 2000 6

HS/ClassicHub StateMachine

HS/ClassicHub

Repeater

HS/ClassicHub

Controller

High Speed Only

Port Port Port

Port

Hub “Classic Pieces”

Repeater – High speed signaling

Also, FS/LS signaling for 1.1 compatibility

– Reclocking

State Machine – HS termination sequencing

HS Detect, Reset, Suspend, Resume

Hub Controller – Respond to hub device class requests/events


http://slidepdf.com/reader/full/garney-hub-additions 7/15May 16, 2000 7

Hub A rch i tectu re

Same as classic hub:

– High & full/low-speed repeaters, determined by upstream facing link

– Hub controller

–No different then classic USB besides high-speed signaling

Minor changes from classic hub:

– Hub state machine (HS detect, HS termination transitions, test mode)

New in hub:

– Transaction Translator

–

Routing logic

HS/ClassicHub

Controller

TransactionTranslator

Full/LowSpeed

High Speed Only

. . . . .

HS/ClassicHub StateMachine

Routing LogicPort Port Port

Port

HS/ClassicHub

Repeater



Routing Logic

Transaction

TranslatorFull/LowSpeed

High Speed Only

Port

Repeater, Controller, ...

Port Port Port

Hub New Pieces

Port Routing Logic – Controllable electrical connection between:

Full/Low (Transaction Translator), or High-Speed (Repeater)

– Route done once per device reset

Transaction Translator – Major addition for USB 2.0

–

Uses split transaction protocol HC support

. . . . .



Hos t Con tro l ler / TT In teract ions

Host

Device

TTX

2

TT buffers full/low speed transaction information (X) locally

1 – SPLIT-s, OUT, DATAx(Start-split)

Host Controller issues start-split transaction to TT

TT R

4 - ...,ACK

TT buffers full/low speed transaction results (R) locally

3 - OUT, DATAx, ...

TT issues full/low speed transaction on downstream bus

6 - …,ACK

TT responds with results

InterruptOut

Example

5 – SPLIT-c, OUT, … (Complete-split)

Host Controller issues complete-split transaction to TT



Transact ion Trans lato r Overview

Two separate portions to Transaction Translator – Bulk/Control support

– Interrupt/Isochronous support

Bulk/Control uses USB flow control to make progress – PING not used

Interrupt/Isochronous uses a scheduled full/low speedtransaction “pipeline”

Separate buffers are used for each TT portion

Transaction Translator

Bulk &Control

Interrupt &Isochronous



TT Bu lk / Con tro l

TT buffers 2 or more bulk/control transactions

TT issues full/low speed transaction when no periodic

transactions pending Host controller issues split transactions to TT

– Allows starting/completing full/low-speed transactions each microframe

– Normal approach of “bandwidth reclamation” is used

– Tries to issue HS start-split; if successful, next attempt does complete-split

TT

Bulk/Ctrl #1 Bulk/Ctrl #2

High Speed Start-/Complete-Split

Full/Low Speed Transaction



TT In t. / Isoch . Pipeline

Host software budgets when full/low-speed transaction will run

Host schedules start-split before “earliest” start time

Host schedules complete-split at “latest” finish times

Scheduling accounts for variation due to bit-stuffing

and timeouts, etc.

TT

High Speed Start-Split High Speed Complete-Split

Start-splitFIFO Complete-splitFIFO

StartHandler

CompleteHandler

Full/LowHandler



TT

Start-splitFIFO

Complete-splitFIFO

Full/LowHandler

StartHandler

CompleteHandler

X

2

TT buffers full/low speed transaction information locally

1 – SPLIT-s, OUT, DATAx

Host Controller issues start-split transaction to TT

3 - OUT, DATAx, ...

TT issues full/low speed transaction on downstream bus

5 – SPLIT-c, OUT, ...

Host Controller issues complete-split transaction to TT

6 - …,ACK

TT responds with results

Example: In t. OUT Spli t Trans .

R

4 - ...,ACK

TT buffers full/low speed transaction results locally

Start-splitFIFO



Hub Cos t / Complexi tyEstimate

Classic Hub + new things – Classic Hub - implementation dependent, but knowable baseline – New things

Signaling

Required for any High-Speed device Logic (routing, TT) RAM (buffer space, transaction pipeline)

Total (approximate) – 40KGates + 1800 Bytes with 4 downstream ports

–

28KGates + (3KG * # of downstream ports) + 1800 Bytes

TT FIFOs

TT Logic

Port

High-Speed “Classic Hub”

Port Port Port

Routing Logic



May 16, 2000 15

USB2.0 HubAdd i tions Summary

Hub Ports Support all Speeds (High/Full/Low)

– Isolation of High and Full/Low Speeds via TT

Simultaneous High and Full/Low-Speed Transactions

– Full/Low Speed (12Mb/s) bus per TT

Can be TT per hub or TT per port

TT Internals Overview

–Bulk/Control buffering

– Interrupt/Isochronous scheduled pipeline

garney hub additions

Documents