gate level design. outline introduction analysis procedure design methods gate-level (ssi)...
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Gate Level Design
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Introduction (1/2)
Two classes of logic circuits: combinational Sequential
Combinational Circuit:
Each output depends entirely on the immediate (present) inputs.
CombinationalLogic: : : :inputs outputs
Introduction (2/2)
Sequential Circuit: (not covered)
Output depends on both present and past inputs.Memory (via feedback loop) contains past information.
CombinationalLogic: :inputs outputs: :
Mem
ory
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Analysis Procedure
Given a combinational circuit, can you analyze its function?
Steps:1. Label the inputs and outputs.
AB F1
F2
A+B
A'+B'
= (A+B).(A'+B')
= (A'+B')' = A.B
2. Obtain the functions of intermediate points and the outputs.
3. Draw the truth table.
A B (A+B) (A'+B') F1 F20 0 0 1 0 00 1 1 1 1 01 0 1 1 1 01 1 1 0 0 1
4. Deduce the functionality of the circuit half adder.
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Design Methods (1/2)
Different combinational circuit design methods: Gate-level method (with logic gates) Block-level design method
Design methods make use of logic gates and useful functional blocks. These are available as Integrated Circuit (IC) chips.
Design Methods (2/2)
Type of IC chips (based on packing density) : Small-scale integration (SSI): up to 12 gates Medium-scale integration (MSI): 12-99 gates Large-scale integration (LSI): 100-9999 gates Very large-scale integration (VLSI): 10,000-99,999 gates Ultra large-scale integration (ULSI): > 100,000 gates
Main objectives of circuit design:(i) reduce cost
reduce number of gates (for SSI circuits) reduce IC packages (for complex circuits)
(ii) increase speed(iii) design simplicity (reuse blocks where possible)
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Gate-level (SSI) Design: Half Adder (1/2)
Design procedure:
1) State ProblemExample: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.Example: Two inputs and two outputs labeled, as
follows:
HalfAdder
X
Y
S
C
(X + Y)
3) Draw truth table.
X Y C S0 0 0 00 1 0 11 0 0 11 1 1 0
Gate-level (SSI) Design: Half Adder (2/2)
4) Obtain simplified Boolean function.
Example: C = X.Y S = X'.Y + X.Y' = XY
X Y C S0 0 0 00 1 0 11 0 0 11 1 1 0
XY
S
C
Half Adder
5) Draw logic diagram.
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Gate-level (SSI) Design: Full Adder (1/5)
Half-adder adds up only two bits.
To add two binary numbers, we need to add 3 bits (including the carry).
Example: 1 1 1 carry0 0 1 1 X
+ 0 1 1 1 Y1 0 1 0 S
Need Full Adder (so called as it can be made from two half-adders).
FullAdder
XYZ
S
C
(X + Y + Z)
Gate-level (SSI) Design: Full Adder (2/5)
Truth table:
X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
Note:Z - carry in (to the current position)C - carry out (to the next position)
Using K-map, simplified SOP form:
C = X.Y + X.Z + Y.Z
S = X'.Y'.Z + X'.Y.Z'+X.Y'.Z'+X.Y.Z
0 1
00 01 11 10XYZ
111
1
C
0 1
00 01 11 10XYZ
11
11
S
Gate-level (SSI) Design: Full Adder (3/5)
Alternative formulae using algebraic manipulation:
C = X.Y + X.Z + Y.Z
= X.Y + (X + Y).Z
= X.Y + ((XY) + X.Y).Z
= X.Y + (XY).Z + X.Y.Z
= X.Y + (XY).Z
S = X'.Y'.Z + X'.Y.Z' + X.Y'.Z' + X.Y.Z
= X‘.(Y'.Z + Y.Z') + X.(Y'.Z' + Y.Z)
= X'.(YZ) + X.(YZ)'
= X(YZ) or (XY)Z
Gate-level (SSI) Design: Full Adder (4/5)
Circuit for above formulae:
C = X.Y + (XY).Z
S = (XY)Z
Full Adder made from two Half-Adders (+ OR gate).
(XY)XY S
C
Z
(XY)
Gate-level (SSI) Design: Full Adder (5/5)
Circuit for above formulae:
C = X.Y + (XY).Z
S = (XY)Z
Full Adder made from two Half-Adders (+ OR gate).
(XY)XY S
C
Z
(X.Y)
HalfAdder
HalfAdder
XY
XY
Sum
Carry
Sum
Carry
Block diagrams.
Outline
Introduction Analysis Procedure Design Methods Gate-level (SSI) Design
Half Adder Full Adder BCD-to-Excess-3 Code Converter
Code Converters
Code converters – take an input code, translate to its equivalent output code.
Codeconverter
Inputcode
Outputcode
Example: BCD to Excess-3 Code Converter
Input: BCD digit
Output: Excess-3 digit
BCD-to-Excess-3 Code Converter (1/2)
Truth table:
BCD Excess-3A B C D W X Y Z
0 0 0 0 0 0 0 1 11 0 0 0 1 0 1 0 02 0 0 1 0 0 1 0 13 0 0 1 1 0 1 1 04 0 1 0 0 0 1 1 15 0 1 0 1 1 0 0 06 0 1 1 0 1 0 0 17 0 1 1 1 1 0 1 08 1 0 0 0 1 0 1 19 1 0 0 1 1 1 0 0
10 1 0 1 0 X X X X11 1 0 1 1 X X X X12 1 1 0 0 X X X X13 1 1 0 1 X X X X14 1 1 1 0 X X X X15 1 1 1 1 X X X X
1
A
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X XA
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X X
A
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X XA
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X X
1
1 11
1
W
1
111
1
1
11
11
11
11
X
Y Z
K-maps:
BCD-to-Excess-3 Code Converter (2/2)
1A
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X X
11
11
Z
A
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X X1
1 11
1
W
W = A + B.C + B.D
X = B'.C + B‘.D + B.C'.D'
Y = C.D + C'.D'
Z = D'
A
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X X
1
111
1
X
A
C
00
01
11
10
00 01 11 10
D
AB
CD
BX XX X
X X1
11
11
Y