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General Iterative Heuristics for VLSI Multiobjective Partitioning

by

Dr. Sadiq M. Sait

Dr. Aiman El-Maleh

Mr. Raslan Al Abaji

King Fahd University

Computer Engineering Department

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• Introduction

• Problem Formulation

• Cost Functions

• Proposed Approaches

• Experimental results

• Conclusion

Outline ….

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Design Characteristics

0.13M12MHz1.5um

CAESystems,Silicon

compilation

7.5M333MHz0.25um

Cycle-basedsimulation,

FormalVerification

3.3M200MHz

0.6um

Top-DownDesign,

Emulation

1.2M50MHz0.8um

HDLs,Synthesis

0.06M2MHz6um

SPICESimulation

Key CAD Capabilities

The Challenges to sustain such an exponential growth to achieve gigascale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology.

VLSI Technology Trend

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Technology 0.1 umTransistors 200 MLogic gates 40 MSize 520 mm2

Clock 2 - 3.5 GHzChip I/O’s 4,000Wiring levels 7 - 8Voltage 0.9 - 1.2Power 160 WattsSupply current ~160 Amps

PerformancePower consumptionNoise immunityAreaCostTime-to-market

Tradeoffs!!!

The VLSI Chip in 2006

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1. System Specification

2. Functional Design

3. Logic Design

4. Circuit Design

5. Physical Design

6. Design Verification

7. Fabrication

8. Packaging Testing and Debugging

•VLSI design process is carried out at a number of levels.

VLSI Design Cycle

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Physical Design converts a circuit description into a geometric description. This description is used to manufacture a chip.

1. Partitioning

2. Floorplanning and Placement

3. Routing

4. Compaction

The physical design cycle consists of:

Physical Design

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• Decomposition of a complex system into smaller subsystems.

• Each subsystem can be designed independently speeding up the design process (divide-and conquer-approach).

• Decompose a complex IC into a number of functional blocks, each of them designed by one or a team of engineers.

• Decomposition scheme has to minimize the interconnections between subsystems.

Why we need Partitioning ?

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System Level Partitioning

Board Level Partitioning

Chip Level Partitioning

System

PCBs

Chips

Subcircuits/ Blocks

Levels of Partitioning

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Need for Power optimization

• Portable devices.

• Power consumption is a hindrance in further integration.

• Increasing clock frequency.

Need for delay optimization

• In current sub micron design wire delay tend to dominate gate delay. Larger die size imply long on-chip global routes, which affect performance.

• Optimizing delay due to off-chip capacitance.

Motivation

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Objective

• Design a class of iterative algorithms for VLSI multi objective partitioning.

• Explore partitioning from a wider angle and consider circuit delay , power dissipation and interconnect in the same time, under balance constraint.

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Objectives :

• Power cost is optimized AND

• Delay cost is optimized AND

• Cutset cost is optimized

Constraint

• Balanced partitions to a certain tolerance degree. (10%)

Problem formulation

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• Based on hypergraph model H = (V, E)

• Cost 1: c(e) = 1 if e spans more than 1 block

• Cutset = sum of hyperedge costs

• Efficient gain computation and update

cutset = 3

Cutset

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SE1 SE2C1 C4 C5

C3

C2

C6

Cu

t Lin

e

CoffChip

C7

Metal 1

Metal 2

path : SE1 C1C4C5SE2.

Delay = CDSE1 + CDC1+ CDC4+ CDC5+ CDSE2

CDC1 = BDC1 + LFC1 * ( Coffchip + CINPC2+ CINPC3+ CINPC4)

Delay Model

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PinetPicell

netDelaycellDelay )()(Delay(Pi) =

Picell

cellDelay )(Delay(Pi) =

Pi: is any path Between 2 cells or nodes

P : set of all paths of the circuit.

)(: PiDelayMaxObjectivePPi

Delay

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The average dynamic power consumed by CMOS logic gate in a synchronous circuit is given by:

iLoadi

cycle

ddaveragei NC

T

VP

2

5.0

Ni : is the number of output gate transition per cycle( switching Probability)

LoadiC : Is the Load Capacitance

Power

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extrai

basici

Loadi CCC basiciC : Load Capacitances driven by a cell

before Partitioning

extraiC : additional Load due to off chip

capacitance.( cut net)

ii

extrai

basici

cycle

dd NCCT

VP

2Total Power dissipation of a Circuit:

Power

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vi

iNobjective

:

basici

extrai CC

extraiC : Can be assumed identical for all nets

v :Set of Visible gates Driving a load outside the partition.

Power

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The Balance as constraint is expressed as follows:

TolblockscellsBlockTolblockscells i //

PercentTolblockcellsTol */However balance as a constraint is not appealing because it may prohibits lots of good moves.

Objective : |Cells(block1) – Cells( block2)|

Balance

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• Imprecise values of the objectives– best represented by linguistic terms that are

basis of fuzzy algebra• Conflicting objectives• Operators for aggregating function

Fuzzy logic for cost function

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1. The cost to membership mapping.

2. Linguistic fuzzy rule for combining the membership values in an aggregating function.

3. Translation of the linguistic rule in form of appropriate fuzzy operators.

Use of fuzzy logic for Multi-objective cost function

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• And-like operators– Min operator = min (1, 2)– And-like OWA

= * min (1, 2) + ½ (1- ) (1+ 2)

Or-like operators– Max operator = max (1, 2)– Or-like OWA

= * max (1, 2) + ½ (1- ) (1+ 2)Where is a constant in range [0,1]

Some fuzzy operators

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Where Oi and Ci are lower bound and actual cost of objective “i”

i(x) is the membership of solution x in set “good ‘i’ ”

gi is the relative acceptance limit for each objective.

Membership functions

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• A good partitioning can be described by the following fuzzy rule

IF solution has

small cutset AND

low power AND

short delay AND

good Balance.

THEN it is a good solution

Fuzzy linguistic rule

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The above rule is translated to AND-like OWA

BDPC

BDPCx

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,,,min)(

Represent the total Fuzzy fitness of the solution, our aim is to Maximize this fitness.

)(x

BDPC ,,, Respectively (Cutset, Power, Delay , Balance ) Fitness.

Fuzzy cost function

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Algorithm (Genetic_Algorithm)

Construct_Population(Np);

For j = 1 to Np

Evaluate_Fitness (Population[j]) End For;

For i = 1 to Ng

For j = 1 to No

(x,y) Choose_parents;offspring[j] Crossover(x,y)

EndFor;

Population Select ( Population, offspring, Np )

For k = 1 to Np

Apply Mutation (Population[k]) EndFor; EndFor;

GA for multiobjective Partitioning

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Solution representation

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• Different population sizes• Parent selection: Roulette wheel

– The probability of selecting a chromosome for crossover is

Np is the population size

Np

1i

choice

μ(i)

μ(x)P

GA implementation

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•Simple single pointcrossover:

•Selection before mutation

•Roulette wheel (rlt)

• Elitism random (ernd)

GA implementation

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Algorithm Tabu_Search Start with an initial feasible solution S Initialize tabu list and aspiration levelFor fixed number of iterations Do

Generate neighbor solutions V* N(S)Find best S* V*If move S to S* is not in T Then

Accept move and update best solutionUpdate T and AL

Else If Cost(S*) < AL ThenAccept move and update best solution

Update T and ALEnd IfEnd For

Tabu Search

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• Neighbor solution – Change the block of a randomly selected cells.

• The Tabu list size depends on the circuit size.

TS implementation

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Tabu list

• Store index of one of the swapped cell.

• Various sizes for tabu list.

Aspiration Level

• The best neighbor is better than the global best.

TS implementation

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Experimental Results

ISCAS 85-89 Benchmark Circuits

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GA Vs Tabu Multi-objective

Circuit S13207 GA

Circuit S13207 TS

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Circuit S13207 GA Vs TS time

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Conclusion

• The present work successfully addressed the important issue of reducing power and delay consumption in VLSI circuits.

• The present work successfully formulate and provide solutions to the problem of multiobjective VLSI partitioning

• TS partitioning algorithm outperformed GA in terms of quality of solution and execution time

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Thank you.