generalized scaling theory and its application micrometer

452 IEEE TRANiACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 4, APRIL 1984

Carlo method,” J. Appl. Phys., vol. 41, no. 9, pp. 3843-3845’, ical analysis of stability criteria of GaAs FET’s,”ZEEE Trans. Elec- 1970. iron Devices, vol. ED-23, pp. 1283-1290, 1976.

[17] K. Yamaguchi, T. Toyabe, and H. Kadera, “Two-dimension:ll [I91 W. Shockley, “A unipolar ‘field-effect’ transistor,”Proc. IRE, vol. analysis of vertical junction gate FET’s,” Proc. 7th ConJ Sold 40, pp. 1365-1376, 1952. State Devices 1975, Suppl. to Japan. J. Appl. Phys., vol. 15, PI). [20] D. P. Kennedy and R. R. O’Brien, “Computer aided two-dimen- 163-168,1976. sional analysis of the junction field-effect transistors,”ZBM J. Res.

[18 ] K. Yamaguchi, S . Asai, and H. Kodera, “Two-dimensional numet- Dev., vol. 14, pp. 95-116, 1970.

Generalized Scaling Theory and Its Application to a Micrometer MOSFET Design

Abstract-In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions a11d applied voltages, while still maintaining constant the shape of t ~ e electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increar,e. The resulting design flexibility allows the design of FET’s with quartlx- micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scallirig theory are then investigated in detail, leading to the conclusion tkat the limiting FET performances are not reached at the 0.25-pm chanllel length, Further improvements are possible in the future, provided certain technology breakthroughs are achieved.

NOMENCLATURE Boltzmann constant. Current ideality factor. Electron concentration. Subthreshold current ideality factor. Hole concentration. Electron charge. Inversion-layer thickness. Carrier saturation velocity. Depletion width. Junction depth. Device area. Depletion capacitance. Inversion-layer capacitance, - a Q,/a &. Gate-channel capacitance, - aQn/aVGs. Oxide capacitance. Electron diffusivity. Electric field. Average normal field within the channel. Critical field for velocity saturation.

Manuscript received January 19, 1983;revised May 10, 1983. The authors are with the IBM Thomas J . Watson Research Center,

Yorktown Heights, NY 10598. G. Baccarani is on leave from the llni- versity of Bologna, Bologna, Italy.

Arbitrary electric field. Surface field at threshold. Electron current density. Channel length. Debye length. Acceptor concentration. Substrate acceptor concentration. Donor concentration. Electron density per unit area. Mobile charge density per unit area. Projected range. Drain parasitic resistance. Source parasitic resistance. Sheet resistance. Spreading resistance. Absolute temperature. Bulk-source voltage. Drain-source voltage. Gate-source voltage. Low logic level. Threshold voltage. Channel width. Silicon dielectric constant. Drain-induced barrier lowering coefficient. Potentials scaling factor. Linear dimensions scaling factor. Electron mobility within the channel. Electron mobility at the field Eo. Effective electron mobility within the channel. Resistivity in the source region. Standard deviation. Electric potential. Surface potential. Surface potential at threshold. Low logic level variation.

0018-9383/84/040C~-0452$01 .OO 0 1984 IEEE

BACCARANI et al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 453

I I. INTRODUCTION

N THE LAST decade the miniaturization limits of MOS devices have been the subject of several investigations [ 11 -

[6]. In 1972 Hoeneisen and Mead [ l ] identified the drain- source punchthrough and the gate-oxide breakdown as the most important limiting factors. The subsequent development of the channel implant as a tool to adjust the threshold voltage added further flexibility to the device design, allowing for better tradeoffs between drain-induced barrier lowering and substrate sensitivity.

In the same year the scaling theory was first presented [7] , identifying concise design criteria for small dimension FET's. According to such a theory, if the device physical dimensions and applied potentials are scaled by a common factor I/K, ( K > 1) and the impurity concentration is increased by K , the shape of the electric-field pattern within the scaled device remains constant. Therefore, two-dimensional effects such as drain-source punchthrough and threshold sensitivity to channel length and drain voltage remain under control. Such a theory was confirmed by the successful fabrication of 1-,um channel devices exhibiting the expected, properly-scaled characteristics with respect to those of a typical 5-pm FET technology [8] .

Although the scaling theory has been widely used in the past as a guide to MOSFET miniaturization down to the 1-pm level, its limited flexibility does not allow one to properly design a quarter-micron channel FET by its straightforward application, the limiting factors being:

1) The temperature variation of threshold voltage (e - 1 mV/"C) which leads to a large threshold fluctuation if an extended operating temperature range must be guaranteed. This limiting sensitivity basically results from the temperature dependence of the Fermi level in the substrate and of the band bending required to reach the onset of strong inversion;

2) The nonscalability of the junction built-in potential, which leads to a larger depletion width relative to the device physical dimensions, and makes the short-channel effect more severe.

Both of the above properties call for the threshold and supply voltages to be reduced less than conventional scaling would indicate.

In view of the above considerations, it would be desirable to generalize the scaling theory, and identify the design criteria that, while allowing the local field to increase, still conserve the shape of the electric field and potential distributions within the scaled device. So doing, the FET physical dimensions and the applied potentials can be scaled by independent factors, thus considerably improving the design flexibility while, at the same time, keeping two-dimensional effects under control.

In the next section we present such a generalization, identify the new rules to be followed for a proper scaling, and investi- gate its consequences in terms of achievable device performance. In Section 111, we indicate the avenues of attack of a quarter-micrometer channel FET design, for both room and liquid-nitrogen temperature operations. In so doing, we account for reasonable manufacturing tolerances and assume, as a reference, a typical 1-pm process [9], [IO].

In Sections IV-VI1 we discuss the most important physical

limitations which affect the behavior of very small devices, and develop improved models to account for such effects in the evaluation of the device performance. Among these, we shall consider:

1) The effect of the finite inversion-layer thickness (or limited inversion-layer capacitance) which results in a transconductance degradation. Although this effect was already incorporated in the early model by Pao and Sah [ 1 I ] , it is only more recently that its importance has been pointed out in connection with reduced oxide thickness [ 121 ;

2) The mobility degradation effect due to the influence of increasing normal fields [ 131 - [ 151 . Such an effect is responsi- ble for degraded output characteristics in the triode region;

3) The saturation of the drift velocity occurring at large parallel fields [ 161 - [ 181 ;

4) The effect of the source-drain contact and spreading resistances, which negatively influences the device characteristics both in the triode region and in saturation [ 191 , [20] . Such a degradation is of course more severe as the channel width and length are reduced according to the: scaling rules.

Conclusions are drawn in Section VIII, where we estimate the FET performance achievable at the quarter-micrometer level and discuss the feasibility of further device scaling.

11. GENERALIZED SCALING THEORY For any given device geometry and set of boundary condi-

tions, the field configuration within a MOSFET results from the solution of Poisson's and current continuity equations, i.e.,

aZ$ a2$ a2$ axz a y 2 a z z - t - - t - = - - ( p - n t N D - N A )

where

Jn = -qp,,n grad $ + 40, grad n. (3)

In subthreshold conditions the electron concentration neglig- ibly contributes to the space charge on the RHS of (1). There- fore, (1) and ( 2 ) can be decoupled, and we can refer to (1) only. Let us consider the variable transformation

by which (1) becomes

and, simplifying

Equation ( 5 ) is formally identical to (I), and can be interpreted as Poisson's equation for a scaled device. If the boundary conditions (i.e., potentials at source, drain, and gate electrodes) are proportionally reduced by K , solutions of (1) and ( 5 ) only

454 IEEE TRP.NSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 4, APRIL 1984

differ by a scale factor, and the shape of the electric-f.eld pattern is the same in the two devices. The intensity of the field, however, varies by X / K and does therefore increas: if h>K.

Equation (4) represents the generalized scaling rules to be applied when the voltages cannot be reduced in direct propor- tion to the device physical dimensions. Since the field pattern is conserved within the scaled device, punchthrough and dr;lin- induced barrier lowering are expected to remain essentially tm- modified, in spite of the increase in the electric field strenEth. It is straightforward to verify that, when h = K , (4) tend to !he conventional scaling rules [7], [8].

The implicit assumption underlying (4) is that, by suita Ay scaling applied voltages and doping profiles, electron and Inole concentrations increase by the factor X 2 / ~ . As n and p Bre exponential functions of 4, such an assumption is not justified except for holes in the neutral region. Within the deple.t:on region, however, (n , p ) << NA , so that the space-charge density is not affected by electron and hole concentrations and scales by the proper factor.

The Debye length L D = ( E , ~ T / ~ ~ N A ) " ~ , which represetlts the width of the intermediate layer between neutral and spat:e- charge regions, scales by K'"/?L Thus only for constant voltzge scaling ( K = 1) is the Debye length reduced proportionally with the linear dimensions. However, so long as LD is much smaller than the depletion width, the effect of a nonscaling transition width has a negligible influence on the overall pokn- tial and field distribution.

When the FET operates in strong inversion (1) and (2) c m - not be decoupled anymore because the electron concentrati In effectively contributes to the space charge, and, due to the nonlinearity of the transport equation, we cannot expect n 1.0 scale, as required, by the factor X 2 / ~ within the channel. Never- theless, so long as the inversion layer is thin enough to negli- gibly contribute to the surface potential, the total electron density per unit area Ni still varies, as expected, by h / ~ . Tlt~us the scaling principle still applies, even in strong inversion, in the limit of a vanishingly small channel thickness which pins the surface potential at the onset value of strong inversion. The channel thickness tinv is, within a classical model, i n - versely proportional to the surface field and therefore scales by ~ / h . Thus only for constant voltage scaling does tinv scale with the device physical dimensions. In general, tinv increases by the factor K relative to the oxide thickness, giving rise tc a transconductance degradation effect to be discussed in Section IV .

Table I reports the scaling factors associated with the most important physical quantities, in the general case of h f. K. For n-channel logic circuits, gate delay and power consunl3- tion are primarily determined by the depletion-load chargillg current which, in turn, equals the enhancement device currel~t at the circuit logic threshold. In this condition, the dril't velocity is generally not saturated at room and higher temperatures, while the opposite holds true at 77 K. Hence, tv,o scaling factors are reported for a number of parameters inch 1- ing current, gate delay, and power consumption. The factor k , in the expression of the current for saturated drift velociry is a slowly increasing function of the ratio (l',s/LE,), L ' , being the critical field for velocity saturation [21]. Thus I : ,

TABLE I GENERALIZED SCALING FACTORS ASSOCIATED WITH THE MOST

IMPORTANT PHYSICAL QUANTITIES Physical Parameter Expression Scaling factor

300'K 77'K

Lin. Dimensions w. L. to,, x, 1 /A

Potentials 00, os, 0, l / K

Impurity Conc. NA, ND h 2 / K

Electric Fieid E A / K

Capacitances A Cox, A C, 1 /X

Current (uns. vel.) (W/L)pCox(Vos-VT) VDs X / K 2

Current (sat. vel.) ks w cox (Vas- VT)V,,, I / K

Power ID VDD X/k3 l/n2

Power Density I D VDD 1 A X 3 / 2 X2/r2

Gate Delay Co VDD 1 ID . /h2 1 /A

Power-Delay Pr. ID vDD td l / h K 2

Line Resistance p l / A X

Current Density ID / A X 3 / 2 X2/r

Time Constant R, C, I

slightly varies vs h / ~ but is regarded as a constant throughout the table. Therefore, the predicted scaling factors at 77 K for drain current and gate delay are rather pessimistic for h > K ,

while those associated with power and current densities are perhaps slightly optimistic.

The most important limitations resulting from the choice h > K are represented by the increases in power density by h 3 / ~ 3 , and in current density within the interconnection lines by h 3 / ~ 2 , For a given chip size, the former effect leads to an increased power dissipation and enhanced heat-removal problems. The latter is of special concern due to electromigration and long-term reliability. Also, the increased oxide field must be contained within acceptable limits, because the mean time to failure is an exponential function of the oxide field itself

The scaling laws for the constant-voltage scaling case may be found by setting K = 1. In order to conserve the shape of the electric-field pattern within the scaled device, the bulk impurity concentration must increase by h 2 . In a recent paper [ 191 , Chatterjee et al. suggested a criterion for MOSFET miniaturization at constant supply voltage implying an increase of the bulk impurity concentration by X and a reduction of the oxide thickness by l lh1 t2 , Such a criterion, however, does not conserve the shape of the electric-field pattern, allows for relatively more extended depletion regions and reduces the gate control over the channel, making the short-channel effect more severe, and ultimately leading to a source-drain punchthrough. Within the cohstant voltage scaling scheme, the gate delay and power-delay product improve by X2 and X, respectively, while the power/circuit increases by the latter factor. The power density, however, increases by X3 and so does the current density within the interconnection lines. Besides, the field increase by X at still large applied voltages is of considerable concern due to increased impact ionization and related breakdown phenomena. Hot-electron injection into the oxide [23] represents an additional limitation associated with a pure

[221 .

BACCARANI e t al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 455

TABLE I1 PROPOSED ROOM-TEMPERATURE QUARTER-MICROMETER DEVICE

DESIGN(QMDT) COMPARED WITH A 1-prn DESIGN (LATV) ALONG W I T H ASSOCIATED SCALING PARAMETERS

Physical Parameter LAW QMDT Sealing Factor

Channel length (pm) 1.3 0.25 5.2

Oxide thickness (nm) 25 5 5.0

Junction depth (pm) 0.35 0.07-0.14 5.0-2.5

Supply voltage (V) 2.5 1 .O 2.5

Threshold voltage (V) 0.6 0.25 2 .4

Band bending (VI 1.8 0.8 2.25

Impurity Conc. 3xlOl’ 3 ~ 1 0 ’ ~ 0.1

constant-voltage scaling, which makes it impossible to properly design submicrometer FET’s while maintaining the (to day) standard 5-V supply.

III. 1/4 MICROMETER MOSFET DESIGN

In this section we discuss the design tradeoffs for a quarter- micrometer channel FET, assuming a manufacturing tolerance of kO.1 pm. Both room temperature and liquid-nitrogen operations are considered, leading to different device designs. In doing so, we make use of the generalized scaling theory and assume, as a reference, a typical 1-micrometer process called LATV [ 9 ] , [ l o ] , developed at IBM in the mid-seventies.

Table I1 compares the most important physical parameters for the LATV and the proposed quarter micrometer device technology (QMDT) and lists the corresponding scaling factors. Assuming X = 5 , the required oxide thickness and junction depth turn out to be 5 nm and 0.07 pm, respectively. While it certainly represents a challenging task to properly grow and control a 5-nm oxide, such an objective does not seem far beyond today’s capabilities, in view of the large experience gained in 20 years of studies and experimental activities on the subject. Similarly, a 0.07-pm deep junction can be obtained as a lightly-doped source-drain extension, using a suitable spacer technology [24]. The most serious limitations of such an approach would be the large sheet resistance of the source/drain extensions (R, 100 n/O) the implication of which is discussed in detail in Section VI. A viable alternative could be that of using a somewhat deeper source-drain region having a smaller sheet resistance. Even though such a choice represents a deviation with respect to the scaling theory, two- dimensional simulations using FIELDAY [25] show that no punchthrough effect occurs with junction depths up to 0.14 pm, even at the lowest dimensional size o f L = 0.15 pm, while the threshold sensitivity to channel length and drain voltage is only slightly affected by the increased junction depth.

In the design of a quarter-micrometer FET, the choice of the threshold voltage is a crucial one, for it basically determines the supply voltage to be used. If the design is intended for logic applications, the criterion one should refer to is the noise margin that can be afforded, accounting for threshold sensitivity to effective channel length and drain voltage, operating temperature range, and process tolerances. An estimate of the lowest possible threshold voltage, accounting for the above

TABLE I11

DESIGN(QMDT) COMPARED WITH A 1 - w n DESIGN ( L A W PROPOSED LIQUID-NITROGEN QUARI-ER-MICROMET-ER DEViCE

ALONG Wll -H ASSOCIATED SCALIKG PARAMElERS

Physical Parameter LATV QMDT Seallog Fpctor

Channel length (pm) 1.3 0.25 5.2

Oxide thickness (nm) 25 5 5.0

Junction depth (pm) 0.35 0.07-0.14 5.0-2.5

Supply voltage (V) 2.5 0.6 4.2

Threshold voltage (V) 0.6 0.15 4.0

Band bending (V) 1.8 0.5 3.6

Impurity Conc. (cm-3) 3x10’’ 2 ~ 1 0 ’ ~ 0.15

effects, and assuming the temperature range 0-75”C, leads to the choice of VT = 250 mV at the largest operating temperature (Le., 75°C). From circuit requirement considerations, the supply voltage is then set at VDD = 4VT = 1 V, and therefore K turns out to be 2.5. This small power supply voltage is chosen to reduce power at a given performance level as well as to minimize the adverse effects of velocity saturation, mobility degradation, and other high field effects. In order to reduce the band bending as far as possible by the same factor, the backgate bias (- 1 V for the LATV process) is reduced to zero; this leads to a potential drop across the depletion region of 0.8 V, as compared to 1.8 V for the LATV design. The corresponding scaling factor is 2.25, fairly close to the desired value of K = 2.5. Finally, the impurity concentration is chosen according to the generalized scaling rules, using the appropriate factor A’/K = 10.

The relative advantages of liquid-nitrogen € E T operation in terms of speed, reliability and heat removal problems have been widely discussed by Gaensslen et al. [26] . Table I11 reports the proposed physical parameters for the liquid-nitrogen temperature design. In this case two factors allow us to substantially reduce the threshold voltage: 1) the stability of the operating temperature, and 2) the possibility of positively biasing the back contact, which makes the threshold voltage more insensitive to channel-length variations. The optimum choice of the substrate bias must be as large as possible, but still low enough as to avoid any appreciable forward-bias current. Experimental results show that such a current is a slowly increasing function of the applied voltage, so long as the latter is maintained below 0.9 V. A reasonable compromise that accounts for the various constraints is the choice of VT = 0.15 V and VDD = 0.6 V, with the backgate contact tied up to VDD. So doing, the need of an additional supply source is avoided. The resulting potential drop across the depletion region turns out to be 0.5 V, with a corresponding scaling factor of 3.6, so that all the potentials are scaled by approximately a value of 4.

In most small dimensions MOSFET designs, one or more boron channel implants are performed which enhance the concentration of acceptors in the channel region near the surface. The implants have a twofold function: their primary use is to adjust the threshold voltage to the desired value; however they also help reduce the depletion width under the gate and at the junction curvature, thus suppressing punchthrough effects.

In order to properly design the channel impurity profile, an

456 IEEE TR.ILNSACTIONS ON ELECTRON DEVICES, VOL. E D - ~ I , NO. 4, APRIL 1984

algorithm has been developed by which the implant paramcters are determined for any desired depletion width xd within a permissible range. The implanted profile can be either peg ked at the interface or within the semiconductor. In the 12 tter case, the following equations must be fulfilled

1:6a)

where E , i and represent the surface field and the surfxe potential, respectively, at the onset of strong inversion; N(l is the peak, R , the projected range, and u the standard deviat Ion of the assumed Gaussian impurity profile superimposed 0 : a constant background doping N B , and NA(x) is the result.ing doping profile. In (6) the former terms represent the contri w- tion to the surface field (or potential) due to the space charge within the depletion region, while the latter is the contributjon due to the space charge within the quasi-neutral region [27] .

The choice of the threshold voltage and substrate bias uniquely determines E , i and q5s, i , after the oxide thickn.l:ss and the background doping have been chosen. Consequenl ly (6) contains four variables, namely N o , R,, a, and xd. 'Ne assume that a fixed ratio exists between projected range and standard deviation, as suggested by experience, and treat ':d

as an independent variable. The self-consistent solution of ( '6) for any value of xd then determines R , , u, and N o . Figs, 1 a zd 2 show the projected range and implanted dose against .the depletion width, which provide a threshold voltage 0.3 V at 75°C for a long-channel device. Such a value corresponds to about 0.25 V for a nominal channel length of 0.25 pm. The dotted lines in Fig. 1 intersect the solid curve at points rep:e- senting a well-defined ratio between (xd - R,) and the stall& ard deviation u. Of course, the choice of a smaller depleticn width leads to a more pronounced substrate sensitivity of threshold voltage.

For several implant conditions, 2-D simulations using FIEL- DAY [25] were performed, and the threshold dependence on channel length and drain voltage was investigated. Fig. 3 shows the parameter 7 = - (dV, /dV~s) against the long-channel depletion width, and the 2-D simulation results are compared with the theory by Ratnakumar et al. [28] . A junction dep.:h of 0.1 pm was assumed in the calculation. The agreement i.s remarkably good for each considered channel length, and jt appears that, from the standpoint of short-channel effect, it is generally desirable to reduce the depletion width to the louv- est practical value. From Fig. 3 it appears that the factor 17 can be as low as 30 mV/V in the nominal case of L = 0.25 p ~ : : ~ but it raises to about 80 mV/V at the lowest dimensional &;e

R,=2.o r,, = 5 nm N, 3 . ~ 1 0 ' ~ cme3 V, = 0.3 V

2o I ID

0 ' I 1 , I I I

50 60 70 80 90 100 I10

DEPLETION WIOTH (nm)

Fig. 1. Projected range of the channel implant against depletion width for the present room temperature FET design. The resulting threshold voltage is 0.3 V for a long-channel device and 0.25 for a quarter- micrometer FET. The dotted lines intersect the solid line at a depletion width extending beyond the peak of the implant by the indicated number of standard deviations.

4.0 1 I I I I I

3.5

- 3.0

- T,, = 5 nm N, = 3.~10" cm.$ V, = 0.3 V Rp 2.a

T v, 0.0 Y

v 1 = 7 5 C Y

D Y

2.0

iE 1.5

1.0

0.5 -

0.0

z

1 I 1 I I

50 60 70 80 90 100 110

DEPLETION WIDIH (nm)

Fig. 2. Implanted dose of the channel implant against depletion width for the present room-temperature FET design.

0 50 100 150 200

DEPLETION WIDTH (om)

Fig. 3. Drain-induced barrier lowering coefficient against depletion width. The solid line represents the theory by Ratnakumar etal . [ 211, while the discrete points are the result of numerical simulations.

of L = 0.15 pm. The choice of V , = 0.25 V already accounts for this worst-case threshold dependence upon drain potential. The choice of the depletion width must therefore be made trading off substrate sensitivity of the threshold voltage and short-channel effect.

BACCARANI e t al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 457

Similar considerations apply to the choice of the channel implant for the liquid-nitrogen device design. The substantially reduced band bending and supply voltage allow a better control of the threshold voltage which, therefore, can be set at 0.15 V in this design.

IV. EFFECT OF FINITE INVERSION-LAYER CAPACITANCE In MOSFET modeling it is generally assumed that the mobile

channel charge increases linearly with gate voltage for biases above threshold. This is indeed the case so long as the oxide thickness is much larger than the inversion-layer width, and for relatively large applied voltages. Using ideal constant-field scaling, the inversion-layer thickness remains essentially constant while the oxide thickness is reduced according to the scaling factor. Consequently, the oxide capacitance increases relative to the inversion-layer capacitance, Cj = -(aQ,/&$,) leading to a sub-linear channel-charge variation and to a degraded transconductance. The effect of the inversion-layer capacitance was already incorporated in the early model by Pao and Sah [ 111 , assuming a uniform impurity concentration. Modern FET's, however, invariably require a channel implant which considerably alters the surface field. Consequently, their integral expression cannot be expected to provide quantitatively good results.

To calculate the inversion-layer capacitance, we take advantage of the fact that the inversion-layer width is generally much thinner than the scale of length over which the doping density appreciably varies, and solve Poisson's equation within the inversion layer, assuming as a doping the surface value Ns [30] . At the position where n = Ns we impose the value of the electric field resulting from the solution of Poisson's equation within the depletion region, where the carrier density is ne- glected. So doing, the value of the inversion-layer capacitance and channel charge can easily be determined, within a classical model, by accounting for the proper surface field,

It is well known that the motion of electrons normal to the interface is quantized within the inversion layer [3 11 , and that the conduction band is split in several sub-bands, each of which represents a two-dimensional continuum associated with a well-defined energy level. Accounting for these quantum effects requires the simultaneous solution of Poisson's and Schroedinger's equations; besides, at room and higher temperatures several sub-bands are occupied, which makes the com- putational problem extremely heavy. Although less appealing from the conceptual point of view, the classical model turns out to quantitatively interpret the effect under investigation, as shown in Figs. 4 and 5 . The former represents the gate- channel capacitance CGC = - ( aQ, / aV~s) measured at room temperatures with the quasi-static C-V technique [32] on a structure having a 10-nm thick oxide; the latter represents the channel charge Q,, obtained by integration of the channel capacitance. As can be seen, the agreement is excellent over the whole range of applied voltages, indicating that the classical model can adequately interpret the above behavior at room and higher temperatures. It should be observed that the above fittings contain two adjustable parameters: the oxide thickness, which sets the asymptotic behavior of the channel capacitance, and the flat-band voltage, which is known with a limited degree

0.0 0.0 0.5 1.0 1.5 2.0 2.5 3,O

GATE VOLTAGE (V)

Fig. 4. Normalized theoretical and experimental gate-channel capacitance against gate voltage for an FET having an oxide thickness of 10.3 run.

4 I 3 I

0.0 0.5 1.0 1.5 2.0 2.5 3.0

GATE VOLTAGE (V)

Fig. 5 . Theoretical and experimental channel charge against gate voltage for an FET having an oxide thickness of 10.3 nm.

0.0 0.2 0.4 0.6 0.8 1.0

GATE VOLTAGE (V)

Fig. 6. Theoretical channel charge against gate voltage having an oxide thickness of 5 n m .

for an FET

of accuracy due to the uncertainty on the exact position of the Fermi level within the degenerately-doped poly-gate. The doping profile within the semiconductor was separately determined with an independent measurement, and wasnot adjusted to fit the capacitance and charge data.

Fig. 6 shows calculated results using the same model for inversion-layer charge versus gate v.oltage at 75°C for an FET having a 5-nm gate oxide and a channel implant such that V , = 0.3 V. At the largest gate voltage, the total channel

458 IEEE TRAPISACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 4, APRIL 1984

charge turns out to be 15 percent less than expected by re - glecting the effect of the inversion-layer capacitance. ?'-le quantitative extent of this charge decrease is therefore far i a s important than predicted by El-Mansy [20] who, within the constant-voltage scaling scheme, assumed a constant inversic:n- layer thickness of 10 nm regardless of the surface field, a Id reached the conclusion that a 50-percent degradation occlirs with an oxide thickness of 5 nm.

V. MOBILITY DEGRADATION EFFECT. The electron channel mobility is known to be a decreasing

function of the normal field [ 131 - [15] . In order to experi- mentally determine such a functional dependence, a combilr~a- tion of channel capacitance and drain current measuremerits were digitally performed at room temperature on large arc:a, thin oxide FET's, using the technique described in [ 151 , :3y integration of the inversion-layer capacitance, the chanllel charge was determined for each value of the gate voltage, and the experimental curve was fitted with the model described in the previous section, using flat-band voltage and oxide capacitance as adjustable parameters. The turn-on characteristic measured with a constant drain voltage, VDS = 100 mV, was then used to determine the channel mobility. It was found that the drain voltage was by no means small enough to keep the inversion layer uniform throughout the channel, except at the largest gate voltages. If not properly accounted for, 1he channel nonuniformity produces a fictitious mobility maxi- mum in the vicinity of threshold, and severely reduces ..he achievable accuracy, even in strong inversion. When the n'm- uniformity of the channel was accounted for by using :he generalized Pao-Sah integral expression, such a maximIm disappeared, and the carrier mobility turned out to monotc'ni- cally decrease as the normal field increases. As already Ib- served by Sabnis and Clemens [14], the various mobility curves, when plotted against the average normal field exp:ri- enced by the carriers within the inversion layer, merged h t o one universal curve as shown in Fig. 7. Here we report the mobility data extracted from 4 samples, having oxide thick- nesses of 10 and 26 nm, and different channel implants. Over the range of average fields 2 X lo4-6 X lo5 V/cm, the elect 'on mobility can be described by the empirical expression

pn =p0(~0/~ , )113 = 3.25 . 1o4~;;I3 17)

where po is the carrier mobility at the arbitrary field E o . A possible choice of the above parameters is po = 700 cm2/W s, and Eo = lo5 V/cm.

Mobility is reduced in small dimension FET's relative to larger devices due to an increase in the average normal f d d in the inversion layer. This may be brought about by yon- proportional voltage scaling (X > K). Even when proporticlnal scaling (X = K) is applied, E, will increase due to the r on- scalability of the work-function difference between the degenerately-doped poly-gate and the inversion layer.

Using (6) within the generalized Pao-Sah formula, the t l m -

on characteristic shown in Fig. 8 is found for a square IiET with a 5-nm oxide and an n+ poly-gate, at 75°C. For sw:h a device, the decreasing mobility is compensated for by the increase in the inversion-layer capacitance in such a way :hat

900 800 - 700 -

600 -

500 -

400 ~ ,

- 103 -

300 ~

T,, = IO nm, V,, 0.0 V T,, IO nm, VIS 1 0.5 V

104 105 106

AVERAGE FIELD ( V / c m )

Fig. 7. Experimental electron mobility against average field at room temperature.

4 / 0 I I 1

0.0 0.2 0.4 0.6 0.8 1.0

GATE VOLTAGE (V)

Fig. 8. Predicted turn-on characteristic for the quarter-micrometer FET.

a remarkably linear characteristic results in the over-threshold condition. If one tries to extract the carrier mobility from the slope of the curve at the inflection point by simply dividing by the oxide capacitance, an effective mobility p,ff = 318 cm2/V . s is found, while the actual mobility value at that point is about pn = 380 cm2/V s. This nearly-linear turn-on characteristic allows an easy estimate of the achievable device performance, as we shall see in Section VIII.

VI. SATURATION OF THE DRIFT VELOCITY The gate delay in n-MOS circuits is basically determined by

the depletion-load charging current which, in turn, equals the enhancement device current at the circuit logic threshold. In our room-temperature FET design, the electron drift velocity is not saturated at the circuit logic threshold (assumed equal to VDD/2) while it happens to be so at VDs = Vcs = 1 V. For the liquid-nitrogen operating FET, instead, saturation of the drift velocity occurs even at the logic threshold, so that different projections are to be made when investigating the effect of scaling.

If the device current is limited by the saturation of the drift velocity rather than channel pinchoff, we may refer to the expression [ 2 1 ]

where k, is a slowly-varying function of the ratio ( V G S - VT)/

BACCARANI et al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 459

LE,, E , being the critical field for velocity saturation. By neglecting the weak dependence of k, and uMt upon X/K, the device current turns out to vary as 1 / ~ and the gate delay scales by l / h , independent of K . This is indeed the case at liquid-nitrogen temperature, where increasing the electric field by a nonproportional voltage scaling does not produce any appreciable speed advantage and only increases the power/ circuit. At room temperature, instead, a considerable speed gain can be obtained for n-MOS circuits by choosing K <h, until saturation of the drift velocity occurs at logic threshold.

VII. EFFECT OF THE SOURCE-DRAIN PARASITIC RESISTANCES.

The increasing importance of the parasitic source-drain resistances as the FET physical dimensions are progressively shrunk, was pointed out by Chatterjee et aZ. [I91 and by El- Mansy [20] , who investigated the resulting reduction in gain factor at the largest operating voltage. For n-MOS circuits, however, it is the current at the logic threshold that mostly matters, for the gate delay is dominated by the rise time which, in turn, depends upon the depletion-load current. The effect of the parasitic resistance is two-fold: first, it reduces the enhancement-device current at the logic threshold, thus re- quiring a smaller depletion-load charging current; next it raises the low logic level, thus impairing the noise-immunity margins. As far as the former effect is concerned, the current at VGS = VDS = VDD/2, assuming VT = V D D / 4 , turns out to be

few-hundreds C? pm is tolerable at the 1/4 micrometer channel level.

The source resistance results from the combined effect of a contact resistance [33], a geometrical resistance related to the shape factor of the source region, and a spreading resistance due to the crowding of the current-flow lines in the vicinity of the channel [34]. The contact resistance has been investigated by Scott et aZ. [30] using a transmission-line equivalent circuit model for a variety of geometries. It should be stressed, however, that the contact resistance is a technological problem rather than a fundamental one, and that improvements can be expected in the future as the study of contact metallurgy pro- gresses. So far, a resistance of 15 C? on a square micrometer contact, using A1-Ti has been reported [32] . Such a value is very encouraging, for it is one order of magnitude below the estimated limits for performance degradation given above. The geometrical and spreading resistances are certainly of a more fundamental nature than the contact resistance, since the conductivity of heavily-doped silicon is a material property, and a major breakthrough in this area cannot be expected in the near future. The geometrical resistance can be kept to a minimum value by using self-aligned silicided junctions with short and relatively conductive .source/drain extensions.

The spreading resistance effect was investigated by a simpli- fied two-wire model [36], using a Schwartz-Christoffel con- formal transformation. In reasonably general conditions the following result was found

where n, = 1 + C,/C,,, C, is the depletion capacitance, and R, is the source resistance. In order to limit the current degradation to less than 5 percent in our design, the technology must provide a source resistance such that WRs < 228 SZ * pm. The voltage drop AVL on the source drain resistances (Rs t RD) at the low logic level is

AVL = (Rs + R D ) IDLT ( 10)

and turns out to be 10 mV, assuming R s = R D and WRs = 228 i2 . pm, as before. Such a value is certainly compatible with the available noise margins; it is quite clear, however, that a resistance value of the order of 1 ki2 . pm would signif- icantly impair both noise margins and gate delay.

At liquid-nitrogen temperature, the current is limited by velocity saturation; its value at the logic threshold is

and a 5-percent reduction occurs for WRs = 145 C? - pm, assuming k , = 0.4, and usat = lo7 cm/s.

Due to the higher current at the logic threshold, the liquid- nitrogen design is thus more severely affected by the parasitic source resistance, and poses more demanding requirements on its upper limit. The low logic level VL varies according to (1 o), and again the increased current leads to a more pronounced variation of VL. From the above considerations, however, it can be generally stated that a parasitic source resistance of a

Rspr = - In (0.75xj/tin,) 2 R X'

7 1 w where R, represents the sheet resistance of the source region, and xi the junction depth. Equation (12) must be added to the geometrical resistance. This resistance wa.s evaluated for the two limiting cases of xi = 0.14 where R, = 50 f2 and 0.07 pm where R, = 500 SZ. The resistivity for these two cases was determined by process simulation and experience for a given hot processing cycle. In these structures the srnaller ratio xi/tinv relative to the latter case is more than counterbalanced by the larger resistivity, so that the total spreading resistance turns out to be approximately 90 f2-w or four times larger than in the former case. From the above considerations, it appears that the lightly-doped source-drain extensions must be carefully designed, trading off parasitic source resistance and short-channel effect.

VIII. DISCUSSION AND CONCLUSIONS.

By taking into account all the physical limitations discussed so far, it appears that scaling down to a 4 micrometer channel length still leads to a considerable speed advantage, compared to larger device geometries. The achievable gate delay versus power is reported in Fig. 9 and compared with LATV [9] results, assuming for both cases a fan out of 3 and properly scaled capacitance loads. As it appears from the figure, a gate delay of 300 ps is possible at a power/circ:uit of 25 pW/gate. Increasing the power/gate to 60 pW would lead to a gate delay of 200 ps. These projections contradict previous results by El-Mansy [20] and by Shichijo [37] who predicted an opti-

460 IEEE TRtlNSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 4, APRIL 1984

10-5 1 @-' 10-3

POWERjClRCUlT (W)

Fig. 9. Gate delay against power/circuit at 75°C for the LATV technology and the proposed QMDT. The calculation assumes a f.0. = 3 and properly scaled load capacitance.

mum device performance at 1- and 0.5-pm channel length, respectively. The reason for the above discrepancies is tllat different assumptions were made by these authors, leading to entirely different results. El-Mansy considers a constant-vcllt- age scaling down to the quarter micrometer channel leng :h, and assumes a constant inversion-layer thickness of 10 nm, regardless of the value of the normal field. As shown in S w tion IV, however, such an assumption is not justified and leads to a pessimistic estimate of the inversion-layer capacitance effect. Shichijo, instead, considers several kind of scaling schemes, and investigates the impact on the gain factor and t.le saturation current of the various limitations discussed so filr. In doing so, however, he assumes a sheet resistance varyi::tg inversely with the 5th power of junction depth and lets tlle junction depth proportionally scale like all other physical tLi- mensions. Therefore, the parasitic source-drain resistantx turns out to be the primary cause of performance degradatio 11. Two orders of objections can be raised about the above pr3- cedure: first, if the sheet resistance of an implanted layer is effectively increasing with the 5th power of l / x i , it is totally unreasonable to let xi proportionally scale with the devic:e physical dimensions. On the other hand, it is well known that the influence of junction depth on drain-induced barrier lowering is weak [38], and punchthrough can be prevented by #a suitable channel implant. Consequently, a better tradeoff calls for a nonproportional scaling of the junction depth, to the advantage of the parasitic source-drain resistance. Next, a shal- lower junction can be obtained in several ways: reducing the irtl- planation dose for a given processing cycle is the simplest, but a viable alternative is to reduce the annealing temperature and the implant energy. If such a strategy is pursued, a weaker shect resistance variation against junction depth can be obtained.

Fig. 10 shows a similar comparison at liquid-nitrogen terr - perature. The smaller voltage used in this design considerabti reduces the power dissipation so that, for a given power/circuil the performance improvement over that of the LATV technology is even more pronounced. A gate delay of 100 ps can bl: achieved at a power/circuit of 50 pW.

Recently, 0.3-pm channel FET's have been manufacturetl

p, ;; , , , , , , , , , , , I '. ....., 1o-'Q ...... *... ........ .. .. ..............._

1 Q i 10.' 10-3

POWER/CIRCUIT (W)

Fig. 10. Gate delay against power/circuit at liquid-nitrogen temperature for the LATV technology and the proposed QMDT. The calculation assumes a f.0. = 3 and properly scaled load capacitances.

[39] using X-ray lithographic techniques and maintaining the vertical profiles typical of the I-pm technology. These devices have demonstrated an excellent speed performance, reaching a gate delay of 30 ps in an unloaded ring oscillator. The ques- tion is therefore in order: is the effort of reducing all the vertical dimensions (including oxide thickness) worthwhile, if the same performance can be obtained with somewhat more re- laxed conditions? In our opinion, the basic limitation of these devices is the large threshold sensitivity to drain voltage [40], which makes the achievable voltage gain fairly small, i.e., 2-3 only, with a negative effect on noise immunity margins. Such an effect can be alleviated by increasing the substrate doping, but then a more severe threshold sensitivity on backgate bias would result. Also, the relatively small gate capacitance (and transconductance) makes them more susceptible to the influence of interconnect capacitances, unless unreasonably large aspect ratios or higher voltages are used, with an accordingly increased power dissipation. In our proposed design, instead, the proper scaling of the horizontal and vertical device dimensions allows us to keep constant the drain-induced barrier lowering factor 9, so that the available voltage gain remains constant, and no noise-immunity margin degradation is expected. Besides, so long as the interconnect capacitances scale by the proper factor, no increased susceptibility to their influence is expected. From the standpoint of device manu- facturability, the proposed design does not require major modifications of the MOS technology as it is today, but rather an evolution toward thinner gate oxides and proportionally reduced fabrication tolerances.

Although the primary goal of this paper was that of demon- strating the feasibility of a quarter-micrometer n-channel FET for logic applications, most of the above considerations apply to p-channel devices as well. Due to the smaller hole mobility, and to the larger sheet resistance of p+ shallow junctions, however, quantitatively different results are obtained in this case, leading to somewhat modified design tradeoffs. Also considerations related to the effect of the parasitic source resistance on the gate delay of CMOS circuits should be revised to account for the specific switching mechanisms of CMOS gates. In spite

BACCARANI e t al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 46 1

of the more severe limitations of p-channel FET’s, however, characteristics for high-perf,ormance logic applications,” IEEE J. the inherently low power dissipation of CMOS circuits makes Solid-St. Circuits, vol. SC-14, pp. 247-255, Apr. 1979. them attractive candidates for VLSI applications.

[ 111 H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator) semiconductor transistors,”

supply of 1 v would be certainly beneficial from the perfor- [ 121 Y . Hayashi, “Static characteristics of extremely thin gate oxide

mance point of view, because it would allow to exploit the [13] F. F. Fang and A. B. Fowler, “Transport properties of electrons carrier saturated velocity at the circuit logic threshold, and in inverted silicon surfaces,” Phys. Rev., vol. 169, pp. 619-63 1, even take advantage Of overshoot effects [371 ’ but

[ 141 A. G. Sabnis and J. T. Clemens, “Characterization of the electron will probably require major technology breakthroughs: among mobility in the inverted (100) Si surface,” in IEDM Tech. Dig., these, we mention that of developing an improved insulator pp. 18-21, Dec. 1979. material having a dielectric constant at least twice as large as [ 151 s. C. Sun and J. D. Plummer, “Electron mobility in inversion and

Further scaling down to O.l,um channel length at the constant Solid-state Electron., vol. 9, pp. 927-937, 1966.

MOS transistors,” Electron. Lett., vol. 11, pp. 618-620, 1975.

May 1968.

. .

silicon dioxide’s, so that its thickness need not be scaled down to limits incompatible with reproducibility and reliability, and and the tunneling of electrons across the insulator can be kept to an insignificant level. Also, an improved gate material with a high conductivity and a more suitable work-function [29] for the required threshold voltage would be desirable. Alterna- tively, new device structures with more contained short-chan- ne1 effect should be devised, so that scaling the channel length would be compatible with the vertical profiles typical of larger devices. In any case, it is anticipated that power density and related heat removal problems, along with increased current .

accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1497-1508, Aug. 1980.

161 F. F. Fang and A. B. Fowler, “Hot electron effects and saturation velocitiesin silicon inversion layers,” J: Appl . Phys., vol. 41, pp. 1825-1831, Mar. 1970.

171 R. W. Coen. and R. S. Muller, “Velocity o$ surface carriers in inversion layers in silicon,” Solid-state Electron., vol. 23, pp. 35- 40, 1980.

181 J. A. Cooper and D. F. Nelson, “Measurement of the high-field drift velocity of electrons in inversion layers in silicon,” IEEE Electron Device Lett., vol. EDL-2, July 1981.

191 P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The impact of scaling laws on the choice of n-channel or p-chan- ne1 for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, DU. 220-223. Oct. 1980.

density within the interconnect wires, will be the major problems to be carefully considered, and will ultimately establish whether the goal of a 0.1 -pm FET is worth the effort.

ACKNOWLEDGMENT The authors are grateful to C. J. Han and R. P. Havreluk for

their help in the electrical characterization. The personnel of the Silicon Fabrication group at the T. J. Watson Research Center is also acknowledged for fabrication of the hardware used in this paper.

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[4 ] R. W. Keyes, “Physical limits in digital electronics,” Proc. IEEE, vol. 63, pp. 740-767, May 1975.

[5] B. Hoefflinger, H. Sibbert, and G. Zimmer, “Model and performance o f hot-electron MOS transistors for VLSI,” IEEE Trans. Electron Devices, vol. ED-26, pp. 513-520, Apr. 1979.

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[7] R. H. Dennard, F. H. Gaensslen, L. Kuhn, and H. N. Yu, “Design of micron MOS switching devices,” presented IEEE Int. Electron Device Meet., Washington, DC, Dec. 1972.

[SI R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bas- sous, and A. Le Blanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol.

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SC-9, pp. 556-268, Oct. 1974.. 191 H. N. Yu, A. Riesman. C. M. Osburn. and D. L. Critchlow, “1-um . .

MOSFET VLSI technology: Part l l A n overview,’’ IEEE Truns. Electron Devices, vol. ED-26, pp. 318-324, Apr. 1979.

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[22] C. M. Osburn and E. Basspus, “Improved dielectric reliability of SiOz films with polycrystalline silicon electrodes,” J: Electro- chem. Soc., vol. 122, pp. 89-92, Jan. 1972.

[23] T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Osburn, S. E. Shuster, and H. N. Yu, “1-pm MOSFET VLSI technology: Part IV-Hot-electron design constraints,” IEEE Trans. Electron De- vices, vol. ED-26, pp. 346-353, Apr. 1979.

[24] C. M. Osburn, M. Y. Tsai, S. Roberts, C. J. Lucchese, and C. Y. Ting, “High conductivity diffusions and gate regions using self- aligned silicide technology,” presented at Electrochem. SOC. 1st Int. Symp. on VLSI (Detroit, MI), 1982.

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[32] C. G. Sodini, T. W. Ekstedtd, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MIS transistors,” in Device Res. Con8 Proc., June 1980.

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pp. 94-95, Sept. 1981; also IEEE Trans. Electron Devices, vol.

[34] P. Antognetti, C. Lombardi, and D. Antoniadis, “Use of proc.ess and 2-D simulation in the study of doping profile influence on S/D resistance in short-channel MOSFET’s,” presented at IEEE Int. Electron Device Meet., Washington, DC, Dec. 1981.

[35] C. Y . Ting and B. L. Crowder, “Electrical properties of AlliTi contact metallurgy for VLSI applications,” J. Electrochem. Sot., to be published.

[36] G. Baccarani and G. A. Sai Halasz, “Spreading resistance in MI IS- FET’s,” IEEE Electron Device Lett., vol. EDL4 , pp. 27-28, Ft:b. 1983.

(371 H. Shichijo, “A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI,” in IEDM Tech.

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[40] W. Fichtner, E. N. Fuls, R. L. Johnston, T. T. Sheng, and R. K. Watts, “Experimental and theoretical characterization of submicron MOSFET’s,” in IEDM Tech. Dig., pp. 24-27, Dec. 1980.

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Recombination Lifetime Using the Pulsed MOS Capacitor

DIETER K. SCHRODER, SENIOR MEMBER, IEEE, JAMIS D. WHITFIELD, AND CHARLES J..VARKER, MEMBER, IEEE

Abstract-The pulsed MOS capacitor is routinely used to measure h e generation lifetime. A new technique is described here in which h e same device is used to obtain the recombination lifetime. The measurement technique is identical to the commonly used pulsed C-t met1 od except that the device is operated at an elevated temperature of ’; Q- 100°C, where quasi-neutral current originating below the space-chaLrge region dominates over space-charge region currents. The new techniq de, coupled with established techniques, makes possible the simultaneous determination of T~ and 7,.

T INTRODUCTION

HE CARRIER lifetime is an important parameter in the operation of many semiconductor devices. For example,

the switching time of bipolar devices, the leakage current of F .=n junction diodes and charge-coupled devices, and the refresh time of dynamic RAM’S all depend on the lifetime. Becatse the lifetime depends directly on foreign impurities and crys :a1 defects, it is also frequently used as a process control measu.e.

Among the many lifetime measurement techniques, the pulsed MOS capacitor has found wide acceptance as a method

Manuscript received June 3, 1983; revised October 31, 1983. The Arizona State University portion of this work was partially supported by the National Science Foundation under Grant ECS-82-12336.

D. K. Schroder is with Arizona State University, Tempe, AZ 85287 J. D. Whitfield and C. J. Varker are with Motorola, Inc., Product

Development Laboratory, SRDL, Phoenix, AZ 85008.

to measure the generation lifetime rg since its introduction in 1966 [ l] . A number of refinements have been added [2] - [ 5 ] , but the extracted information is still generally T ~ . The technique is useful because an MOS capacitor is usually in- cluded in wafer test patterns. The generation lifetime can be used to characterize the generation rate of reverse biased space- charge regions for p-n junction diodes and capacitors and therefore provides information on the charge storage properties of DRAM’S and CCD’s. It has the additional advantage that it samples a well-defined volume of the material, which is determined by the gate area and space-charge region (scr) width, the latter being controlled by the applied voltage and therefore under the operator’s control.

Recombination processes are characterized by the recombination lifetime r, which is generally different from rg [6] . The generation lifetime, determined by thermal emission processes, is very sensitive to the energy level of the dominant impurity or defect, while recombination is relatively insensitive to it. r, is usually measured on diode structures using the reverse recovery or open circuit voltage decay methods or on bulk materials using optical methods like photoconductive decay or surface photovoltage. The volume sampled by recombination lifetime measurement techniques is not under the experimenter’s control because one of the dimensions in this volume is the minority-carrier diffusion length, and this is a material property.

001 8-9383/84/0400~0462$01 .OO 0 1984 IEEE

generalized scaling theory and its application micrometer

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