getting started with the xilinx foundation f2

8/22/2019 Getting Started With the XILINX Foundation F2

1/77

vsdt_Lab_Tute_02

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USERMANUAL

1

ContentsDesign Flow OverviewTypes of Devices: FPGA and CPLDProject Manager

Starting a new project: Schematic Entrya. Open a new projectb. Schematic entryi. Placing symbolsii. Adding I/O Buffers, Pads or I/O terminalsiii. Drawing linesiv. Adding pin locationsv. Adding name, title and datevi. Netlist and integrity testvii. Saving schematicviii. Adding the schematic to projectEntering a design with ABELEntering a design with VHDL

Simulating a designa. Functional simulationb. Timing simulationMacros and Hierarchical Schematicsa. Macro from a schematicb. Macro with ABEL

o c. Macro with VHDLd. Top level schematicDraw busesBus TapsState EditorDesign implementationUser constraint file: Constraint Editor

Configuring the devicea. Using the Xilinx Demoboardb. Using the XC40 boardFPGAEEPROMc. Using the X95 boardMost common mistakesBoard descriptions:FPGA DemoboardXS40XS95

Pin outs:

XC4000 - 84 pinsXC9500

The Xilinx foundation (TM) CAE system is a development tool that consists of an integrated set ofprograms to create, simulate and implement digital designs in a FPGA or CPLD target device. All thetools use a graphical user interface (GUI) that allows all programs to be executed from toolbars,menus or icons. On-line help is available from most windows.

This write-up is intended to get you started with the Foundation tools. It gives a quick overview of howto create a design, simulate it and download it into a FPGA or CPLD. For more detailed informationplease consult the on-line XILINX documentation and tutorials. The Foundation 2.1i User Guide isavailable on line.


2/77

vsdt_Lab_Tute_02


2

1.1 Design Flow Overview

The design flow for CPLDs or FPGAs consists of three main steps as is illustrated in Figure 1. Thedesign process can be broken down in (a) Design entry, (b) design implementation and (c) designverification.

Designs can be entered in two basic modes: Schematicand HDL (Hardware Description Language)mode. A hardware description language allows you to describe the behaviour of a system rather thanas individual gates. There are several popular hardware description languages such as VHDL, Verilogand ABEL.

The schemat ic f low mod eallows you to create a design that consists of either a top-level schematic

or top-level ABEL file. It can contain underlying schematic diagrams, state machine macros,instantiated HDL (ABEL, VHDL or Verilog) macros, LogiBLOX, CORE Generator modules.

The HDL f low m odecan contain a VHDL (or Verilog) or a schematic top-level design with underlyingVHDL, Verilog, schematic modules, as well as LogiBLOX, CORE Generator and Finite State Machinemodules. Notice that for a top level ABEL-based design, you will need to use the Schematic mode. Inorder to create VHDL or Verilog designs you will need the Synopsis FPGA Express package whichcomes with the Foundation Base Express and Foundation Express tools. Figures 2 and 3 show amore detailed view of the different steps involved in the creation of a design in the schematic flowmode and HDL flow mode, respectively. Notice the extra Synthesis step that is required in case of aHDL flow design. Also, the target device and the top-level module is specified during the synthesisstep in the HDL flow mode.

The implementation tools fit the entered design into the target device architecture. The tools compile adesign file into a configuration file that is optimized in terms of use of logic gates and interconnectionsfor the targeted device. Downloading of the bitstream can be done easily from a PC into a FPGA(using the Xilinx demoboard, the XS40 or XSV boards) or into a CPLD (on the XS95 board). Bothdevices can also be programmed in-the-system (ISP) by connecting a JTAG or XChecker cable to thedevice's programming pins.

Design verification includes functional simulation, in-circuit testing, and timing simulation. Functionalsimulation can be done after the design entry to verify the proper operation of the circuit. However,functional simulation does not provide timing information, such as delays, race condition, set-up andhold-time violations. This information is obtained from the static timing simulator and is done after thedesign has been compiled for the target device. Figure 2 shows the design flow for a Schematic Flowproject.


3/77

vsdt_Lab_Tute_02


3

Figure 3 shows the design flow for a HDL Flow project. The top-level module and the target devicearen't specified until the Synthesis step as shown in the figure below.


4/77

vsdt_Lab_Tute_02


4

Figure 3: Overview of the design and implementation sequence of a HDL Flow project. [2].

1.2 Types of Devices: FPGA and CPLD

There are two types of programmable logic devices. One is called a field programmable gate array(FPGA) and the other a complex logic device (CPLD). The CPLD XC9500 device has a PAL-likearchitecture and is non-volatile. It gives relatively good performance (up to 250 MHz) and is wellsuited for combinational logic circuits and control logic of medium complexity (up to about 10,000 logicgates). The FPGA device (ex. XC4000 series) has an array-like architecture and is volatile (SRAMbased). It makes use of lookup tables (stored in the SRAM memory) to implement logic functions. It isgood to realize complex logic functions that contain both combinational and sequential circuits. Itscapacity is usually limited by the number of input/output pins and not by its complexity. FPGAs cancurrently implement up to 1 million logic gates and operate up to 150 MHz. The XC4000XL andXC9500XL are 3.3V devices with a 3.3V Vcc but with 5V tolerant I/Os.

The devices come in a variety of packages. The ones used on the FPGA demoboard or the XS40 andXS95 boards are packaged in an 84 pin PLCC and have the following part names: XC4010EPC84,

XC4005XLPC84 and XC95108PC84 . To find out which device you will be using, check the boardyou have available in the lab. Detailed information on these devices is given in the Xilinx


5/77

vsdt_Lab_Tute_02


5

Programmable Logic Data Book. The pin outs of the XC4000 and the XC9500 84-pin devices areavailable on the tutorial webpage.

1.3 Project Manager

When you launch the Foundation tools, the Project Manager window will open as is shown in Figure 4for a Schematic Flow project. The Project Manager gives you access to all the tools that are neededto design, simulate and implement a project. From the Manager you can also create a new project,open an existing project or delete projects.

You can launch the Xilinx Project Manager by going to the START/PROGRAMS/Xilinx FoundationSeries 2.1i menu. You can also click on the Project Manager icon at the bottom toolbar.

When you create a new project e.g. MyProj, the Foundation tools will create the following files: aproject configuration file (PDF), called Project Description File (myproj.pdf), and three library files, theproject library file (myproj), the simulation library file (simprims) and the device library (xc4000x) files.The libraries are shown in the left window pane (called the Hierarchy browser) of the Project Manager.

A project must always have one or more top level design files. In case the top-level cell is a

schematic, the file will be shown in the hierarchy browser with an extension .sch (e.g. myproj.sch) ascan be seen in Figure 4 above. The foundation tools will create additional folders and files duringdifferent stages of the project design/implementation.
http://www.xilinx.com/partinfo/databook.htmhttp://www.xilinx.com/partinfo/databook.htmhttp://www.seas.upenn.edu:8080/~ee201/boards/xc4000pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc4000pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc9500pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc9500pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc9500pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc4000pins.htmlhttp://www.xilinx.com/partinfo/databook.htm


6/77

vsdt_Lab_Tute_02


6

The right window pane in the Project Manager has several tabs. The Flow tab graphically shows thedifferent steps involved in the design of a project as was shown schematically in Figure 2. You canclick on the icons to access a particular tool as will be shown later on.

The bottom window pane gives status and error or warning messages. The different features of theProject Manager will become clear later on when doing the tutorial exercises. For more information,go to the HELP -> PROJECT MANAGER HELP TOPICS menu.

In case a library is missing (e.g. the device library), the tools will give you a warning. This will alsoshow up when you try to open the schematic, as symbols will be missing or blanked out. If thathappens, you can add the library to the project. In the Project Manager, go to FILE ->PROJECTLIBRARIES. This will open the Project Libraries window, shown in Figure 5. The left side panel showsthe "Attached Libraries" and the right side windows the Project Libraries, such as myproj, xc4000xand simprims. If any of these are missing, you can add them from the list in the left side window.Scroll until you find the right library (e.g. XC4000X) and click the ADD button.

If the required library does not show up in the left side window, you need to attach the library first.Click the Lib Manager button to open the Library Manager. Go to the LIBRARY -> ATTACH menu toopen the Attach Library. You can now select the required library and click the OK button. Thesystems' libraries are usually found in the c:\fndtn\active\syslib directory. The newly selected librarywill appear in Attached Library list. You can now add the library to your project. Notice that librarieswhich are already attached will not be displayed in the Libraries list.

1.4 Creating a new project: Schematic Entry

The design entry is the first step in the process of creating a new design. Design can be enteredeither as a schematic or as a text-based entry (ABEL, VHDL or Verilog). An overview of the overall

process of creating a design in the Schematic Flow mode is shown in Figure 2 of the introductionsection.

In this tutorial you will learn how to create a new project and enter a design using the SchematicEditor in the Schematic Flow mode. In later sections you will learn how to create more complicatedprojects using macros and hierarchies. For now let us assume you want to build a really simple circuit,as shown in Figure 1, using the Schematic Editor. This circuit will be used in a car to generate awarning signal when "The Ignition key is in the lock AND the door is open OR the seatbelt is notused". The corresponding Boolean expression is:

F = IGNITION.(DOOR' + SBELT')
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Figure%202http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Figure%202


7/77

vsdt_Lab_Tute_02


7

1.4.1 . Open a new project

To start the Xilinx Foundation tools (click on the icon on the desktop or go to the window'sSTART menu -> Programs -> Xilinx Foundation Series F2.1i-> Project Manager). First, a smallwindow will pop up asking to open an existing project or to create a new one. Select "New Project".This will bring up the new project window

Fill out the name of the project, the directory where you want to store the project, and theType. Let's give it the project Name: EasyProj . The project name is not case sensitive. Do

not use more than 8 characters in the project name.

Directory: Select the proper directory (folder) where you want to save your project. Use theBrowse button to change the directory.

For the type select F2.1i.

Under Flow, select Schemat ic f lowsince we will use the Schematic editor to create ourdesign. The three pulldown boxes at the bottom of the New Project window refer to the devicefamily, the part and the speed grade.

The family refers to the device family. If you are using a FPGA, select XC4000E (for theFPGA demoboard) or XC4000XL (for the XS40 board); if you are using a CPLD, selectXC9500 (for the XS95 board).


8/77

vsdt_Lab_Tute_02


8

The second box is for the part which refers to the specific target device. Check the type ofdevice you have on the board. The XS40 FPGA board will probably be populated with theXC4005XL-3PC84C; the XC95 board with a a 95108PC84 CPLD; the FPGA Demoboard witha 4010EPC84. Select the proper Part depending on the device you work with. You can

change the target device at a later time by going to the FILE -> PROJECT TYPE in theProject Manager window (Figure 3).

The speed refers to the speed specification of the device and can be found on top of thedevice following the "-" after the device name (ex. XC4010E - 3 indicates a speed 3).

The Project Manager window will open as shown inFigure 3. This window shows the design flow aswell as the associated tools.

Figure 3: Xilinx Foundation Project Manager window (Schematic Design Entry)(Screen clip from Xilinx (TM) Foundation software)

The project will have a .PDF extension. Other project files such as schematics, netlists, macros, etc.,will be stored in a subdirectory with the project name. A project can have only one top schematic (orHDL source file). Sub-schematics can be added to the project as macros.

For more information about the Project Manager, use the online help function by selecting HELP ->PROJECT MANAGER FOUNDATION HELP CONTENTS in the Project Manager window. To accessthe Foundation 2.1i User Guide, go to the HELP ->ONLINE DOCUMENTATION menu. Next, click onthe WEB BOOKS button and on Foundation Series 2.1i Software link.

1.4.2 b. Schematic Entry

To create the circuit of Figure 3.1 using the Schematic editor, click on the Schematic editor icon in theProject Manager window or select the TOOLS menu -> DESIGN ENTRY -> SCHEMATIC EDITOR. ASchematic Capture window will appear as in Figure 4.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.html


9/77

vsdt_Lab_Tute_02


9

Figure.4: Xilinx Foundation Schematic Capture window with blank schematic (Screenclip from Xilinx (TM) Foundation software)

i. Placing symbolsYou can add the logic symbols by clicking on the Symbol Toolbox (Symbols icon) on the toolbar onthe left. An SC Symbols Toolbox will pop up. You can scroll down the list and select AND2 or type thesymbol name at the bottom box of the list. Notice that a brief description of the selected symbolappears at the bottom. You can now place the gate with your cursor on the schematic by clicking themouse. To place another AND gate just click on the previous one and a second gate will be attachedto the cursor. Every time you click another gate of the same type will be placed in the schematic untilyou press the Escape (ESC) key.. Place two 2-input NAND gates. Next, select OR2 from the SCSymbol Toolbox and drop one OR gate. Figure 5 shows the schematic with the symbols added.


10/77

vsdt_Lab_Tute_02


10

Figure 5: Xilinx Foundation Schematic Capture window with Symbols added (Screenclip from Xilinx (TM) Foundation software).

You can mirror a symbol by pressing Ctrl+M keys or rotate it by pressing the Ctrl+L keys.

To redraw the screen press the F10 function key.

Side note: The FPGA (not the CPLD) comes with an on-chip oscillator of 8 MHz. This can be used by

placing the symbol OSC4 in the schematic (or HDL code). An internal divider makes the followingsignals available: 8MHz, 500 kHz, 16 kHz, 490 Hz and 15 Hz. The frequencies are not very welldefined and can vary between -50% and +25%.

ii. Adding I/O buffers, pads and I/O terminals

FPGAs and CPLDs have input/output blocks that act as an interface between the internal circuitry andthe pins which connect to the external world. The I/O block can be configured by the user. It consistsof input and output buffers (designated by the library symbols IBUF and OBUF), tri-state output buffer(OBUFT) and flip-flops (edge-trigger D flip flop (IFD) or a latch (ILD)).

Buffers:

Buffers are needed for input and output signals which go to a pin of your device (FPGA or CPLD).

Place the buffers on the schematic in a similar fashion as you did for the other symbols. For the inputbuffers select the IBUF symbol and for the output buffer select OBUF from the SC Symbol list. In caseyou would like to add a tri-state buffer, you can select OBUFT. Do not forget to add buffers or yourschematic will not compile later on!

Pads:

You will also need to add I/O pads to the input and output buffers. These pads represent the actualpins on the XILINX device. A pad is a physical component in the Xilinx Unified Library and is placedlike any other component (ex. AND, NAND, etc.). The names of pads are IPAD (input), OPAD (foroutput), IOPAD (bi-directional), IPAD4 and OPAD4, etc. All device pins MUST be represented withone of these I/O pads! Pads should be given a name and possibly a pin number (pin location). Thiscan be done by double clicking on the pad to bring up the Symbol Properties window (see Adding pin

locations below). Output pads are pulled-high or pulled-low through a pull-up or pulldown resistor ofabout 10 kOhm, respectively, when not in use to prevent floating outputs. During normal operation,the pull-up/down is deactivated.


11/77

vsdt_Lab_Tute_02


11

Pins

An I/O terminal (pin: ), which is available by clicking on the I/O Terminal button at the bottom of theleft-hand side toolbar or at the top of the SC Symbols window, is not a physical device and cannot be

used as an I/O pad (although, sometimes the software may treat it as an I/O pad, but there is noguarantee). I/O terminals should only be used to provide connections between levels of hierarchy inthe design. Thus they are used in macros to connect signals to the corresponding pins on the macrosymbol. However, signals that span multiple pages of a flat design do not require terminals or off-pageconnectors. To indicate device pins on the top-level schematicin a hierarchical design, one should notuse I/O terminals but pads to indicate device pins.

If the schematic is going to become a cell or macro that will be used later on in a larger schematic youneed to use I/O terminals to indicate the terminals of the device. As explained above you can add anI/O terminal (pin) by clicking on the Hierarchy Connector icon and entering the name of the terminal.For macros, you don't need to place buffers in the schematic (IBUF or OBUF) since the inputs andoutputs will not be connected to a physical pin of the FPGA or CPLD. For macros or hierarchicaldesign, see the section on "Macros and Hierarchical Schematics".

iii. Drawing lines and naming wires

To connect one gate to the other, use the Draw Wire feature. This can be done by clicking on the wiresymbol just below the Symbol Toolbox icon of the left side toolbar. All symbols must be connectedwith wires.

Nets (wires) should be user-defined for readability and documentation purposes. You can name awire by clicking on the "Name Wire Icon" just below "bus" icon on the vertical toolbar. Type in a namein the Net Name window and put the cursor over the location of the wire. Make sure you point to thewire that you want to name, otherwise the name will not be connected to anything. A shortcut tonaming nets is double clicking on the net. You can now fill out the net name between the pads andbuffers for the three inputs (DOOR, IGNITION AND SBELT) and the output (BUZZER). Net namesshould appear in blue (green names indicate that the name is not connected to a net).

iv. Adding pin locations

You can assign pin numbers to each input and output pad. If you don't do this, the compiler will assignthe pin numbers for you. There are two ways you can assign pin numbers. First, you can place the pinnumbers on the schematic using the LOC or Description property. This is done by double clicking onthe PAD symbol. In the pop-up Symbol Properties window (Figure 6), go to the Parameters sectionand enter as Parameter Name: LOC, and for the Parameter Description: P#, in which # representsthe pin number as shown in Figure 6 (the letter P is required in front of the number). Click on the ADDbutton. To display the pin location, double click on the LOC=P44 until two diamonds appear next to it.When finished click OK.

The name can be moved by double clicking on the pad until the Symbol Properties window appears.

Select LOC=P# and select MOVE. You can now move the pin location label around.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.html


12/77

vsdt_Lab_Tute_02


12

Figure 6: Symbol Properties window to assign pin locations (Screen clip from Xilinx

(TM) software window)

An alternative way is to not assign pins on the schematic, but specify the pin numbers later, beforecompiling the design. This can done by creating a User Constraint File (see constraint editorsection).The advantage of the latter method is that the schematic is more generic and you can easily changepins without having to modify the schematic (or the HDL code).

When using the Demoboard, the XS40, or the XS95 boards, certain pins have been pre-assigned andsome are connected to LEDs and switches for ease of testing (consult the descriptions of theDemoboard,XS40or the XS95boards). Assign the pin numbers so that you can make use of thesedevices. The pinouts of the 84 pin PLCC XC4000and XC9500devices are available on the web. Incase you are using the XS40 board, you can connect the inputs "DOOR", "IGNITION" and "SBELT" tothe pins of the parallel port connector (e.g. pins 44, 45 and 46, respectively - see Table 1 of the XS40board description) and the output to one of the LED segments (e.g. segment "a" or pin 19). Figure 7

shows the finished schematic.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.html#user%20constraint%20fileshttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.html#user%20constraint%20fileshttp://www.seas.upenn.edu:8080/~ee201/boards/demoboard.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/demoboard.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc40board.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc40board.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc9500board.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc9500board.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc4000pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc4000pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/.boards/xc9500pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/.boards/xc9500pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/.boards/xc9500pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc4000pins.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc9500board.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/xc40board.htmlhttp://www.seas.upenn.edu:8080/~ee201/boards/demoboard.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.html#user%20constraint%20files


13/77

vsdt_Lab_Tute_02


13

Figure 7: Schematic of the finished circuit including pin numbers locations (Screenclip from Xilinx (TM) Foundation software.

v. Add your name, title of project and date

It is good practice to label the schematics clearly. There is a standard way of doing so. Go to thebottom of the page and fill out the small rectangle. If the box has a predefined name, you can changethis by going to the FILE->TABLE SETUP. You can now change the address, Name, Description,Date, etc.

vi. Netlist and Integrity Test

You will need to generate a netlist which is in a format that is readable by the compiler. This is doneby going to the OPTIONS menu-> CREATE NETLIST. When finished, it is always a good idea tocheck that the schematic has no electrical design rule errors. This is done from the OPTIONS menu -> INTEGRITY TEST. You can now also generate a EDIF netlist by going to the OPTIONS menu ->EXPORT NETLIST. If you don't do this, do not worry - the system will prompt you later to do so.

vii. Save your schematic

Go to the FILE menu -> SAVE or click the floppy disk icon on the top toolbar. Give your schematic aname with the extension .SCH (ex. EASYPROJ.sch). When finished with the schematic, exit theSchematic capture program which will bring you back to the Foundation Program Manager window

(Figure 3.3).

viii. Adding the schematic to the project

If the created schematic is not listed in the Project Manager window under the Project you created(ex. easyproj1.sch), you have to go to the DOCUMENT menu -> ADD in the Project Manager window.

A window with a list of f iles will appear. To show only the type "Schematic" display *.SCH in the dialogwindow. Then select the schematic (EASYPROJ.sch) you would like to add to your project (EasyProj).

ix. Copy your project to another disk.

If you want to save your project on another disk (e.g. floppy disk) you can to do this from within Xilinx.Go to the Project Manager. Open the FILE->COPY PROJECT menu. Give the name of the Drive and

directory to which you would like to copy your project.


14/77

vsdt_Lab_Tute_02


14

You can also archive your project as a ZIP file. In the Project Manager, go to FILE -> ARCHIVEPROJECT. This will open the Archive Project Wizard window. The zip file is convenient when youneed to email your project or when the file is too large to store on a disk.

The next step is to simulateorcompile (implement)the circuit.

Formore informat ion, go to the HELP -> SCHEMATIC EDITOR HELP CONTENTS menu in theSchematic Editor window. You can also read the "Design Methodologies - Schematic Flow" in theFoundation Series 2.1i User Guide. Check also the "most common mistakes"section.

1.5 Design Implementation

The implementation tools will translate the netlist (schematic, HDL), place and route (or fit for CPLDs)the design in the target device and generate a bitstream that can be downloaded into the device. Theimplementation is typically done, after the design has been verified by the functional simulator, asshown in Figure 1 below. Implemenation needs to be done prior to doing a timing simulation, sincetiming information depends on a specific target device and the way the design has been placed and

routed on the device (See Figures 2and 3 of the introduction).

Figure 1: Overview of the Design Flow.

a. Implementation

Go back to the Project Flowchart in the Project Manager window. If this is the first time you

implement the design, click on the Implementation icon in the flow section of the Project Managerwindow. This will open the Implement Design window, shown in Fig. 2 below. If you haveimplemented earlier an earlier version and would like to create a new revision or new version, go tothe PROJECT -> CREATE REVISION or CREATE VERSION menu. This will open the CreateRevision or Version window, similar to the Implement Design window shown in Fig. 2. The ImplementDesign Window lets you specify the target device and speed grade. In case you get a messagesaying "Schematic Netlist is older than the Schematic. Update netlist from Schematic Editor?", clickthe YES button. The target device is already specified as 4005XLPC84 as this is the one we selectedwhen the project was created. If needed, you can change the target device. The Revision andVersion name is automatically filled in with rev1 and ver1. You can change the name if you want to.The implementation options allow you to specify how the design is optimized, mapped, placed, routedand configured. In general, the default settings should be good enough for introductory lab exercises.When you click on the SET button, the Settings dialog box will open. This allows you to specify control

files such as a specific Constraint, Guide or Floorplan files. The default settings are usually fine. Incase you are using the HDL Flow mode for your project, the Implementation Settings window willopen. Click on the RUN button to start the implementation process.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sim2.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sim2.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.htmlhttp://toolbox.xilinx.com/docsan/2_1i/http://toolbox.xilinx.com/docsan/2_1i/http://www.seas.upenn.edu:8080/~ee201/foundation/commistakes.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/commistakes.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Figure%202http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Figure%202http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Project%20Managerhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Project%20Managerhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Project%20Managerhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_intro.html#Figure%202http://www.seas.upenn.edu:8080/~ee201/foundation/commistakes.htmlhttp://toolbox.xilinx.com/docsan/2_1i/http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sim2.html


15/77

vsdt_Lab_Tute_02


15

Figure 2: Implement Design Window (Screen clip from Xilinx (TM) Foundation software)

Note: If you need to switch to another device family, you can do so by going to the

FILE -> DEVICE TYPE menu in the Project Manager window. The change ProjectType window will pop up. Under Flow, select the new device type (ex. XC9500 incase want to switch to a CPLD device).

When you click on the RUN button in the Implement Design window, the Flow Engine window willopen and display the progress through the different steps in the implementation process. Figure 3shows the Flow Engine window in case the target device is a FPGA.


16/77

vsdt_Lab_Tute_02


16

Figure 3: Flow Engine window for a FPGA target device (Screen clip from Xilinx (TM) Foundationsoftware)

The first step is the translation of the design file (EDIF file) in a proper format (NGD file - Native

Generic Database). This implies that the representation of your schematic (gates) or HDL file istranslated into FPGA elements corresponding to the target device (look-up tables, etc). The next stepis mapping of the design to the specific target device. The mapper optimizes the logic, trims or"optimizes out" (removes) logic and maps the design in the targetted FPGA device. Next is thePlace&Route operation, followed by the generation of the timing information for use by the timingsimulator. The final step is the generation of the Bitstream which is a configuration file that can beused to program the FPGA. In case you want to program a PROM, you will run the bitstream throughthe PROM File Formatter. You can follow the status of each step in the Flow Engine window.

When the implementation is complete a small window will pop up informing you that the Flow Engineis Completed Successfully. Click OK. In case errors occurred you should refer to ImplementationLog file, in the Project Manager (click on the Reports tap on top of the right window pane), as shownin Figure 4 below. In the hierarchy browser (left pane window) of the Project Manager, click on the

Versions tab and you will see the status of the implementation.

Figure 4: Project Manager showing the status of the implemented version and the reports. (Screenclip from Xilinx (TM) Foundation software)

In case you are targeting the design for a CPLD device, the Flow Engine looks like the one in Figure5. The bitstream generates a .jed file..


17/77

vsdt_Lab_Tute_02


17

Figure 5: Flow Engine window for a CPLD device. (Screen clip from Xilinx (TM) Foundation software)

For a CPLD the .jed (bitstream) needs to be first tranlsated into a format that is compatible with theCPLD device before it can be downloaded. This is done as follows.

In the Poject Manager, click on the Programming Icon in the Flow section, or go to TOOLS ->DEVICE PROGRAMMING -> JTAG PROGRAMMER. The JTAG Programmer window willopen, shown in Fig. 6.


18/77

vsdt_Lab_Tute_02


18

Figure 6: JTAG Programmer Window (Screen clip from Xilinx (TM) Foundation software)

In the JTAG Programmer window, go to OUTPUT -> CREATE SVF FILE.

In the SVF Options window, select the " Through Test-Logic-Reset" radio button and click OK.

Save the my_proj.svf file. You can save it in any directory, but the easiest is to save it in thedirectory corresponding to the revision and version of the current project. You will need toremember later where you saved the .svf file for programming the CPLD.

Next, go to OPERATIONS -> PROGRAM in the JTAG Programmer window. Select "EraseBefore Programming" and click the OK button. When the operation is successfully you will getthe following message "All operations were completed successfully". Click OK. button

Close the JTAG Programmer window. The .svf file can be used to configure the CPLD.

b. Viewing the Implementation Results

You can also view the reports from the Project Manager (Fig. 4). Reports are associated with eachversion. In the Project Manager, click on the Versions tab in the left-hand pane. Select the version andrevision for which you would like to see the reports. You can then click on the Report Browser icon onthe top toolbar. Or you can also click on the Reports tab in the right-hand window pane. Next, doubleclick on the Implementation Report Files. This will open the report browser window. In case you areusing a FPGA target device, you will see the Translation, Map, Place&Route, Pad reports and others.Click on the Pad report to see the assignments of the I/O pins. You will recognize the same names asthe ones you specified on the schematic (Door, Ignition, Sbelt and Buzzer). Check the pin locations.

Another interesting report is the Map report which will tell you if logic has been removed (as part of theoptimization) or added. The Place&Route report indicates how much of the device has been utilized. It

gives also a rough estimate of the average interconnection delay.


19/77

vsdt_Lab_Tute_02


19

In case you have implemented your design on a CPLD the Translation, Fitting and Post Layout Timingreports will be generated. Open the Fitting report to check the pin locations of the input and outputsignals.

c. Constraint Files:Assigning pins with the user constraint files: Constraint Editor

There are two types of constraints: (1) location and (2) timing. In general location constraints allowyou to control mapping and positioning of logic elements in the target device, such as the location ofthe pads (I/O pins). Timing constraints inform the system which paths are critical and need shortinterconnections (high speed lines) in order to ensure that your design's performance functionsproperly under worst-case conditions. You can also specify the slew rate (fast or slow) and to usepullup or pulldown resistors for the output pads. We will concentrate on the location constraints. Moreinformation can be found from the HELP -> FOUNDATION HELP CONTENTS: Entering Constraints.

Constraints can be entered in various ways. One way is to place constraints on the schematic or inthe ABEL file, as we have done with the pin location. Other ways are to use the Constraint Editor oredit the user constraint file (projectname.ucf) directly.

Constra int Edi torIf you did not assign pin numbers to the input and outputs in your schematic (or HDL code), youshould do it now, before compiling the design. If you don't assign the pins, the compiler will assignthem for you. When using the Demoboard, or the XC40 or XC95 boards you should assign the pinsyourself to make use of the on board switches and LEDs on the FPGA demoboard,or the XS40andXS95boards.

The Constraint Editor is a Graphical User Interface that you run after the translate program.Notice that you can access the Constraint Editor only after you have created a version of the projectand thus after running the tranlation once. Using the constraint editor can be a littel confusing inparticular when you have created different versions. You need to make sure that you are editing andusing the right constraint file. Follow the instructions carefully:

To open the Constraint Editor, go to TOOLS -> IMPLEMENTATION -> CONSTRAINTEDITOR in the Project Manager window. In case you have created different versions orrevision, you should first go to the Version Tab in the left window pane of the ProjectManager. Select the version you would like to work with. Then click with the right mousebutton and select "Edit Implementation Constraints". The Editor window will open. It consistsof a main window and three tab windows, called Global, Ports and Advanced. We areinterested in specifying pad locations.

Click on the Ports tab which will open the Ports window as shown in Figure 7. At the top of thewindow you will see a list of all the port names you have specified in the schematic as well asthe location (if you specified any). To change the location, or to add a location, click with theright mouse button on the Port Name. A small window will pop up that allows you to type the

(new) location as P# (note: use capital P). For our example, the pin location should beBUZZER (P19), DOOR (P44), IGNITION (P45) and SBELT (P46), in case you are using theXS40 board. Don't forget to put "P" in front of each pin number. Alternatively, you can type thepin location directly in the Location column.

When finishedentering all the pin locations, go to FILE -> SAVE. When you get a messagesaying "You must rerun the Translate Step to have your new constraint applied to the design",click OK.

For more information about each constraint, use the on-line help in each dialog box or go tothe HELP -> HELP TOPICS menu in the Constraint Editor window.
http://www.seas.upenn.edu:8080/~ee201/boards/demoboard.html#General%20Purpose%20Input%20Switches%20(SW3)http://www.seas.upenn.edu:8080/~ee201/boards/demoboard.html#General%20Purpose%20Input%20Switches%20(SW3)http://www.seas.upenn.edu:8080/~ee201/boards/XS40Board.html#Seven-segmenthttp://www.seas.upenn.edu:8080/~ee201/boards/XS40Board.html#Seven-segmenthttp://www.seas.upenn.edu:8080/~ee201/boards/XS95Board.html#Seven-segmenthttp://www.seas.upenn.edu:8080/~ee201/boards/XS95Board.html#Seven-segmenthttp://www.seas.upenn.edu:8080/~ee201/boards/XS95Board.html#Seven-segmenthttp://www.seas.upenn.edu:8080/~ee201/boards/XS40Board.html#Seven-segmenthttp://www.seas.upenn.edu:8080/~ee201/boards/demoboard.html#General%20Purpose%20Input%20Switches%20(SW3)


20/77

vsdt_Lab_Tute_02


20

Figure 7: Constraint Editor window (Screen clip from Xilinx (TM) Foundation software)

In order for the system to use the new constraint file you have to re-run the tranlateoperation. This is done by going back to the left window pane (versions tab) in the ProjectManager and selecting the same Revision and Version for which you have defined thecontraints. Place the mouse over the revision/version name and click the right mouse button.Select "Invoke Interactive Flow Engine". This will open the Flow Engine window. You mayhave to back up to make sure that you redo the translation step (in order to use the modifiedconstraint file). Start the implementation including Translate, Map, etc. When theimplementation is successful check the Pad report or Fitting report (corresponding to theversion you just implemented) to make sure the pads have been properly placed as specifiedin the new user constraint file, in case of a FPGA or CPLD, respectively.

When you create a new version or revision a window like the one in Figure 2will pop up. To makesure you are using the right user constraint file, click on the SET button. When the Settings windowopens, you can select the desired user constraint file (ucf) by using the pull-down box for the "Usecontraint file from" menu (see Figure 8). Use "custom" to browse the directory. If you do not specify aucf file, the one corresponding to the last revision will be used.
http://www.seas.upenn.edu:8080/~ee201/foundation/#Implementhttp://www.seas.upenn.edu:8080/~ee201/foundation/#Implementhttp://www.seas.upenn.edu:8080/~ee201/foundation/#Implement


21/77

vsdt_Lab_Tute_02


21

Figure 8: Setting window that allows you to specify a specific user constraint file.(Screen clip from Xilinx (TM) Foundation software)

You can also use the Constraint Editor to specify whether an output should have a Pullup or Pulldown

resistor, and have a Slow or Fast slew rate. You can specify these by clicking on the I/O ConfigurationOption box. This will add a few columns to the Ports window. You can now specify the Slew Rate andPullup/Pulldown option using the pull down menus in the corresponding colums.

Edit the User Constraint FileAn alternative way to specify constraints is to edit the user constraint file directly after you have runthe translate program once. This file has the same name as the project with a .ucf extension. Theeasiest way to edit the .ucf file is by using the HDL editor, by clicking on the HDL Editor icon in theProject Manager, or by going to TOOLS -> DESIGN ENTRY -> HDL EDITOR menu. Select "OpenExisting Document". The user constraint file is located in the xproj folder, inside the correspondingversion/revision folder. You will notice that the existing .ucf file contains a lot of comments explaininghow to create a constraint file. Right now we are interested in defining pin locations. Scroll to thebottom of the file and add the pin locations as follows.

NET "BUZZER" LOC = "P19"; # output: DOORNET "DOOR" LOC = "P44"; # inputNET "IGNITION" LOC = "P45"; # inputNET "SBELT" LOC = "P46"; # input

Be careful - the constraint file is case sensitive. Make sure you use exactly the same name in theconstraint file as the one you have defined in your schematic or in the HDL file. The "#" is used forcomments. When done, save the file. You can now re-run the implementation tools by selecting theversion in the left window pane (versions tab) of the Project Manager. Click on the version with theright mouse button and select "Invoke Interactive Flow Engine". Start the Flow Engine. When finishedsuccessful, check the Pad or Fitting report to make sure that the right pin locations have beenassigned.

d. Create Design Version and Implementation version


22/77

vsdt_Lab_Tute_02


22

If you want to create a new version or new revision, go to the Project Manager. Select PROJECT ->CREATE VERSION or CREATE REVISION. This will bring up the Create Version or the CreateRevision window. These windows look similar to the Implement window discussed earlier. You canspecify which constraint file to use by clicking on the SET button next to Control File. Use the pull

down menu to select a contraint file from a previous version/revision, as shown in Figure 8. If you donot specify a constraint file it will use the constraint file of the last revision. The versions will appear inthe left hand window pane of the Project manager, under the Version tab. Once a new version orrevision has been created you can run the implemenation program.

e. Looking at the Floor Plan

You can use the FPGA Editor to look how the device's resources have been use and placed on theFPGA. You can also use this application to place and route critical components before running theautomatic place and route tools on your design. To open the FPGA editor, go to the Project Manager,and select TOOLS -> IMPLEMENTATION -> FPGA EDITOR.

The Editor allows you to display different levels of details on the FPGA such as short wires, longwires, switch boxes, routing between components, components, etc. The level of detail that isdisplayed can be controlled by clicking icons on the top level toolbar. Figure 9 shows the FPGA editorwindow with a view of the FPGA floorplan, around the area where the logic circuit has been placed.The three blue boxes are the I/O blocks of the DOOR, IGNITION and SBELT signals, and the red oneis the logic block. The switching network and the routing of the signals to the logic block are shown aswell.

Figure 9: FPGA Editor window with view of the floorplan for the logic circuit ofFig.1(Schematic Entrysection).(Screen clip from Xilinx (TM) Foundation software)
http://www.seas.upenn.edu:8080/~ee201/foundation/#Implementhttp://www.seas.upenn.edu:8080/~ee201/foundation/#Implementhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.html#Figure%203.1http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.html#Figure%203.1http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.html#Figure%203.1http://www.seas.upenn.edu:8080/~ee201/foundation/#Implement


23/77

vsdt_Lab_Tute_02


23

To look at a particular block on the FPGA, you can zoom in by clicking on the maginifying glass on thetop toolbar. The bottom left window, labeled World shows a red dot that correspond to the signal thatyou selected in the List window on top. By moving the white rectangle and placing it on top of thedesired signal (red dot) you can zoom into the specific block in the left window, shown as a red

rectangle. You can now double click on the red block in the left window to see more details of theselected component.

For more information about the FPGA Editor, select HELP -> HELP TOPICS from the FPGA Editorwindow.

In case you are implementing your design on a CPLD, you can use the Chip Viewer to see how theresource inside the CPLD has been used. The ChipViewer tool allows you to examine inputs andoutputs, macrocell details, equations, and pin assignments. You can examine both pre-fitting andpost-fitting results. To start the tool, go to TOOLS -> IMPLEMENTATION -> CPLD CHIP VIEWER inthe Project Manager window. For additional information go to the HELP -> HELP TOPICS menu in theChip Viewer window.

References:

1. "Foundation Series 2.1i User Guide chapters on "Foundation Constraints" and "DesignImplementation", available on the Xilinx website.

2. Foundation Series online help, "Entering Contraints" (in the Project Manager go to HELP ->FOUNDATION HELP CONTENTS).

3. D. Van den Bout, "The Practical Xilinx Designers Lab Book", Prentice Hall, Upper Saddle, NJ,1998


24/77

vsdt_Lab_Tute_02


24

1.6 Entering a VHDL-based Design

An alternative way to using the Schematic or the ABEL editor is to enter a VHDL/Verilog-based design. In this section you will learn how to enter a VHDL-based design using the HDL-f low mod e. If you

are not familiar with VHDL, consult the VHDL Reference Guide (on the Xilinx web site) or a textbookon VHDL. Figure 1 shows schematically the different steps involved in the creation of a HDL-basedproject.

Figure 1: Overview of the design and implementation sequence of a HDL Flow project.

In this tutorial you will learn how to enter and synthesize a VHDL based design. Once you havesynthesized the VHDL file, the remaining steps of implementation and downloading will be identical asthe ones for the Schematic Flow mode.

i. Open a Project in the Foundation Project Manager

If you are not in the Foundation Project Manager, open it now and create a new project called

EasyVHDL. We will create the same logic function as was done before in the Schematic Entry section(circuit of Figure 2). Go to the FILE -> NEW PROJECT menu. In the pop up window, select for flow


25/77

vsdt_Lab_Tute_02


25

"HDL". The family and part pull down menus will not be displayed, since you will specify this laterduring the synthesis process (Figure 1 above).

Figure 2: Logic circuit to be implemented as a VHDL file.

ii. Create a VHDL Design and assign port names with the HDL Wizard

In the Foundation Project Manager, click on the HDL Editor icon or go to the TOOLS -> DESIGNENTRY ->HDL EDITOR menu. Select HDL Design Wizard. In the Design Wizard window click NEXTand go to the Design Wizard Language window. Select VHDL as the design language. Click on NEXTbutton which will open the Design Wizard Name window. Enter the name of your design. Lets call itEasyVHDL. You can give it another name, but the name should not be larger than 8 characters.

Then click NEXT. The Design Wizard Ports window will appear showing a symbol on the left. Followthe instructions in this window. You can create here the input and output pins (ports). Use the samenames as you did for the schematic of Figure 2 (DOOR, IGNITION, SBELT and BUZZER). Click onthe NEW button and enter the Name, select as Direction Input or Output, depending on the type ofport. For output pins you go to the ADVANCED button which will open the Advanced Port Settingwindows. Select STD_LOGIC. When done, click on the FINISH button. The HDL Editor window willopen at this point.

iii. Create the Source with the VHDL Editor

The HDL editor window will open a template which contains the Entity and Architecture section. TheEntity section contains the input and output Port declarations made in the previous step. You shouldverify that all the inputs and outputs are present. The Architecture section contains the logic

description of the circuit. Logic descriptions can be entered in a variety of ways: Equations, TruthTables, and State Description (for sequential circuits). We will be using an equation to define the logicfunction of Figure 2. Under the Architecture section ( ) type thefollowing equation:

BUZZER


26/77

vsdt_Lab_Tute_02


26

Figure 3: VHDL Editor window for the circuit if Figure 1 (Screen clip from Xilinx (TM) Foundationsoftware)

To find out more about the VHDL syntax click on the Language Assistant icon on the top right thetoolbar, or select TOOLS -> LANGUAGE ASSISTANT. This will bring up a window with language andsynthesis templates. The language templates shows basic language constructs while the synthesis

templates give the code of functional blocks such as counters, multiplexers, adders, flip-flops andarchitectures features such as Boundary Scan and RAM blocks. Figure 4 shows the Language

Assistant window.

Figure 4: VHDL Language Assistant window showing the template for a multiplexer. (Screen clip fromXilinx (TM) Foundation software)


27/77

vsdt_Lab_Tute_02


27

iv. Check Syntax

Lets make sure no syntax errors have been made. Go to the SYNTHESIS -> CHECK SYNTAX menu.If successful, a pop-up window will show "Check Successful". Also, the bottom window pane in the

Project Manager will display a status of the process or report any errors. To learn more about theerrors, open the synthesis report (SYNTHESIS -> VIEW REPORT in the HDL Editor window).

v. Add the design to the Project

To make the HDL source file part of the Project go to the PROJECT -> ADD TO PROJECT menu inthe HDL Editor window. The easyvhdl.vhd file should now appear in the Project Directory on theProject Manager Window (Files tab). You can now exit the HDL editor. You will notice that the rightwindow pane in the Project Manager shows an additional icon for the Synthesis operation (Figure 5).In case you want to create a macro, select PROJECT -> CREATE MACRO (see section on Macrosand Hierarchical designs)

Figure 5: Project Manager for the HDL flow mode. (Screen clip from Xilinx (TM) Foundation software)

vi. Analyzing and Synthesizing the Design

First you will analyze the syntax by going to SYNTHESIS -> ANALYZE ALL SOURCES menu in theProject Manager window. To view warnings or errors click on the HDL Errors, Warnings of MessagesTab at the bottom of the Project Manager. When the files have been successfully analyzed you can

translate the design into gates, optimized for the target device.


28/77

vsdt_Lab_Tute_02


28

You can check the Synthesis Options and change the default settings if needed, by going tothe SYNTHESIS -> OPTIONS menu in the Project Manager window. Click OK when done. If itask you to re-analyze all sources, go to the SYNTHESIS -> FORCE ANALYSIS of ALLSOURCES menu.

Click on the Synthesis icon in the Project Manager window (Flow tab). This will open theSynthesis/Implementation settings window, shown below. You can now specify the top levelmodule (in the HDL mode you specify the top-level module during the synthesis operation incontrast to the Schematic flow mode when you specify the top level module when you createyour project). In our case we only have one module, called EasyVhdl. However, for more acomplicated design you need to specify what the top level design is. The processing will thenstart from this module and progress through all the underlying designs. Fill out the versionname, select the target family and device. If you check "Edit Synthesis/Implementationconstraints", you will be able to enter constraints for your design using the Express ConstraintEditor. When you "View Estimated Performance after Optimization" you can view theestimated performance results.

Figure 6: Synthesis Settings/Implementation window. (Screen clip from Xilinx (TM) Foundationsoftware)

Click on the SET button. In the Setting window you can ask to optimize the synthesis for Areaor Speed. You can also specify the target clock frequency. Select Insert I/O pads. This willadd input and output pads to the top-level module. When done, click OK.


29/77

vsdt_Lab_Tute_02


29

Figure 7: Synthesis settings window. (Screen clip from Xilinx (TM) Foundation software)

Click RUN to start the synthesis of the design.

You can now proceed with a functional simulation by clicking on the Simulation Icon in the ProjectManager. Alternatively, you can implementyour design.

1.7 Macros and Hierarchical Designs

It is always a good practice to keep a design modular and hierarchical. This is important for designs ofmoderate and high complexity. Often, you will use a circuit (consisting of different logic gates or HDLcode) over and over again. Instead of drawing these logic gates every time you need them, it wouldbe more efficient to make a module or macro out of them with its own symbol. You can then use thismacro every time you need it by adding the macro to your schematic. Also, the use of macros keepsthe schematic neater and easier to read. A macro does not have to be a schematic, but can bedefined by an ABEL, VHDL description, LogiBLOX, CORE Generator module or Finite State Machinemodule. Macros can be created in both the Schematic and HDL Flow modes. In the schematic flow,

macros are added after the creation of the top level schematic, as illustrated in Figure 1a. In case ofthe DHL flow, the top-level module will be defined at a later stage, during the synthesis step as can beseen in Figure 1b.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sim2.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_impl4.htmlhttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sim2.html


30/77

vsdt_Lab_Tute_02


30

Figure 1: Design and Implementation sequence of a Schematic (a) and HDL flow (b) projet.

In this section we will briefly discuss how to create macros in the Schemat ic Flowmode. You willlearn how to create a macro from a schematic, an ABEL and VHDL file, and how to instantiate these

macros in a top level schematic. The procedure for creating macros in the HDL Flowmode is verysimilar. The main difference is the synthesis step as illustrated in Figure 1 above.

We will illustrate the creation of macros using a simiple example of a 4-bit comparator that comparestwo 4-bit words and outputs a logic "1" if the two words are identical, otherwise a logic "0". However,to keep the comparator more general, the X inputs can be selected from two different words (A or B)using a 2:1 multiplexer. If the X (i.e. A or B) and Y signals are the same, the comparator generates alogic "1", otherwise a logic "0". Figure 2 shows the overall schematic. Each comparator compares onebit of each word. If the four comparators outputs Zi are equal to "1", the AND gate will give a "1".

Figure 2: Two 4-bit word comparator

We will build this circuit in a modular way, using macros. First, we will create a macro for a 1-bitcomparator using the schematic entry tool. We will call this macro "COMP1ME". Then, we will build a


31/77

vsdt_Lab_Tute_02


31

macro for the 2:1 multiplexer using HDL. Once these two macros are created, we will build the overallcircuit schematic (top level schematic).

User-defined macros can be created in several ways. A convenient method is using the Symbol

Wizard which can be used to create both schematic and HDL based macros. With the Symbol Wizardtool you create the symbol first and the underlying schematic or HDL file later.

An alternative way to create a user-defined macro is to create the underlying source file first, such asthe schematic or HDL file. If the source file is a schematic, go to HIERARCHY menu -> CREATE AMACRO SYMBOL from the Current Sheet in the schematic editor. In case of a HDL file, go toPROJECT menu -> CREATE MACRO in the HDL Editor. If the underlying macro is a State MachineDiagram, go to the PROJECT menu -> CREATE MACRO. A symbol will be created and placed in theproject library in all three cases. We will illustrate these methods in the next example.

Lets first create a new project, called "COMP4ME" (go to the FILE menu ->CREATE NEW PROJECTin the Project Manager window). Fill out the Project Name, Directory, select "Schematic Flow", fill outthe Device Family (ex. XC400XL), Part (4005XLPC84) and Speed as you did in the section on"Schematic Entry".

1.7.1 a. Create a Macro for the 1-bit comparator using the schematic editor

The Boolean expression for a 1-bit comparator is given by,Z = X.Y + X'.Y'

The corresponding schematic is shown in Figure 3. Notice that the 1-bit comparator is actually anXNOR gate. In principle, we can use the XNOR gate to build our 4-bit comparator. However, for thepurpose of illustrating the use of macros, we will recreate this 1-bit comparator by using AND gatesand inverters as shown in Figure 3.

Figure 3: 1-bit comparator schematic and symbol

a1. Using the Symbol W izardi. Create a Symbol

Open the Schematic Entry tool by clicking on the Schematic Entry icon in the Project ManagerWindow.

Lets use the Symbol Wizard tool. In the Schematic Entry window, go to the TOOLS menu ->SYMBOL WIZARD. A Wizard will guide you through by asking several questions.

For the Symbol Name, type in the name you want to give to the 1-bit comparator. Lets call it"COMP1ME".

Select the Schematic for Contents.

Then push the NEXT button. Fill out the name of the input and output port names. When allinput and output ports have been defined, push the NEXT button. Follow the instructions.

When finished push the FINISH button.

The symbol will now be created and added to the project library. An underlying design file will also becreated that has the defined port names. The schematic editor will open showing an empty schematicpage for the comparator macro, except for the input and output pins.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.htm#Creating%20a%20new%20project:http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.htm#Creating%20a%20new%20project:http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.htm#Creating%20a%20new%20project:


32/77

vsdt_Lab_Tute_02


32

ii. Creating an underlying schematic file for the macro

On the schematic of the macro you can now draw the logic gates (Figure 3) for the COMP1MEmacro. Creating the schematic is basically the same as explained above in section on "Schematic

Entry". However, there are two difference:

1. You do not need to add input or output buffers (IBUF or OBUF) since the cell inputsand outputs will not become routed to the output of the FPGA or CPLD at this point.

2. You do not use IPADs or OPADs for the input and output ports. Use I/O terminalsinstead to indicate the input and output I/Os. Actually, if you used the Symbol Wizardas outlined above, these I/O terminals would have already been added to theschematic for you. In case you created the macro from an existing schematic you canadd an I/O terminal (pin) by clicking on the I/O Terminal icon (hierarchy connector) onthe left-hand side of the toolbar or at the top of the SC Symbols window. A pop-upTerminal window will open. Fill out the name of the terminal (ex. X, Y or Z) andindicate whether it is an Input or Output. Be careful to indicate the right direction forthe inputs and outputs.

Figure 4 shows the completed schematic of the 1-bit comparator.

Figure 4: 1-bit comparator schematic used as a macro (Screen clip from Xilinx FoundationFoundation software).

When finished save the schematic. To check if the macro has been created, in the schematic editorgo to FILE->OPEN->MACRO. The macro COMP1ME should appear. At this point you can simulatethe macro.

To simulate the macro, go to the TOOLS -> SIMULATE CURRENT MACRO in the Schematic Editorwindow of the macro COMP1ME. This will open the simulator. You can now add the signals andstimuli. You can do a functional simulation and verify the operation of the 1-bit comparator.

Alternatively, you can first place the macro on the main schematic. You will find the macro in theSymbol Toolbox of the Schematic Editor under the name COMP1ME. Next, go to the simulator byclicking on the SIM icon on the top toolbar.

In the Waveform viewer, click on the Add Signals icon (or go to SIGNALS -> ADD SIGNALS).In the middle panel of the Component Selection window, called Chip Selection you will seethe name of the macro, COMP1ME. Double click on it. In the right panel, Scan Hierarchy, allthe input and output pins will be displayed. Select these pins by double clicking. When done,

click the Close button.


33/77

vsdt_Lab_Tute_02


33

Open the stimulator window and define the stimuli to the input pins using the Binary counter.You can now do a functional simulation and verify the operation.

a2. Using an exist ing sch emat ic as a macro

In case you created a schematic as part of another project and would like to use this schematic as amacro in a new project you can do so.

First you will have to add the old schematic to the current (new) project. In the ProjectManager window, go to the FILE->ADD DOCUMENT menu. Use the browser to locate theschematic of interest. When done, you will see that the schematic has been added to theproject in the left window page (Files tab). Lets assume that the schematic is namedTEST1.sch.

You may want to modify this schematic, e.g. to change the pin names, replace input PADS(IPADS) by I/O terminals and remove buffers (BUF). Remember that for macros you do notuse IPADs or OPADS (these indicate the physical pins of the device) but I/O terminals (seesection "Schematic Entry" on I/O pins, Buffers and Pads).

Next you need to create a macro from the schematic. This is done as follows: go toHIERARCHY menu -> CREATE MACRO SYMBOL FROM CURRENT SHEET. A window willpop up. You can change the name of the macro, and add a brief description in the commentline. Lets call the macro MACRO1. You can also check the input and output signals. Click OK.

When you convert the schematic TEST1.sch into the macro MACRO1, there is no longer anyrelationship between the schematic TEST1.sch and the projectCOMP4ME, even though youcan still open the schematic TEST1.sch. You can remove the schematic from the projectdirectory using the Windows Explorer.

a3.Creating a Schematic first

An alternative way to create the macro, is to create the schematic first and then the symbol. In thatcase you will open a new sheet and draw the schematic. For the input and output ports you need touse I/O terminals and not IPAD, OPAD, IBUF and OBUF as explained above. When finished with theschematic of the macro, you need to create a symbol. This is done in the same way as above. Go tothe HIERARCHY ->CREATE MACRO SYMBOL FROM CURRENT SHEET menu. The CreateSymbol window will appear. For the Symbol Name, type in the name you want to give to the 1-bitcomparator. Lets call it "COMP1ME2". Make sure that all input and output pins appear in the Pinsection of the Create Symbol window. In the comment field, type any comment you like. Click OK.The symbol will be added to the SC Symbols toolbox list. You can now use the newly created macro(symbol) as you would do with any other symbol. You can complete your top level schematic at thispoint, or create another macro.

1.7.2 b. Create an ABEL macro

Here we will demonstrate how to create a new symbol (or macro) for a 2:1 multiplexer (Figure 2) with

ABEL. The symbol for the multiplexer is shown in Figure 5. The MUX selects between two 4-bitwords: when S1 is 0, word A will appear at the output; when S1 is 1, word B is connected to theoutput. We can consider this multiplexer a quad 2:1 MUX. We will now create an ABEL macro for thisquad multiplexer. Lets call this macro "MUX4X2ME".

Figure 5: Symbol for the quad 2:1 MUX.
http://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.htm#Adding%20I/O%20buffershttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.htm#Adding%20I/O%20buffershttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.html#Creating%20the%20schematichttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.html#Creating%20the%20schematichttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_macros6.html#Creating%20the%20schematichttp://www.seas.upenn.edu:8080/~ee201/foundation/foundation_sch1.htm#Adding%20I/O%20buffers


34/77

vsdt_Lab_Tute_02


34

Lets assume that you have already created a project called COMP4ME of which the macro for theMUX will become part.

i. Open the Project: COMP4ME and open the Schematic Editor window.

ii. Create new symbol

In the Schematic Editor window select TOOLS -> SYMBOL WIZARD. Click NEXT.

In the Design Wizard Contents window enter the name of the Symbol: MUX4X2ME. Note: thename of the ABEL macro should not have more than 8 characters. The synthesizer willgive an error without saying what caused the error. In the contents section select the HDL and

ABEL Radio buttons. Click NEXT.

In the Design Wizard Ports window, click on the NEW button to enter the name of the inputsand outputs. Enter S1 in the name field and select Input in the Direction field. Click NEW andenter A[3:0] in the Name field; select Input in the Direction section. Do the same for the B[3:0]input. Next, click on NEW again and enter C[3:0] in the Name field and select Output for theDirection. Go to the ADVANCED button and select the 'combinational' port. Create also theinput S1. When finished defining input and outputs, click on NEXT.

In the Attribute window fill out a short comments (ex. ABEL code) and long comments (4-bit2:1 MUX in ABEL). Click the NEXT and FINISH buttons.

You can now place the MUX4X2ME on the new schematic page (COMP4ME1.sch). You will noticethat the inputs A[3:0], B[3:0] and output C[3:0] are shown as buses, rather than as individual inputs.This makes the schematic easier to read and less complicated. We will see later how to use buses.(Note: if you created the symbol using the HDL Editor from the Project Manager window, the signalswill not be represented as buses but as individual signals A0, A1, A2, etc. This is an annoying feature,particularly when working with wide buses. To prevent this, use the Symbol Wizard in the SchematicEditor window, as outlined above, to create the symbol).

In case you want to modify the symbol, such as changing the shape of the symbol,adding, renaming, or removing I/O pins, you can do so. In the Schematic Editorwindow, select TOOLS -> SYMBOL EDITOR. Or you can also click on the macrosymbol on the schematic. The Symbol Properties window will open. Click on SymbolEditor. This will open the HDL Editor window. You can now define the ABEL file in theHDL Editor window as explained next.

iii. Create an ABEL macro

You still need to define the new macro for which you have created the MUX4X2ME symbol.

After placing the symbol on the schematic click the "H" icon (Hierarchy).

Next, double click on the MUX4X2ME symbol. The ABEL editor will open its Editor window.

You will notice that the pins have already been declared in the HDL Editor window. Make surethat the output pin C3..C0 has been specified as an istype 'com' and not 'reg' because the C

is the output of a combinational circuit.

In the equation section, type the expression for the 2:1 multiplexer. The expression for themultiplexer output is as follows, according to the Truth Table I. Be careful, input and outputnames are case sensitive!

C = !S1 & A # S1 & B;TABLE I: Truth Table of the 2:1 MUX

S1 C


35/77

vsdt_Lab_Tute_02


35

0 A

1 B

In order to simplify the expression we made use of sets in the ABEL description (A = [A3..A0], etc.).

Each member of the set will undergo the same logicoperations (see ABEL Primer - section 5b on Sets). Thus the above expression is equivalent to fourindividual expressions:

C0 =!S1 & A0 # S1 & B0;:C3 =!S1 & A3 # S1 & B3;

Figure 6 shows the ABEL editor window. Notice that the sets for A, B and C are already defined. Enterin the equation section the expression for C.

Figure 6: ABEL editor window for the quad 2:1 multiplexer (Screen clip from Xilinx Foundation (TM)Foundation software).

When finished, check the syntax (go to the SYNTHESIS->CHECK SYNTAX menu).

Exit. When prompted to update the macro, select YES. The synthesis of the macro will nowproceed.

An alternative way to create an ABEL macro is to open the HDL Editor from the Project Manager:

In the Project Manager window, click on the HDL icon or select TOOLS -> DESIGN ENTRY -> HDL Editor. In the HDL Editor window select "Use HDL Design Wizard". Next, click theNEXT button.

In the Design Language window, select the ABEL radio button. Then click NEXT.

Follow the instructions as outlined above. When the symbol has been created, the HDL Editorwill open. Enter the ABEL code.


36/77

vsdt_Lab_Tute_02


36

When finished with entering the ABEL code, check the synthesis.

To create the macro, go to PROJECT menu -> Make MACRO. Give the macro a name. Whenfinished the macro symbol will be added to the project library.

As was noted above, this method has the annoying feature that it will expand thebuses for the signals A[0:3], B[0:3] etc. which makes the schematic quickly unwealdy,particularly when working with wide buses.

1.7.3 c. Create a VHDL macro

In the previous section we demonstrated how to create an ABEL macro. An alternative way is todefine the macro as a VHDL module. In this section we will define the 2:1 MUX as a VHDL file. Theprocedure is similar to the one for an ABEL macro.

i. Open the Project: COMP4ME and open the Schematic Editor window.

ii. Create new symbol

In the Schematic Editor window select TOOLS -> SYMBOL WIZARD. Click NEXT.

In the Design Wizard Contents window enter the name of the Symbol: MUX4X2VH. Note: thename of the VHDL macro should not have more than 8 characters. Click NEXT.

In the Design Wizard Ports window, click on the NEW button to enter the name of the inputsand outputs. Enter S1 in the name field and select Input in the Direction field. Click NEW andenter A[3:0] in the Name field; select Input in the Direction section. Do the same for the B[3:0]input. Next, click on NEW again and enter C[3:0] in the Name field and select Output for theDirection. Go to the ADVANCED button and select the 'STD_LOGIC_VECTOR' port. Createalso the input S1. When finished defining input and outputs, click on NEXT.

In the Attribute window fill out short comments (ex. VHDL code) and long comments (4-bit 2:1

MUX in VHDL). Click the NEXT and FINISH buttons.

You can now place the MUX4X2VH on the new schematic page (COMP4ME1.sch). You will noticethat inputs A[3:0], B[3:0] and output C[3:0] are shown as buses rather than as individual inputs. Thismakes the schematic easier to read and less complicated. We will see later on how to use buses.

In case you want to modify the symbol, such as changing the shape of the symbol,adding, renaming, or removing I/O pins, you can do so. In the Schematic Editorwindow, select TOOLS -> SYMBOL EDITOR. Or you can also click on the macrosymbol on the schematic. The Symbol Properties window will open. Click on SymbolEditor. This will open the HDL Editor window. You can now define the ABEL file in theHDL Editor window as explained next.

iii. Create a VHDL macro

You still need to define the new macro for which you have created the MUX4X2VH symbol.

After placing the symbol on the schematic click the "H" icon (Hierarchy).

Next, double click on the MUX4X2VH symbol. The VHDL editor will open its Editor window.

You will notice that the pins have already been declared in the HDL Editor window.In the architecture section, type the expression for the 2:1 multiplexer. The expression for themultiplexer output is as follows, according to the Truth Table I. Be careful, input and outputnames are case sensitive!

C(0)


37/77

vsdt_Lab_Tute_02


37

C(3) Check Syntax

Select PROJECT -> UPDATE MACRO.

Save and exit the editor.

An alternative way to create an ABEL macro is to open the HDL Editor from the Project Manager:

In the Project Manager window, click on the HDL icon or select TOOLS -> DESIGN ENTRY -> HDL Editor. In the HDL Editor window select "Use HDL Design Wizard". Then click theNEXT button.

In the Design Language window, select the VHDL radio button. Then click NEXT.

Follow the instructions as outlined above. When the symbol has been created, the HDL Editorwill open. Enter the VHDL code.

When finished with entering the VHDL code, check the synthesis.To create the macro, go to PROEJCT menu -> CREATE MACRO. Give the macro a name.When finished the macro symbol will be added to the project library.

1.7.4 d. Create a top level schematic: 4-bit comparator

A top-level module can be a schematic or an ABEL file. However, it is not recommended to have anABEL top-level module for a FPGA design. The top-level module can have underlying schematic,ABEL, VHDL or Verilog, LogiBLOXs, Finite State Machine and CORE Generator Modules. In thisexample we will limit ourselves to a schematic and ABEL or VHDL macro, defined above.

We are now ready to design our 4-bit comparator of Figure 2 using the macros for the 1-bitcomparator and the quad 2:1 MUX. Go to the Schematic Editor window. The sheet COMP4ME.schwill open.


38/77

vsdt_Lab_Tute_02


38

i. Adding macro and logic symbols

Lets add the 1-bit comparator cells by clicking on the Symbol icon on the left toolbar. Type comp to goto the COMP1ME symbol. Select COMP1ME and place it on the schematic. Then click on the symbol

to place multiple copies of it. Next add the quad 2:1 MUX. Add next the 4 input AND gate (AND4). Ifthe symbol name of COMP1 does not show and you want to display it, select the symbol and doubleclick. In the Symbol Properties window, press the Attributes key and select "Show Symbol Name".

Lets assume that we want to implement the 4-bit into a FPGA or CPLD. Thus we need to indicate theinput and output pads (unless you want to make another macro for the 4-bit comparator; in that casefollow the same procedure as above). First you have to add the input buffers. Select IBUF4 in the SCSymbol window and place it on the schematic. Do this for each input A, B and Y (see Figure 8). Forthe S1 input signal, place a single IBUF. Then add the OBUF. Next, place the input pads (IPAD4) andoutput pad (OPAD) to indicate the connection to the actual pin of the FPGA or CPLD.

Figure 8: Top level schematic of the 4-bit comparator (Screen clip from Xilinx Foundation (TM)Foundation software).

ii. Adding wires and net names

Connect the IPADS to the IBUF and the OBUF to the OPAD using the Draw Wire command. Also,connect the output of the AND gate to the input of the OBUF and the output of the four 1-bitcomparators to the input of the 4-input NAND gate.

Next, we want to label the input, output nets and the compartor outputs. Select the Add Net Namesicon on the left toolbar. The Net Name window will pop up. Enter the Net Name A0. To speed up the

net naming, select the REPEAT button. Every time you click on a net, a new name will be placed andthe name index will be incremented by one. Press the ESC key to finish the command. Do the same


39/77

vsdt_Lab_Tute_02


39

of the B inputs and the Z outputs of the 1-bit comparators. Don't forget to name the S1 input net. Next,we will use the Draw Buses command to connect the inputs.

iii. Draw Buses

To connect the IBUF4 outputs to the MUX inputs A[3:0] and B[3:0] we will use the Draw Buscommand. Click on the Draw Buses icon or go to the MODE -> DRAW BUSES menu. Click on theinput A[3:0] of the MUX and draw the bus as shown in Figure 9. Click to make a corner in the bus.Click on the right mouse button or double click to end the bus. An Add Terminal/Label or Edit Buswindow will appear, as shown in Figure 9. If not, double click at the end of the bus. In the windowenter in the Name field: ABUS. Select a bus width: from 3 to 0. This bus is not an input or output bus,so the I/O markershould say None. Click OK. Do the same for the B-bus and the C bus and call thisbus BBUS and CBUS, respectively.

Figure 9: Edit Bus window (Screen clip from Xilinx Foundation (TM) Foundation software).

Bus Taps

Now we can connect the inputs of the 1-bit comparators to the buses. This is done by clicking on theDraw Bus Taps icon or going to the MODE menu ->DRAW BUS TAPS. Click first on the bus name ABUS to select the bus you want to tap into. The status line will show that the first bus tap ABUS0(usually the member with the lowest index) has been selected for placement. Next click the cursor onthe A0 output of the first input buffer (IBUF4) (least significant bit). Then, click on A1 outputs of the

2nd, 3rd and 4th buffer. When finished click on the ESC key twice. Repeat the process for the BBUSand CBUS as shown in Figure 8. Make sure that the tap numbers correspond to the numbers of theinput signal (A0 connected to ABUS0, A1 to ABUS1, etc.).

Note: The default start number for the tap is 0. You can use the up and down arrow keys to selectwhich bus bit will be tapped. If the down arrow key was pressed last, the bus tap numbers willdecrease.

If you want to connect a single wire to a bus, you need to draw a wire that starts or ends at the bus.Next you will need to label the wire with the name of a bus memberto which you want to connect. Forinstance, you want to access the most significant bit in the carry-cout bus (CBUS). You need to namethe wire CBUS3. If you do not name the wire, there will be no connection (a warning will begenerated) or if you give it different name from the bus, there will be an error.

Complex buses


40/77

vsdt_Lab_Tute_02


40

To simplify a schematic, you can combine buses and individual wires into a complex bus. This is doneby naming the complex bus with a compound label. A compound label consists of several label names(with or without ranges), separated with commas. To enter a compound label, use the followingformat:

NAME[F:L:I],NAME,NAME[F:L],...

where F is the first number, L is the last number, and I is the interval between the numbers in therange. If no interval is specified, the interval is 1. As an example we could combine the LED-OUTbuses and the Error signal in a complex bus with the name

LED_ONE[6:0], LED_TWO[6:0],ERROR

or we can use a selected number of wires: LED_ONE[3:0], LED_TWO[4:2],ERROR

It is important that each of the bus segments, such as LED_ONE[6:0] have been defined beforehand.For more information about buses, in the Schematic Entry window, select HELP -> SCHEMATICEDITOR HELP CONTENTS. In the help window select INDEX and type buses.

I/O terminals vs. PADS.

In case you decide to use this schematic as another macro and do not intend to implement thisparticular schematic in a FPGA or CPLD, you do not need to add PADS and BUFFERS. In that case,when you draw the input buses to connect the inputs A and B, you will indicate in the AddTerminal/Label window (Figure 5) that the bus is an input (or output, if appropriate). The name of thebus will now be the name of the inputs to the macro. To create a macro from the schematic go to theHIERARCHY ->CREATE MACRO SYMBOL FROM CURRENT SHEET menu. When the schematic isfinished save it.

iv. Going down the hierarchy

To push into a schematic of a macro, select the "H" icon (Hierarchy icon) and double click on thedesired macro symbol (ex. comp1). To go back to the upper level schematic, double click on the

background of the lower level schematic.

v. Netlist and Integrity Test

When the schematic is finished you can create a netlist and do an integrity test. This is done by goingto the OPTIONS menu-> CREATE NETLIST. When finished, it is always a good idea to check that theschematic has no electrical design rule errors. This is done from the OPTIONS menu -> INTEGRITYTEST. You can now also generate a EDIF netlist by going to the OPTIONS menu -> EXPORTNETLIST.

vi. Simulation

You can now do a functional simulation of the schematic as was explained in the section on"Simulation". The only difference is the presence of buses. In order to assign signals to the individualinputs of the A and B bus, you need to expand the bus into the individual signals. This is done byselecting the bus A or B in the Waveform Viewer window and then going to the SIGNAL->BUS ->FLATTEN. You can now assign outputs of the binary counter to the individual A and B inputs. You canclick on the Bus Expansion Icon on the top toolbar to collapse or expand the bus (after creating itfirst), or go to the SIGNAL -> BUS -> COMBINE menu after selecting the signals you want to collapseinto one bus (i

getting started with the xilinx foundation f2

Documents