gisel status 2017 final - llvmllvm.org/devmtg/2017-10/slides/bougacha-colombet-globalisel.pdf ·...
TRANSCRIPT
LLVM DevMtg October 2017
Ahmed Bougacha Quentin Colombet
GlobalISel Past, Present, and Future
GlobalISel Recap
GlobalISel Recap
Revamp of our instruction selection framework
GlobalISel Recap
Revamp of our instruction selection framework
LLVM Dev Meeting talks: https://www.youtube.com/watch?v=F6GGbYtae3g https://www.youtube.com/watch?v=6tfb344A7w8
GlobalISel Recap
Revamp of our instruction selection framework
LLVM Dev Meeting talks: https://www.youtube.com/watch?v=F6GGbYtae3g https://www.youtube.com/watch?v=6tfb344A7w8
LLVM Dev RFCs: http://lists.llvm.org/pipermail/llvm-dev/2013-August/064696.html http://lists.llvm.org/pipermail/llvm-dev/2015-November/092566.html
GlobalISel Pipeline
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
GenericMachineInstr MachineInstr
Past
Generic MachineInstr More Concise Type System
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_ADD %2, %1 %4(_,p0) = G_INTTOPTR %3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)%4(_,p0) = G_GEP %0, %1
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)%4(_,p0) = G_GEP %0, %1
Alignment%0(_,p0) = COPY %x0
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_AND %2, %1 %4(_,p0) = G_INTTOPTR %3
%1(_,s64) = G_CONSTANT ~3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)%4(_,p0) = G_GEP %0, %1
Alignment%0(_,p0) = COPY %x0
%2(_,s64) = G_PTRTOINT %0 %3(_,s64) = G_AND %2, %1 %4(_,p0) = G_INTTOPTR %3
%1(_,s64) = G_CONSTANT ~3
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)%4(_,p0) = G_GEP %0, %1
Alignment %0(_,p0) = COPY %x0%4(_,p0) = G_PTR_MASK %0, 2
Generic MachineInstr More Concise Type System
Displacement%0(_,p0) = COPY %x0 %1(_,s64) = G_CONSTANT 4
%5(_,s32) = G_LOAD %4(_,p0)%4(_,p0) = G_GEP %0, %1
Alignment %0(_,p0) = COPY %x0%4(_,p0) = G_PTR_MASK %0, 2
%0(_,p0) = COPY %x0 %1(_,s64) = G_PTRTOINT %0 %2(_,s64) = G_CONSTANT 4 %3(_,s64) = G_ADD %1, %2 %4(_,p0) = G_INTTOPTR %3 %5(_,s32) = G_LOAD %4(_,p0)
%0(_,p0) = COPY %x0 %1(_,s64) = G_PTRTOINT %0 %2(_,s64) = G_CONSTANT ~3 %3(_,s64) = G_AND %1, %2 %4(_,p0) = G_INTTOPTR %3
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓✓ Fallback
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓✓✓
Fallback
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓✓✓✓
Fallback
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select
@fct1 ... @fctI ... @fctN
✓✓✓✓✓
Fallback
-global-isel-abort=0 or -global-isel-abort=2 (for warnings)
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
@fct1 ... @fctI ... @fctN
✓✓✓✓✓
Fallback
-global-isel-abort=0 or -global-isel-abort=2 (for warnings)
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:... = op1 ......... = opN ...
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = op1 ...
...
... = opN ...
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = op1 ...
...
... = opN ...
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
✓
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
✓
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
✓ 𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
✓ 𐄂
𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
✓ 𐄂
𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
fctI:
✓
... = legOp1 ...
...
... = legOpN ...
✓ 𐄂
𐄂
-
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
✓ ✓ 𐄂 -
fctI:... = legOp1 ... ... ... = legOpN ...
𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
✓ ✓ 𐄂 -
fctI:... = legOp1 ... ... ... = legOpN ...
𐄂
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
✓ ✓ 𐄂 -
fctI:
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
✓ ✓ 𐄂 -
fctI:
Fallback to SelectionDAG Easier Bring Up
(G)MIIRTranslatorLLVM IR Legalizer RegBank Select MIInstruction
Select SDISelReset
Machine Function
✓ ✓ 𐄂 -
fctI:... = tgtOp1 ......... = tgtOpN ...
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
What Changed?
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
CallLowering API More instructions supported
What Changed?
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
Legalizer Fundamentals
%6(_,s128) G_OR %4, %5=%6(_,s128) G_OR %4, %5=
Legalizer Fundamentals
.low%6 (_,s64) = G_OR %4.low, %5.low
.high%6 (_,s64) = G_OR %4.high, %5.high
Legalizer Fundamentals
%6(_,s128) =
%7(_,s64) = G_OR %4.low, %5.low%8(_,s64) = G_OR %4.high, %5.high
G_SEQUENCE %7 %8
Legalizer Fundamentals
%6(_,s128) =
%7(_,s64) = G_OR %4.low, %5.low%8(_,s64) = G_OR %4.high, %5.high
G_SEQUENCE %7, %8
Legalizer Fundamentals
%6(_,s128) =
%7(_,s64) = G_OR %4.low, %5.low%8(_,s64) = G_OR .high, .high
G_SEQUENCE %7, %8
Legalizer Fundamentals
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_SEQUENCE %7, %8
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalizer Fundamentals
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_SEQUENCE %7, %8
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_SEQUENCE %7, %8
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_SEQUENCE
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_SEQUENCE
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
%0(_,s64), %1(_,s64) = G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
Same type
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%0(_,s64), %1(_,s64) =
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_EXTRACT , 0, 64%4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%0(_,s64), %1(_,s64) =
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_UNMERGE_VALUES %4%2(_,s64), %3(_,s64) = G_EXTRACT , 0, 64%5
Legalization Artifacts Simpler More Regular Semantic
Same type
%7, %8
%0(_,s64), %1(_,s64) = G_UNMERGE_VALUES
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_UNMERGE_VALUES %4%2(_,s64), %3(_,s64) = G_UNMERGE_VALUES %5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%0(_,s64), %1(_,s64) =
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_UNMERGE_VALUES %4%2(_,s64), %3(_,s64) = G_UNMERGE_VALUES %5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%0(_,s64), %1(_,s64) =
• G_SEQUENCEs are gone
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_UNMERGE_VALUES %4%2(_,s64), %3(_,s64) = G_UNMERGE_VALUES %5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%0(_,s64), %1(_,s64) =
• G_SEQUENCEs are gone
• G_EXTRACTs still exist but have only one result
%6(_,s128)=
%7(_,s64) = G_OR %0, %2%8(_,s64) = G_OR %1, %3
G_MERGE_VALUES
G_UNMERGE_VALUES %4%2(_,s64), %3(_,s64) = G_UNMERGE_VALUES %5
Legalization Artifacts Simpler More Regular Semantic
%7, %8
%0(_,s64), %1(_,s64) =
• G_SEQUENCEs are gone
• G_EXTRACTs still exist but have only one result
• G_[UN]MERGE_VALUES is used instead for these uses cases
Legalization Algorithm How Does It Work?
Legalization Algorithm How Does It Work?
setAction({Opcode, [OpIdx,] Type}, Action)
Legalization Algorithm How Does It Work?
setAction({Opcode, [OpIdx,] Type}, Action)
Legal
Legalization Algorithm How Does It Work?
setAction({Opcode, [OpIdx,] Type}, Action)
LegalNarrowScalar
Legalization Algorithm How Does It Work?
setAction({Opcode, [OpIdx,] Type}, Action)
LegalNarrowScalarWidenScalar
Legalization Algorithm How Does It Work?
setAction({Opcode, [OpIdx,] Type}, Action)
LegalNarrowScalarWidenScalarFewerElementsMoreElements
LowerLibcallCustomUnsupportedNotFound
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16) = G_UREM %1 %2,
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({G_UREM, 0, s16}, LegalizerInfo::WidenScalar)
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16) = G_UREM %1 %2,
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({G_UREM, 0, s16}, LegalizerInfo::WidenScalar)
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)= G_UREM
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT%5(_,s32)
= G_TRUNC %5%3 %4,
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)= G_UREM
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT%5(_,s32)
= G_TRUNC %5%3 %4, %4%3
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)= G_UREM
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT%5(_,s32)
= G_TRUNC %5%3 %4,
setAction({G_UREM, 0, s32}, LegalizerInfo::Lower) %4%3
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,setAction({G_UREM, 0, s32}, LegalizerInfo::Lower) = G_UDIV
%7(_,s32) = G_MUL %6, = G_SUB , %7
%6(_,s32)
%3%4
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,= G_UDIV%7(_,s32) = G_MUL %6,
= G_SUB , %7
%6(_,s32)
%3%4
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,= G_UDIV%7(_,s32) = G_MUL %6,
= G_SUB , %7
%6(_,s32)
%3%4
setAction({G_SUB, 0, s32}, LegalizerInfo::Legal)
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,= G_UDIV%7(_,s32) = G_MUL %6,
= G_SUB , %7
%6(_,s32)
%3%4
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,= G_UDIV%7(_,s32) = G_MUL %6,
= G_SUB , %7
%6(_,s32)
%3%4
setAction({G_MUL, 0, s32}, LegalizerInfo::Legal)
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,= G_UDIV%7(_,s32) = G_MUL %6,
= G_SUB , %7
%6(_,s32)
%3%4
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3 %4,= G_UDIV%7(_,s32) = G_MUL %6,
= G_SUB , %7
%6(_,s32)
%3%4
setAction({G_UDIV, 0, s32}, LegalizerInfo::LibCall)
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3
%7(_,s32) = G_MUL %6, = G_SUB , %7
%6(_,s32)
%3%4
setAction({G_UDIV, 0, s32}, LegalizerInfo::LibCall)
%r0 = COPY%4%r1 = COPY
= COPY %r0%r0 = BLX uidivmod %r0, %r1
Legalization Algorithm How Does It Work?
Legal NarrowScalar WidenScalar FewerElements MoreElements
Lower Libcall Custom Unsupported NotFound
setAction({Opcode, [OpIdx,] Type}, Action)
%0(_,s16)
%1%2
%3(_,s32) = G_ZEXT%4(_,s32) = G_ZEXT
%5(_,s32)= G_TRUNC %5
%3
%7(_,s32) = G_MUL %6, = G_SUB , %7
%6(_,s32)
%3%4
%r0 = COPY%4%r1 = COPY
= COPY %r0%r0 = BLX uidivmod %r0, %r1
%0(_,s16) = G_UREM %1 %2,
(G)MI Legalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
(G)MILegalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
(G)MILegalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
What Changed?
(G)MILegalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
Partial TableGen support Statically allocated structures
What Changed?
(G)MILegalizer RegBank Select
Instruction SelectIRTranslatorLLVM IR MI
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
DAGISel Emitter [SD].inc
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
DAGISel Emitter
GlobalISel Emitter
[SD].inc
[GI].inc
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
Selection DAG
Compat.td
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
Selection DAG
Compat.td
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
def : GINodeEquiv<G_ADD, add>;
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
Selection DAG
Compat.td
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
def : GINodeEquiv<G_ADD, add>;
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
XXXInstr Info.td
addsub_shifted_imm32
def gi_addsub_shifted_imm32:
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
addsub_shifted_imm32
XXXInstr Info.td
def gi_addsub_shifted_imm32:GIComplexOperandMatcher <s32, “selectArithImmed”>,
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
def gi_addsub_shifted_imm32:GIComplexOperandMatcher <s32, “selectArithImmed”>,GIComplexPatternEquiv <addsub_shifted_imm32>;
addsub_shifted_imm32
XXXInstr Info.td
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
def gi_addsub_shifted_imm32:GIComplexOperandMatcher <s32, “selectArithImmed”>,GIComplexPatternEquiv <addsub_shifted_imm32>;
addsub_shifted_imm32
XXXInstr Info.td
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
bool AArch64DAGToDAGISel:: SelectArithImmed( SDValue N, [...])
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
bool AArch64DAGToDAGISel:: SelectArithImmed( SDValue N, [...])
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
class addsub_shifted_imm<i32> : Operand<i32>, ComplexPattern<i32, 2, “SelectArithImmed", [imm]>
bool AArch64DAGToDAGISel:: SelectArithImmed( SDValue N, [...])
InstructionSelector::ComplexRendererFn AArch64InstructionSelector:: selectArithImmed( MachineOperand &Root) const
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
GIR_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
GIR_ComplexRenderer, [...]GIR_EraseFromParent, /*InsnID*/0,
GIR_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
GIR_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
GIR_ComplexRenderer, [...]GIR_EraseFromParent, /*InsnID*/0,
GIR_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
GIR_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
GIR_ComplexRenderer, [...]GIR_EraseFromParent, /*InsnID*/0,
GIR_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
_ComplexRenderer, [...] _EraseFromParent, /*InsnID*/0,
_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
GIR
GIRGIR
GIR
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
_ComplexRenderer, [...] _EraseFromParent, /*InsnID*/0,
_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
GIR
GIRGIR
GIR
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
_ComplexRenderer, [...] _EraseFromParent, /*InsnID*/0,
_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
GIR
GIRGIR
GIR
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
_ComplexRenderer, [...] _EraseFromParent, /*InsnID*/0,
_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
GIR
GIRGIR
GIR
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
/*ADDWri Pattern*/ ADDWri : [( , ( , :$imm))]
set GPR32sp:$Rdadd GPR32sp:$Rn
addsub_shifted_imm32
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
_ComplexRenderer, [...] _EraseFromParent, /*InsnID*/0,
_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
GIR
GIRGIR
GIR
Instruction Select TableGen Support
[SD].td CodeGenDAG Patterns
GlobalISel Emitter [GI].inc
_Try, /*On fail goto*//*Label 478*/ 30417,_CheckNumOperands, /*MI*/0, /*Expected*/3,
_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, _CheckRegBankForClass, [...]GPR32spRegClassID,
_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
_BuildMI, [...] /*Opcode*/AArch64::ADDWri,
_ComplexRenderer, [...] _EraseFromParent, /*InsnID*/0,
_Done
[...]
[...]
[...]
[...]
GIMGIMGIMGIM
GIM
GIR
GIRGIR
GIR
Present
Present Status
• Non-optional library
Present Status
• Non-optional library
• Ports in progress:
Present Status
• Non-optional library
• Ports in progress:
Present Status
X86 AMDGPU AArch64 ARM Hexagon PowerPC Mips SystemZ WebAssembly AVR NVPTX Sparc
BPF XCore Lanai RISCV MSP430 Nios2 ARC
• Non-optional library
• Ports in progress:
Present Status
X86 AMDGPU AArch64 ARM Hexagon PowerPC Mips SystemZ WebAssembly AVR NVPTX Sparc
BPF XCore Lanai RISCV MSP430 Nios2 ARC
• Non-optional library
• Ports in progress:
Present Status
X86 AMDGPU AArch64 ARM Hexagon PowerPC Mips SystemZ WebAssembly AVR NVPTX Sparc
BPF XCore Lanai RISCV MSP430 Nios2 ARC
Present Status: AArch64 -O0
• Test Suite + SPEC
Present Status: AArch64 -O0
• Test Suite + SPEC
Present Status: AArch64 -O0
% Instructions handled without fallback
• Test Suite + SPEC
• Clang self-host
Present Status: AArch64 -O0
% Instructions handled without fallback
• Test Suite + SPEC
• Clang self-host
Present Status: AArch64 -O0
% Instructions handled without fallback
• Test Suite + SPEC
• Clang self-host
• Our internal software
Present Status: AArch64 -O0
% Instructions handled without fallback
• Test Suite + SPEC
• Clang self-host
• Our internal software
Present Status: AArch64 -O0
% Instructions handled without fallback
Present Status: Select TableGen
• AArch64
Present Status: Select TableGen
• AArch64
Present Status: Select TableGen
% Imported patterns
• AArch64
Present Status: Select TableGen
Lots of vectors
% Imported patterns
• AArch64
• ARM
Present Status: Select TableGen
Lots of vectors
% Imported patterns
• AArch64
• ARM
Present Status: Select TableGen
Lots of vectors
% Imported patterns
• AArch64
• ARM
• X86
Present Status: Select TableGen
Lots of vectors
% Imported patterns
• AArch64
• ARM
• X86
Present Status: Select TableGen
Lots of vectors
% Imported patterns
• AArch64
• ARM
• X86
Present Status: Select TableGen
Lots of vectors
Even more vectors% Imported patterns
PresentPerformance
Performance Code size
Performance Code size
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
FastISel
Performance Code size
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
Performance Constant placement
%5(_,s64) = G_ADD %2, %6%4(_,s64) = G_MUL %1, %6
%6(_,s64) = G_CONSTANT 10
Performance Constant placement: -regalloc=fast
%9(_,s64) = G_LOAD %fi%5(_,s64) = G_ADD %2, %9
%8(_,s64) = G_LOAD %fi%4(_,s64) = G_MUL %1, %8
%6(_,s64) = G_CONSTANT 10G_STORE %6, %fi Spill
Performance Constant placement: Localizer
%9(_,s64) = G_CONSTANT 10%5(_,s64) = G_ADD %2, %9
%8(_,s64) = G_CONSTANT 10%4(_,s64) = G_MUL %1, %8
FastISel
Performance Code size: before
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
FastISel
Performance Code size: with localizer
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
Performance Compile time
Performance Compile time
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
FastISel
Performance Compile time
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
FastISel
Performance Compile time
80%
90%
100%
110%
120%
130%
140%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
GlobalISelSelectionDAG
157% 152% 203%
Performance Compile time: per pass
Performance Compile time: per pass
0%
25%
50%
75%
100%
125%
150%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
IRTranslatorRegBankSelectLegalizerLocalizerInstructionSelect
FastISel
Performance Compile time: per pass
0%
25%
50%
75%
100%
125%
150%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
IRTranslatorRegBankSelectLegalizerLocalizerInstructionSelect
FastISel
Performance Compile time: per pass
0%
25%
50%
75%
100%
125%
150%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
IRTranslatorRegBankSelectLegalizerLocalizerInstructionSelectSelectionDAG
Performance Compile time: per pass, normalized
0%
20%
40%
60%
80%
100%
kc
SPASS
tramp3
d-v4
cons
umer-
types
et
bulle
t
lenco
d
pairlo
calal
ign
clamsc
an
7zip-
benc
hmark
sqlite
3
IRTranslatorRegBankSelectLegalizerLocalizerInstructionSelect
GlobalISel
Performance Runtime: SPEC2006
Performance Runtime: SPEC2006
100%
125%
150%
175%
200%
470.l
bm46
2.libq
uantu
m43
3.milc
482.s
phinx
346
4.h26
4ref
429.m
cf44
7.dea
lII44
4.nam
d45
6.hmmer
471.o
mnetpp
483.x
alanc
bmk
401.b
zip2
473.a
star
450.s
oplex
453.p
ovray
445.g
obmk
458.s
jeng
403.g
cc40
0.perl
benc
h
Performance Runtime: SPEC2006
100%
125%
150%
175%
200%
470.l
bm46
2.libq
uantu
m43
3.milc
482.s
phinx
346
4.h26
4ref
429.m
cf44
7.dea
lII44
4.nam
d45
6.hmmer
471.o
mnetpp
483.x
alanc
bmk
401.b
zip2
473.a
star
450.s
oplex
453.p
ovray
445.g
obmk
458.s
jeng
403.g
cc40
0.perl
benc
h
FastISel
Performance Runtime: Test Suite
100%
125%
150%
175%
200%
FastISel
Future
Future Beyond -O0
• Flesh out the pass pipeline
Future Beyond -O0
• Flesh out the pass pipeline
• Kill Localizer
Future Beyond -O0
• Flesh out the pass pipeline
• Kill Localizer
• Kill CodeGenPrepare
Future Beyond -O0
Future Beyond the SelectionDAG GlobalISelEmitter
• Emit legality info
Future Beyond the SelectionDAG GlobalISelEmitter
• Emit legality info
Future Beyond the SelectionDAG GlobalISelEmitter
def : Pat< (i32 (mul (GPR32:$Rn, GPR32:$Rm))), (...) >;
• Emit legality info
Future Beyond the SelectionDAG GlobalISelEmitter
setAction({G_MUL, 0, s32}, Legal)
def : Pat< (i32 (mul (GPR32:$Rn, GPR32:$Rm))), (...) >;
• Emit legality info
• Emit register bank mapping
Future Beyond the SelectionDAG GlobalISelEmitter
• Emit legality info
• Emit register bank mapping
• Support pure GlobalISel patterns
Future Beyond the SelectionDAG GlobalISelEmitter
Future Beyond SelectionDAG
• Feature parity (remember vectors?)
Future Beyond SelectionDAG
• Feature parity (remember vectors?)
• Improved performance
Future Beyond SelectionDAG
• Feature parity (remember vectors?)
• Improved performance
• More testing!
Future Beyond SelectionDAG
Future Combines: Leveraging Patterns
Future Combines: Leveraging Patterns
def : Pat< (f32 (fma (fneg (FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)), (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra) >;
Future Combines: Leveraging Patterns
def Mul2ToShl1 : Combine< (mul type0:$src0, 2), (shl type0:$src0, 1), >;
Future Combines: Leveraging Patterns
TableGen Backend
def Mul2ToShl1 : Combine< (mul type0:$src0, 2), (shl type0:$src0, 1), >;
Future Combines: Leveraging Patterns
TableGen Backend
Inst Combine .incdef Mul2ToShl1 : Combine<
(mul type0:$src0, 2), (shl type0:$src0, 1), >;
Future Combines: Leveraging Patterns
TableGen Backend
Inst Combine .inc
GISel Combine .inc
def Mul2ToShl1 : Combine< (mul type0:$src0, 2), (shl type0:$src0, 1), >;
Future Combines: Leveraging Patterns
TableGen Backend
Inst Combine .inc
GISel Combine .inc
def Mul2ToShl1 : Combine< (mul type0:$src0, 2), (shl type0:$src0, 1), >;
Future Combines: Leveraging Patterns
TableGen Backend
Inst Combine .inc
GISel Combine .inc
def Mul2ToShl1 : Combine< (mul type0:$src0, 2), (shl type0:$src0, 1), >;
Target Config .td Target
Combine .inc
def : RunWhen<Mul2ToShl1, [BeforeLegalized, AfterLegalized]>
def MyPattern : (MyOp(...)); def : RunWhen<MyPattern, [AfterRegBankSelect]>
Future Tools to Help the Transition
• Better .mir test format
Future Tools to Help the Transition
• Better .mir test format
• Better MachineInstr API
Future Tools to Help the Transition
• Better .mir test format
• Better MachineInstr API
• Regression tests generator
Future Tools to Help the Transition
• Better .mir test format
• Better MachineInstr API
• Regression tests generator
• SDNode to GMIR migrator
Future Tools to Help the Transition
Contributions Welcome!
Questions?