gowin programmable io (gpio)

Gowin Programmable IO (GPIO)

User Guide

UG289-2.0E, 01/24/2022

Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.

, Gowin, LittleBee, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.

Disclaimer

GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

Revision History

Date Version Description

05/17/2016 1.05E Initial version published.

07/15/2016 1.06E The graphics standardized.

08/02/2016 1.07E GW2A series of FPGA Products Data Sheet supported.

10/27/2016 1.08E GW2A series of FPGA Products Data Sheet supported.

09/01/2017 1.09E Features of GW1N-6/9 and GW1NR updated.

10/12/2017 1.10E IDES16/OSER16 related notes added.

12/12/2017 1.2E

IDDR/ODDR RESET signal removed.

LVDS description updated.

Input/output description with memory added.

04/08/2018 1.3E The chart in Chapter 7 updated.

05/14/2020 1.4E GPIO Primitive updated.

GW1N-6, GW1NR-6 devices deleted.

08/27/2020 1.5E The chapter structure modified.

Chapter 4 Input/Output Logic and Chapter 5 IP Generation added.

01/07/2021 1.6E IODELAYB added.

02/02/2021 1.7E The description of MIPI_IBUF_HS and MIPI_IBUF_LP added.

GW2AN-55C and GW1NR-2 devices added.

03/25/2021 1.8E GW1NZ-2 removed.

Devices supported of MIPI_OBUF and MIPI_OBUF_A updated.

06/21/2021 1.9E GW1N-2B, GW1N-1P5, GW1N-1P5B, GW1NR-2B, GW2AN-18X and

GW2AN-9X added.

Help information removed on IP configuration GUI.

10/21/2021 1.9.1E The description of GPIO level standard updated.

11/23/2021 1.9.2E Input logic view optimized.

01/24/2022 2.0E The description of input/output buffer improved.

Sample code formatting adjusted.

Contents

UG289-2.0E i

Contents

Contents ............................................................................................................... i

List of Figures .................................................................................................... iv

List of Tables ...................................................................................................... vi

1 About This Guide ............................................................................................ 1

1.1 Purpose .............................................................................................................................. 1

1.2 Related Documents ............................................................................................................ 1

1.3 Terminology and Abbreviations ........................................................................................... 2

1.4 Support and Feedback ....................................................................................................... 2

2 GPIO Overview ................................................................................................ 3

3 Input/Output Buffer ......................................................................................... 5

3.1 GPIO Level Standard.......................................................................................................... 5

3.2 GPIO Banking ..................................................................................................................... 6

3.3 Power Supply Requirements .............................................................................................. 6

3.3.1 LVCMOS Buffer Configuration ......................................................................................... 6

3.3.2 Differential Buffer Configuration....................................................................................... 7

3.4 Emulated Differential Circuit Matching Network ................................................................. 7

3.4.1 Emulated LVDS ............................................................................................................... 7

3.4.2 Emulated LVPECL ........................................................................................................... 7

3.4.3 Emulated RSDS ............................................................................................................... 8

3.4.4 Emulated BLVDS ............................................................................................................. 8

3.5 GPIO Software Configuration ............................................................................................. 9

3.5.1 Location ........................................................................................................................... 9

3.5.2 Level Standard ................................................................................................................. 9

3.5.3 Drive Strength .................................................................................................................. 9

3.5.4 Pull Up/Pull Down ............................................................................................................ 9

3.5.5 Voltage Reference ........................................................................................................... 9

3.5.6 Hysteresis ........................................................................................................................ 9

3.5.7 Open Drain ...................................................................................................................... 9

3.5.8 Slew Rate ........................................................................................................................ 9

3.5.9 Termination Matching Resistors for Single-ended Signal .............................................. 10

3.5.10 Termination Matching Resistor for Differential Signal .................................................. 10

Contents

UG289-2.0E ii

3.6 GPIO Primitive .................................................................................................................. 10

3.6.1 IBUF ............................................................................................................................... 10

3.6.2 OBUF ............................................................................................................................. 11

3.6.3 TBUF.............................................................................................................................. 12

3.6.4 IOBUF ............................................................................................................................ 13

3.6.5 LVDS Input Buffer .......................................................................................................... 14

3.6.6 LVDS Ouput Buffer ........................................................................................................ 16

3.6.7 LVDS Tristate Buffer ...................................................................................................... 18

3.6.8 LVDS Inout Buffer .......................................................................................................... 20

3.6.9 MIPI_IBUF ..................................................................................................................... 22

3.6.10 MIPI_OBUF ................................................................................................................. 24

3.6.11 MIPI_OBUF_A ............................................................................................................. 26

3.6.12 I3C_IOBUF .................................................................................................................. 28

3.6.13 MIPI_IBUF_HS/MIPI_IBUF_LP ................................................................................... 29

4 Input/Output Logic ........................................................................................ 32

4.1 SDR Mode ........................................................................................................................ 33

4.2 DDR Mode Input Logic ..................................................................................................... 33

4.2.1 IDDR .............................................................................................................................. 33

4.2.2 IDDRC ........................................................................................................................... 35

4.2.3 IDES4 ............................................................................................................................ 37

4.2.4 IDES8 ............................................................................................................................ 40

4.2.5 IDES10 .......................................................................................................................... 43

4.2.6 IVIDEO ........................................................................................................................... 46

4.2.7 IDES16 .......................................................................................................................... 49

4.2.8 IDDR_MEM .................................................................................................................... 53

4.2.9 IDES4_MEM .................................................................................................................. 56

4.2.10 IDES8_MEM ................................................................................................................ 59

4.3 DDR Mode Output Logic .................................................................................................. 63

4.3.1 ODDR ............................................................................................................................ 63

4.3.2 ODDRC .......................................................................................................................... 66

4.3.3 OSER4 ........................................................................................................................... 69

4.3.4 OSER8 ........................................................................................................................... 72

4.3.5 OSER10 ......................................................................................................................... 76

4.3.6 OVIDEO ......................................................................................................................... 79

4.3.7 OSER16 ......................................................................................................................... 82

4.3.8 ODDR_MEM .................................................................................................................. 86

4.3.9 OSER4_MEM ................................................................................................................ 89

4.3.10 OSER8_MEM .............................................................................................................. 94

4.4 Delay Module .................................................................................................................... 99

Contents

UG289-2.0E iii

4.4.1 IODELAY ....................................................................................................................... 99

4.4.2 IODELAYC ................................................................................................................... 101

4.4.3 IODELAYB ................................................................................................................... 104

4.5 IEM.................................................................................................................................. 107

5 IP Generation ............................................................................................... 110

5.1 IP Configuration .............................................................................................................. 110

5.2 IP Generation Files ......................................................................................................... 112

List of Figures

UG289-2.0E iv

List of Figures

Figure 2-1 IOB Structure View ........................................................................................................... 3

Figure 3-1 LVDS25E Matching Network ............................................................................................ 7

Figure 3-2 LVPECL Matching Network .............................................................................................. 7

Figure 3-3 RSDSE Matching Network ............................................................................................... 8

Figure 3-4 BLVDS Matching Network ................................................................................................ 8

Figure 3-5 IBUF Port Diagram ........................................................................................................... 10

Figure 3-6 OBUF Port Diagram ......................................................................................................... 11

Figure 3-7 TBUF Port Diagram .......................................................................................................... 12

Figure 3-8 IOBUF Port Diagram ........................................................................................................ 13

Figure 3-9 TLVDS_IBUF/ELVDS_IBUF Port Diagram ....................................................................... 14

Figure 3-10 TLVDS_OBUF/ELVDS_OBUF Port Diagram ................................................................. 16

Figure 3-11 TLVDS_TBUF/ELVDS_TBUF Port Diagram ................................................................... 18

Figure 3-12 TLVDS_IOBUF/ELVDS_IOBUF Port Diagram ............................................................... 20

Figure 3-13 MIPI_IBUF Port Diagram ................................................................................................ 22

Figure 3-14 MIPI_OBUF Port Diagram .............................................................................................. 25

Figure 3-15 MIPI_OBUF_A Port Diagram .......................................................................................... 26

Figure 3-16 I3C_IOBUF Port Diagram ............................................................................................... 28

Figure 3-17 MIPI_IBUF_HS/MIPI_IBUF_LP Port Diagram ................................................................ 30

Figure 4-1 I/O Logic View-Output ...................................................................................................... 32

Figure 4-2 I/O Logic View-Input ......................................................................................................... 33

Figure 4-3 IDDR Logic Diagram ......................................................................................................... 33

Figure 4-4 IDDR Timing Diagram ....................................................................................................... 34

Figure 4-5 IDDR Port Diagram ........................................................................................................... 34

Figure 4-6 IDDRC Port Diagram ........................................................................................................ 36

Figure 4-7 CALIB Timing Diagram ..................................................................................................... 38

Figure 4-8 IDES4 Port Diagram ......................................................................................................... 38

Figure 4-9 IDES8 Port Diagram ......................................................................................................... 41

Figure 4-10 IDES10 Port Diagram ..................................................................................................... 44

Figure 4-11 IVIDEO Port Diagram ..................................................................................................... 47

Figure 4-12 IDES16 Port Diagram ..................................................................................................... 50

Figure 4-13 IDDR_MEM Port Diagram .............................................................................................. 54

Figure 4-14 IDES4_MEM Port Diagram ............................................................................................ 57

List of Figures

UG289-2.0E v

Figure 4-15 IDES8_MEM Port Diagram ............................................................................................ 60

Figure 4-16 ODDR Logic Diagram ..................................................................................................... 63

Figure 4-17 ODDR Timing Diagram ................................................................................................... 64

Figure 4-18 ODDR Port Diagram ....................................................................................................... 64

Figure 4-19 ODDRC Logic Diagram .................................................................................................. 66

Figure 4-20 ODDRC Port Diagram .................................................................................................... 67

Figure 4-21 OSER4 Logic Diagram ................................................................................................... 69

Figure 4-22 OSER4 Port Diagram ..................................................................................................... 69

Figure 4-23 OSER8 Logic Diagram ................................................................................................... 73

Figure 4-24 OSER8 Port Diagram ..................................................................................................... 73

Figure 4-25 OSER10 Port Diagram ................................................................................................... 77

Figure 4-26 OVIDEO Port Diagram ................................................................................................... 80

Figure 4-27 OSER16 Port Diagram ................................................................................................... 83

Figure 4-28 ODDR_MEM Logic Diagram .......................................................................................... 86

Figure 4-29 ODDR_MEM Port Diagram ............................................................................................ 87

Figure 4-30 OSER4_MEM Logic Diagram ......................................................................................... 90

Figure 4-31 OSER4_MEM Diagram .................................................................................................. 90

Figure 4-32 OSER8_MEM Logic Diagram ......................................................................................... 94

Figure 4-33 OSER8_MEM Port Diagram ........................................................................................... 95

Figure 4-34 IODELAY Port Diagram .................................................................................................. 99

Figure 4-35 IODELAYC Port Diagram ............................................................................................... 101

Figure 4-36 IODELAYB Diagram ....................................................................................................... 104

Figure 4-37 IODELAYB Port Diagram ................................................................................................ 105

Figure 4-38 IEM Port Diagram ........................................................................................................... 107

Figure 5-1 IP Customization of DDR .................................................................................................. 110

List of Tables

UG289-2.0E vi

List of Tables

Table 1-1 Abbreviations and Terminology .......................................................................................... 2

Table 3-1 IBUF Port Description ........................................................................................................ 10

Table 3-2 OBUF Port Description ....................................................................................................... 11

Table 3-3 TBUF Port Description ....................................................................................................... 12

Table 3-4 IOBUF Port Description...................................................................................................... 13

Table 3-5 TLVDS_IBUF/ELVDS_IBUF Port Description .................................................................... 15

Table 3-6 TLVDS_OBUF/ELVDS_OBUF Port Description ................................................................ 16

Table 3-7 TLVDS_TBUF/ELVDS_TBUF Port Description .................................................................. 18

Table 3-8 TLVDS_IOBUF Devices Supported ................................................................................... 20

Table 3-9 TLVDS_IOBUF/ELVDS_IOBUF Port Description .............................................................. 21

Table 3-10 MIPI_IBUF Devices Supported ........................................................................................ 22

Table 3-11 MIPI_IBUF Port Description ............................................................................................. 22

Table 3-12 MIPI_OBUF Devices Supported ...................................................................................... 24

Table 3-13 MIPI_OBUF Port Description ........................................................................................... 25

Table 3-14 MIPI_OBUF_A Devices Supported (Added) .................................................................... 26

Table 3-15 MIPI_OBUF_A Port Description ....................................................................................... 26

Table 3-16 I3C_IOBUF Devices Supported ....................................................................................... 28

Table 3-17 I3C_IOBUF Port Description ............................................................................................ 28

Table 3-18 MIPI_IBUF_HS/MIPI_IBUF_LP Devices Supported ........................................................ 29

Table 3-19 MIPI_IBUF_HS Port Description ...................................................................................... 30

Table 3-20 MIPI_IBUF_LP Port Description ...................................................................................... 30

Table 4-1 IDDR Port Description ........................................................................................................ 34

Table 4-2 IDDR Parameter Description ............................................................................................. 34

Table 4-3 IDDRC Port Description ..................................................................................................... 36

Table 4-4 IDDRC Parameter Description ........................................................................................... 36

Table 4-5 IDES4 Port Description ...................................................................................................... 38

Table 4-6 IDES4 Parameter Description ............................................................................................ 39

Table 4-7 IDES8 Port Description ...................................................................................................... 41

Table 4-8 IDES8 Parameter Description ............................................................................................ 41

Table 4-9 IDES10 Port Description .................................................................................................... 44

Table 4-10 IDES10 Parameter Description ........................................................................................ 44

Table 4-11 IVIDEO Port Description ................................................................................................... 47

List of Tables

UG289-2.0E vii

Table 4-12 IVIDEO Parameter Description ........................................................................................ 47

Table 4-13 IDES16 Devices Supported ............................................................................................. 49

Table 4-14 IDES16 Port Description .................................................................................................. 50

Table 4-15 IDES10 Parameter Description ........................................................................................ 50

Table 4-16 IDDR_MEM Devices Supported ...................................................................................... 53

Table 4-17 IDDR_MEM Port Description ........................................................................................... 54

Table 4-18 IDDR_MEM Parameter Description ................................................................................. 54

Table 4-19 IDES4_MEM Devices Supported ..................................................................................... 56

Table 4-20 IDES4_MEM Port Description .......................................................................................... 57

Table 4-21 IDES4_MEM Parameter Description ............................................................................... 57

Table 4-22 IDES8_MEM Devices Supported ..................................................................................... 59

Table 4-23 IDES8_MEM Port Description .......................................................................................... 60

Table 4-24 IDES8_MEM Parameters Description .............................................................................. 61

Table 4-25 ODDR Port Description .................................................................................................... 64

Table 4-26 ODDR Parameter Description .......................................................................................... 64

Table 4-27 ODDRC Port Description ................................................................................................. 67

Table 4-28 ODDRC Parameter Description ....................................................................................... 67

Table 4-29 OSER4 Port Description .................................................................................................. 70


Table 4-31 OSER4 Port Description .................................................................................................. 73


Table 4-33 OSER10 Port Description ................................................................................................ 77

Table 4-34 OSER10 Parameter Description ...................................................................................... 77

Table 4-35 OVIDEO Port Description ................................................................................................ 80

Table 4-36 OVIDEO Parameter Description ...................................................................................... 80

Table 4-37 OSER16 Devices Supported ........................................................................................... 82

Table 4-38 OSER16 Port Description ................................................................................................ 83

Table 4-39 OSER16 Parameter Description ...................................................................................... 83

Table 4-40 ODDR_MEM Devices Supported ..................................................................................... 86

Table 4-41 ODDR_MEM Port Description ......................................................................................... 87

Table 4-42 ODDR_MEM Parameter Description ............................................................................... 87

Table 4-43 OSER4_MEM Devices Supported ................................................................................... 89

Table 4-44 OSER4_MEM Port Description ........................................................................................ 90

Table 4-45 OSER4_MEM Parameter Description .............................................................................. 91

Table 4-46 OSER8_MEM Devices Supported ................................................................................... 94

Table 4-47 OSER4_MEM Port Description ........................................................................................ 95

Table 4-48 OSER4_MEM Parameter Description .............................................................................. 95

Table 4-49 IODELAY Port Description ............................................................................................... 99

Table 4-50 IODELAY Parameter Description ..................................................................................... 100

Table 4-51 IODELAYC Devices Supported ........................................................................................ 101

List of Tables

UG289-2.0E viii

Table 4-52 IODELAYC Port Description............................................................................................. 101

Table 4-53 IODELAYC Parameter Description .................................................................................. 102

Table 4-54 Devices Supported ........................................................................................................... 104

Table 4-55 IODELAYB Port Description ............................................................................................. 105

Table 4-56 IODELAYB Parameter Description .................................................................................. 105

Table 4-57 IEM Port Description ........................................................................................................ 108

Table 4-58 IEM Parameter Description .............................................................................................. 108

1 About This Guide 1.1 Purpose

UG289-2.0E 1(112)

1 About This Guide

1.1 Purpose Gowin Programmable IO (GPIO) User Guide provides descriptions of

the level standard, banking of the input/output buffer, and input/output logic functions supported by GOWINSEMI FPGA products. Gowin GPIO architecture and Gowin Software usage are also provided to help you better understand the GPIO functions and rules.

1.2 Related Documents The latest user guides are available on the GOWINSEMI Website.

You can find the related documents at www.gowinsemi.com:

DS100, GW1N series of FPGA Products Data Sheet

DS117, GW1NR series of FPGA Products Data Sheet

DS821, GW1NS series of FPGA Products Data Sheet

DS841, GW1NZ series of FPGA Products Data Sheet

DS861, GW1NSR series of FPGA Products Data Sheet

DS871, GW1NSE series of SecureFPGA Products Data Sheet

DS881, GW1NSER series of SecureFPGA Products Data Sheet

DS891, GW1NRF series of Bluetooth FPGA Products Data Sheet

DS102, GW2A series of FPGA Products Data Sheet

DS226, GW2AR series of FPGA Products Data Sheet

DS961, GW2ANR series of FPGA Products Data Sheet

DS971, GW2AN-18X & 9X Data Sheet

DS976, GW2AN-55 Data Sheet

http://www.gowinsemi.com/en/

http://cdn.gowinsemi.com.cn/DS100E.pdf


http://cdn.gowinsemi.com.cn/DS117-2.8_GW1NR系列FPGA产品数据手册.pdf




http://cdn.gowinsemi.com.cn/DS861-1.4.2_GW1NSR系列FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS871-1.01_GW1NSE系列安全FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS881-1.01_GW1NSER系列安全FPGA产品数据手册.pdf



http://cdn.gowinsemi.com.cn/DS102-2.1.2_GW2A系列FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS226-1.8.1_GW2AR系列FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS961-1.0_GW2ANR系列FPGA产品数据手册.pdf



1 About This Guide 1.3 Terminology and Abbreviations

UG289-2.0E 2(112)

1.3 Terminology and Abbreviations Table 1-1 shows the abbreviations and terminology used in this

manual.

Table 1-1 Abbreviations and Terminology

Terminology and Abbreviations Meaning

IOB Input/Output Block

I/O Buffer Input/Output Buffer

I/O Logic Input/Output Logic

CFU Configurable Function Unit

CRU Configurable Routing Unit

Slew Rate Slew Rate

Bus Keeper Bus Keeper

Open Drain Open Drain

SDR Single Data Rate

DDR Double Data Rate

SER Serializer

DES Deserializer

TLDO True LVDS Output

ELDO Emulated LVDS Output

GPIO Gowin Programmable Input/Output

1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive

technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways.

Website: www.gowinsemi.com

E-mail: [email protected]

http://www.gowinsemi.com/en/

mailto:[email protected]

2 GPIO Overview

UG289-2.0E 3(112)

2 GPIO Overview

Gowin GPIO meets a variety of I/O standards and supports both single-ended and differential level standards, providing an easy connection with external buses, storage devices, video applications, and other standards.

The basic blocks of the GPIO in the GOWINSEMI FPGA products are IOB, including I/O buffer, I/O logic, and the relevant programmable routing unit. The programmable routing unit is similar to the CRU in CFU.

As shown in Figure 2-1, each IOB contains two pins (A and B). They can be used as a differential pair or as a single-end input/output. The I/O buffer supports both single-ended and differential standards. The I/O logic supports deserializer, serializer, delay control, and byte alignment, and is suitable for high-speed data transmission. The programmable routing unit is used to inter-connect I/O blocks with other on-chip resources.

Figure 2-1 IOB Structure View

PAD B

Buffer Pair A & B

True Comp

PAD A

Routing

Differential Pair

IO Logic

A

IO Logic

B

TO

DO

DI

TO

DO

DI

Rou

ting

Ou

tput

CLK

Rou

ting

Inpu

t

Rou

ting

Ou

tput

CLK

Rou

ting

Inpu

t

2 GPIO Overview

UG289-2.0E 4(112)

The features of the input/output blocks in Gowin FPGA series are:

VCCO is supplied based on bank.

Supports LVCMOS, PCI, LVTTL, LVDS, SSTL, and HSTL.

Some devices [1] support MIPI level standard and MIPI I3C OpenDrain/PushPull conversion.

Support input hysteresis option

Support output drive strength option

Support output slew rate option

Support individual bus keeper, pull-up/down resistor, and open drain output options

Support hot socket

I/O logic supports SDR mode and DDR mode, etc.

Note!

[1]: For devices that support MIPI and I3C, please refer to the devices supported of 3.6.9, 3.6.10 and 3.6.12.

3 Input/Output Buffer 3.1 GPIO Level Standard

UG289-2.0E 5(112)

3 Input/Output Buffer

3.1 GPIO Level Standard GOWINSEMI FPGA products support both single-ended and

differential standards. The single-ended standard can use built-in IO voltage as a reference voltage or any I/O voltage as an external reference voltage input. All banks in GOWINSEMI FPGA products support differential input. Emulated LVDS differential output is implemented by using external resistors and differential LVCMOS buffer output. For banks supporting true LVDS differential output and differential input matching, please refer to 3.2 GPIO Banking for more details.

For the pin voltage requirements for different level standards supported by GOWINSEMI FPGA products, please refer to the "I/O Level Standards" section in the corresponding data sheets:

DS100, GW1N series of FPGA Products Data Sheet

DS117, GW1NR series of FPGA Products Data Sheet

DS821, GW1NS series of FPGA Products Data Sheet

DS841, GW1NZ series of FPGA Products Data Sheet

DS861, GW1NSR series of FPGA Products Data Sheet

DS871, GW1NSE series of SecureFPGA Products Data Sheet

DS881, GW1NSER series of SecureFPGA Products Data Sheet

DS891, GW1NRF series of Bluetooth FPGA Products Data Sheet

DS102, GW2A series of FPGA Products Data Sheet

DS226, GW2AR series of FPGA Products Data Sheet

DS961, GW2ANR series of FPGA Products Data Sheet

DS971, GW2AN-18X & 9X Data Sheet

DS976, GW2AN-55 Data Sheet



http://cdn.gowinsemi.com.cn/DS117-2.8_GW1NR系列FPGA产品数据手册.pdf




http://cdn.gowinsemi.com.cn/DS861-1.4.2_GW1NSR系列FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS871-1.01_GW1NSE系列安全FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS881-1.01_GW1NSER系列安全FPGA产品数据手册.pdf



http://cdn.gowinsemi.com.cn/DS102-2.1.2_GW2A系列FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS226-1.8.1_GW2AR系列FPGA产品数据手册.pdf


http://cdn.gowinsemi.com.cn/DS961-1.0_GW2ANR系列FPGA产品数据手册.pdf



3 Input/Output Buffer 3.2 GPIO Banking

UG289-2.0E 6(112)

3.2 GPIO Banking The generic attributes of GPIO are:

All banks support emulated LVDS differential output using external resistance.

All banks support pull up, pull down, and bus-keeper settings.

Each bank supports one kind of pin voltage.

Each bank supports one reference voltage signal, whether it is from an external pin or from the internal reference voltage generator.

3.3 Power Supply Requirements GOWINSEMI FPGA products can be powered and operated when VCC

and VCCO reach a certain threshold and POR is set. By default, the GPIO is tristate input weak pull-up for blank chips. There are no power-on and power-off sequence requirements for core voltage and pin voltage for GOWINSEMI FPGA products.

Each bank supports one reference voltage input (VREF). Any I/O in one Bank can be configured as an input reference voltage. To support SSTL and HSTL, the reference voltage can be set as half of the I/O voltage. The input reference voltage can also be generated by the internal reference voltage generator. The internal reference voltage generator and the external reference voltage cannot be effective at the same time because each bank has only one reference voltage.

The GOWINSEMI FPGA GPIO includes two input/output pins, marked as A and B respectively. Pin A corresponds to the T (True) of the differential pair, and Pin B corresponds to the C (Comp) of the differential pair.

3.3.1 LVCMOS Buffer Configuration

All GPIOs contain LVCMOS buffers. These LVCMOS buffers can be configured in a variety of modes to support different applications. Each LVCMOS buffer can be configured as weak pull-up, weak pull-down, and bus-keeper. The pull-up and pull-down offer a fixed characteristic, which is useful when creating wired logic such as wired ORs. The bus-keeper latches the signal in the last driven state, holding it at a valid level with minimal power consumption. Input leakage can be reduced by turning off the bus-hold circuit.

All LVCMOS buffers have programmable drive strength. Please refer to the corresponding data sheets for the detailed drive strength of different IO standards. The drive strength of GOWINSEMI FPGA products is guaranteed with minimum drive strength for each drive setting.

The de-hysteresis setting is used to prevent quick successive changes of levels in a noisy environment. All LVCMOS buffers support the de-hysteresis setting.

The slew rate setting takes effect at both the rising edge and the falling edges. The LVCMOS buffer can be configured for either low noise (SLOW) or high speed performance (FAST).

3 Input/Output Buffer 3.4 Emulated Differential Circuit Matching Network

UG289-2.0E 7(112)

When a differential pair is configured as two single-ended pins, the relative delay between the two pins is maintained at a minimum, and the signal consistency is the best.

3.3.2 Differential Buffer Configuration

When a GPIO buffer is configured as a differential receiver, the input de-hysteresis and bus-hold will be disabled for the buffer.

BANK0 in GW1N devices supports on-chip programmable 100 Ohm input differential matched resistance.

BANK0/1 in GW2A devices supports on-chip programmable 100 Ohm input differential matched resistance.

All the single-ended GPIO buffer pairs can be configured to support emulated LVDS differential output standards, such as LVPECL33E, MLVDS25E, BLVDS25E, etc. An off-chip impedance matching network is also required.

3.4 Emulated Differential Circuit Matching Network

3.4.1 Emulated LVDS

GOWINSEMI FPGA products can build compatible LVCMOS output standards via the complementary LVCMOS output and external matching network. Figure 3-1 shows the external matching network.

Figure 3-1 LVDS25E Matching Network

+

-

On chip On chipOff chip

8mA

8mA

2.5V

2.5V158ohm

158ohm

14

0o

hm

10

0o

hm

3.4.2 Emulated LVPECL

GOWINSEMI FPGA products can build compatible LVPECL output standards via the complementary LVCMOS output and external matching network. Figure 3-2 shows the external matching network.

Figure 3-2 LVPECL Matching Network

+

-


16mA

16mA

3.3V

3.3V93ohm

93ohm

19

6o

hm

10

0o

hm

3 Input/Output Buffer 3.4 Emulated Differential Circuit Matching Network

UG289-2.0E 8(112)

3.4.3 Emulated RSDS

GOWINSEMI FPGA products can build compatible RSDS output standards via the complementary LVCMOS output and external matching network. Figure 3-3 shows the external matching network.

Figure 3-3 RSDSE Matching Network

+

-


8mA

8mA

2.5V

2.5V

12

1o

hm

10

0o

hm

294ohm

294ohm

3.4.4 Emulated BLVDS

GOWINSEMI FPGA products can build compatible BLVDS output standards via the complementary LVCMOS output and external matching network. Figure 3-4 shows the external matching network.

Figure 3-4 BLVDS Matching Network

16mA

16mA

2.5V

2.5V

16mA

16mA

2.5V

2.5V

16mA

16mA

2.5V

2.5V

16mA

16mA

2.5V

2.5V

+

-

+

-

+

-

+

-

80ohm

80ohm

80ohm

80ohm

80ohm

80ohm

80ohm

80ohm

45o

hm

~9

0o

hm

45o

hm

~9

0o

hm

3 Input/Output Buffer 3.5 GPIO Software Configuration

UG289-2.0E 9(112)

3.5 GPIO Software Configuration You can set GPIO location, attributes, etc. through Floorplanner in

Gowin Software, or you can customize the CST file to achieve this. The following is a detailed description of the physical constraints supported by CST files.

3.5.1 Location

Lock the physical location of GPIO:

IO_LOC "xxx" H4 exclusive;

3.5.2 Level Standard

Set the level standard for GPIO:

IO_PORT "xxx" IO_TYPE=LVCMOS18D;

3.5.3 Drive Strength

Set the drive strength of output pins or IO pins:

IO_PORT "xxx" DRIVE=12;

3.5.4 Pull Up/Pull Down

Set pull up/down modes, such as UP (pull-up), DOWN (pull down), KEEPER (bus-hold), and NONE (high impedance).

IO_PORT "xxx" PULL_MODE=DOWN;

3.5.5 Voltage Reference

Set reference voltage for GPIO. The reference voltage can be from external pins or internal reference voltage generator.

IO_PORT "xxx" VREF=VREF1_LOAD;

3.5.6 Hysteresis

Set the hysteresis value for input pins or bidirectional IO pins. The value is NONE, H2L, L2H, HIGH from small to large in sequence.

IO_PORT "xxx" HYSTERESIS=L2H;

3.5.7 Open Drain

Open Drain is available for both output and bidirectional IO pins. The values are ON and OFF.

IO_PORT "xxx" OPEN_DRAIN=ON;

3.5.8 Slew Rate

Specify slew rate for output pins or bidirectional IO pins. SLOW: low noise mode. FAST: high speed mode.

IO_PORT "xxx" SLEW_RATE=SLOW;

3 Input/Output Buffer 3.6 GPIO Primitive

UG289-2.0E 10(112)

3.5.9 Termination Matching Resistors for Single-ended Signal

Set termination matching resistors for single-ended signals. The values are OFF and 100 ohm.

IO_PORT "xxx" SINGLE_RESISTOR=100;

3.5.10 Termination Matching Resistor for Differential Signal

Set termination matching resistors for differential signals. The values are OFF and 100 ohm.

IO_PORT "xxx" Diff_RESISTOR=100;

3.6 GPIO Primitive IO Buffer with buffer function includes normal buffer, emulated LVDS,

and true LVDS.

3.6.1 IBUF

Primitive Introduction

Input Buffer (IBUF)

Port Diagram

Figure 3-5 IBUF Port Diagram

I OIBUF

Port Description

Table 3-1 IBUF Port Description

Port I/O Description

I Input Data input signal

O Output Data output signal

Primitive Instantiation

Verilog Instantiation:

IBUF uut(

.O(O),

.I(I)

);

Vhdl Instantiation:

COMPONENT IBUF

PORT (

O:OUT std_logic;


UG289-2.0E 11(112)

I:IN std_logic

);

END COMPONENT;

uut:IBUF

PORT MAP (

O=>O,

I=>I

);

3.6.2 OBUF


Output Buffer (OBUF).

Port Diagram

Figure 3-6 OBUF Port Diagram

I OOBUF

Port Description

Table 3-2 OBUF Port Description






OBUF uut(

.O(O),

.I(I)

);

Vhdl Instantiation:

COMPONENT OBUF

PORT (

O:OUT std_logic;

I:IN std_logic

);


UG289-2.0E 12(112)

END COMPONENT;

uut:OBUF

PORT MAP (

O=>O,

I=>I

);

3.6.3 TBUF


Output Buffer with Tristate Control (TBUF), active-low.

Port Diagram

Figure 3-7 TBUF Port Diagram

OENOTBUF

I

Port Description

Table 3-3 TBUF Port Description



OEN Input Output tristate enable signal




TBUF uut(

.O(O),

.I(I),

.OEN(OEN)

);

Vhdl Instantiation:

COMPONENT TBUF

PORT (


UG289-2.0E 13(112)

O:OUT std_logic;

I:IN std_logic;

OEN:IN std_logic

);

END COMPONENT;

uut:TBUF

PORT MAP (

O=>O,

I=>I,

OEN=>OEN

);

3.6.4 IOBUF


Bi-Directional Buffer (IOBUF) is used as an input buffer when OEN is high and is used as an output buffer when ONE is low.

Port Diagram

Figure 3-8 IOBUF Port Diagram

OEN

OIOBUF

I

IO

Port Description

Table 3-4 IOBUF Port Description




IO Inout Input and output signals, bidirectional.




IOBUF uut(

.O(O),

.IO(IO),

.I(I),


UG289-2.0E 14(112)

.OEN(OEN)

);

Vhdl Instantiation:

COMPONENT IOBUF

PORT (

O:OUT std_logic;

IO:INOUT std_logic;

I:IN std_logic;

OEN:IN std_logic

);

END COMPONENT;

uut:IOBUF

PORT MAP(

O=>O,

IO=>IO,

I=>I,

OEN=> OEN

);

3.6.5 LVDS Input Buffer


LVDS includes TLVDS_IBUF and ELVDS_IBUF.

True LVDS Input Buffer (TLVDS_IBUF).

Note!

GW1NZ-1 and GW1N-1S do not support TLVDS_IBUF.

Emulated LVDS Input Buffer (ELVDS_IBUF).

Note!

GW1NZ-1 does not support ELVDS_IBUF.

Port Diagram

Figure 3-9 TLVDS_IBUF/ELVDS_IBUF Port Diagram

IO

IB

+

-

TLVDS_IBUF/

ELVDS_IBUF


UG289-2.0E 15(112)

Port Description

Table 3-5 TLVDS_IBUF/ELVDS_IBUF Port Description


I Input Differential input A port signal

IB Input Differential input B port signal



Example One


TLVDS_IBUF uut(

.O(O),

.I(I),

.IB(IB)

);

Vhdl Instantiation:

COMPONENT TLVDS_IBUF

PORT (

O:OUT std_logic;

I:IN std_logic;

IB:IN std_logic

);

END COMPONENT;

uut:TLVDS_IBUF

PORT MAP(

O=>O,

I=>I,

IB=>IB

);

Example Two


ELVDS_IBUF uut(

.O(O),

.I(I),

.IB(IB)


UG289-2.0E 16(112)

);

Vhdl Instantiation:

COMPONENT ELVDS_IBUF

PORT (

O:OUT std_logic;

I:IN std_logic;

IB:IN std_logic

);

END COMPONENT;

uut:ELVDS_IBUF

PORT MAP(

O=>O,

I=>I,

IB=>IB

);

3.6.6 LVDS Ouput Buffer


LVDS includes TLVDS_OBUF and ELVDS_OBUF.

True LVDS Output Buffer (TLVDS_OBUF).

Note!

GW1N-1, GW1NR-1, GW1NZ-1 and GW1N-1S do not support TLVDS_OBUF.

Emulated LVDS Output Buffer (ELVDS_OBUF).

Port Diagram

Figure 3-10 TLVDS_OBUF/ELVDS_OBUF Port Diagram

OB

OI

+

-

TLVDS_OBUF/

ELVDS_OBUF

Port Description

Table 3-6 TLVDS_OBUF/ELVDS_OBUF Port Description



OB Output Differential output B signal

O Output Differential output A Signal


UG289-2.0E 17(112)


Example One


TLVDS_OBUF uut(

.O(O),

.OB(OB),

.I(I)

);

Vhdl Instantiation:

COMPONENT TLVDS_OBUF

PORT (

O:OUT std_logic;

OB:OUT std_logic;

I:IN std_logic

);

END COMPONENT;

uut:TLVDS_OBUF

PORT MAP(

O=>O,

OB=>OB,

I=> I

);

Example Two


ELVDS_OBUF uut(

.O(O),

.OB(OB),

.I(I)

);

Vhdl Instantiation:

COMPONENT ELVDS_OBUF

PORT (

O:OUT std_logic;

OB:OUT std_logic;

I:IN std_logic


UG289-2.0E 18(112)

);

END COMPONENT;

uut:ELVDS_OBUF

PORT MAP(

O=>O,

OB=>OB,

I=> I

);

3.6.7 LVDS Tristate Buffer


LVDS tristate buffer includes TLVDS_TBUF and ELVDS_TBUF.

True LVDS Tristate Buffer (TLVDS_TBUF), active-low.

Note!

GW1N-1, GW1NR-1, GW1NZ-1 and GW1N-1S do not support TLVDS_TBUF.

Emulated LVDS Tristate Buffer (ELVDS_TBUF), active-low

Port Diagram

Figure 3-11 TLVDS_TBUF/ELVDS_TBUF Port Diagram

OB

OTLVDS_TBUF/

ELVDS_TBUFI

+

-

OEN

Port Description

Table 3-7 TLVDS_TBUF/ELVDS_TBUF Port Description




OB Output Differential B port output signal

O Output Differential A port output signal


Example One


TLVDS_TBUF uut(

.O(O),

.OB(OB),

.I(I),


UG289-2.0E 19(112)

.OEN(OEN)

);

Vhdl Instantiation:

COMPONENT TLVDS_TBUF

PORT (

O:OUT std_logic;

OB:OUT std_logic;

I:IN std_logic;

OEN:IN std_logic

);

END COMPONENT;

uut:TLVDS_TBUF

PORT MAP(

O=>O,

OB=>OB,

I=> I,

OEN=>OEN

);

Example Two


ELVDS_TBUF uut(

.O(O),

.OB(OB),

.I(I),

.OEN(OEN)

);

Vhdl Instantiation:

COMPONENT ELVDS_TBUF

PORT (

O:OUT std_logic;

OB:OUT std_logic;

I:IN std_logic;

OEN:IN std_logic

);

END COMPONENT;


UG289-2.0E 20(112)

uut:ELVDS_TBUF

PORT MAP(

O=>O,

OB=>OB,

I=> I,

OEN=>OEN

);

3.6.8 LVDS Inout Buffer


The LVDS inout buffer includes TLVDS_IOBUF and ELVDS_IOBUF.

True LVDS Bi-Directional Buffer (TLVDS_IOBUF) is used as true differential input buffer when OEN is high and used as true differential output buffer when OEN is low.

Devices Supported

Table 3-8 TLVDS_IOBUF Devices Supported

Product Family Series Device

Arora

GW2A GW2A-18, GW2A-18C, GW2A-55, GW2A-55C

GW2AN GW2AN-55C

GW2AR GW2AR-18,GW2AR-18C

GW2ANR GW2ANR-18C

LittleBee®

GW1N GW1N-4, GW1N-4B, GW1N-4C

GW1NR GW1NR-4, GW1NR-4B, GW1NR-4C

GW1NRF GW1NRF-4B

ELVDS_IOBUF is used as emulated differential input buffer when OEN is high and used as emulated differential output buffer when OEN is low.

Note!

The GW1NZ-1 does not support ELVDS_IOBUF.

Port Diagram

Figure 3-12 TLVDS_IOBUF/ELVDS_IOBUF Port Diagram

IOB

OTLVDS_IOBUF/

ELVDS_IOBUFI+

-

OENIO


UG289-2.0E 21(112)

Port Description

Table 3-9 TLVDS_IOBUF/ELVDS_IOBUF Port Description





IOB Inout Differential B port input/output

IO Inout Differential A port input/output



ELVDS_IOBUF uut(

.O(O),

.IO(IO),

.IOB(IOB),

.I(I),

.OEN(OEN)

);

Vhdl Instantiation:

COMPONENT ELVDS_IOBUF

PORT (

O:OUT std_logic;

IO:INOUT std_logic;

IOB:INOUT std_logic;

I:IN std_logic;

OEN:IN std_logic

);

END COMPONENT;

uut:ELVDS_IOBUF

PORT MAP(

O=>O,

IO=>IO,

IOB=>IOB,

I=> I,

OEN=>OEN

);


UG289-2.0E 22(112)

3.6.9 MIPI_IBUF


MIPI Input Buffer (MIPI_IBUF) includes HS input mode and LP bi-direction mode, and HS mode supports dynamic resistance configuration.

Devices Supported

Table 3-10 MIPI_IBUF Devices Supported


LittleBee®

GW1N GW1N-9,GW1N-9C, GW1N-2

GW1NR GW1NR-9,GW1NR-9C, GW1NR-2

GW1NS GW1NS-2, GW1NS-2C, GW1NS-4, GW1NS-4C

GW1NZ GW1NZ-2

GW1NSE GW1NSE-2C

GW1NSER GW1NSER-4C

GW1NSR GW1NSR-2, GW1NSR-2C, GW1NSR-4, GW1NSR-4C

Arora GW2AN GW2AN-18X, GW2AN-9X

Functional Description

MIPI_IBUF supports LP and HS mode. IO and IOB are connected to pad.

LP mode: Supports bi-directional. When OEN is low, I is input and IO is output; when OEN is high, IO is input and OL is output; when OENB is low, IB is input and IOB is output; when OENB is high, IOB is input and OB is output.

HS mode: IO and IOB are the differential inputs. OH is the output, then HSREN controls the termination resistor.

Port Diagram

Figure 3-13 MIPI_IBUF Port Diagram

MIPI_IBUF

IIB

OENOENB

HSREN

OHOL

IO

IOB

OB

+

-

Port Description

Table 3-11 MIPI_IBUF Port Description


I Input In LP mode, I is the input when OEN is low.


UG289-2.0E 23(112)


IB Input In LP mode, IB is the input when OENB is low.

HSREN Input In HS mode, controls termination resistance.

OEN Input In LP mode, inputs/outputs tristate control signal.

OENB Input In LP mode, inputs/outputs tristate control signal.

OH Output In HS mode, data output signal.

OL Output In LP mode, OL is the output when OEN is high.

OB Output In LP mode, OB is the output when OENB is high.

IO Inout

In LP mode, IO is output when OEN is low and input when OEN is high.

In HS mode, IO is input.

IOB Inout

In LP mode, IOB is output when OENB is low and IOB is input when OENB is high.

In HS mode, IOB is input.



MIPI_IBUF uut(

.OH(OH),

.OL(OL),

.OB(OB),

.IO(IO),

.IOB(IOB),

.I(I),

.IB(IB),

.OEN(OEN),

.OENB(OENB),

HSREN(HSREN)

);

Vhdl Instantiation:

COMPONENT MIPI_IBUF

PORT (

OH:OUT std_logic;

OL: OUT std_logic;

OB:OUT std_logic;

IO:INOUT std_logic;

IOB:INOUT std_logic;


UG289-2.0E 24(112)

I:IN std_logic;

IB:IN std_logic;

OEN:IN std_logic;

OENB:IN std_logic;

HSREN:IN std_logic

);

END COMPONENT;

uut: MIPI_IBUF

PORT MAP(

OH=>OH,

OL=>OL,

OB=>OB,

IO=>IO,

IOB=>IOB,

I=> I,

IB=>IB,

OEN=>OEN,

OENB=>OENB,

HSREN=>HSREN

);

3.6.10 MIPI_OBUF


MIPI Output Buffer (MIPI_OBUF) includes HS mode and LP mode.

MIPI_OBUF is used as (HS) MIPI output buffer when MODESEL is high and used as (LP) MIPI output buffer when MODESEL is low.

Devices Supported

Table 3-12 MIPI_OBUF Devices Supported


LittleBee®

GW1N GW1N-9,GW1N-9C

GW1NR GW1NR-9,GW1NR-9C


GW1NZ GW1NZ-2

GW1NSE GW1NSE-2C

GW1NSER GW1NSER-4C



UG289-2.0E 25(112)

Port Diagram

Figure 3-14 MIPI_OBUF Port Diagram

OBMIPI_OBUFI

+

-

MODESELO

IB

Port Description

Table 3-13 MIPI_OBUF Port Description


I Input A-ended data input signal for HS mode or LP mode

IB Input B-ended data input signal in LP mode

MODESEL Input Mode selection signal, HS or LP mode.

O Output A-ended data output signal, A differential output in HS mode, A single-ended output in LP mode.

OB Output B-ended data output signal, B differential output in HS mode, B single-ended output in LP mode.



MIPI_OBUF uut(

.O(O),

.OB(OB),

.I(I),

.IB(IB),

.MODESEL(MODESEL)

);

Vhdl Instantiation:

COMPONENT MIPI_OBUF

PORT (

O:OUT std_logic;

OB:OUT std_logic;

I:IN std_logic;

IB:IN std_logic;

MODESEL:IN std_logic

);

END COMPONENT;

uut: MIPI_OBUF

PORT MAP(


UG289-2.0E 26(112)

O=>O,

OB=>OB,

I=> I,

IB=>IB,

MDOESEL=>MODESEL

);

3.6.11 MIPI_OBUF_A


MIPI_OBUF_A includes HS mode and LP mode.

MIPI Output Buffer with IL Signal (MIPI_OBUF_A) is used as (HS) MIPI output buffer when MODESEL is high and used as (LP) MIPI output buffer when MODESEL is low. The difference with MIPI_OBUF is the addition of the IL port as an A input in LP mode.

Devices Supported

For the devices supported by MIPI_OBUF_A, apart from the devices listed in Table 3-12, you can also see the table below.

Table 3-14 MIPI_OBUF_A Devices Supported (Added)

Product Famliy Series Device

LittleBee

®

GW1N GW1N-2, GW1N-1P5, GW1N-2B, GW1N-1P5B

GW1NR GW1NR-2, GW1NR-2B

Port Diagram

Figure 3-15 MIPI_OBUF_A Port Diagram

OBMIPI_OBUF_A

I +

-

MODESEL

O

IB

IL

Port Description

Table 3-15 MIPI_OBUF_A Port Description


I Input A-ended data input signal in HS mode

IB Input B-ended data input signal in LP mode

IL Input A-ended data input signal in LP mode

MODESEL Input Mode selection signal, HS or LP mode

O Output A-ended data output signal, A differential output in HS mode, A single-ended output in LP mode.


UG289-2.0E 27(112)


OB Output B-ended data output signal, B differential output in HS mode, B single-ended output in LP mode.



MIPI_OBUF_A uut(

.O(O),

.OB(OB),

.I(I),

.IB(IB),

.IL(IL),

.MODESEL(MODESEL)

);

Vhdl Instantiation:

COMPONENT MIPI_OBUF_A

PORT (

O:OUT std_logic;

OB:OUT std_logic;

I:IN std_logic;

IB:IN std_logic;

IL: IN std_logic;


);

END COMPONENT;

uut: MIPI_OBUF_A

PORT MAP (

O=>O,

OB=>OB,

I=> I,

IB=>IB,

IL=>IL,

MDOESEL=>MODESEL

);


UG289-2.0E 28(112)

3.6.12 I3C_IOBUF


I3C Bi-Directional Buffer (I3C_IOBUF) includes Normal mode and I3C mode.

I3C_IOBUF is used as a bi-directional buffer when MODESEL is high and used as a normal buffer when MODESEL is low.

Devices Supported

Table 3-16 I3C_IOBUF Devices Supported


LittleBee®

GW1N GW1N-9,GW1N-9C

GW1NR GW1NR-9,GW1NR-9C


GW1NSE GW1NSE-2C

GW1NSER GW1NSER-4C


Port Diagram

Figure 3-16 I3C_IOBUF Port Diagram

OI3C_IOBUF

I

MODESEL

IO

Port Description

Table 3-17 I3C_IOBUF Port Description

Ports I/O Description


IO Inout Input and output signal, bidirectional.

MODESEL Input Mode selection signal, Normal mode or I3C mode




I3C_IOBUF uut(

.O(O),

.IO(IO),

.I(I),


UG289-2.0E 29(112)

.MODESEL(MODESEL)

);

Vhdl Instantiation:

COMPONENT I3C_IOBUF

PORT (

O:OUT std_logic;

IO:INOUT std_logic;

I:IN std_logic;


);

END COMPONENT;

uut: I3C_IOBUF

PORT MAP (

O=>O,

IO=>IO,

I=>I,

MDOESEL=>MODESEL

);

3.6.13 MIPI_IBUF_HS/MIPI_IBUF_LP


MIPI_IBUF_HS implements HS mode for differential input and MIPI_IBUF_LP implements LP mode via single-ended input.

Devices Supported

Table 3-18 MIPI_IBUF_HS/MIPI_IBUF_LP Devices Supported

Family Series Device

LittleBee® GW1NR GW1NR-2


You can use the combination of MIPI_IBUF_HS and MIPI_IBUF_LP to support HS and LP modes via Floorplanner. Input I of MIPI_IBUF_HS and I of MIPI_IBUF_LP should be connected to the same signal, and input IB of MIPI_IBUF_HS and IB of MIPI_IBUF_LP should be connected to the same signal.


UG289-2.0E 30(112)

Port Diagram

Figure 3-17 MIPI_IBUF_HS/MIPI_IBUF_LP Port Diagram

MIPI_IBUF_HSI

IBOH MIPI_IBUF_LP

I

IB

OL

OB

Port Description

Table 3-19 MIPI_IBUF_HS Port Description


I Input In HS mode, differential input A-ended signal.

IB Input In HS mode, differential input B-ended signal.

OH Output In HS mode, data output signal.

Table 3-20 MIPI_IBUF_LP Port Description


I Input In LP mode, A single-ended input signal.

IB Input In LP mode, B single-ended input signal.

OL Output In LP mode, A-ended output singal.

OB Output In LP mode, B-ended output singal.

Connection Rule

The output OH of MIPI_IBUF_HS can be connected to Iologic.

The output OL and OB of MIPI_IBUF_LP are not allowed to be connected to Iologic.



MIPI_IBUF_HS hs (

.OH(OH),

.I(I),

.IB(IB)

);

MIPI_IBUF_LP lp (

.OL(OL),

.OB(OB),

.I(I),

.IB(IB)


UG289-2.0E 31(112)

);

Vhdl Instantiation:

COMPONENT MIPI_IBUF_HS

PORT (

OH:OUT std_logic;

I:IN std_logic;

IB:IN std_logic

);

END COMPONENT;

COMPONENT MIPI_IBUF_LP

PORT (

OL: OUT std_logic;

OB:OUT std_logic;

I:IN std_logic;

IB:IN std_logic

);

END COMPONENT;

hs: MIPI_IBUF_HS

PORT MAP(

OH=>OH,

I=>I,

IB=>IB

);

lp: MIPI_IBUF_LP

PORT MAP(

OL=>OL,

OB=>OB,

I=>I,

IB=>IB

);

4 Input/Output Logic

UG289-2.0E 32(112)

4 Input/Output Logic

I/O logic in GOWINSEMI FPGA products supports SDR and DDR modes, etc. In each mode, pin control (or pin differential signal pairs) can be configured as output signal, input signal, bi-directional signal and tristate output signal (output signal with tristate control).

Note!

IOL6 and IOR6 pins of devices of GW1N-1, GW1NR-1, GW1NZ-1, GW1NS-2, GW1NS-2C, GW1NSR-2C, GW1NSR-2 and GW1NSE-2C do not support IO logic.

IOT2 and IOT3A pins of GW1N-2, GW1NR-2, GW1N-1P5, GW1N-2B, GW1N-1P5B, GW1NR-2B devices do not support IO logic.

IOL10 and IOR10 pins of the devices of GW1N-4, GW1N-4B, GW1NR-4, GW1NR-4B, GW1NRF-4B, GW1N-4C and GW1NR-4C do not support IO logic.

Figure 4-1 shows the output of the I/O logic in GOWINSEMI FPGA products.

Figure 4-1 I/O Logic View-Output

TRIREG

OSER

OREG

ISI

GND

IODELAY

TX

D

Q1

Q0

OTMUX

ODMUX

ODELMUX

TO

DOPAD

Logic View-Output

Figure 4-2 shows the input of the I/O logic in GOWINSEMI FPGA products.

4 Input/Output Logic 4.1 SDR Mode

UG289-2.0E 33(112)

Figure 4-2 I/O Logic View-Input

PAD

IODELAY

IDELMUX

CI

IREG

IDES

Q

DI

Q0-Qn-1

IEMLAG

LEAD

Logic View-Input

Note！

CI is the GCLK input signal and cannot connect to Fabric; DI is directly entered into Fabric.

4.1 SDR Mode The input/output logic supports SDR mode and provides input register

(IREG), output register (OREG) and tristate control register (TRIREG), the functions of which are the same as FF/LATCH in CFU. The FF/LATCH can be used as Iologic when the input D of the FF/LATCH is driven by a Buffer/IODELAY that does not drive other Iologics, or when the output Q of the FF/LATCH only drives a Buffer/IODELAY and the Buffer is not a MIPI Buffer.

4.2 DDR Mode Input Logic

4.2.1 IDDR


Input Double Data Rate (IDDR)


Output data is provided to FPGA logic at the same clock edge in IDDR mode. IDDR logic diagram is as shown in Figure 4-3 and its timing diagram is as shown in Figure 4-4.

Figure 4-3 IDDR Logic Diagram

DFFN

CLK

DQ

DFF

CLK

D

QDFF

CLK

D

Q

DFF

CLK

D

Q

CLK

D

Q0

Q1

4 Input/Output Logic 4.2 DDR Mode Input Logic

UG289-2.0E 34(112)

Figure 4-4 IDDR Timing Diagram

Port Diagram

Figure 4-5 IDDR Port Diagram

Q1IDDR

D

CLK

Q0

Port Description

Table 4-1 IDDR Port Description


D Input IDDR data input signal

CLK Input Clock input signal

Q0,Q1 Output IDDR data output signal

Parameter Description

Table 4-2 IDDR Parameter Description

Name Value Default Description

Q0_INIT 1'b0 1'b0 Initial value of Q0 output

Q1_INIT 1'b0 1'b0 Initial value of Q1 output

Connection Rule

Input D of IDDR can be directly from IBUF or from the output DO of IODELAY module.


The primitive can be instantiated directly, or generated by the IP Core Generator tool. For more information, you can refer to 5 IP Generation.


IDDR uut(


UG289-2.0E 35(112)

.Q0(Q0),

.Q1(Q1),

.D(D),

.CLK(CLK)

);

defparam uut.Q0_INIT=1'b0;


Vhdl Instantiation:

COMPONENT IDDR

GENERIC (Q0_INIT:bit:='0';

Q1_INIT:bit:='0'

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D:IN std_logic;

CLK:IN std_logic

);

END COMPONENT;

uut:IDDR

GENERIC MAP (Q0_INIT=>'0',

Q1_INIT=>'0'

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

D=>D,

CLK=>CLK

);

4.2.2 IDDRC


Dual Data Rate Input with Asynchronous Clear (IDDRC) is similar to IDDR to realize double data rate input and can be reset asynchronously.


Output data is provided to FPGA logic at the same clock edge in


UG289-2.0E 36(112)

IDDRC mode.

Port Diagram

Figure 4-6 IDDRC Port Diagram

IDDRCCLEAR

CLKQ1

DQ0

Port Description

Table 4-3 IDDRC Port Description


D Input IDDRC data input signal


CLEAR Input Asynchronous reset input signal, active-high.

Q0,Q1 Output IDDRC data output signal


Table 4-4 IDDRC Parameter Description


Q0_INIT 1'b0 1'b0 The initial value of Q0 output

Q1_INIT 1'b0 1'b0 The initial value of Q1 output

Connection Rule

Data input D of IDDRC can be directly from IBUF or from the output DO of IODELAY module.




IDDRC uut(

.Q0(Q0),

.Q1(Q1),

.D(D),

.CLK(CLK),

.CLEAR(CLEAR)

);



UG289-2.0E 37(112)

defparam uut.Q1_INIT = 1'b0;

Vhdl Instantiation:

COMPONENT IDDRC

GENERIC (Q0_INIT:bit:='0';

Q1_INIT:bit:='0'

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D:IN std_logic;

CLEAR:IN std_logic;

CLK:IN std_logic

);

END COMPONENT;

uut:IDDRC

GENERIC MAP (Q0_INIT=>'0',

Q1_INIT=>'0'

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

D=>D,

CLEAR=>CLEAR,

CLK=>CLK

);

4.2.3 IDES4


The 1 to 4 Deserializer (IDES4) is a deserializer of 1 bit serial input and 4 bits parallel output.


IDES4 mode realizes 1:4 serial parallel conversion and output data is provided to FPGA logic at the same clock edge. CALIB is supported to adjust the sequence of output data. The data is shifted by one bit per pulse. After four shifts, the data output will be the same as the data before the shift. CALIB Timing diagram is as shown in Figure 4-7.


UG289-2.0E 38(112)

Figure 4-7 CALIB Timing Diagram

Note!

The pulse width and timing of the CALIB signal in the example are for reference only and can be adjusted as needed, the pulse width is equal to or greater than TPCLK.

PCLK is usually obtained by FCLK frequency division：

1 2PCLK FCLKf f.

Port Diagram

Figure 4-8 IDES4 Port Diagram

IDES4PCLK

FCLK

RESET

Q2CALIB

D Q0

Q1

Q3

Port Description

Table 4-5 IDES4 Port Description


D Input IDES4 data input signal

FCLK Input High speed clock Input signal

PCLK Input Primary clock input signal

CALIB Input CALIB signal, used to adjust the sequence of output data, active-high.

RESET Input Asynchronous reset input signal, active-high.

Q3=Q0 Output IDES8 data output signal


UG289-2.0E 39(112)

Parameters Description

Table 4-6 IDES4 Parameter Description


GSREN "false", "true" "false" Enable global reset

LSREN "false", "true" "true" Enable local reset

Connection Rule

Data input D of IDES4 can be directly from IBUF or from the output DO of IODELAY module.




IDES4 uut(

.Q0(Q0),

.Q1(Q1),

.Q2(Q2),

.Q3(Q3),

.D(D),

.FCLK(FCLK),

.PCLK(PCLK),

.CALIB(CALIB),

.RESET(RESET)

);

defparam uut.GSREN="false";

defparam uut.LSREN ="true";

Vhdl Instantiation:

COMPONENT IDES4

GENERIC (GSREN:string:="false";

LSREN:string:="true"

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;


UG289-2.0E 40(112)

D:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IDES4

GENERIC MAP (GSREN=>"false",

LSREN=>"true"

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

Q2=>Q2,

Q3=>Q3,

D=>D,

FCLK=>FCLK,

PCLK=>PCLK,

CALIB=>CALIB,

RESET=>RESET

);

4.2.4 IDES8




IDES8 mode realizes 1:8 serial parallel conversion and output data is provided to FPGA logic at the same clock edge. CALIB is supported to adjust the sequence of output data. The data is shifted by one bit per pulse. After four shifts, the data output will be the same as the data before the shift.

PCLK is usually obtained by FCLK frequency division： 1 4PCLK FCLKf f

.


UG289-2.0E 41(112)

Port Diagram


IDES8PCLK

FCLK

RESET

Q4CALIB

DQ0

Q2

Q6

Q1

Q3

Q5

Q7

Port Description




FCLK Input High speed clock input signal


CALIB Input CALIB input signal, used to adjust the sequence of output data, active-high.








Connection Rule

Data input D of IDES8 can be directly from IBUF or from DO in IODELAY module.




IDES8 uut(

.Q0(Q0),

.Q1(Q1),

.Q2(Q2),


UG289-2.0E 42(112)

.Q3(Q3),

.Q4(Q4),

.Q5(Q5),

.Q6(Q6),

.Q7(Q7),

.D(D),

.FCLK(FCLK),

.PCLK(PCLK),

.CALIB(CALIB),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT IDES8



);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;

Q4:OUT std_logic;

Q5:OUT std_logic;

Q6:OUT std_logic;

Q7:OUT std_logic;

D:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IDES8


UG289-2.0E 43(112)


LSREN=>"true"

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

Q2=>Q2,

Q3=>Q3,

Q4=>Q4,

Q5=>Q5,

Q6=>Q6,

Q7=>Q7,

D=>D,

FCLK=>FCLK,

PCLK=>PCLK,

CALIB=>CALIB,

RESET=>RESET

);

4.2.5 IDES10




IDES10 mode realizes 1:10 serial parallel conversion and output data is provided to FPGA logic at the same clock edge. CALIB is supported to adjust the sequence of output data. The data is shifted by one bit per pulse. After ten shifts, the data output will be the same as the data before the shift.


1 5PCLK FCLKf f.


UG289-2.0E 44(112)

Port Diagram


IDES10PCLK

FCLK

RESET

Q5CALIB

DQ1

Q3

Q7

Q2

Q4

Q6

Q8

Q0

Q9

Port Description














Connection Rule





IDES10 uut(

.Q0(Q0),

.Q1(Q1),


UG289-2.0E 45(112)

.Q2(Q2),

.Q3(Q3),

.Q4(Q4),

.Q5(Q5),

.Q6(Q6),

.Q7(Q7),

.Q8(Q8),

.Q9(Q9),

.D(D),

.FCLK(FCLK),

.PCLK(PCLK),

.CALIB(CALIB),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT IDES10



);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;

Q4:OUT std_logic;

Q5:OUT std_logic;

Q6:OUT std_logic;

Q7:OUT std_logic;

Q8:OUT std_logic;

Q9:OUT std_logic;

D:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;


UG289-2.0E 46(112)

CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IDES10


LSREN=>"true"

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

Q2=>Q2,

Q3=>Q3,

Q4=>Q4,

Q5=>Q5,

Q6=>Q6,

Q7=>Q7,

Q8=>Q8,

Q9=>Q9,

D=>D,

FCLK=>FCLK,

PCLK=>PCLK,

CALIB=>CALIB,

RESET=>RESET

);

4.2.6 IVIDEO


The 1 to 7 Deserializer ( IVIDEO ) is a deserializer of 1 bit serial input and 7 bits parallel output.


IVIDEO mode realizes 1:7 serial parallel conversion and output data is provided to FPGA logic at the same clock edge. CALIB is supported to adjust the sequence of output data. The data is shifted by two bits per pulse. After seven shifts, the data output will be the same as the data before the shift.



UG289-2.0E 47(112)

1 3.5PCLK FCLKf f.

Port Diagram

Figure 4-11 IVIDEO Port Diagram

IVIDEOPCLK

FCLK

RESET

Q2

CALIB

D

Q4

Q1

Q3

Q5

Q0

Q6

Port Description

Table 4-11 IVIDEO Port Description


D Input IVIDEO data input signal





Q6~Q0 Output IVIDEO data output signal


Table 4-12 IVIDEO Parameter Description




Connection Rule

Data input D of IVIDEO can be directly from IBUF or from DO in IODELAY module.




IVIDEO uut(

.Q0(Q0),


UG289-2.0E 48(112)

.Q1(Q1),

.Q2(Q2),

.Q3(Q3),

.Q4(Q4),

.Q5(Q5),

.Q6(Q6),

.D(D),

.FCLK(FCLK),

.PCLK(PCLK),

.CALIB(CALIB),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT IVIDEO



);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;

Q4:OUT std_logic;

Q5:OUT std_logic;

Q6:OUT std_logic;

D:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IVIDEO


UG289-2.0E 49(112)


LSREN=>"true"

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

Q2=>Q2,

Q3=>Q3,

Q4=>Q4,

Q5=>Q5,

Q6=>Q6,

D=>D,

FCLK=>FCLK,

PCLK=>PCLK,

CALIB=>CALIB,

RESET=>RESET

);

4.2.7 IDES16



Devices Supported

Table 4-13 IDES16 Devices Supported


LittleBee®

GW1N GW1N-1S, GW1N-9, GW1N-9C, GW1N-2, GW1N-1P5, GW1N-2B, GW1N-1P5B

GW1NR GW1NR-9, GW1NR-9C, GW1NR-2, GW1NR-2B


GW1NZ GW1NZ-2

GW1NSE GW1NSE-2C

GW1NSER GW1NSER-4C



IDES16 mode realizes 1:16 serial parallel conversion and output data is provided to FPGA logic at the same clock edge. CALIB is supported to


UG289-2.0E 50(112)

adjust the sequence of output data. Each pulse data is shifted by one bit. After sixteen shifts, the data output will be the same as the data before the shift.


.

Port Diagram


PCLK

FCLK

RESET

CALIB

D

IDES16

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Q15

Q14

Q13

Q12

Q11

Q10

Port Description








Q15~Q0 Output IDES16 data output signal






Connection Rule



UG289-2.0E 51(112)




IDES16 uut(

.Q0(Q0),

.Q1(Q1),

.Q2(Q2),

.Q3(Q3),

.Q4(Q4),

.Q5(Q5),

.Q6(Q6),

.Q7(Q7),

.Q8(Q8),

.Q9(Q9),

.Q10(Q10),

.Q11(Q11),

.Q12(Q12),

.Q13(Q13),

.Q14(Q14),

.Q15(Q15),

.D(D),

.FCLK(FCLK),

.PCLK(PCLK),

.CALIB(CALIB),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT IDES16



);

PORT(


UG289-2.0E 52(112)

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;

Q4:OUT std_logic;

Q5:OUT std_logic;

Q6:OUT std_logic;

Q7:OUT std_logic;

Q8:OUT std_logic;

Q9:OUT std_logic;

Q10:OUT std_logic;

Q11:OUT std_logic;

Q12:OUT std_logic;

Q13:OUT std_logic;

Q14:OUT std_logic;

Q15:OUT std_logic;

D:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IDES16


LSREN=>"true"

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

Q2=>Q2,

Q3=>Q3,

Q4=>Q4,

Q5=>Q5,

Q6=>Q6,


UG289-2.0E 53(112)

Q7=>Q7,

Q8=>Q8,

Q9=>Q9,

Q10=>Q10,

Q11=>Q11,

Q12=>Q12,

Q13=>Q13,

Q14=>Q14,

Q15=>Q15,

D=>D,

FCLK=>FCLK,

PCLK=>PCLK,

CALIB=>CALIB,

RESET=>RESET

);

4.2.8 IDDR_MEM


The Input Double Data Rate with Memory (IDDR_MEM) realizes double data rate input with memory.

Devices Supported

Table 4-16 IDDR_MEM Devices Supported


Arora


GW2AN GW2AN-55C


GW2ANR GW2ANR-18C


IDDR_MEM output data is provided to FPGA logic at the same clock edge. IDDR_MEM needs to be used with DQS. ICLK connects the DQSR90 of DQS output signals and sends data to IDDR_MEM according to the ICLK clock edge. WADDR [2: 0] connects the WPOINT output signal of DQS; RADDR [2: 0] connects the RPOINT output signal of DQS.

The frequency relation between PCLK and ICLK is PCLK ICLKf f.

You can determine the phase relationship between PCLK and ICLK according to the DLLSTEP value of DQS.


UG289-2.0E 54(112)

Port Diagram

Figure 4-13 IDDR_MEM Port Diagram

IDDR_MEM

D

ICLK

PCLK

WADDR

RADDR

RESET

Q0

Q1/

/

3

3

Port Description

Table 4-17 IDDR_MEM Port Description


D Input IDDR_MEM data input signal

ICLK Input Clock input signal from DQSR90 in DQS module


WADDR[2:0] Input Write address signal from WPOINT in DQS module

RADDR[2:0] Input Read address signal from RPOINT in DQS module


Q1~Q0 Output IDDR_MEM data output signal


Table 4-18 IDDR_MEM Parameter Description




Connection Rule

Data input D of IDDR_MEM can be directly from IBUF or from DO in IODELAY module.

ICLK needs DQSR90 from a DQS module.

WADDR[2:0] needs WPOINT from DQS module

RADDR[2:0] needs RPOINT from DQS module;



IDDR_MEM iddr_mem_inst(

.Q0(q0),


UG289-2.0E 55(112)

.Q1(q1),

.D(d),

.ICLK(iclk),

.PCLK(pclk),

.WADDR(waddr[2:0]),

.RADDR(raddr[2:0]),

.RESET(reset)

);



Vhdl Instantiation:

COMPONENT IDDR_MEM



);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D:IN std_logic;

ICLK:IN std_logic;

PCLK:IN std_logic;

WADDR:IN std_logic_vector(2 downto 0);

RADDR:IN std_logic_vector(2 downto 0);

RESET:IN std_logic

);

END COMPONENT;

uut:IDDR_MEM


LSREN=>"true"

)

PORT MAP (

Q0=>q0,

Q1=>q1,

D=>d,

ICLK=>iclk,


UG289-2.0E 56(112)

PCLK=>pclk,

WADDR=>waddr,

RADDR=>raddr,

RESET=>reset

);

4.2.9 IDES4_MEM


The 1 to 4 Deserializer with Memory (IDES4_MEM) realizes 1:4 serial-parallel with memory.

Devices Supported

Table 4-19 IDES4_MEM Devices Supported


Arora


GW2AN GW2AN-55C


GW2ANR GW2ANR-18C


IDES4_MEM realizes 1:4 serial parallel conversion and the output data is provided to FPGA logic at the same clock edge. CALIB is supported to adjust the sequence of output data. Each pulse data is shifted by one bit. After four shifts, the data output will be the same as the data before the shift.

The ICLK connects the output signal DQSR90 of DQS and sends data to IDES4_MEM according to the ICLK clock edge. WADDR [2: 0] connects the output signal WPOINT of DQS; RADDR [2: 0] connects the output signal RPOINT of DQS.

The frequency relation between PCLK, FCLK and ICLK is

1 2 1 2PCLK FCLK ICLKf f f .



UG289-2.0E 57(112)

Port Diagram

Figure 4-14 IDES4_MEM Port Diagram

IDES4_MEM

D

ICLK

PCLK

WADDR

RADDR

RESET

Q0

Q1

FCLK

CALIB

Q2

Q3/

/3

3

Port Description

Table 4-20 IDES4_MEM Port Description


D Input IDES4_MEM data input signal








Q3~Q0 Output IDES4_MEM data output signal


Table 4-21 IDES4_MEM Parameter Description




Connection Rule

Data input D of IDES4_MEM can be directly from IBUF or from DO in IODELAY module.




UG289-2.0E 58(112)

RADDR[2:0] needs RPOINT from DQS module;



IDES4_MEM ides4_mem_inst(

.Q0(q0),

.Q1(q1),

.Q2(q2),

.Q3(q3),

.D(d),

.ICLK(iclk),

.FCLK(fclk),

.PCLK (pclk),

.WADDR(waddr[2:0]),

.RADDR(raddr[2:0]),

.CALIB(calib),

.RESET(reset)

);



Vhdl Instantiation:

COMPONENT IDES4_MEM



);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;

D:IN std_logic;

ICLK:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;




UG289-2.0E 59(112)

CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IDES4_MEM


LSREN=>"true"

)

PORT MAP (

Q0=>q0,

Q1=>q1,

Q2=>q2,

Q3=>q3,

D=>d,

ICLK=>iclk,

FCLK=>fclk,

PCLK=>pclk,

WADDR=>waddr,

RADDR=>raddr,

CALIB=>calib,

RESET=>reset

);

4.2.10 IDES8_MEM


The 1 to 8 Deserializer with Memory (IDES8_MEM) realizes 1:8 serial parallel with memory.

Devices Supported

Table 4-22 IDES8_MEM Devices Supported


Arora


GW2AN GW2AN-55C


GW2ANR GW2ANR-18C


IDES8_MEM realizes 1:8 serial parallel conversion and output data is


UG289-2.0E 60(112)

provided to FPGA logic at the same clock edge. CALIB is supported to adjust the sequence of output data. The data is shifted by one bit per pulse. After eight shifts, the data output will be the same as the data before the shift. The ICLK connects the output signal DQSR90 of DQS and sends data to IDES8_MEM according to the ICLK clock edge. WADDR[2:0] connects the output signal WPOINT of DQS; RADDR[2:0] connects output signal RPOINT of DQS.

The frequency relation between PCLK, FCLK and ICLK is

1 4 1 4PCLK FCLK ICLKf f f .


Port Diagram

Figure 4-15 IDES8_MEM Port Diagram

IDES8_MEM

D

ICLK

PCLK

RESET

Q0

Q1FCLK

CALIB

Q2

Q3

Q4

Q5

Q6

Q7

WADDR

RADDR /

/3

3

Port Description

Table 4-23 IDES8_MEM Port Description


D Input IDES8_MEM data input signal


FCLK Input High speed clock Input signal






Q7~Q0 Output IDES8_MEM data output signal


UG289-2.0E 61(112)


Table 4-24 IDES8_MEM Parameters Description




Connection Rule

Data input D of IDES8_MEM can be directly from IBUF or from DO in IODELAY module.



RADDR[2:0] needs RPOINT from DQS module.



IDES8_MEM ides8_mem_inst(

.Q0(q0),

.Q1(q1),

.Q2(q2),

.Q3(q3),

.Q4(q4),

.Q5(q5),

.Q6(q6),

.Q7(q7),

.D(d),

.ICLK(iclk),

.FCLK(fclk),

.PCLK (pclk),

.WADDR(waddr[2:0]),

.RADDR(raddr[2:0]),

.CALIB(calib),

.RESET(reset)

);



Vhdl Instantiation:

COMPONENT IDES8_MEM


UG289-2.0E 62(112)



);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

Q2:OUT std_logic;

Q3:OUT std_logic;

Q4:OUT std_logic;

Q5:OUT std_logic;

Q6:OUT std_logic;

Q7:OUT std_logic;

D:IN std_logic;

ICLK:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;



CALIB:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IDES8_MEM


LSREN=>"true"

)

PORT MAP (

Q0=>q0,

Q1=>q1,

Q2=>q2,

Q3=>q3,

Q4=>q4,

Q5=>q5,

Q6=>q6,

Q7=>q7,

4 Input/Output Logic 4.3 DDR Mode Output Logic

UG289-2.0E 63(112)

D=>d,

ICLK=>iclk,

FCLK=>fclk,

PCLK=>pclk,

WADDR=>waddr,

RADDR=>raddr,

CALIB=>calib,

RESET=>reset

);

4.3 DDR Mode Output Logic

4.3.1 ODDR


Dual Data Rate Output (ODDR)


ODDR mode is used for transferring double data rate signals from FPGA devices. Where Q0 is the double rate data output, Q1 is used for the OEN signal of IOBUF/TBUF connected by Q1. ODDR logic diagram is as shown in Figure 4-16 and its timing diagram is as shown in Figure 4-17.

Figure 4-16 ODDR Logic Diagram

DFF

CLK

D QDFF

CLK

D QDFFN

CLK

D Q

MUX2

DFF

CLK

D Q

DFF

CLK

D QDFF

CLK

D QD1I0

I1

SEL

CLK

D0

Q0O

DFF

CLK

D QDFF

CLK

D QDFFN

CLK

D QDFF

CLK

D Q MUX2

I1

I0

SEL

OTX

TXCLK_POL

Q1

TRI-DDRX1


UG289-2.0E 64(112)

Figure 4-17 ODDR Timing Diagram

Port Diagram

Figure 4-18 ODDR Port Diagram

ODDRD1

CLKQ0

TXD0 Q1

Port Description

Table 4-25 ODDR Port Description


D0,D1 Input ODDR data input signal

TX Input Q1 generated by TRI-DDRX1


Q0 Output ODDR data output signal

Q1 Output ODDR tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.


Table 4-26 ODDR Parameter Description


TXCLK_POL 1'b0, 1'b1 1'b0

Q1 output clock polarity control

1'b0:Q1 posedge output;


UG289-2.0E 65(112)


1'b1:Q1 negedge output

INIT 1'b0 1'b0 Initial value of ODDR output

Connection Rule

Q0 can be directly connected to OBUF, or connected to input port DI through IODELAY module;

Q1 shall be connected to the OEN signal of IOBUF/TBUF connected to Q0, or left floating.




ODDR uut(

.Q0(Q0),

.Q1(Q1),

.D0(D0),

.D1(D1),

.TX(TX),

.CLK(CLK)

);

defparam uut.INIT=1'b0;

defparam uut.TXCLK_POL=1'b0;

Vhdl Instantiation:

COMPONENT ODDR

GENERIC (CONSTANT INIT: std_logic:='0';

TXCLK_POL:bit:='0'

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

TX:IN std_logic;

CLK:IN std_logic

);


UG289-2.0E 66(112)

END COMPONENT;

uut:ODDR

GENERIC MAP (INIT=>'0',

TXCLK_POL=>'0'

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

D0=>D0,

D1=>D1,

TX=>TX,

CLK=>CLK

);

4.3.2 ODDRC


Dual Data Rate Output with Asynchronous Clear (ODDRC) is similar to ODDR to realize double data rate and can be reset asynchronously.


ODDRC mode is used for transferring double data rate signals from FPGA devices. Where Q0 is the double rate data output, Q1 is used for the OEN signal of IOBUF/TBUF connected to Q1. Its logic diagram is as shown in Figure 4-19.

Figure 4-19 ODDRC Logic Diagram

DFFC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

QDFFNC

CLK

D

CLEAR

Q

MUX2

DFFC

CLK

D

CLEAR

Q

DFFC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

QD1I0

I1

SEL

CLK

D0

CLEARQ0O

DFFC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

QDFFNC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

Q MUX2

I1

I0

SEL

OTX

TXCLK_POL

Q1

TRI-DDRX1


UG289-2.0E 67(112)

Port Diagram

Figure 4-20 ODDRC Port Diagram

ODDRCCLEAR

CLK

D0

Q0D1

TXQ1

Port Description

Table 4-27 ODDRC Port Description


D0, D1 Input ODDRC data Input Signal

TX Input Input Q1 generated by TRI-DDRX1


CLEAR Input Asynchronous reset input signal, active-high.

Q0 Output ODDRC data output signal

Q1 Output ODDR tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.


Table 4-28 ODDRC Parameter Description




1'b0:Q1 posedge output;

1'b1:Q1 negedge output

INIT 1'b0 1'b0 Initial value of ODDRC output

Connection Rule

Q0 can directly connect OBUF, or connect input port DI in IODELAY module;

Q1 shall connect the OEN signal of IOBUF/TBUF connected by Q0, or left floating.




ODDRC uut(

.Q0(Q0),


UG289-2.0E 68(112)

.Q1(Q1),

.D0(D0),

.D1(D1),

.TX(TX),

.CLK(CLK),

.CLEAR(CLEAR)

);

defparam uut.INIT=1'b0;


Vhdl Instantiation:

COMPONENT ODDRC

GENERIC (CONSTANT INIT : std_logic :='0';

TXCLK_POL:bit:='0'

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

TX:IN std_logic;

CLK:IN std_logic;

CLEAR:IN std_logic

);

END COMPONENT;

uut:ODDRC

GENERIC MAP (INIT=>'0',

TXCLK_POL=>'0'

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

D0=>D0,

D1=>D1,

TX=>TX,

CLK=>CLK,


UG289-2.0E 69(112)

CLEAR=>CLEAR

);

4.3.3 OSER4


The 4 to 1 Serializer (OSER4) is a serializer of 4 bits parallel input and 1 bit serial output.


OSER4 mode realizes 4:1 parallel to serial conversion, and Q0 is the serial output, Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0. Its logic diagram is as shown in Figure 4-21.

Figure 4-21 OSER4 Logic Diagram

ODDRX2

TRI-DDRX2

2

4

TXTX0,TX1

D0~D3D

PCLK

FCLK

RESET

PCLK

FCLK

RESET

PCLK

FCLK

RESET

Q1

Q0

OEN

I O

TBUF

OSER4

DO


.

Port Diagram

Figure 4-22 OSER4 Port Diagram

OSER4FCLK

TX1~TX0

RESET

PCLK

D3~D0

Q1

Q0


UG289-2.0E 70(112)

Port Description

Table 4-29 OSER4 Port Description


D3~D0 Input OSER4 data input signal

TX1~TX0 Input Q1 generated by TRI-DDRX2




Q0 Output OSER4 data output signal

Q1 Output OSER4 tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.








1'b0: data posedge output

1'b1: data negedge output

HWL "false", "true" "false"

OSER4 data d_up0/1 timing relationship control

"False ": d_up1 is one cycle ahead of d_up0.

"True ": d_up1 and d_up0 have the same timing.

Connection Rule


Q1 shall connect the OEN signal of IOBUF/TBUF connected to Q0, or left floating.




OSER4 uut(

.Q0(Q0),

.Q1(Q1),


UG289-2.0E 71(112)

.D0(D0),

.D1(D1),

.D2(D2),

.D3(D3),

.TX0(TX0),

.TX1(TX1),

.PCLK(PCLK),

.FCLK(FCLK),

.RESET(RESET)

);



defparam uut.HWL ="false";

defparam uut.TXCLK_POL =1'b0;

Vhdl Instantiation:

COMPONENT OSER4


LSREN:string:="true";

HWL:string:="false";

TXCLK_POL:bit:='0'

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

D2:IN std_logic;

D3:IN std_logic;

TX0:IN std_logic;

TX1:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;


UG289-2.0E 72(112)

uut:OSER4


LSREN=>"true",

HWL=>"false",

TXCLK_POL=>'0'

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

D0=>D0,

D1=>D1,

D2=>D2,

D3=>D3,

TX0=>TX0,

TX1=>TX1,

FCLK=>FCLK,

PCLK=>PCLK,

RESET=>RESET

);

4.3.4 OSER8




OSER8 mode realizes 8:1 parallel to serial. Where Q0 is the serial output, Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0. Its logic diagram is as shown in Figure 4-23.


UG289-2.0E 73(112)

Figure 4-23 OSER8 Logic Diagram

ODDRX4

TRI-DDRX4

4

8

TXTX0~TX3

D0~D7D

PCLK

FCLK

RESET

PCLK

FCLK

RESET

PCLK

FCLK

RESET

Q1

Q0

OEN

I O

TBUF

OSER8

DO


.

Port Diagram


OSER8FCLK

TX3~TX0

RESET

PCLK

D7~D0

Q1

Q0

Port Description




TX3~TX0 Input Q1 generated by TRI-DDRX4




Q0 Output OSER8 data output signal

Q1 Output OSER8 tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.


UG289-2.0E 74(112)











OSER8 data d_up0/1 timing relationship control

"false ": d_up1 is one cycle ahead of d_up0.

"true ": d_up1 and d_up0 have the same timing.

Connection Rule


Q1 shall connect the OEN signal of IOBUF/TBUF connected to Q0, or left floating.




OSER8 uut(

.Q0(Q0),

.Q1(Q1),

.D0(D0),

.D1(D1),

.D2(D2),

.D3(D3),

.D4(D4),

.D5(D5),

.D6(D6),

.D7(D7),

.TX0(TX0),

.TX1(TX1),

.TX2(TX2),

.TX3(TX3),


UG289-2.0E 75(112)

.PCLK(PCLK),

.FCLK(FCLK),

.RESET(RESET)

);




defparam uut.TXCLK_POL =1'b0;

Vhdl Instantiation:

COMPONENT OSER8




TXCLK_POL:bit:='0'

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

D2:IN std_logic;

D3:IN std_logic;

D4:IN std_logic;

D5:IN std_logic;

D6:IN std_logic;

D7:IN std_logic;

TX0:IN std_logic;

TX1:IN std_logic;

TX2:IN std_logic;

TX3:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;


UG289-2.0E 76(112)

uut:OSER8


LSREN=>"true",

HWL=>"false",

TXCLK_POL=>'0'

)

PORT MAP (

Q0=>Q0,

Q1=>Q1,

D0=>D0,

D1=>D1,

D2=>D2,

D3=>D3,

D4=>D4,

D5=>D5,

D6=>D6,

D7=>D7,

TX0=>TX0,

TX1=>TX1,

TX2=>TX2,

TX3=>TX3,

FCLK=>FCLK,

PCLK=>PCLK,

RESET=>RESET

);

4.3.5 OSER10




OSER10 mode realizes 10:1 parallel to serial conversion. PCLK is

usually obtained by FCLK frequency division, 1 5PCLK FCLKf f

.


UG289-2.0E 77(112)

Port Diagram


OSER10FCLK

RESET

PCLK

D9~D0

Q

Port Description







Q Output OSER10 data output signal


Table 4-34 OSER10 Parameter Description




Connection Rule

Q can directly connect to OBUF, or connect to input port DI in IODELAY module.




OSER10 uut(

.Q(Q),

.D0(D0),

.D1(D1),


UG289-2.0E 78(112)

.D2(D2),

.D3(D3),

.D4(D4),

.D5(D5),

.D6(D6),

.D7(D7),

.D8(D8),

.D9(D9),

.PCLK(PCLK),

.FCLK(FCLK),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT OSER10



);

PORT(

Q:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

D2:IN std_logic;

D3:IN std_logic;

D4:IN std_logic;

D5:IN std_logic;

D6:IN std_logic;

D7:IN std_logic;

D8:IN std_logic;

D9:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);


UG289-2.0E 79(112)

END COMPONENT;

uut:OSER10


LSREN=>"true"

)

PORT MAP (

Q=>Q,

D0=>D0,

D1=>D1,

D2=>D2,

D3=>D3,

D4=>D4,

D5=>D5,

D6=>D6,

D7=>D7,

D8=>D8,

D9=>D9,

FCLK=>FCLK,

PCLK=>PCLK,

RESET=>RESET

);

4.3.6 OVIDEO


The 7 to 1 Serializer (OVIDEO) is a serializer of 7 bits parallel input and 1 bit serial output,


OVIDEO mode realizes 7:1 parallel to serial conversion. PCLK is

usually obtained by FCLK frequency division: 1 3.5PCLK FCLKf f

.


UG289-2.0E 80(112)

Port Diagram

Figure 4-26 OVIDEO Port Diagram

OVIDEOFCLK

RESET

PCLK

D6~D0

Q

Port Description

Table 4-35 OVIDEO Port Description


D6~D0 Input OVIDEO data input signal




Q Output OVIDEO data output signal


Table 4-36 OVIDEO Parameter Description




Connection Rule

Q can directly connect to OBUF, or connect to input port DI in IODELAY module;




OVIDEO uut(

.Q(Q),

.D0(D0),

.D1(D1),


UG289-2.0E 81(112)

.D2(D2),

.D3(D3),

.D4(D4),

.D5(D5),

.D6(D6),

.PCLK(PCLK),

.FCLK(FCLK),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT OVIDEO



);

PORT(

Q:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

D2:IN std_logic;

D3:IN std_logic;

D4:IN std_logic;

D5:IN std_logic;

D6:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:OVIDEO


LSREN=>"true"

)

PORT MAP (


UG289-2.0E 82(112)

Q=>Q,

D0=>D0,

D1=>D1,

D2=>D2,

D3=>D3,

D4=>D4,

D5=>D5,

D6=>D6,

FCLK=>FCLK,

PCLK=>PCLK,

RESET=>RESET

);

4.3.7 OSER16



Devices Supported

Table 4-37 OSER16 Devices Supported


LittleBee®

GW1N GW1N-1S, GW1N-9, GW1N-9C, GW1N-2, GW1N-1P5, GW1N-2B, GW1N-1P5B

GW1NR GW1NR-9, GW1NR-9C, GW1NR-2, GW1NR-2B


GW1NZ GW1NZ-2

GW1NSE GW1NSE-2C

GW1NSER GW1NSER-4C



OSER16 mode realizes 16:1 parallel to serial conversion. PCLK is

usually obtained by FCLK frequency division： 1 8PCLK FCLKf f

.


UG289-2.0E 83(112)

Port Diagram


OSER16FCLK

RESET

PCLK

D15~D0

Q

Port Description







Q Output IDES8_MEM data output signal


Table 4-39 OSER16 Parameter Description




Connection Rule

Q can directly connect to OBUF, or connect to input port DI in IODELAY module;




OSER16 uut(

.Q(Q),

.D0(D0),

.D1(D1),

.D2(D2),


UG289-2.0E 84(112)

.D3(D3),

.D4(D4),

.D5(D5),

.D6(D6),

.D7(D7),

.D8(D8),

.D9(D9),

.D10(D10),

.D11(D11),

.D12(D12),

.D13(D13),

.D14(D14),

.D15(D15),

.PCLK(PCLK),

.FCLK(FCLK),

.RESET(RESET)

);



Vhdl Instantiation:

COMPONENT OSER16



);

PORT(

Q:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

D2:IN std_logic;

D3:IN std_logic;

D4:IN std_logic;

D5:IN std_logic;

D6:IN std_logic;

D7:IN std_logic;

D8:IN std_logic;


UG289-2.0E 85(112)

D9:IN std_logic;

D10:IN std_logic;

D11:IN std_logic;

D12:IN std_logic;

D13:IN std_logic;

D14:IN std_logic;

D15:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:OSER16


LSREN=>"true"

)

PORT MAP (

Q=>Q,

D0=>D0,

D1=>D1,

D2=>D2,

D3=>D3,

D4=>D4,

D5=>D5,

D6=>D6,

D7=>D7,

D8=>D8,

D9=>D9,

D10=>D10,

D11=>D11,

D12=>D12,

D13=>D13,

D14=>D14,

D15=>D15,

FCLK=>FCLK,


UG289-2.0E 86(112)

PCLK=>PCLK,

RESET=>RESET

);

4.3.8 ODDR_MEM


Dual Data Rate Output with Memory (ODDR_MEM) realizes double data rate output with memory.

Devices Supported

Table 4-40 ODDR_MEM Devices Supported


Arora


GW2AN GW2AN-55C


GW2ANR GW2ANR-18C


ODDR_MEM mode is used for transferring double data rate signals from FPGA devices. Unlike ODDR, the output double data rate with memory (ODDR_MEM) needs to be used with DQS. TCLK connects to the DQSW0 or DQSW270 of DQS output signal, and outputs data from ODDR_MEM according to the TCLK clock edge. Where Q0 is the double rate data output, Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0. Its logic diagram is as shown in Figure 4-28.

Figure 4-28 ODDR_MEM Logic Diagram

DFFC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

QDFFNC

CLK

D

CLEAR

Q

MUX2

DFFC

CLK

D

CLEAR

Q

DFFC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

QD1I0

I1

SEL

TCLK

D0

RESETQ0O

DFFC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

QDFFNC

CLK

D

CLEAR

QDFFC

CLK

D

CLEAR

Q MUX2

I1

I0

SEL

OTX

TXCLK_POL

Q1

TRI-MDDRX1

PCLK

The frequency relation between PCLK and TCLK is PCLK TCLKf f.

You can determine the phase relationship between PCLK and TCLK according to DLLSTEP and WSTEP value of DQS.


UG289-2.0E 87(112)

Port Diagram

Figure 4-29 ODDR_MEM Port Diagram

ODDR_MEM

D1~D0

TCLK

RESET

Q0

Q1

TX

PCLK

Port Description

Table 4-41 ODDR_MEM Port Description


D1~D0 Input ODDR_MEM data input signal

TX Input Q1 generated by TRI-MDDRX1

TCLK Input Clock input signal from DQSW0 or DQSW270 in DQS module



Q0 Output ODDR_MEM data output signal

Q1 Output ODDR_MEM tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.


Table 4-42 ODDR_MEM Parameter Description








TCLK_SOURCE "DQSW", "DQSW270"

"DQSW"

TCLK source selection

"DQSW" comes from DQSW0 in DQS module.

"DQSW270" comes from DQSW270 from DQS module.


UG289-2.0E 88(112)

Connection Rule

Q0 can directly connect to OBUF, or connect to input port DI in IODELAY module;

Q1 shall connect to the OEN signal of IOBUF/TBUF connected to Q0, or left floating.

TCLK needs DQSW0 or DQSW270 from DQS module and you need to configure the corresponding parameters.



ODDR_MEM oddr_mem_inst(

.Q0(q0),

.Q1(q1),

.D0(d0),

.D1(d1),

.TX(tx),

.TCLK(tclk),

.PCLK(pclk),

.RESET(reset)

);



defparam uut.TCLK_SOURCE ="DQSW";


Vhdl Instantiation:

COMPONENT ODDR_MEM



TXCLK_POL:bit:='0';

TCLK_SOURCE:string:="DQSW"

);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

TX:IN std_logic;


UG289-2.0E 89(112)

TCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:ODDR_MEM


LSREN=>"true",

TXCLK_POL=>'0',

TCLK_SOURCE=>"DQSW"

)

PORT MAP (

Q0=>q0,

Q1=>q1,

D0=>d0,

D1=>d1,

TX=>tx,

TCLK=>tclk,

PCLK=>pclk,

RESET=>reset

);

4.3.9 OSER4_MEM


The 4 to 1 Serializer with Memory (OSER4_MEM) realizes 4:1 parallel serial conversion with memory.

Devices Supported

Table 4-43 OSER4_MEM Devices Supported


Arora


GW2AN GW2AN-55C


GW2ANR GW2ANR-18C


OSER4_MEM realizes 4:1 parallel serial conversion. The TCLK connects to the output signal DQSW0 or DQSW270 of DQS, and outputs


UG289-2.0E 90(112)

data from the OSER4_MEM according to the TCLK clock edge, and Q0 is the serial output, Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0. Its logic diagram is as shown in Figure 4-30.

Figure 4-30 OSER4_MEM Logic Diagram

ODDRX2

TRI-MDDRX2

2

4

TXTX0,TX1

D0~D3D

PCLK

FCLK

RESET

PCLK

FCLK

RESET

PCLK

FCLK

RESET

Q1

Q0OEN

I O

TBUF

OSER4_MEM

DO

TCLK

TCLK TCLK

The frequency relation among PCLK, FCLK and TCLK is

1 2 1 2PCLK FCLK TCLKf f f .

You can determine the phase realationship between FCLK and TCLK according to the DLLSTEP and WSTEP values of DQS.

Port Diagram

Figure 4-31 OSER4_MEM Diagram

OSER4_MEM

D3~D0

FCLK

RESET

Q0

Q1

TCLK

TX1~TX0

PCLK

Port Description

Table 4-44 OSER4_MEM Port Description


D3~D0 Input OSER4_MEM data input signal

TX1~TX0 Input Q1 generated by TRI-MDDRX2


UG289-2.0E 91(112)






Q0 Output OSER4_MEM data output signal

Q1 Output OSER4_MEM tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.


Table 4-45 OSER4_MEM Parameter Description








TCLK_SOURCE "DQSW","DQSW270" " DQSW "

TCLK source selection

"DQSW" comes from DQSW0 in DQS module.



OSER4_MEM data d_up0/1 timing relationship control

"False ": d_up1 is one cycle ahead of d_up0.

"True ": d_up1 and d_up0 have the same timing.

Connection Rule

Q0 can directly connect to OBUF, or connect to input port DI in IODELAY module;

Q1 shall connect to the OEN signal of IOBUF/TBUF connected to Q0, or suspend.

TCLK needs DQSW0 or DQSW270 from DQS module and you need to


UG289-2.0E 92(112)

configure the corresponding parameters.



OSER4_MEM oser4_mem_inst(

.Q0(q0),

.Q1(q1),

.D0(d0),

.D1(d1),

.D2(d2),

.D3(d3),

.TX0(tx0),

.TX1(tx1),

.TCLK (tclk),

.FCLK (fclk),

.PCLK (pclk),

.RESET(reset)

);






Vhdl Instantiation:

COMPONENT OSER4_MEM




TXCLK_POL:bit:='0';


);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;


UG289-2.0E 93(112)

D2:IN std_logic;

D3:IN std_logic;

TX0:IN std_logic;

TX1:IN std_logic;

TCLK:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:OSER4_MEM


LSREN=>"true",

HWL=>"false",

TXCLK_POL=>'0',

TCLK_SOURCE=>"DQSW"

)

PORT MAP (

Q0=>q0,

Q1=>q1,

D0=>d0,

D1=>d1,

D2=>d2,

D3=>d3,

TX0=>tx0,

TX1=>tx1,

TCLK=>tclk,

FCLK=>fclk,

PCLK=>pclk,

RESET=>reset

);


UG289-2.0E 94(112)

4.3.10 OSER8_MEM


The 8 to 1 Serializer with Memory (OSER8_MEM) realizes 8:1 parallel serial with memory.

Devices Supported

Table 4-46 OSER8_MEM Devices Supported


Arora


GW2AN GW2AN-55C


GW2ANR GW2ANR-18C


OSER8_MEM mode realizes 8:1 parallel serial conversion. The TCLK connects the output signal DQSW0 or DQSW270 of DQS, and outputs data from the OSER8_MEM according to the TCLK clock edge, and Q0 is the serial output, Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0. Its logic diagram is as shown in Figure 4-32.

Figure 4-32 OSER8_MEM Logic Diagram

ODDRX4

TRI-MDDRX4

4

8

TXTX0~TX3

D0~D7D

PCLK

FCLK

RESET

PCLK

FCLK

RESET

PCLK

FCLK

RESET

Q1

Q0OEN

I O

TBUF

OSER8_MEM

DO

TCLK

TCLK TCLK

The frequency relation between PCLK, FCLK and TCLK is

1 4 1 4PCLK FCLK TCLKf f f .

You can determine the phase realationship between FCLK and TCLK according to DLLSTEP and WSTEP values of DQS.


UG289-2.0E 95(112)

Port Diagram

Figure 4-33 OSER8_MEM Port Diagram

OSER8_MEM

D7~D0

FCLK

RESET

Q0

Q1

TCLK

TX3~TX0

PCLK

Port Description

Table 4-47 OSER4_MEM Port Description

Port Name I/O Description

D7~D0 Input OSER8_MEM data input signal

TX3~TX0 Input Q1 generated by TRI-MDDRX4





Q0 Output OSER8_MEM data output signal

Q1 Output OSER8_MEM tristate enable control data output can be connected to the IOBUF/TBUF OEN signal connected to Q0, or left floating.


Table 4-48 OSER4_MEM Parameter Description



LSREN "false", "true" "true" Enable Local Reset





TCLK_SOURCE "DQSW","DQSW270" " DQSW " TCLK source selection

"DQSW" comes from DQSW0 in DQS


UG289-2.0E 96(112)


module.



OSER8_MEM data d_up0/1 timing relationship control

"false ": d_up1 is one cycle ahead of d_up0.

"true ": d_up1 and d_up0 have the same timing.

Connection Rule

Q0 can directly connect to OBUF, or connect to input port DI in IODELAY module.

Q1 shall connect to the OEN signal of IOBUF/TBUF connected to Q0, or left floating.

TCLK needs DQSW0 or DQSW270 from DQS module and you need to configure the corresponding parameters.



OSER8_MEM oser8_mem_inst(

.Q0(q0),

.Q1(q1),

.D0(d0),

.D1(d1),

.D2(d2),

.D3(d3),

.D4(d4),

.D5(d5),

.D6(d6),

.D7(d7),

.TX0(tx0),

.TX1(tx1),

.TX2(tx2),

.TX3(tx3),

.TCLK (tclk),


UG289-2.0E 97(112)

.FCLK (fclk),

.PCLK (pclk),

.RESET(reset)

);






Vhdl Instantiation:

COMPONENT OSER8_MEM




TXCLK_POL:bit:='0';


);

PORT(

Q0:OUT std_logic;

Q1:OUT std_logic;

D0:IN std_logic;

D1:IN std_logic;

D2:IN std_logic;

D3:IN std_logic;

D4:IN std_logic;

D5:IN std_logic;

D6:IN std_logic;

D7:IN std_logic;

TX0:IN std_logic;

TX1:IN std_logic;

TX2:IN std_logic;

TX3:IN std_logic;

TCLK:IN std_logic;

FCLK:IN std_logic;

PCLK:IN std_logic;


UG289-2.0E 98(112)

RESET:IN std_logic

);

END COMPONENT;

uut:OSER8_MEM


LSREN=>"true",

HWL=>"false",

TXCLK_POL=>'0',

TCLK_SOURCE=>"DQSW"

)

PORT MAP (

Q0=>q0,

Q1=>q1,

D0=>d0,

D1=>d1,

D2=>d2,

D3=>d3,

D4=>d4,

D5=>d5,

D6=>d6,

D7=>d7,

TX0=>tx0,

TX1=>tx1,

TX2=>tx2,

TX3=>tx3,

TCLK=>tclk,

FCLK=>fclk,

PCLK=>pclk,

RESET=>reset

);

4 Input/Output Logic 4.4 Delay Module

UG289-2.0E 99(112)

4.4 Delay Module

4.4.1 IODELAY


Input/Output delay (IODELAY) is a programmable delay unit in IO module.


Each IO contains an IODELAY module, providing a total of 128 (0~127) delays. The GW1N series of FPGA has a single-step delay time of about 30ps. And the GW2A series of FPGA has a single-step delay time of about 18ps. IODELAY can be used for input or output of I/O logic, but not for both at the same time.

Port Diagram

Figure 4-34 IODELAY Port Diagram

IODELAY

SDTAP

VALUE

DO

DF

DI

SETN

Port Description

Table 4-49 IODELAY Port Description


DI Input Data input signal

SDTAP Input

Controls loading static delay step

0: loads static delay

1: adjusts the dynamic delay

SETN Input

Sets the direction of dynamic delay adjustment

0: Increases delay

1: Decreases delay

VALUE Input VALUE is the delay value of negedge dynamic adjustment, and it moves one delay step per pulse.

DO Output Data output signal

DF Output An output flag that represents under-flow or over-flow in dynamic delay adjustment


UG289-2.0E 100(112)

Parameters Description

Table 4-50 IODELAY Parameter Description


C_STATIC_DLY 0~127 0 Controls the static delay step



IODELAY iodelay_inst(

.DO(dout),

.DF(df),

.DI(di),

.SDTAP(sdtap),

.SETN(setn),

.VALUE(value)

);

defparam iodelay_inst.C_STATIC_DLY=0;

Vhdl Instantiation:

COMPONENT IODELAY

GENERIC (C_STATIC_DLY:integer:=0

);

PORT(

DO:OUT std_logic;

DF:OUT std_logic;

DI:IN std_logic;

SDTAP:IN std_logic;

SETN:IN std_logic;

VALUE:IN std_logic

);

END COMPONENT;

uut:IODELAY

GENERIC MAP (C_STATIC_DLY=>0

)

PORT MAP (

DO=>dout,

DF=>df,


UG289-2.0E 101(112)

DI=>di,

SDTAP=>sdtap,

SETN=>setn,

VALUE=>value

);

4.4.2 IODELAYC


Input/Output delay (IODELAY) is a programmable delay unit in IO module.

Devices Supported

Table 4-51 IODELAYC Devices Supported


LittleBee®

GW1N GW1N-9C

GW1NR GW1NR-9C


Each IO contains the IODELAYC module, which provides a total of 128 (0 to 127) delays, adding more delay adjustments compared to IODELAY. IODELAYC can only be used for I/O logic input, not for I/O logic output.

Port Diagram

Figure 4-35 IODELAYC Port Diagram

IODELAYC

SDTAP

VALUE

DO

DF

DI

SETN

DASEL[1:0]

DAADJ[1:0]

DAO

Port Description

Table 4-52 IODELAYC Port Description



SDTAP Input



1: adjusts the dynamical delay

SETN Input Sets the direction of dynamical delay adjustment


UG289-2.0E 102(112)


0: Increases delay

1: Decreases delay

VALUE Input VALUE is the delay value of negedge dynamical adjustment, and each pulse moves one delay step.

DASEL[1:0] Input Dynamically controls DAO delay mode

DAADJ[1:0] Input Dynamically controls the delay value of the DAO relative to the DO.


DAO Output Output signal of data delay adjustment

DF Output An output flag that represents under-flow or over-flow in dynamical delay adjustment.


Table 4-53 IODELAYC Parameter Description


C_STATIC_DLY 0~127 0 Controls the static delay step

DYN_DA_SEL "True"/ "false"

false

false: selects parameter DA_SEL to statically control DAO delay mode.

true: selects the signal DASEL to dynamically control DAO delay mode.

DA_SEL 2'b00~2'b11 2'b00 Static control of DAO delay mode



IODELAYC iodelayc_inst(

.DO(dout),

.DAO(douta),

.DF(df),

.DI(di),

.SDTAP(sdtap),

.SETN(setn),

.VALUE(value),

.DASEL(dasel),

.DAADJ(daadj)

);

defparam iodelayc_inst.C_STATIC_DLY=0;

defparam iodelayc_inst.DYN_DA_SEL="true";


UG289-2.0E 103(112)

defparam iodelayc_inst.DA_SEL=2'b01;

Vhdl Instantiation:

COMPONENT IODELAYC

GENERIC (C_STATIC_DLY:integer:=0;

DYN_DA_SEL:string:="false";

DA_SEL:bit_vector:="00"

);

PORT(

DO:OUT std_logic;

DAO:OUT std_logic;

DF:OUT std_logic;

DI:IN std_logic;

SDTAP:IN std_logic;

SETN:IN std_logic;

VALUE:IN std_logic;

DASEL : IN std_logic_vector(1 downto 0);

DAADJ : IN std_logic_vector(1 downto 0)

);

END COMPONENT;

uut:IODELAYC

GENERIC MAP (C_STATIC_DLY=>0,

DYN_DA_SEL=>"true",

DA_SEL=>"01"

)

PORT MAP (

DO=>dout,

DAO=>dout,

DF=>df,

DI=>di,

SDTAP=>sdtap,

SETN=>setn,

VALUE=>value,

DASEL=>dasel,

DAADJ=>daadj

);


UG289-2.0E 104(112)

4.4.3 IODELAYB


Input/Output delay (IODELAYB) is a programmable delay unit in IO module.

Devices Supported

Table 4-54 Devices Supported

Family Series Device

LittleBee®

GW1N GW1N-2, GW1N-1P5, GW1N-2B, GW1N-1P5B

GW1NR GW1NR-2, GW1NR-2B


Each IO contains the IODELAYB module, which provides a total of 128 (0 to 127) delay. IODELAYB adds more delay adjustments compared to IODELAY. IODELAYB can only be used for I/O logic input, not for I/O logic output, and the diagram is as shown in Figure 4-36.

Figure 4-36 IODELAYB Diagram

DLY_ADJSDTAP

VALUE

DI

SETN

DELAY_MUX

#100ps

dlyout_mid

DOdel_0 del_1 del_2 del_5 del_6 del_7

dmux_o

0

1

2

3

DELAY_MUX[1:0]

SEL

DA

AD

J_M

UX

1

0 1 2 3SEL

DA

AD

J_M

UX

0

0 1 2 3

SEL

DA

SEL_

MU

X

0 1 2 3

SEL

del

_2

del

_1

de

l_0

dmux

_o

del

_3

dm

ux_

o

del

_4

del_

5

de

l_6

del_

7

DAO

DO

DAADJ[1:0] DAADJ[1:0]

DA_SEL[1:0]

50ps


UG289-2.0E 105(112)

Port Diagram

Figure 4-37 IODELAYB Port Diagram

IODELAYB

SDTAP

VALUE

DO

DF

DI

SETN

DAADJ[1:0]

DAO

Port Description

Table 4-55 IODELAYB Port Description

Port Name I/O Description


SDTAP Input



1: adjusts the dynamical delay

SETN Input

Sets the direction of dynamical delay adjustment

0: Increases delay

1: Decreases delay

VALUE Input VALUE is the delay value of negedge dynamical adjustment, and each pulse moves one delay step.

DAADJ[1:0] Input Dynamically controls the delay value of the DAO relative to the DO


DAO Output Output signal of data delay adjustment

DF Output An output flag that represents under-flow or over-flow in dynamical delay adjustment.


Table 4-56 IODELAYB Parameter Description


C_STATIC_DLY 0~127 0 Controls Static delay step

DELAY_MUX 2'b00~2'b11 2'b00

Delay MUX options:

2'b00:dmux_o=DI

2'b01:#100ps dmux_o=DI

2'b10:dmux_o=dlyout_mid

2'b11:dmux_o=DO

DA_SEL 2'b00~2'b11 2'b00 DAO delay mode in static control


UG289-2.0E 106(112)

Note!

When IODELAYB used, the connection of parameters DELAY_MUX and DA_SEL are as follows:

DELAY_MUX:2/3 -> DA_SEL:0/1. When DELAY_MUX is 2 or 3, DA_SEL can be 0 or 1.

DELAY_MUX:0/1 -> DA_SEL:0/2/3. When DELAY_MUX is 0 or 1, DA_SELcan be 0, 2 or 3.

Connection Rule

DO can not connect to IDDR/IDES, and DAO can only connect to data input of IDDR/IDES.



IODELAYB iodelayb_inst(

.DO(dout),

.DAO(douta),

.DF(df),

.DI(di),

.SDTAP(sdtap),

.SETN(setn),

.VALUE(value),

.DAADJ(daadj)

);

defparam iodelayb_inst.C_STATIC_DLY=0;

defparam iodelayb_inst. DELAY_MUX = 2'b00;

defparam iodelayb_inst.DA_SEL=2'b00;

Vhdl Instantiation：

COMPONENT IODELAYB

GENERIC (C_STATIC_DLY:integer:=0;

DELAY_MUX : bit_vector := "00";

DA_SEL:bit_vector:= "00"

);

PORT(

DO:OUT std_logic;

DAO:OUT std_logic;

DF:OUT std_logic;

DI:IN std_logic;

SDTAP:IN std_logic;

4 Input/Output Logic 4.5 IEM

UG289-2.0E 107(112)

SETN:IN std_logic;

VALUE:IN std_logic;

DAADJ : IN std_logic_vector(1 downto 0)

);

END COMPONENT;

uut:IODELAYB

GENERIC MAP (C_STATIC_DLY=>0,

DELAY_MUX =>"00",

DA_SEL=>"00"

)

PORT MAP (

DO=>dout,

DAO=>douta,

DF=>df,

DI=>di,

SDTAP=>sdtap,

SETN=>setn,

VALUE=>value,

DAADJ=>daadj

);

4.5 IEM Primitive Introduction

Input Edge Monitor (IEM) is a sampling module in IO module.


IEM is used for sampling data edge, which can be used together with delay module to adjust the dynamic sampling window for DDR mode.

Port Diagram

Figure 4-38 IEM Port Diagram

IEM

CLK

MCLK

LAG

LEAD

D

RESET


UG289-2.0E 108(112)

Port Description

Table 4-57 IEM Port Description


D Input Data input signal



MCLK Input IEM detecting clock, from user logic, acts on output flag.

LAG Output The lag flag after IEM edge comparison

LEAD Output The lead flag after IEM edge comparison


Table 4-58 IEM Parameter Description


WINSIZE "SMALL","MIDSMALL", "MIDLARGE","LARGE"

"SMALL" Window size setting





IEM iem_inst(

.LAG(lag),

.LEAD(lead),

.D(d),

.CLK(clk),

.MCLK(mclk),

.RESET(reset)

);

defparam iodelay_inst.WINSIZE = "SMALL";

defparam iodelay_inst.GSREN = "false";

defparam iodelay_inst.LSREN = "true";

Vhdl Instantiation:

COMPONENT IEM

GENERIC (WINSIZE:string:="SMALL";

GSREN:string:="false";



UG289-2.0E 109(112)

);

PORT(

LAG:OUT std_logic;

LEAD:OUT std_logic;

D:IN std_logic;

CLK:IN std_logic;

MCLK:IN std_logic;

RESET:IN std_logic

);

END COMPONENT;

uut:IEM

GENERIC MAP (WINSIZE=>"SMALL",

GSREN=>"false",

LSREN=>"true"

)

PORT MAP (

LAG=>lag,

LEAD=>lead,

D=>d,

CLK=>clk,

MCLK=>mclk,

RESET=>reset

);

5 IP Generation 5.1 IP Configuration

UG289-2.0E 110(112)

5 IP Generation

The software only supports DDR at present. Click DDR in the IP Core Generator interface, and a summary of DDR will be displayed on the right side of the interface.

5.1 IP Configuration Double-click "DDR", and the "IP Customization" window pops up. This

includes the "File", "Options", and port diagram, as shown in Figure 5-1.

Figure 5-1 IP Customization of DDR

1. File: The File configuration box is used to configure the generated IP

5 IP Generation 5.1 IP Configuration

UG289-2.0E 111(112)

design file.

Device: Displays the configured Device.

Part Number: Displays the configured Part Number.

Language: Hardware description language used to generate the IP design files. Click the drop-down list to select the language, including Verilog and VHDL.

Synthesis Tool: Selects synthesis tools.

Module Name: The module name of the generated IP design files. Enter the module name in the text box. Module name cannot be the same as the primitive name. If it is the same, an error will be reported.

File Name: The name of the generated IP design files. Enter the file name in the text box.

Create In: The path in which the generated IP files will be stored. Enter the target path in the box or select the target path by clicking the option.

2. Options: The Options configuration box is used to customize the IP, as shown Figure 5-1.

DDR Mode: Configures DDR mode, including input, output, tristate and bi-directional state;

Data Width: Configures the data width of the DDR. The range is 1~64;

Ratio: DDR data conversion ratio, including 2,4,7,8,10,16;

Reset: When Ratio is 2, this option can be enabled or disabled, and IDDRC or ODDRC will be instantiated when enabled;

IODELAY: Configures whether DDR uses a delay module;

- "Delay Mode": Configures the delay mode. "None" means no IODELAY; "Dynamic" means using IODELAY and adjusting the delay step dynamically; "Static" means using IODELAY and adjusting the delay step statically.

- "Delay Step": Selects the number of steps to statically adjust the delay, ranging 1 to 128.

- "Delay Direction": In bidirectional mode, When DDR Mode is "bidirectional", if IODELAY is used, select whether IODELAY is connected to input or output.

Use CLKDIV: CLKDIV will be instantiated and the frequency of fclk will be divided when CLKDIV is enabled. When Ratio is 2, it cannot be checked.

3. Port Diagram: The port diagram displays a sample diagram of IP Core configuration, as shown in Figure 5-1.

5 IP Generation 5.2 IP Generation Files

UG289-2.0E 112(112)

5.2 IP Generation Files After configuration, it will generate three files that are named after the

"File Name".

The IP design file "gowin_ddr.v" is a complete verilog module, which generates DDR modules with corresponding functions according to the configuration.

"Gowin_ddr_tmp.v" is the template file;

"gowin_padd.ipc" file is IP configuration file. You can load the file to configure the IP.

Note!

If VHDL is selected as the hardware description language, the first two files will be named with .vhd suffix.