grid synchronization for power converters marco liserre [email protected] grid synchronization for...

Marco Liserre [email protected]

Grid synchronization for power converters


Marco Liserre

[email protected]



• Grid requirements for DG inverters• PLL Basics, PLL in power systems• Design of PLL• PLL for single-phase systems

– Methods to create the orthogonal component– Methods using adaptive filters

• PLL for three-phase systems• Conclusions• Reference papers

Outline



Grid Distrurbances

Thomsen,1999; CIGRE WG14-31, 1999

Grid disturbances are not at all a new issue, and the utilities are aware of them. However, they have to take a new look because of the rapidly changing customers’ needs and the nature of loads (CIGRE WG14-31, 1999)



Grid requirements for DG inverters

The following conditions should be met, with voltages in RMS and measured at the point of utility connection.

When the utility frequency is outside the range of +/- 1 Hz the inverter should cease to energize the utility line within 0.2 seconds.The PV system shall have an average lagging power factor greater than 0,9 when the output is greater than 50% rated.

Thus the grid voltage and frequency should be estimated and monitored fast and accurate enough in order to cope with the standard



Grid synchronization requirements

A good synchronization of the current with the grid voltage is necessary as:

the standards require a high power factor (> 0.9) a ”clean” reference for the current is necesarry in order to cope with the harmonic requirements of grid standards and codes grid connection transients needs to be minimized in order not to trip the inverter

Distributed Generation systems of higher power have also requirements in terms of voltage support or reactive power injection capability and of frequency support or active power droop

Micro-grid distributed generation systems have wider range of voltage and frequency and the estimated grid voltage parameters are often involved in control loops



Grid synchronization options and challenges

There are two basical synchronization methods: Filtered Zero Cross Detection (ZCD) PLL

Single-phase systems:The classical solution for single-phase systems was Filtered ZCD as for the PLL two orthogonal voltages are required. The trend now is to use the PLL technique also by creating ”virtual” orthogonal components using different techniques!

Three-phase systems: Three-phase PLL should deal with unbalnace hence with negative sequence Moreover in three-phase systems dynamics would be better if synchronizing to all three phase voltages, i.e. based on space vectors rather then on a scalar voltage



Zero Cross Detection (ZCD) circuits

Resistive feedback hysteresis circuit

Dual point interpolation circuit

Dynamic hysteresis comparator circuit

Source: R.W. Wall, “Simple methods for detecting zero crossing,” IEEE IECON’03, pp. 2477-2481



Filtered Zero Cross Detection (ZCD) based monitoring and synchronization

v

21x d t

T

1

2

T

f

V

s i n I

I

O V / U V

O F / U F

T R I P

F i l t e r

m a xV

m inV

m i nf

m a xf

R M S C A L C

2

x

R S T

ku

f i lvZ C D

m a xV

m i nV

m i nfm a xf

V

f

v f i lv

Filtering introduces delay. There are digital predictive FIR filters without delay bu with high complexity (very high order!)The RMS voltage and frequency are calculated once in a period poor detection of changes (sags, dips, etc.)



-200

-100

0

100

200

v [

V]

Basic idea of synchronization based on a phase-locked loop:

Phase-locked technology is broadly used in military, aerospace, consumer electronics systems where some kind of feedback is used to synchronize some local periodic event with some recognizable external event

Many biological processes are synchronized to environmental events. Actually, most of us schedule our daily activities phase-locking timing information supplied by a clock.

A grid connected power converter should phase-lock its internal oscillator to the grid voltage (or current), i.e., an amplitude and phase coherent internal signal should be generated.

Event based synchronization(simple, discontinuous, …)

in

v

Phase-locked synchronization(continuous, predictive,…)

PLL basis



Basic blocks:

Phase Detector (PD). This block generates an output signal proportional to the phase difference between its two input signals. Depending on the type of PD, high frequency ac components appear together the dc phase difference signal.

Loop Filter (LF). This block exhibits low pass characteristic and filters out the high frequency ac components from the PD output. Typically this is a 1-st order LPF or PI controller.

Voltage Controlled Oscillator (VCO). This block generates at its output an ac signal whose frequency varies respect a central frequency as a function of the input voltage.

Phase Detector

LoopFilter

VoltageControlledOscillator

fvvvdv

PLL basis



PLL in power systems

va

vb

T1 T3

Evdc

T5

vc

ia

T4 T6 T2

LS

+-

LLRL

In 1968 Ainsworth proposed to use a voltage controlled oscillator (VCO) inside the control loop of a High Voltage Direct Current (HVDC) transmission system to deal with the novel, at that time, harmonic instability problem.

Subsequently, analog phase lockedloops (PLL) were proposed to be used as measurement blocks, which provide frequency adaptation in motor drives.



Phase Locked Loop tuning

cos( )x

p ik k

ok

dk

c

esdv sin in inA t

PD LF

VCO

sin ωin in inv A t

cos ωVCO c outv t

Reference:

VCO output:

PD/Mixer output: sin ω cos ω sin sin2

dd d in in c out in c in out in c in out

Akv Ak t t t t

VCO angle: c o e out o et k s dt k s dt

if , then ,

Sm

all

sig

nal

an

alys

is: inωc sin 2 sin

2d

d in in out in out

Akv t

in out sin 22

dd in in in out

Akv t

The average value is 2

dd in out

Akv

sin in out in out if , then ,



Phase Locked Loop tuning

2

( )( )

( )

pp

out i

pinp

i

kk s

s TH s

kss k s

T

;2p ip

ni

k Tk

T

1.8r

n

t

29.2;

2.3s

p is

tk T

t

11p

i

kT s

esdv

PD LF - HPI VCO

in outokmk

1

s

1 1o mk k assuming

that can be written as

2

2 2

( ) 2( )

( ) 2out n n

in n n

s sH s

s s s

with

4.6s

n

t

The PLL can be tuned as function of the damping and of the settling time

then



The hold range H is the frequency range at which a PLL is able to maintain lock statically.

Key parameters of the PLL

(0)H o mk k LF

The lock range L is the frequency range within which a PLL locks within one-single beat note between the reference frequency and the output frequency.

For the PI, LF(0)=∞ and the hold range is only limited by the frequency range of the VCO

2 2 pL n

i

k

T

Pull-in time:

2L

n

T

The pull-in range P is the frequency range at which a PLL will always became locked, but the process can become rather slow. For the PI loop filter this range trends to infinite.

0 0.5 1 1.5 2 2.50

100

200

300

400

t [s]

[

rad

/s]

0 0.5 1 1.5 2 2.50

2

4

6

8

t [s]

[

rad

]

Lock-in time:

22

316in

Pn

T



Phase Locked Loop: the need of the orthogonal component

11p

i

KsT

X

X

cos

sin

s

1

in

Vsin -in out

Vsin in int

Vcos in int

in outt

+++-

To eliminate the 2° harmonic oscillation from sin 2 sin2

din in out in out

Akt

and obtain it should be considered that sin2

din out

Ak

sin - sin cos cos sinin out in out in out



Park transformation in the PD

cos( ) sin( )

sin( ) cos( )d out out

q out out

v v

v v

Park transformation:

sin( )

cos( )in

in

vV

v

sin cos cos sin sin

sin sin cos cos cosd in out in out in out

q in out in out in out

vV V

v

Assuming in=out :

sin

cosd in out

q in out

vV

v

11p

i

kT s

fvdv

LF VCO

1

sc

qv

dq

v

v

out

out

PD

inv Quadrature Signal

Generator

v

v

qv

dv

in

out

sin( )inv V v



Park transformation in the PD

0

0int

d

q

v

02out

t

sin( ) ; 0in qv V v

0

0int

d

q

v

0

0outt

sin( ) ; 0in dv V v 11p

i

kT s

fvdv

LF VCO

1

sc

dq

v

v

out in

out

PD


Generator

qv v

11p

i

kT s

fv

LF VCO

1

sc

qv

dq

v

v 2out in

out

PD


Generator

dv v

PI on vd

PI on vq

From here on, it will be considered:

and PI on vq,, i.e.,

Therefore:

sinin inv v V 0qv

andout in dv v V



Methods to create the orthogonal component

Transport Delay T/4

The transport delay block is easily implemented through the use of a first-in-first-out (FIFO) buffer, with size set to one fourth the number of samples contained in one cycle of the fundamental frequency.

This method works fine for fixed grid frequency. If the grid frequency is changing with for ex +/-1 Hz, then the PLL will produce an error

If input voltage consists of several frequency components, orthogonal signals generation will produce errors because each of the components should be delayed one fourth of its fundamental period.

11p

i

kT s

esdv

LF VCO

1

sc

qv

dqDelayT/4

v

v

PD

inv

inv



Methods to create the orthogonal component Inverse Park Transformation

A single phase voltage (v) and an internally generated signal (v’) are used as inputs to a Park transformation block (αβ-dq). The d axis output of the Park transformation is used in a control loop to obtain phase and frequency information of the input signal.

v’ is obtained through the use of an inverse Park transformation, where the inputs are the d and q-axis outputs of the Park transformation (dq-αβ). fed through first-order low pass filters.

Although the algorithm of the PLL based on the inverse Park transformation is easily implemented, requiring only an inverse Park and two first-order low-pass filters

11p

i

kT s

esdv

LF VCO

1

sc

qv

dq

v

v

PD

inv

inv

dq

LPF

LPF

dv

qvv

v



Methods to create the orthogonal component Second Order Generalized Integrator

2 2( ) ( )

d sS s s

f s

SOGI

d

q

f

2

2 2( ) ( )

qT s s

f s

2 2( ) ( )

v k sD s s

v s k s

2

2 2( ) ( )

qv kQ s s

v s k s

-60

-40

-20

0

20

Ma

gn

itud

e (

dB

)

10-1

100

101

102

103

104

-90

-45

0

45

90

Ph

ase

(d

eg

)

Frequency (Hz)

k=0.1k=1k=4

-60

-40

-20

0

20

Ma

gn

itud

e (

dB

)

10-1

100

101

102

103

104

-180

-135

-90

-45

0P

ha

se (

de

g)

Frequency (Hz)

k=0.1k=1k=4

( )D

( )Q



k

k

outvvinv

cos

sin

OSCILLATOR

Methods using adaptive filters

Adaptive Notch Filter (ANF)2 2

2 2( ) ( )out

in

v sANF s s

v s ks

vout=0 when:

vout can not be directly used as PD in the PLL

t

vout=0 when:

vout can be used as PD in the PLL

int

koutv

vinv

cos

OSCILLATOR

cosin inv A t



Methods using adaptive filters ANF-based PLL

PD

kv

cos

inv es

LF

VCO

1

scAdaptive Notch Filter

dvck

1

s

Very sensible to frequency variation ANF+PLL EPLL

More robust

Faster dynamic response

PDkv

cos

inv 11p

i

kT s

es

LF VCO

1

sc

sinAdaptive Notch Filter

dv

Conventional PLL structure

1

s

Combination of an ANF with a conventional PLL gives rise to the Enhanced PLL (EPLL)



dv

kv v

PI

cos

ju u

v ( )V

ABPF

ff

v v’

sin

VCO

LF

PD

Enhanced PLL (EPLL)

Original structure of the EPLL


×

K

×

×

90°

Kp

Ki sin

+ +

+

+

+-

y

A

Δω

ω0

θ

BPAF LP VCO

v e

1s

1s

1s



2 2( ) ( )

v k sD s s

v s k s

SOGI-PLL


2 2( ) 1 ( ) ( )

v ksABPF s ANF s s

v s ks

Adaptive band-pass filter:

Damping factor is a function of the detected frequency value

Second order generalized integrator follower:

If ’ can change, SOGI follower can be seen as an adaptive band-pass filter with damping factor set by k and unitary gain

As in the EPLL, a standard PLL can be used to detect grid frequency and angle

ju is 90º-leading v’ when the PLL is synchronized in steady state

ju=-qu and qu qv’

It seems intuitive to use -qu (instead ju) as the feedback signal for the PD of the PLL

v

VCO

kv v

qv

PI

juffsin

LF

SOGI

v

PD

Conventional PLL structure



SOGI-based Frequency Locked Loop (SOGI-FLL)


vk

v v

qv

SOGI

1

ff

v

qv

FLL

Does not need any trigonometric function since neither synchronous reference frame nor voltage controlled oscillator are used in its algorithm.

Is frequency-adaptive by using a FLL and not a PLL.

Is highly robust in front of transient events since grid frequency is more stable than voltage phase-angle.

Attenuates high-order harmonics of the grid voltage.

Entails light computational burden, using only five integrators for detection of both sequence components.



Distorted and unbalanced voltage vector

Three-phase grid synchronization

tt

1SV

1SV

SV

a

b

c

1SV

1SV

11 SS VV11 SS VV

1 2 1 2 1 1 1( ) ( ) 2 cos( 2 )S S S S SV V V V t v

1 11

1 1 1

sin( 2 )tan

cos( 2 )S

S S

V tt

V V t

a

b

c

SV

1SV

5SV

5SV

1SV

v S S Sn

S SnV V V V n t 1 2 2 12 1cos

tV n t

V V n tSn

S Sn

ta ns in

cos1

1

1

1

Neither constant amplitude nor rotation speed



Characterization of voltage dips

0 0.02 0.04 0.06 0.08 0.1-1.5

-1

-0.5

0

0.5

1

1.5

V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995

t [s]

v abc [p

u]

0 0.02 0.04 0.06 0.08 0.1-1.5

-1

-0.5

0

0.5

1

1.5

V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995

t [s]

v [p

u]

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995

v [pu]

v [p

u]

312 2

312 2

Type C

Sa

Sb

Sb

V F

V F jV

V F jV

31

2 2

312 2

Type D

Sa

Sb

Sb

V V

V V jF

V V jF

1 12

1 12

Type C

S

S

V V F

V V F

1 12

1 12

Type D

S

S

V V F

V V F

Phase-voltages from characteristic parameters

Sequence components from characteristic parameters



Three-phase Synchronous Reference Frame PLL


PIs1

SavSbvScv

dqT

Sdv

Sqv

ˆSd Sv v

-150

-100

-50

0

50

100

150

0

1

2

3

4

5

6

7

0 25 50 75 100-50

0

50

100

150

t [ms]

-150

-100

-50

0

50

100

150

0

1

2

3

4

5

6

7

0 25 50 75 100-50

0

50

100

150

t [ms]

Balanced voltage

Unbalanced voltage

Sv

Sv

ˆ t

t

Sd Sv v

0Sqv

Sd Sv v

0Sqv

11 1

1( )

ˆ ˆcos( ) cos( )

ˆ ˆsin( ) sin( )

Sd

S S Sdq Sq

v t tV V

v t t

v



-150

-100

-50

0

50

100

150

0

1

2

3

4

5

6

7

-50

0

50

100

150



The SRF is not able to track instantaneous evolution of the voltage vector when the PLL bandwidth is low

Sv

ˆ t

Sdv

Sqv

0 25 50 75 100-150

-100

-50

0

50

100

150

t [ms]

t 1ˆ Sv

1 1

( )

1 cos( 2 )v

' sin( 2 )S S Sdq

tV V

t t

' t Near of synchronization:

sin( ') 't t cos( ') 1t ' 2t t PI

s1

SavSbvScv

dqT

Sdv

Sqv

ˆSd Sv v

1

1 11sin(2 ) ' 'S

Sq S SS

Vv V t t V

V

1

1sin(2 )S

S

Vt t

V

i

p

kk

s

1

s1

SV *

1Sqv

2

2 2

ˆ 2( ) ( )

2c c

c c

sP s s

s s

1c S iV k

1

2p S

i

k V

k



-150

-100

-50

0

50

100

150



Setting a low PLL bandwidth and using a low-pass filter it is possible to obtain a reasonable approximation of the positive sequence voltage but the dynamic is too slow.

Sv

0

1

2

3

4

5

6

7

-50

0

50

100

150

Sqv

Sdv

0 25 50 75 100-150

-100

-50

0

50

100

150

t [ms]

1ˆ Sv

PIs

1

SavSbvScv

dqT

Sdv

Sqv

ˆSd Sv v

Repetitive controller

Advanced filtering strategies can be used to cancel out the double frequency oscillation keeping high locking dynamics, e.g., a repetitive controller based on a DFT algorithm. Additional improvements are added to these filters to make them frequency adaptive.



Decoupled Doubled SRF-PLL. Decoupling


1

11 1

11 1

1( )( )

ˆ ˆcos( ) cos( )

ˆ ˆsin( ) sin( )

SdS S S Sdqdq Sq

v t tT V V

v t t

v v

1

11 1

11 1

1( )( )

ˆ ˆcos( ) cos( )

ˆ ˆsin( ) sin( )

SdS S S Sdqdq Sq

v t tT V V

v t t

v v

' t Near of synchronization:

1

11 1

1( )

1 cos( 2 )ˆ sin( 2 )

S S Sdq

tV V

tt

v

1

11 1

1( )

cos(2 ) cos( )

sin(2 ) sin( )S S Sdq

tV V

t

v

cos(( ) ) sin(( ) )cos( )cos( ) sin( )

sin(( ) ) cos(( ) )sin( )

n

n

n nSd m m m mS

S Sn nSq S

v n m t n m tVV V

v n m t n m tV

cos(( ) ) sin(( ) )cos( )cos( ) sin( ) .

sin(( ) ) cos(( ) )sin( )

m

m

m mSd n n n nS

S Sm mSq S

v n m t n m tVV V

v n m t n m tV

Generic decoupling cell:

cos

nSdv

sin

mSdv mSq

v

nSqv

*nSd

v

*nSq

v

m

nDC

nd

nq

mdmq *nd

*nq

n-m

This terms act as interferences on

the SRF dqn rotating at n frequency and

viceversa




y

.

Decoupled Doubled SRF-PLL

1Sdv

1Sqv

1d1q

1

1DC

1d1q

*1d

*1q

1Sdv

1Sqv

*1Sd

v

*1Sq

v

*1Sd

v

*1Sq

v

1Sdv

1Sqv

1

1ˆ SSdv

v

1Sqv

T Sv

1dqT

1dqT

abcSv

1d 1q

1

1DC

1d1q

*1d

*1q

ip kk

LPF

LPF

LPF

LPF

1

*

Sqv

*1Sq

v

2 2q d qv v v

f

f

PLL input normalization



Conclusions

PLL is a very useful method that enable the grid inverters to: Create a "clean" current reference synchronized with the grid Comply with the grid monitoring standards

The PLL generate is able to track the frequency and phase of the input signal in a designed settling time

By setting a higher settling time a "filtering" effect can be achieved in order to obtain a "clean" reference even with a polluted grid.

Some PLLs need two signals in quadrature at the input. For single-phase systems as there is only one signal available, the

orthogonal signal needs to be created artificially. Transport Delay, Inverse Park Transformation, or Second Order

Generalized Integrators are some the methods used for quadrature signal generation.

Adaptive notch filters canceling fundamental utility frequency are used as phase detectors in PLLs

FLL based on a SOGI is a very effective method for single phase synchronization



References1. J. D. Ainsworth, “The phase-locked oscillator-a new control system for controlled static

convertors,” IEEE Transactions on Power Apparatus and Systems, vol. 87, no. 3, pp. 859-865,

Mar. 1968.

2. G. C. Hsieh, J. C. Hung, Phase-locked loop techniques – A survey, IEEE Trans. On Ind.

Electronics, vol.43, pp.609-615, Dec.1996.

3. F. M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.

4. L. D. Zhang, M. H. J. Bollen Characteristic of voltage dips (sags) in power systems, IEEE Trans.

Power Delivery, vol.15, pp.827-832, April 2000.

5. F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, “Overview of Control and Grid

Synchronization for Distributed Power Generation Systems”, IEEE Trans. on Ind. Electronics, Vol.

53, Oct. 2006 Page(s):1398 – 1409

6. M. K. Ghartemani, M.R. Iravani, “A method for synchronization of power electronic converters in

polluted and variable-frequency environments,” IEEE Trans. Power Systems, vol. 19, pp. 1263-

1270, Aug. 2004.

7. M.K. Ghartemani, M.R. Iravani, “A Method for Synchronization of Power Electronic Converters in

Polluted and Variable-Frequency Environments,” IEEE Trans. Power Systems, vol. 19, Aug.

2004, pp. 1263-1270.

8. H.-S. Song and K. Nam, “Dual current control scheme for PWM converter under unbalanced input

voltage conditions,” IEEE Trans. On Industrial Electronics, vol. 46, no. 5, pp. 953–959, 1999.



References1. P. Rodríguez, A. Luna, I. Candela, R. Teodorescu, and F. Blaabjerg, “Grid Synchronization

of Power Converters using Multiple Second Order Generalized Integrators,” IECON’08, Nov.

2008.

2. P. Rodríguez, J. Pou, J. Bergas, J.I. Candela, R. Burgos and D. Boroyevich, “Decoupled

Double Synchronous Reference Frame PLL for Power Converters Control,” IEEE Trans. on

Power Electronics, March 2007.

3. P. Rodriguez, R. Teodorescu, R.; I. Candela, I.; A.V. Timbus, M. Liserre, F. Blaabjerg, “New

Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under

Faulty Grid Conditions,” PESC '06, June 2006.

4. M Ciubotaru, Teodorescu, R., Blaabjerg, F., “A New Single-Phase PLL Structure Based on

Second Order Generalized Integrator”, PESC’06, June 2006.

5. P. Rodríguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “Advanced Grid

Synchronization System for Power Converters under Unbalanced and Distorted Operating

Conditions,” IECON’06, Nov. 2006.

6. S.-K. Chung, “Phase-Locked Loop for grid-connected three-phase power conversion

systems,” IEE Proceedings on Electronic Power Applications, vol. 147, no. 3, pp. 213–219,

2000.

7. Francisco Daniel Freijedo Fernández, “Contributions to Grid-Synchronization Techniques for

Power Electronic Converters”, PhD Thesis, Vigo University, Spain, 2009



Acknowledgment

Part of the material is or was included in the present and/or past editions of the

“Industrial/Ph.D. Course in Power Electronics for Renewable Energy Systems – in theory and practice”

Speakers: R. Teodorescu, P. Rodriguez, M. Liserre, J. M. Guerrero,

Place: Aalborg University, Denmark

The course is held twice (May and November) every year

grid synchronization for power converters marco liserre [email protected] grid synchronization for...

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