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Lecture 12

PVT Variations

Device Mismatch

R. Dutton, B. Murmann

R. Dutton, B. Murmann 1EE114 (HO # 15)

an or n vers y

Re-cap

What weve covered so far

Device modeling

Analysis tools (Miller approximation, ZVTC)

Fundamental stage configurations (CS, CG, CD)

What we have implicitly assumed

We have nearly ideal current and voltage sources available

to set up the transistors bias points

Transistor parameters and supply voltage do not vary

The next set of lectures will move us toward the practical

R. Dutton, B. Murmann 2

implementation of transistor stages

Focusing on biasing schemes that are insensitive to

variations commonly seen in IC technology

EE114 (HO # 15)

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Process Variations

Wafer made yesterday

All NMOS are slow

All PMOS are nominal

Wafer made today

All NMOS are fast

All PMOS are fast

Parameter Slow Nominal Fast

Vt 0.65V 0.5V 0.35V

Cox (NMOS) 40 A/V2 50 A/V2 60 A/V2

Cox (PMOS) 20 A/V2 25 A/V2 30 A/V2

All C are fast

All C are slow

R. Dutton, B. Murmann 5EE114 (HO # 15)

Rpoly2 60/ 50/ 40/

Rnwell 1.4 k/ 1 k/ 0.6 k/

Cpoly-poly2 1.15 fF/m2 1 fF/m2 0.85 fF/m2

Temperature Coeffic ients

Parameter Approximate TC

Vt -1.2 mV/C

Cox (NMOS) -0.33 %/C

Cox (PMOS) -0.33 %/C

Rpoly2 +0.2 %/C

Rnwell +1 %/C

Cpoly-poly2 -30 ppm/C

R. Dutton, B. Murmann 6EE114 (HO # 15)

* The defaul t t emper ature i n Spi ce i s 25 degr ees Cel si us

* The f ol l owi ng command set s t he temperat ure t o 100 degr ees Cel si us

. t emp 100

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Mismatch

Upon closer inspection, device parameters not only vary fromlot-to-lot or wafer-to-wafer, but there are also differences

between closely spaced, nominally identical devices on the

same c p

These differences are called mismatch

L

WC

L

WC

VVV

oxox

ttt

=

=

21

21

R. Dutton, B. Murmann 11EE114 (HO # 15)

CCC = 21

Statistical Model

Experiments over the past decades have shown that

mismatches in device parameters (Vt, C, ) are typicallyrandom and well-described by a Gaussian distribution

With zero mean and a standard deviation that depends on

the process and the size of the device

Empirically, the standard deviation of the mismatch between two

closely spaced devices can be modeled using the following

expression

WL

AX

X=

R. Dutton, B. Murmann 12EE114 (HO # 15)

where WL represents the area of the device, and X is the

device parameter under consideration

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Coefficients for the EE114 Technology

Parameter Value

AVt 20 mV-m

A/ 2 %-m

AC/C (Poly-Poly2 capacitor) 2.5 %-m

AR/R (Poly2 resistor) 10 %-m

R. Dutton, B. Murmann 13EE114 (HO # 15)

Example

Example: MOSFET with W= 20m, L=1 m

%mV 220.m.

tV

2020====

http://en.wikipedia.org/wiki/Image:Standard_deviation_diagram.svg

mV.t

V 5133 =

R. Dutton, B. Murmann 14EE114 (HO # 15)

%.3513 =

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Mismatch in EE114

Again, for simplicity, we do not want to go overboard in EE114in terms of taking mismatch into account

More on this topic in EE315A, EE315B

Nonetheless, we should use the information from the previous

slides to guide our expectation on how well two transistors on

the same chip can match

Important e.g. in the context of current mirrors (lecture 13)

Typical numbers to remember

Vt of a close-by pair of MOSFETS typically shows mismatch

R. Dutton, B. Murmann 15

on e or er o m

=CoxW/L of a close-by pair of MOSFETS typically shows

mismatch on the order of 0.52%

EE114 (HO # 15)

Aside: Well Proximity Effects

Modern technologies Many fancy issues that can cause mismatch

between two devices

R. Dutton, B. Murmann 16EE114 (HO # 15)

P. G. Drennan et al., "Implications of Proximity Effects for Analog Design," Proc. CICC, pp.169-176, Sep. 2006.