h64rfp course work uk guideline part2

7/30/2019 H64RFP Course Work UK Guideline Part2

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H64RFP Course work

D o w n l o a d i n g t h e p r o j e c t f i l e.

To start the course work you will need to download from the course website the project file.

This can be found at http://hermes.eee.nott.ac.uk/teaching/h64rfp/h64rfl.zap. Download the

file and place in the directory c:\users\default. When internet explorer downloads this file, it

will change the extension from h64rfl.zap to h64rfl.zip ( Firefox does not have this problem.)

To proceed you will need to change the extension of the file. This can be done by opening a

directory folder and changing the extension manually.

This can only be done if you have unchecked the hide extension of known file types underthe view tab of folder options.

S t ar t i n g t h e A D S p r o g r a m

To start the program click on the advance system design which can be found on the start

menu. (see figure below)

At which point a dialog window will open telling you that the software is initialising. This

window will not disappear for several minutes.
http://hermes.eee.nott.ac.uk/teaching/h64rfp/h64rfl.zaphttp://hermes.eee.nott.ac.uk/teaching/h64rfp/h64rfl.zap


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When the dialog box disappears two windows appear. The top one invites you to decide on

an option. This window is displayed below. You should close this window.

The remaining window is the control window for the ADS program.


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U n a r c h i v i n g t h e p r o j ec t f i l e

To unarchive the project file select the unarchive project menu item which can be found

under file. The following dialog box should open.

Select the unarchive file by selecting the browse tab. The ADS program does not like spaces

in the filename or directories. So do not put your project file in my documents.

I recommend that you leave the To Directory at the default value of C:\users\default

During the unarchiving process you may see warning windows. Please close the window andignore these warning whenever they occur.

Several other windows may open which would allow you to start your design process. At this

stage I would close the project so that the project can be renamed. The project can be closed

from the ADS control window and finding the close project option under the file menu.

This will automatically close any schematic or layout windows associated with the project.

S t ar t o f d e s i g n p r o c e s s .

Obviously, I cannot use the course work has a design example so I am going to design a8GHz transistor with a VDS=1V and IDS=10mA. Note these are not the optimum values.

Choice of Bias condition

The data sheet for the transistor is provided on the module web site. This data sheet should be

read and the appropriate bias point chosen. You must choose the bias point so that the gain is

above that stated in the specifications whilst the noise figure is below the specification value.

The Avago website also provides data files containing the measured S-parameters for use in

simulations. For your convenience, these data files are contained in the project directory. The

names of the files and the appropriate bias conditions are given in the table below

Filename VDS IDS NoiseF361630o.s2p 0 0 No


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F361631a.s2p 1.5 10mA Yes

F361631b.s2p 1.5 15mA Yes

F361631c.s2p 1.5 20mA Yes

F361630o.s2p 0 (VGS=-1.5V) 0 No

F361632a.s2p 2 10mA Yes

F361632b.s2p 2 15mA YesF361632c.s2p 2 20mA Yes

F361632o.s2p 2 (VGS=-1.5V) 0 No

Simulations using experimentally derived S-parameters reflect real life better than those

derived from the SPICE.

Finding the bias conditions

Once you have chosen the bias point you will need to find the required VGS to get the

appropriate drain current. This can be achieved by using the schematic design sheet calledTestDC.dsn. This can be opened from the ADSA control window by clicking on the

networks directory and then the appropriate file ( see the diagram below)

This should open a new schematic design window containing the following schematic.


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The schematic contains several items of interest. The first along the top is the toolbar with

small icons which allows you to perform a variety of tasks. These tasks can also be

accomplished by selecting the correct menu items.

The important ones are in the table below:

Simulate the circuit. This will automatically

open a data display window when the

simulation has stopped.

Wire components together. To the right ofthis control is the icon to name a wire. If two

wires have the same name they are

electrically connected even if there is no

physical wire in the schematic.

Save current design

Zoom to extents of the design. To the right of

this control there are four other zoom

controls for area, zoom to the point , zoom in

by a factor of two and zoom out by a factorof two.

Disable control or component. This is used to

remove a component from the simulation. I

use this facility to switch between the Spice

model of the transistor and the s-parameter

model.

When designing circuits it is useful to design

subnetworks. You can descend into the sub-

network by using this control. ( Select the

component and then hit the icon. ( The otherway around also works)


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This control changes the palette of controls in

the left hand tool bar. The default is the

lumped-components. This toolbar is used to

select other components and simulation

controls to place on the schematic.

On the schematic I changed the value of VDS and ran the simulation. After the simulationhas run, the simulation results are stored in a data set called TESTDC and a data display sheet

called TestDC is opened to display them. The items on the data display can be changed. If

you save the data display window then those changes will be permanent. The actual name of

the data set and the data sheet opened after the simulation has been run can be changed from

the schematic entry window by clicking the simulation setup menu item on the simulation

drop down menu item.

The example for my case is shown below.

The diagram above shows that I need a VGS of -0.91V.

Obtaining the S-parameters of our amplifier.

The next stage of the design process is to obtain the s-parameters, and decide on the load and

source impedances seen by the transistor. These choices are extremely important since they

will determine the performance of the amplifier.

The staring point for this process is the schematic diagram window. This can be opened by

returning back to the ADS control window and selecting GETSP.dsn under networks.


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The default action of the schematic is to use the SPICE model for the simulation and to set

the bias voltages using the terminators. Although the experimentally derived S-parameters are

more accurate, the SPICE model is used by default because it is more general. Moreover, the

DC voltages are set using the terminators. This effectively simulates the situation where

special components called bias Tees are used at the input and output to deliver the DC bias.

Since there are no experimentally derived S-parameter data for my bias conditions, the

SPICE model will be used to generate the S-parameters for the FET. After simulating the

GETSP data display will open.


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This is quite a complex diagram and the underlying mathematics are not part of this course.

There are several things to note. If the device is stable and we choose to design the matchingcircuits for maximum gain we have no control over the noise figure and so frequently the

source is deliberately not matched. Consequently S11 will not be very small. Please note on

the require specifications no bound for S11 has been set. There is usually a trade off between

gain and noise figure. By mismatching the source we can select the compromise between

gain and noise figure. The purple circles in the above diagram are circles of constant gain.

The actual values of gain can be set by changing the purple values. The green curves are

constant noise circles. The actual values of these circles are set by the green values. The other

important curve, for my case, is the red curve. This is the source mismatch stability curve. At

the frequency I have chosen to design at the transistor is potential unstable and if the wrong

source and load impedances are used the transistor will oscillate. The region of stability is

noted top right. For my case, if the point I choose is outside the red circle, it will be stable.

Since I want a gain of 8 and the lowest possible noise figure, I move the marker on the purple

curve which has a gain of 8 until the noise figure is at the lowest. The noise figure at the

cursor is given bottom left.

The cursor gives me the source reflection coefficient (GS) that must be seen by the input of

the transistor to achieve that gain and noise figure. To understand the different definitions

used in the data display window, the diagram taken from the lecture notes has been modified .

The admittance which requires matching is yIn This value is a normalised value and I have


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assumed the impedance of the transmission line is Z0=50.

The load impedance is chosen so that it is a conjugately matched to the transistor. This means

the impedance seen at the output of the load is chosen for maximum power transfer. The

equations for this are not part of this course. To achieve the required performance you need to

design your output coupler to match yOut.

Once you have chosen designed your Matching network and any biasing network you can use

the schematic sheet Amp_design1 to simulated your results.

ADS allows the simulation of microstrip transmission lines. These components are selectedon the appropriate component toolbar. This can be seen in the figure below where I have

started to design an open stub matching network

Z0YIn

XS

XL

S,ZS, YS


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There are several things you need to note. You will need to determine the length of the stub

and offset. This comes from your Smith charts in terms of the wavelengths.

To find the width of the transmission lines and the wavelength you can use either the

standard txline program or use LineCalc which is part of the Ads program and can be found

under the menu item Tools. Opening this program you will be presented with the following

window


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You will need to enter in the substrate parameters, these are given in the project

documentation and set the frequency. I have selected 50 for Z0 and used an effective length

of 360 degrees. So when I hit the synthesize button LineCalc will determine W and L for me.

W will be the width of the transmission lines in schematic entry and L gives the wavelength. (

Note if you do not use a unit when entering the lengths ADS assumes the length is inmetres!!.)

Once you have designed your input and output matching networks you will need to simulate

your design. After the simulation is complete a data display window will open.


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At this point, the performance may be below what you expected. There are a variety of

reasons. (1) The simple methodology used to calculate the size of the stubs ignores the

fringing capacitance at the end of the line. (2) The junction of the two transmission lines will

have some parasitics associated with the junction and again our simple analysis does not take

this into account. Additional the methods is a single frequency technique but the problem set

requires performance over a frequency range and this will required some minor alterations of

the circuit.

Optimisation

The lengths of the line will need to be modified for the reasons given above. There are

several ways to do this. The first, which is not recommended, is to make the changes

manually and rerun the simulation. The seconded and recommended way is to use the ADStune facility. This is very similar to the first method except that the software automatically

changes the value of the component, reruns the simulation and updates the data display.

The third method is to use optimisation facility within ADS.

Tuning of components

Before the tuning facility can be used, components need to be modified to allow their values

to be changed. This is done by left clicking on the component to open up the properties dialog

box


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On the right hand side of this window, there is a button labelled Tune/Opt/Stat/DOE Setup

: click this to open the dialog box which allows the enabling of tuning for this parameter.

.

Once you have enabled all the parameters you want to include in the optimisation process

you press the tuning fork icon on the toolbar. This opens up the tuning dialog box


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When the sliding scales are moved, the value is updated on the component, the simulation run

and the data display updated. This allows you to tune the lengths of the stubs and the stub

offsets.

Other components

To obtain full marks for the course work you will need to design the bias network. The key

points to remember are

(1) a voltage source appears as a short circuit to a microwave or RF signal

(2) the leads from the board to the external voltage source will act as an inductor. The best

model to use for an external voltage source is shown below.

Vgs

MRSTUB

Stub2

Angle=50

L=2.332 mm

Wi=1.787 mmSubst="MSub1"V_DC

SRC1

Vdc=VGS

DC_Feed

DC_Feed1

The DC feed models the worst case scenario when the inductance of the wire is extremely

high, the wedges shaped component acts like a capacitor. The values shown in the diagramwill give values between 1 and 2 pF depending on the frequency.


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Usually the input and output are isolated from the DC and so a DC blocking series capacitor

will be required. The self-resonant frequency of most conventional capacitors is below the

frequency range of this problem. An alternative is to use an inter-digital capacitor provides

this functionality. This component is shown below and has a typical capacitance between 1 -

4 pF depending on the frequency.

MICAP1

C1

Wf=W50

Wt=W50

Np=6

L=1.1 mm

Ge=0.2 mmG=0.2 mm

W=0.2 mm

Subst="MSub1"

Layout.

At this point you are essentially designing the PCB for the circuit. If you select layout menu

item and the generate/update layout item you can automatically place the components on the

layout.

h64rfp course work uk guideline part2

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