h8s/2138, h8s2134 series - farnell element14 · an on-chip data transfer controller (dtc) is also...

Hitachi 16-Bit Single-Chip Microcomputer

H8S/2138 SeriesH8S/2134 Series

H8S/2138F-ZTAT™H8S/2134F-ZTAT™H8S/2132F-ZTAT™

H8S/2138 HD6432138SW, HD6432138SH8S/2137 HD6432137SW, HD6432137S

H8S/2134 HD6432134SH8S/2133 HD6432133SH8S/2132 HD6432132H8S/2130 HD6432130

H8S/2138F-ZTAT™ HD64F2138, HD64F2138VHD64F2138A, HD64F2138AV

H8S/2134F-ZTAT™ HD64F2134, HD64F2134VHD64F2134A, HD64F2134AV

H8S/2132F-ZTAT™ HD64F2132R, HD64F2132RV

Hardware ManualADE-602-144BRev. 3.04/5/01Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’spatent, copyright, trademark, or other intellectual property rights for information contained inthis document. Hitachi bears no responsibility for problems that may arise with third party’srights, including intellectual property rights, in connection with use of the informationcontained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that youhave received the latest product standards or specifications before final design, purchase oruse.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.However, contact Hitachi’s sales office before using the product in an application thatdemands especially high quality and reliability or where its failure or malfunction may directlythreaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclearpower, combustion control, transportation, traffic, safety equipment or medical equipment forlife support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachiparticularly for maximum rating, operating supply voltage range, heat radiation characteristics,installation conditions and other characteristics. Hitachi bears no responsibility for failure ordamage when used beyond the guaranteed ranges. Even within the guaranteed ranges,consider normally foreseeable failure rates or failure modes in semiconductor devices andemploy systemic measures such as fail-safes, so that the equipment incorporating Hitachiproduct does not cause bodily injury, fire or other consequential damage due to operation ofthe Hitachi product.

5. This product is not designed to be radiation resistant.

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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachisemiconductor products.

Preface

The H8S/2138 Series and H8S/2134 Series comprise high-performance microcomputers with a32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for systemconfiguration.

The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteeninternal 16-bit general registers with a 32-bit configuration, and a concise and optimizedinstruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).Programs based on the high-level language C can also be run efficiently.

Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,providing a quick and flexible response to conditions from ramp-up through full-scale volumeproduction, even for applications with frequently changing specifications.

On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR),watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface(SCI, IrDA), host interface (HIF), D/A converter (DAC), A/D converter (ADC), and I/O ports. AnI2C bus interface (IIC) can also be incorporated as an option.

An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transferwithout CPU intervention.

The H8S/2138 Series has all the above on-chip supporting functions, and can also be providedwith an IIC module as an option. The H8S/2134 Series comprises reduced-function versions, withfewer TMR channels, and no PWM, HIF, IIC, or DTC modules.

Use of the H8S/2138 or H8S/2134 Series enables compact, high-performance systems to beimplemented easily. The comprehensive PC-related interface functions and 16 × 8 matrix key-scan functions are ideal for applications such as notebook PC keyboard control and intelligentbattery and power supply control, while the various timer functions and their interconnectability(timer connection), plus the interlinked operation of the I2C bus interface and data transfercontroller (DTC), in particular, make these devices ideal for use in PC monitors. In addition, thecombination of F-ZTAT™* and reduced-function versions is ideal for applications such as systemunits in which on-chip program memory is essential to meet performance requirements, productstart-up times are short, and program modifications may be necessary after end-product assembly.

This manual describes the hardware of the H8S/2138 Series and H8S/2134 Series. Refer to theH8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of theinstruction set.

Note: * F-ZTAT™ (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

On-Chip Supporting Modules

Series H8S/2138 Series H8S/2134 Series

Product names H8S/2138, 2137 H8S/2134, 2133, 2132,2130

Bus controller (BSC) Available (8 bits) Available (8 bits)

Data transfer controller (DTC) Available —

8-bit PWM timer (PWM) ×16 —

14-bit PWM timer (PWMX) ×2 ×2

16-bit free-running timer (FRT) ×1 ×1

8-bit timer (TMR) ×4 ×3

Timer connection Available —

Watchdog timer (WDT) ×2 ×2

Serial communication interface (SCI) ×3 ×3

I2C bus interface (IIC) ×2 (option) —

Host interface (HIF) ×2 —

D/A converter ×2 ×2

A/D converter ×8 (analog input) ×8 (analog input)

×8(expansion A/D inputs)

×8(expansion A/D inputs)

Main Revisions and Additions in this Edition

Main Revisions and Additions in this Edition

Page Item Revision (See Manual for Details)

All pages ofthis manual

Amendments due to introduction of the A mask versions(HD64F2138A, HD64F2134A)

5 1.1 Overview Table 1.1 Overview

Product lineup amended

6 1.2 Internal Block Diagram Figure 1.1 Internal Block Diagram of H8S/2138 Series

VCC2 (VCL) pin amended

7 Figure 1.2 Internal Block Diagram of H8S/2134 Series

VCC2 (VCL) pin amended

8 1.3.1 Pin Arrangement Figure 1.3 Pin Arrangement of H8S/2138 Series (FP-80A,TFP-80C: Top View)

Pin No.8: VCC2 (VCL) pin amended

9 Figure 1.4 Pin Arrangement of H8S/2134 Series (FP-80A,TFP-80C: Top View)

Pin No. 8: VCC2 (VCL) pin amended

10 1.3.2 Pin Functions in EachOperating Mode

Table 1.2 H8S/2138 Series Pin Functions in Eachoperating Mode


14 Table 1.3 H8S/2134 Series Pin Functions in Eachoperating Mode


17, 20, 22 1.3.3 Pin Functions Table 1.4 Pin Functions

Power supply: VCL added

Serial communication interface (SCI0, SCI1, SCI2): Serialclock description amended

I/O ports: Port 5 and Port 9 description amended

Note amended

All pages ofsection 2

Notes on TAS instruction added

Notes on STM/LDM instruction added

71, 72 3.2.2 System ControlRegister (SYSCR)

Bit 7 description amended

Bit 6 Note added

73 3.2.3 Bus Control Register(BCR)

Bit 1 and Bit 0 Note added


74 3.2.4 Serial Timer ControlRegister (STCR)

Bit 7 and bit 6 description amended

77 3.5 Memory Map in EachOperating Mode

Description added

Do not access the reserved area and ...when theseregions are accessed.

79, 80 Figure 3.2 H8S/2138 F-ZTAT A-mask Version MemoryMap in Each Operating Mode added

87 4.1.1 Exception HandlingTypes and Priority

Table 4.1 Exception Types and Priority

Trace description amended

93 4.3 Interrupts Description amended

Interrupts other than NMI and address break

96 4.6 Notes on Use of theStack

Figure 4.6 Operation when SP Value is Odd amended

97 5.1.1 Features Priorities settable with ICR description amended

All interrupts except NMI and address break

98 5.1.2 Block Diagram Figure 5.1 Block Diagram of Interrupt Controller

Internal interrupt requests amended

99 5.1.4 RegisterConfiguration

Table 5.2 Interrupt Controller Registers

Note 3 amended

101 5.2.2 Interrupt ControlRegisters A to C (ICRA toICRC)

Description amended

Interrupts other than NMI and address break

104 5.2.5 IRQ status register Note added

105 5.2.6 Keyboard MatrixInterrupt Mask Register(KMIMR)

Description amended

Bits 7 to 0 Note amended

109 5.3.1 External Interrupts IRQ7 to IRQ0 Interrupts: description added

When the IRQ6 pin is assigned as the IRQ6 interruptinput pin, then set the KMIMR6 bit to 0.

116 5.5.1 Interrupt ControlModes and InterruptOperation

Description amended

NMI and address break interrupts

117 Table 5.6 Interrupts Selected in Each Interrupt ControlMode

Address break interrupts added

121 5.5.3 Interrupt ControlMode 1

Address break Interrupts description added


135 6.2.2 Wait State ControlRegister (WSCR)


138 6.3.2 Advanced Mode Description amended due to the addition of theH8S/2138F-ZTAT A mask version.

139 6.3.4 I/O Select Signal Table 6.4 IOS Signal Output Range

Note added

145 6.4.5 Wait Control Figure 6.7 Example of Wait State Insertion Timing WRtiming amended


Table 9.2 PWM Timer Module Registers

Note 2 added


Table 10.2 Register Configuration

Note 2 amended

278 11.3.5 Timing of InputCapture Flag (ICF) Setting

Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D)ICRA/B/C/D timing amended

283 11.6 Usage Note Figure 11.21 Contention between OCRAR/OCRAF Writeand Compare-Match (When Automatic Addition FunctionIs Used) added

302 12.2.6. Serial/Timer ControlRegister (STCR)


312 to313

12.3.6 Input CaptureOperation

Added

335 13.3.1 PWM Decoding(PDC Signal Generation)

Figure 13.2 Timing Chart for PWM Decoding amended

354 14.2.2 Timer Control/StatusRegister (TCSR)

Bit 7: Note added

364 15.1.1 Features Capability of transmit and receive clock output descriptionadded

438 16.2.1 I2C Bus DataRegister (ICDR)

TDRE: 1 description amended

445 16.2.5 I2C Bus ControlRegister (ICCR)


449 Bit 1 description amended

455 16.2.6 I2C Bus StatusRegister (ICSR)


461 16.3.1 I2C Bus Data Format Figure 16.4 Formatless added

462 to 464 16.3.2 Master TransmitOperation

Completely amended


464 to 466 16.3.3 Master ReceiveOperation

Completely amended

475, 476 16.3.10 Sample Flowchart Figure 16.14 Flowchart for Master Transmit Mode(Example)

Figure 16.15 Flowchart for Master Receive Mode(Example)

completely amended

478 16.3.11 Initialization ofInternal State

Description amended

Executed in accordance with the setting of bits CLR3 toCLR0 in the DDCSWR register or clearing ICE bit

484 16.4 Usage Notes • Notes on Start Condition Issuance for Retransmission

• Notes I2C Bus Interface Stop Condition InstructionIssuance

added

522 19.2.3 A/D Control Register(ADCR)

Bits 5 to 0 description amended

541 20.3.2 Single-Chip Mode(Modes 2 and 3 (EXPE=0))

Description amendedUndefined values are always read from these bits, andwriting is invalid.

— 21. ROM Description of ROM is added due to the introduction ofthe H8S/2138 and H8S/2134 A-mask version

21. ROM (Mask ROM version, H8S/2138F-ZTAT,H8S/2134F-ZTAT, and H8S/2132F-ZTAT)

22. ROM (H8S/2138F-ZTAT A-mask version andH8S/2134F-ZTAT A-mask version)

548 21.4.3 Flash MemoryOperating Modes

Figure 21.3 Flash Memory Mode TransitionsBit name amended between user mode and user programmode

557 21.5.4 Serial/Timer ControlRegister (STCR)


562 21.6.1 Boot Mode Figure 21.10 RAM Areas in Boot Modeadded

573 21.10.1 Programmer ModeSetting

Notes added

585 21.11 Flash MemoryProgramming and ErasingPrecautions

Description amended


586 21.12 Note on Switchingfrom F-ZTAT Version toRAM Version

Added

587 to 630 22. ROM Added

639 23.9. Clock SelectionCircuit

Added


Table 24.3 Power-Down State Registers

Note 2 added

654 24.5.1 Module Stop Mode MSTP2 bit: Description amendedNote amended

663 to 774 25. ElectricalCharacteristics

Completely amended

All pages ofAppendix A

Notes on TAS instruction added

846, 847 B.2 Register SelectionConditions

H8S/2134 Series H'FF83 SYSCR2 amended

H8S/2138 Series and H8S/2134 Series H'FF94, H'FF95and H'FF98 to H'FF9D amended

—

860

872

874

901

903

B.3 Functions Registers are amended

H'FEEB: ISR

H'FF86, H'FF87 : MSTPCRH/L

H'FF88, H'FFD8 : ICCR1/0

H'FFC4: SYSCR

H'FFC6: BCR

928 to 930 C.2 Port 2 Block Diagrams Figure C.2, C.3, C.4 Port 2 Block Diagram amended

931 C.3 Port 3 Block Diagram Figure C.5 Port 3 Block Diagram amended

932 to 938

939 to 941

948 to 953

954 to 958

C.4 Port 4 Block Diagrams




Figure C.6, C.7, C.8, C.9, C.10, C.11, C.12 Port 4 BlockDiagram amended

Figure C.13, C.14, C.15 Port 5 Block Diagram amended

Figure C.23, C.24, C.25, C.26, C.27, C.28 Port 8 BlockDiagram amended

Figure C.29, C.30, C.31, C.33 Port 9 Block Diagramamended

962, 963 F. Product Code Lineup Amendments due to introduction of the A-mask versions

(HD64F2138A, HD64F2134A)

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Contents

Section 1 Overview ........................................................................................................... 11.1 Overview............................................................................................................................ 11.2 Internal Block Diagram ..................................................................................................... 61.3 Pin Arrangement and Functions......................................................................................... 8

1.3.1 Pin Arrangement................................................................................................... 81.3.2 Pin Functions in Each Operating Mode................................................................ 101.3.3 Pin Functions ........................................................................................................ 17

Section 2 CPU..................................................................................................................... 232.1 Overview............................................................................................................................ 23

2.1.1 Features................................................................................................................. 232.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU................................... 242.1.3 Differences from H8/300 CPU............................................................................. 252.1.4 Differences from H8/300H CPU .......................................................................... 25

2.2 CPU Operating Modes....................................................................................................... 262.3 Address Space.................................................................................................................... 312.4 Register Configuration....................................................................................................... 32

2.4.1 Overview............................................................................................................... 322.4.2 General Registers.................................................................................................. 332.4.3 Control Registers .................................................................................................. 342.4.4 Initial Register Values .......................................................................................... 35

2.5 Data Formats...................................................................................................................... 362.5.1 General Register Data Formats............................................................................. 362.5.2 Memory Data Formats.......................................................................................... 38

2.6 Instruction Set .................................................................................................................... 392.6.1 Overview............................................................................................................... 392.6.2 Instructions and Addressing Modes ..................................................................... 402.6.3 Table of Instructions Classified by Function........................................................ 422.6.4 Basic Instruction Formats..................................................................................... 512.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... 52

2.7 Addressing Modes and Effective Address Calculation ..................................................... 522.7.1 Addressing Mode.................................................................................................. 522.7.2 Effective Address Calculation .............................................................................. 55

2.8 Processing States ............................................................................................................... 592.8.1 Overview............................................................................................................... 592.8.2 Reset State ............................................................................................................ 602.8.3 Exception-Handling State..................................................................................... 612.8.4 Program Execution State ...................................................................................... 622.8.5 Bus-Released State ............................................................................................... 62

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2.8.6 Power-Down State ................................................................................................ 622.9 Basic Timing...................................................................................................................... 63

2.9.1 Overview............................................................................................................... 632.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 632.9.3 On-Chip Supporting Module Access Timing....................................................... 652.9.4 External Address Space Access Timing............................................................... 66

2.10 Usage Note......................................................................................................................... 662.10.1 TAS Instruction .................................................................................................... 662.10.2 STM/LDM Instruction.......................................................................................... 67

Section 3 MCU Operating Modes................................................................................. 693.1 Overview............................................................................................................................ 69

3.1.1 Operating Mode Selection .................................................................................... 693.1.2 Register Configuration ......................................................................................... 70

3.2 Register Descriptions......................................................................................................... 703.2.1 Mode Control Register (MDCR) .......................................................................... 703.2.2 System Control Register (SYSCR)....................................................................... 713.2.3 Bus Control Register (BCR)................................................................................. 733.2.4 Serial Timer Control Register (STCR)................................................................. 74

3.3 Operating Mode Descriptions ............................................................................................ 753.3.1 Mode 1 .................................................................................................................. 753.3.2 Mode 2 .................................................................................................................. 753.3.3 Mode 3 .................................................................................................................. 76

3.4 Pin Functions in Each Operating Mode............................................................................. 763.5 Memory Map in Each Operating Mode............................................................................. 76

Section 4 Exception Handling........................................................................................ 874.1 Overview............................................................................................................................ 87

4.1.1 Exception Handling Types and Priority ............................................................... 874.1.2 Exception Handling Operation ............................................................................. 874.1.3 Exception Sources and Vector Table ................................................................... 88

4.2 Reset................................................................................................................................... 904.2.1 Overview............................................................................................................... 904.2.2 Reset Sequence..................................................................................................... 904.2.3 Interrupts after Reset............................................................................................. 92

4.3 Interrupts ............................................................................................................................ 934.4 Trap Instruction ................................................................................................................. 944.5 Stack Status after Exception Handling .............................................................................. 954.6 Notes on Use of the Stack.................................................................................................. 96

Section 5 Interrupt Controller......................................................................................... 975.1 Overview............................................................................................................................ 97

5.1.1 Features................................................................................................................. 97

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5.1.2 Block Diagram...................................................................................................... 985.1.3 Pin Configuration ................................................................................................. 995.1.4 Register Configuration ......................................................................................... 99

5.2 Register Descriptions......................................................................................................... 1005.2.1 System Control Register (SYSCR)....................................................................... 1005.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 1015.2.3 IRQ Enable Register (IER)................................................................................... 1025.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 1025.2.5 IRQ Status Register (ISR) .................................................................................... 1035.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR).......................................... 1045.2.7 Address Break Control Register (ABRKCR)....................................................... 1065.2.8 Break Address Registers A, B, C (BARA, BARB, BARC)................................. 107

5.3 Interrupt Sources................................................................................................................ 1085.3.1 External Interrupts ................................................................................................ 1085.3.2 Internal Interrupts ................................................................................................. 1095.3.3 Interrupt Exception Vector Table......................................................................... 110

5.4 Address Breaks .................................................................................................................. 1135.4.1 Features................................................................................................................. 1135.4.2 Block Diagram...................................................................................................... 1135.4.3 Operation .............................................................................................................. 1145.4.4 Usage Notes .......................................................................................................... 114

5.5 Interrupt Operation............................................................................................................. 1165.5.1 Interrupt Control Modes and Interrupt Operation ................................................ 1165.5.2 Interrupt Control Mode 0...................................................................................... 1195.5.3 Interrupt Control Mode 1...................................................................................... 1215.5.4 Interrupt Exception Handling Sequence............................................................... 1245.5.5 Interrupt Response Times..................................................................................... 126

5.6 Usage Notes ....................................................................................................................... 1275.6.1 Contention between Interrupt Generation and Disabling..................................... 1275.6.2 Instructions that Disable Interrupts....................................................................... 1285.6.3 Interrupts during Execution of EEPMOV Instruction .......................................... 128

5.7 DTC Activation by Interrupt ............................................................................................. 1295.7.1 Overview............................................................................................................... 1295.7.2 Block Diagram...................................................................................................... 1295.7.3 Operation .............................................................................................................. 130

Section 6 Bus Controller.................................................................................................. 1316.1 Overview............................................................................................................................ 131

6.1.1 Features................................................................................................................. 1316.1.2 Block Diagram...................................................................................................... 1326.1.3 Pin Configuration ................................................................................................. 1336.1.4 Register Configuration ......................................................................................... 133

6.2 Register Descriptions......................................................................................................... 134

iv

6.2.1 Bus Control Register (BCR)................................................................................. 1346.2.2 Wait State Control Register (WSCR)................................................................... 135

6.3 Overview of Bus Control................................................................................................... 1376.3.1 Bus Specifications ................................................................................................ 1376.3.2 Advanced Mode.................................................................................................... 1386.3.3 Normal Mode........................................................................................................ 1386.3.4 I/O Select Signal................................................................................................... 139

6.4 Basic Bus Interface ............................................................................................................ 1406.4.1 Overview............................................................................................................... 1406.4.2 Data Size and Data Alignment ............................................................................. 1406.4.3 Valid Strobes ........................................................................................................ 1416.4.4 Basic Timing......................................................................................................... 1426.4.5 Wait Control ......................................................................................................... 145

6.5 Burst ROM Interface ......................................................................................................... 1476.5.1 Overview............................................................................................................... 1476.5.2 Basic Timing......................................................................................................... 1476.5.3 Wait Control ......................................................................................................... 148

6.6 Idle Cycle........................................................................................................................... 1496.6.1 Operation .............................................................................................................. 1496.6.2 Pin States in Idle Cycle......................................................................................... 150

6.7 Bus Arbitration................................................................................................................... 1506.7.1 Overview............................................................................................................... 1506.7.2 Operation .............................................................................................................. 1506.7.3 Bus Transfer Timing............................................................................................. 151

Section 7 Data Transfer Controller [H8S/2138 Series] .......................................... 1537.1 Overview............................................................................................................................ 153

7.1.1 Features................................................................................................................. 1537.1.2 Block Diagram...................................................................................................... 1547.1.3 Register Configuration ......................................................................................... 155

7.2 Register Descriptions......................................................................................................... 1567.2.1 DTC Mode Register A (MRA)............................................................................. 1567.2.2 DTC Mode Register B (MRB) ............................................................................. 1587.2.3 DTC Source Address Register (SAR) .................................................................. 1597.2.4 DTC Destination Address Register (DAR) .......................................................... 1597.2.5 DTC Transfer Count Register A (CRA)............................................................... 1597.2.6 DTC Transfer Count Register B (CRB) ............................................................... 1607.2.7 DTC Enable Registers (DTCER) ......................................................................... 1607.2.8 DTC Vector Register (DTVECR) ........................................................................ 1617.2.9 Module Stop Control Register (MSTPCR)........................................................... 162

7.3 Operation ........................................................................................................................... 1637.3.1 Overview............................................................................................................... 1637.3.2 Activation Sources................................................................................................ 165

v

7.3.3 DTC Vector Table ................................................................................................ 1667.3.4 Location of Register Information in Address Space............................................. 1687.3.5 Normal Mode........................................................................................................ 1697.3.6 Repeat Mode......................................................................................................... 1707.3.7 Block Transfer Mode............................................................................................ 1717.3.8 Chain Transfer ...................................................................................................... 1737.3.9 Operation Timing ................................................................................................. 1747.3.10 Number of DTC Execution States ........................................................................ 1757.3.11 Procedures for Using the DTC ............................................................................. 1777.3.12 Examples of Use of the DTC................................................................................ 178

7.4 Interrupts ............................................................................................................................ 1807.5 Usage Notes ....................................................................................................................... 180

Section 8 I/O Ports............................................................................................................. 1818.1 Overview............................................................................................................................ 1818.2 Port 1.................................................................................................................................. 188

8.2.1 Overview............................................................................................................... 1888.2.2 Register Configuration ......................................................................................... 1898.2.3 Pin Functions in Each Mode................................................................................. 1918.2.4 MOS Input Pull-Up Function ............................................................................... 192

8.3 Port 2.................................................................................................................................. 1938.3.1 Overview............................................................................................................... 1938.3.2 Register Configuration ......................................................................................... 1958.3.3 Pin Functions in Each Mode................................................................................. 1978.3.4 MOS Input Pull-Up Function ............................................................................... 198

8.4 Port 3.................................................................................................................................. 1998.4.1 Overview............................................................................................................... 1998.4.2 Register Configuration ......................................................................................... 2008.4.3 Pin Functions in Each Mode................................................................................. 2028.4.4 MOS Input Pull-Up Function ............................................................................... 203

8.5 Port 4.................................................................................................................................. 2048.5.1 Overview............................................................................................................... 2048.5.2 Register Configuration ......................................................................................... 2048.5.3 Pin Functions ........................................................................................................ 205


8.7 Port 6.................................................................................................................................. 2128.7.1 Overview............................................................................................................... 2128.7.2 Register Configuration ......................................................................................... 2138.7.3 Pin Functions ........................................................................................................ 2168.7.4 MOS Input Pull-Up Function ............................................................................... 218

vi




Section 9 8-Bit PWM Timers [H8S/2138 Series] .................................................... 2319.1 Overview............................................................................................................................ 231


9.2 Register Descriptions......................................................................................................... 2349.2.1 PWM Register Select (PWSL) ............................................................................. 2349.2.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 2369.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 2369.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 2379.2.5 Peripheral Clock Select Register (PCSR)............................................................. 2389.2.6 Port 1 Data Direction Register (P1DDR) ............................................................. 2389.2.7 Port 2 Data Direction Register (P2DDR) ............................................................. 2399.2.8 Port 1 Data Register (P1DR) ................................................................................ 2399.2.9 Port 2 Data Register (P2DR) ................................................................................ 2399.2.10 Module Stop Control Register (MSTPCR)........................................................... 240

9.3 Operation ........................................................................................................................... 2419.3.1 Correspondence between PWM Data Register Contents

and Output Waveform .......................................................................................... 241

Section 10 14-Bit PWM D/A............................................................................................ 24310.1 Overview............................................................................................................................ 243


10.2 Register Descriptions......................................................................................................... 24510.2.1 PWM D/A Counter (DACNT) ............................................................................. 24510.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 246

vii

10.2.3 PWM D/A Control Register (DACR)................................................................... 24710.2.4 Module Stop Control Register (MSTPCR)........................................................... 249

10.3 Bus Master Interface .......................................................................................................... 25010.4 Operation ........................................................................................................................... 253

Section 11 16-Bit Free-Running Timer ......................................................................... 25711.1 Overview............................................................................................................................ 257

11.1.1 Features................................................................................................................. 25711.1.2 Block Diagram...................................................................................................... 25811.1.3 Input and Output Pins........................................................................................... 25911.1.4 Register Configuration ......................................................................................... 260

11.2 Register Descriptions......................................................................................................... 26111.2.1 Free-Running Counter (FRC)............................................................................... 26111.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 26111.2.3 Input Capture Registers A to D (ICRA to ICRD)................................................. 26211.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 26311.2.5 Output Compare Register DM (OCRDM) ........................................................... 26411.2.6 Timer Interrupt Enable Register (TIER)............................................................... 26411.2.7 Timer Control/Status Register (TCSR) ................................................................ 26611.2.8 Timer Control Register (TCR) ............................................................................. 26911.2.9 Timer Output Compare Control Register (TOCR)............................................... 27111.2.10 Module Stop Control Register (MSTPCR)........................................................... 273

11.3 Operation ........................................................................................................................... 27411.3.1 FRC Increment Timing......................................................................................... 27411.3.2 Output Compare Output Timing........................................................................... 27511.3.3 FRC Clear Timing ................................................................................................ 27611.3.4 Input Capture Input Timing .................................................................................. 27611.3.5 Timing of Input Capture Flag (ICF) Setting......................................................... 27811.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) ................................ 27911.3.7 Setting of FRC Overflow Flag (OVF) .................................................................. 28011.3.8 Automatic Addition of OCRA and OCRAR/OCRAF.......................................... 28011.3.9 ICRD and OCRDM Mask Signal Generation ...................................................... 281

11.4 Interrupts ............................................................................................................................ 28211.5 Sample Application ........................................................................................................... 28211.6 Usage Notes ....................................................................................................................... 283

Section 12 8-Bit Timers ..................................................................................................... 28912.1 Overview............................................................................................................................ 289



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12.2.1 Timer Counter (TCNT)......................................................................................... 29312.2.2 Time Constant Register A (TCORA) ................................................................... 29412.2.3 Time Constant Register B (TCORB) ................................................................... 29512.2.4 Timer Control Register (TCR) ............................................................................. 29512.2.5 Timer Control/Status Register (TCSR) ................................................................ 29912.2.6 Serial/Timer Control Register (STCR)................................................................. 30212.2.7 System Control Register (SYSCR)....................................................................... 30312.2.8 Timer Connection Register S (TCONRS) ............................................................ 30312.2.9 Input Capture Register (TICR) [TMRX Additional Function]............................. 30412.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]................... 30412.2.11 Input Capture Registers R and F (TICRR, TICRF)

[TMRX Additional Functions] ............................................................................ 30512.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] ..................... 30512.2.13 Module Stop Control Register (MSTPCR)........................................................... 306

12.3 Operation ........................................................................................................................... 30712.3.1 TCNT Incrementation Timing.............................................................................. 30712.3.2 Compare-Match Timing ....................................................................................... 30812.3.3 TCNT External Reset Timing............................................................................... 31012.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 31012.3.5 Operation with Cascaded Connection .................................................................. 31112.3.6 Input Capture Operation ....................................................................................... 312

12.4 Interrupt Sources................................................................................................................ 31412.5 8-Bit Timer Application Example ..................................................................................... 31512.6 Usage Notes ....................................................................................................................... 315

12.6.1 Contention between TCNT Write and Clear ........................................................ 31512.6.2 Contention between TCNT Write and Increment................................................. 31612.6.3 Contention between TCOR Write and Compare-Match ...................................... 31712.6.4 Contention between Compare-Matches A and B ................................................. 31812.6.5 Switching of Internal Clocks and TCNT Operation............................................. 318

Section 13 Timer Connection [H8S/2138 Series] ...................................................... 32113.1 Overview............................................................................................................................ 321


13.2 Register Descriptions......................................................................................................... 32413.2.1 Timer Connection Register I (TCONRI).............................................................. 32413.2.2 Timer Connection Register O (TCONRO)........................................................... 32713.2.3 Timer Connection Register S (TCONRS) ............................................................ 32913.2.4 Edge Sense Register (SEDGR)............................................................................. 33113.2.5 Module Stop Control Register (MSTPCR)........................................................... 333

13.3 Operation ........................................................................................................................... 334

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13.3.1 PWM Decoding (PDC Signal Generation)........................................................... 33413.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 33613.3.3 Measurement of 8-Bit Timer Divided Waveform Period..................................... 33713.3.4 IHI Signal and 2fH Modification ......................................................................... 33913.3.5 IVI Signal Fall Modification and IHI Synchronization........................................ 34113.3.6 Internal Synchronization Signal Generation

(IHG/IVG/CL4 Signal Generation) ...................................................................... 34213.3.7 HSYNCO Output.................................................................................................. 34513.3.8 VSYNCO Output.................................................................................................. 34613.3.9 CBLANK Output.................................................................................................. 347

Section 14 Watchdog Timer (WDT) .............................................................................. 34914.1 Overview............................................................................................................................ 349


14.2 Register Descriptions......................................................................................................... 35214.2.1 Timer Counter (TCNT)......................................................................................... 35214.2.2 Timer Control/Status Register (TCSR) ................................................................ 35314.2.3 System Control Register (SYSCR)....................................................................... 35614.2.4 Notes on Register Access ..................................................................................... 357

14.3 Operation ........................................................................................................................... 35814.3.1 Watchdog Timer Operation .................................................................................. 35814.3.2 Interval Timer Operation ...................................................................................... 35914.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 360


14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 36114.5.2 Changing Value of CKS2 to CKS0 ...................................................................... 36114.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 36114.5.4 Counter Value in Transitions between High-Speed Mode,

Subactive Mode, and Watch Mode....................................................................... 36214.5.5 OVF Flag Clear Condition ................................................................................... 362

Section 15 Serial Communication Interface (SCI, IrDA) ........................................ 36315.1 Overview............................................................................................................................ 363


15.2 Register Descriptions......................................................................................................... 36815.2.1 Receive Shift Register (RSR)............................................................................... 368

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15.2.2 Receive Data Register (RDR)............................................................................... 36815.2.3 Transmit Shift Register (TSR).............................................................................. 36915.2.4 Transmit Data Register (TDR) ............................................................................. 36915.2.5 Serial Mode Register (SMR) ................................................................................ 37015.2.6 Serial Control Register (SCR) .............................................................................. 37215.2.7 Serial Status Register (SSR)................................................................................. 37615.2.8 Bit Rate Register (BRR)....................................................................................... 38015.2.9 Serial Interface Mode Register (SCMR) .............................................................. 38815.2.10 Module Stop Control Register (MSTPCR)........................................................... 38915.2.11 Keyboard Comparator Control Register (KBCOMP) .......................................... 391

15.3 Operation ........................................................................................................................... 39215.3.1 Overview............................................................................................................... 39215.3.2 Operation in Asynchronous Mode........................................................................ 39415.3.3 Multiprocessor Communication Function ............................................................ 40515.3.4 Operation in Synchronous Mode .......................................................................... 41315.3.5 IrDA Operation..................................................................................................... 422

15.4 SCI Interrupts..................................................................................................................... 42515.5 Usage Notes ....................................................................................................................... 426

Section 16 I2C Bus Interface [H8S/2138 Series Option] ......................................... 43116.1 Overview............................................................................................................................ 431

16.1.1 Features................................................................................................................. 43116.1.2 Block Diagram...................................................................................................... 43216.1.3 Input/Output Pins.................................................................................................. 43416.1.4 Register Configuration ......................................................................................... 435

16.2 Register Descriptions......................................................................................................... 43616.2.1 I2C Bus Data Register (ICDR).............................................................................. 43616.2.2 Slave Address Register (SAR) ............................................................................. 43916.2.3 Second Slave Address Register (SARX).............................................................. 44016.2.4 I2C Bus Mode Register (ICMR) ........................................................................... 44116.2.5 I2C Bus Control Register (ICCR) ......................................................................... 44416.2.6 I2C Bus Status Register (ICSR) ............................................................................ 45116.2.7 Serial/Timer Control Register (STCR)................................................................. 45616.2.8 DDC Switch Register (DDCSWR)....................................................................... 45716.2.9 Module Stop Control Register (MSTPCR)........................................................... 459

16.3 Operation ........................................................................................................................... 46016.3.1 I2C Bus Data Format............................................................................................. 46016.3.2 Master Transmit Operation................................................................................... 46216.3.3 Master Receive Operation .................................................................................... 46416.3.4 Slave Receive Operation....................................................................................... 46716.3.5 Slave Transmit Operation..................................................................................... 46916.3.6 IRIC Setting Timing and SCL Control................................................................. 47116.3.7 Automatic Switching from Formatless Mode to I2C Bus Format ........................ 472

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16.3.8 Operation Using the DTC..................................................................................... 47316.3.9 Noise Canceler...................................................................................................... 47416.3.10 Sample Flowcharts ............................................................................................... 47416.3.11 Initialization of Internal State ............................................................................... 478

16.4 Usage Notes ....................................................................................................................... 480

Section 17 Host Interface................................................................................................... 48717.1 Overview............................................................................................................................ 487


17.2 Register Descriptions......................................................................................................... 49117.2.1 System Control Register (SYSCR)....................................................................... 49117.2.2 System Control Register 2 (SYSCR2) ................................................................. 49217.2.3 Host Interface Control Register (HICR)............................................................... 49317.2.4 Input Data Register 1 (IDR1) ............................................................................... 49417.2.5 Output Data Register 1 (ODR1) ........................................................................... 49417.2.6 Status Register 1 (STR1) ...................................................................................... 49517.2.7 Input Data Register 2 (IDR2) ............................................................................... 49617.2.8 Output Data Register 2 (ODR2) ........................................................................... 49717.2.9 Status Register 2 (STR2) ...................................................................................... 49717.2.10 Module Stop Control Register (MSTPCR)........................................................... 499

17.3 Operation ........................................................................................................................... 49917.3.1 Host Interface Operation....................................................................................... 49917.3.2 Control States ....................................................................................................... 50017.3.3 A20 Gate............................................................................................................... 50117.3.4 Host Interface Pin Shutdown Function................................................................. 503

17.4 Interrupts ............................................................................................................................ 50517.4.1 IBF1, IBF2............................................................................................................ 50517.4.2 HIRQ11, HIRQ1, and HIRQ12 ............................................................................ 505

17.5 Usage Note......................................................................................................................... 506

Section 18 D/A Converter ................................................................................................. 50718.1 Overview............................................................................................................................ 507


18.2 Register Descriptions......................................................................................................... 51018.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 51018.2.2 D/A Control Register (DACR)............................................................................. 51018.2.3 Module Stop Control Register (MSTPCR)........................................................... 512

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18.3 Operation ........................................................................................................................... 513

Section 19 A/D Converter ................................................................................................. 51519.1 Overview............................................................................................................................ 515


19.2 Register Descriptions......................................................................................................... 51819.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 51819.2.2 A/D Control/Status Register (ADCSR) ................................................................ 51919.2.3 A/D Control Register (ADCR)............................................................................. 52219.2.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 52319.2.5 Module Stop Control Register (MSTPCR)........................................................... 524

19.3 Interface to Bus Master...................................................................................................... 52519.4 Operation ........................................................................................................................... 526

19.4.1 Single Mode (SCAN = 0) ..................................................................................... 52619.4.2 Scan Mode (SCAN = 1) ....................................................................................... 52819.4.3 Input Sampling and A/D Conversion Time .......................................................... 53019.4.4 External Trigger Input Timing ............................................................................. 531


Section 20 RAM ................................................................................................................... 53920.1 Overview............................................................................................................................ 539

20.1.1 Block Diagram...................................................................................................... 53920.1.2 Register Configuration ......................................................................................... 540

20.2 System Control Register (SYSCR).................................................................................... 54020.3 Operation ........................................................................................................................... 541

20.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1))................................................ 54120.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ................................................. 541

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT,H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)........................................ 543

21.1 Overview............................................................................................................................ 54321.1.1 Block Diagram...................................................................................................... 54321.1.2 Register Configuration ......................................................................................... 544

21.2 Register Descriptions......................................................................................................... 54421.2.1 Mode Control Register (MDCR) .......................................................................... 544

21.3 Operation ........................................................................................................................... 54521.4 Overview of Flash Memory............................................................................................... 546

21.4.1 Features................................................................................................................. 54621.4.2 Block Diagram...................................................................................................... 547

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21.4.3 Flash Memory Operating Modes .......................................................................... 54821.4.4 Pin Configuration ................................................................................................. 55221.4.5 Register Configuration ......................................................................................... 552

21.5 Register Descriptions......................................................................................................... 55321.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 55321.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 55521.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 55621.5.4 Serial/Timer Control Register (STCR)................................................................. 557

21.6 On-Board Programming Modes......................................................................................... 55821.6.1 Boot Mode ............................................................................................................ 55921.6.2 User Program Mode ............................................................................................. 563

21.7 Programming/Erasing Flash Memory................................................................................ 56521.7.1 Program Mode ...................................................................................................... 56521.7.2 Program-Verify Mode .......................................................................................... 56621.7.3 Erase Mode........................................................................................................... 56821.7.4 Erase-Verify Mode ............................................................................................... 568

21.8 Flash Memory Protection................................................................................................... 57021.8.1 Hardware Protection............................................................................................. 57021.8.2 Software Protection .............................................................................................. 57021.8.3 Error Protection..................................................................................................... 571

21.9 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 57221.10 Flash Memory Programmer Mode..................................................................................... 573

21.10.1 Programmer Mode Setting ................................................................................... 57321.10.2 Socket Adapters and Memory Map ...................................................................... 57421.10.3 Programmer Mode Operation............................................................................... 57521.10.4 Memory Read Mode............................................................................................. 57621.10.5 Auto-Program Mode............................................................................................. 57921.10.6 Auto-Erase Mode.................................................................................................. 58121.10.7 Status Read Mode................................................................................................. 58221.10.8 Status Polling ........................................................................................................ 58321.10.9 Programmer Mode Transition Time..................................................................... 58421.10.10 Notes on Memory Programming ....................................................................... 584

21.11 Flash Memory Programming and Erasing Precautions ..................................................... 58521.12 Note on Switching from F-ZTAT Version to Mask ROM Version................................... 586

Section 22 ROM (H8S/2138 F-ZTAT A-mask Version,H8S/2134 F-ZTAT A-mask Version)....................................................... 587

22.1 Overview............................................................................................................................ 58722.1.1 Block Diagram...................................................................................................... 58722.1.2 Register Configuration ......................................................................................... 588

22.2 Register Descriptions......................................................................................................... 58822.2.1 Mode Control Register (MDCR) .......................................................................... 588

22.3 Operation ........................................................................................................................... 589

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22.4 Overview of Flash Memory............................................................................................... 59022.4.1 Features................................................................................................................. 59022.4.2 Block Diagram...................................................................................................... 59122.4.3 Flash Memory Operating Modes .......................................................................... 59222.4.4 Pin Configuration ................................................................................................. 59622.4.5 Register Configuration ......................................................................................... 596

22.5 Register Descriptions......................................................................................................... 59722.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 59722.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 59922.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 60022.5.4 Serial/Timer Control Register (STCR)................................................................. 601

22.6 On-Board Programming Modes......................................................................................... 60222.6.1 Boot Mode ............................................................................................................ 60322.6.2 User Program Mode ............................................................................................. 608

22.7 Programming/Erasing Flash Memory................................................................................ 60922.7.1 Program Mode ...................................................................................................... 60922.7.2 Program-Verify Mode .......................................................................................... 61022.7.3 Erase Mode........................................................................................................... 61222.7.4 Erase-Verify Mode ............................................................................................... 612

22.8 Flash Memory Protection................................................................................................... 61422.8.1 Hardware Protection............................................................................................. 61422.8.2 Software Protection .............................................................................................. 61422.8.3 Error Protection .................................................................................................... 615

22.9 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 61622.10 Flash Memory Programmer Mode..................................................................................... 617

22.10.1 Programmer Mode Setting ................................................................................... 61722.10.2 Socket Adapters and Memory Map ...................................................................... 61822.10.3 Programmer Mode Operation............................................................................... 61822.10.4 Memory Read Mode............................................................................................. 62022.10.5 Auto-Program Mode............................................................................................. 62322.10.6 Auto-Erase Mode.................................................................................................. 62422.10.7 Status Read Mode................................................................................................. 62522.10.8 Status Polling ........................................................................................................ 62722.10.9 Programmer Mode Transition Time..................................................................... 62722.10.10 Notes on Memory Programming ....................................................................... 628

22.11 Flash Memory Programming and Erasing Precautions ..................................................... 62822.12 Note on Switching from F-ZTAT Version to Mask ROM Version................................... 630

Section 23 Clock Pulse Generator................................................................................... 63123.1 Overview............................................................................................................................ 631

23.1.1 Block Diagram...................................................................................................... 63123.1.2 Register Configuration ......................................................................................... 631


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23.2.1 Standby Control Register (SBYCR)..................................................................... 63223.2.2 Low-Power Control Register (LPWRCR)............................................................ 633

23.3 Oscillator............................................................................................................................ 63323.3.1 Connecting a Crystal Resonator ........................................................................... 63323.3.2 External Clock Input............................................................................................. 635

23.4 Duty Adjustment Circuit.................................................................................................... 63823.5 Medium-Speed Clock Divider........................................................................................... 63823.6 Bus Master Clock Selection Circuit................................................................................... 63823.7 Subclock Input Circuit ....................................................................................................... 63823.8 Subclock Waveform Shaping Circuit ................................................................................ 63923.9 Clock Selection Circuit ...................................................................................................... 639

Section 24 Power-Down State.......................................................................................... 64124.1 Overview............................................................................................................................ 641

24.1.1 Register Configuration ......................................................................................... 64524.2 Register Descriptions......................................................................................................... 645

24.2.1 Standby Control Register (SBYCR)..................................................................... 64524.2.2 Low-Power Control Register (LPWRCR)............................................................ 64724.2.3 Timer Control/Status Register (TCSR) ................................................................ 64924.2.4 Module Stop Control Register (MSTPCR)........................................................... 650

24.3 Medium-Speed Mode......................................................................................................... 65124.4 Sleep Mode ........................................................................................................................ 652

24.4.1 Sleep Mode........................................................................................................... 65224.4.2 Clearing Sleep Mode ............................................................................................ 652

24.5 Module Stop Mode ............................................................................................................ 65324.5.1 Module Stop Mode ............................................................................................... 65324.5.2 Usage Note ........................................................................................................... 654

24.6 Software Standby Mode..................................................................................................... 65524.6.1 Software Standby Mode ....................................................................................... 65524.6.2 Clearing Software Standby Mode......................................................................... 65524.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode........... 65624.6.4 Software Standby Mode Application Example .................................................... 65624.6.5 Usage Note............................................................................................................ 657

24.7 Hardware Standby Mode ................................................................................

h8s/2138, h8s2134 series - farnell element14 · an on-chip data transfer controller (dtc) is also...

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