hanbat national university prof. lee...

Hanbat National University Prof. Lee Jaeheung

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Sun, H y e -Se ungSun, H y e -Se ung

�� Hanbat National University Prof. Lee Jaeheung

��

��

·��

·Multiplexer·Encoder·Decoder·Random Logic

·Adder·Subtractor·ALU·Lookup Table·Comparator

��

� � � �� Verilog � ��

· � � � � � � � � � ��

· � �� (assign ��)· � � !� � !� � !� � ! " # $" # $" # $" # $ (if��, case��, for��)· % % % % &&&& task ( ' (' (' (' ( ) �) �) �) � event * + ,* + ,* + ,* + , - .- .- .- . / 0 1/ 0 1/ 0 1/ 0 1 )· " 2" 2" 2" 2 3 4 5 43 4 5 43 4 5 43 4 5 4

��6 ��6 ��6 ��6 � . 7 � .. 7 � .. 7 � .. 7 � . 8 �8 �8 �8 �

Verilog � ��

·initial��· 4 � 94 � 94 � 94 � 9 � �� (cmos, nmos, tran ::::)·forever, while, repeat:�:�:�:� ; < �; < �; < �; < �

·wait, event, . �. �. �. � :::: = � >= � >= � >= � > * +* +* +* + � ��

·force-release, fork-join· ' 4 ?' 4 ?' 4 ?' 4 ? task ($finish, $time::::)

�� Verilog � ��


��

� ��

�always �� (sensitivity list)� � ( , a lw a ys � � � � � � � � )��

� � � ! " # $ ; % & ' ( % & ) � * + , � - . ( / 0 1 2 3 4� i f � � �� c ase �

� 5 � � 6 7 � � 8 9 : � ; � < * = � �> � � � �

� � � ! " # $ ; ? @ / A & � � B C D E � / F 2 3 4� � � � � � � ��

� G H � I � J 2K G H �L # 1 M � � / % & � N � O � �

� � � � � � � � � � � � � �

� H P Q R � / S & (r ea d a b ility)T U I V W X Y Z A / [ & T \ W ] ^ , _ `a T b � V I V W c d A e & T f W g


10.1.1 � � � � ��

� 4�� N A N D � � ��

module nand4_op1(a, y);input [3:0] a;output y;

assign y = ~(a[0] & a[1] & a[2] & a[3]); // ��

// assign y = ~&a; // � ��

// nand U0(y, a[0], a[1], a[2], a[3]); // � ��

endmodule

a[0]a[1]a[2]a[3]

y

@ A@ A@ A@ A 10.1 ~ 10.3

� �� , � � � � �� , � � ��


10.1.1 � � � � ��

� 4�� N A N D � � ��

module nand4_if(a, y);input [3:0] a;output y;reg y;

always @(a) beginif(a == 4'b1111) y = 1'b0; else y = 1'b1;

endendmodule @ A@ A@ A@ A 10.4

if �! ��! ��! ��! �


10.1.1 � � � � ��

� 4�� N A N D � � �� ( � � � � � � � � � � � � � � � � )module tb_nand4;reg [3:0] a;wire y;integer i;

nand4_op1 U0(a, y);// nand4_op2 U0(a, y);// nand4_gate U0(a, y);// nand4_if U0(a, y);

initial begina = 0;for(i=1; i < 32; i=i+1)

#20 a = i;end

endmodule @ A@ A@ A@ A 10.5


10.1.1 � � � � ��

4 " #" #" #" # NAND � � � �� $ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.1.1 � � � � ��

� 3�� N O R � � � � � � � � � � � � � � � � � � � � � � � �� , � � � � � � � � � � � � � � � � ��

� � ��

� ��

� � � � � � � � � �

� � � � � � � � � � � � �

� if � � � � � � �


10.1.2 � � � ��

� 4 � �� 2�� N O R � � ��

module nor_op(a, b, y);input [3:0] a, b;output [3:0] y;

assign y = ~(a | b);

// assign y[0] = ~(a[0] | b[0]); // assign y[1] = ~(a[1] | b[1]);// assign y[2] = ~(a[2] | b[2]);// assign y[3] = ~(a[3] | b[3]);


a[3:0]b[3:0]

y[3] y[2] y[1] y[0]

� ��


10.1.2 � � � ��

� 4 � �� 2�� N O R � � ��

module nor_gate(a, b, y);input [3:0] a, b;output [3:0] y;

nor U0 [3:0](y, a, b);


module nor_for(a, b, y);input [3:0] a, b;output [3:0] y;reg [3:0] y;integer i;

always @(a or b) beginfor(i=0; i < 4; i=i+1)

y[i] = ~(a[i] | b[i]);end


� � �� * +* +* +* +

for , - �, - �, - �, - �


10.1.2 � � � ��

� 4 � �� 2�� X O R � � � � � � � � � � � � � � � � � � � � � � � �� , � � � � � � � � � � � � � � � �

��

� ��

� � � � � � � � � � � � �

� fo r � � � � � � �


10.1.3 � � � � ��

� ! " # ! " # ! " # ! " # � � ��

edcbay ⋅+⋅+= )()(

module comb_gate(a, b, c, d, e, y);input a, b, c, d, e;output y;

assign y = ~((a | b) &(c | d) & e);


� ��

edcbay ⋅++⋅=


10.1.4 � ��

� $ % & $ % & $ % & $ % & � � ��

module booth_enc(xin, y, y2, neg);input [2:0] xin;output y, y2, neg;reg [2:0] tmp;

assign y = tmp[2];assign y2 = tmp[1];assign neg = tmp[0];

always @(xin) begincase(xin)

0 : tmp = 3'b000;1,2 : tmp = 3'b100;3 : tmp = 3'b010;4 : tmp = 3'b011;5,6 : tmp = 3'b101;7 : tmp = 3'b001;

endcaseend


case ��

xin[2:0] y y2 neg

000 0 0 0

001 1 0 0

010 1 0 0

011 0 1 0

100 0 1 1

101 1 0 1

110 1 0 1

111 0 0 1

.... 10.2 Booth / 0 1/ 0 1/ 0 1/ 0 1 2 �.2 �.2 �.2 �.


10.1.4 � ��

� $ % & $ % & $ % & $ % & � � ��

module tb_booth_enc;reg [2:0] xin;wire y, y2, neg;integer i;

booth_enc U0(xin, y, y2, neg);

initial beginxin = 0;for(i=1; i < 16; i=i+1)

#20 xin = i;end


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6


10.1.4 � ��

$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )

7 87 87 87 8 10.6 0 90 90 90 9 10.11��:�:�:�: ( )( )( )( )


10.1.4 � ��

� � � � � � � � � $ % & $ % & $ % & $ % & V e r i l o g H D L �� , � � � � � � � � � � � � � � � � ��

xin[2:0] yz y2 neg add

000 0 1 0 1

001 1 0 0 0

010 1 0 0 0

011 1 1 0 0

100 1 1 1 1

101 1 0 1 1

110 1 0 1 1

111 0 1 1 1

.... 10.3 Booth / 0 1/ 0 1/ 0 1/ 0 1 2 �.2 �.2 �.2 �.(2)


10.1.5 Lookup Table��

� L o o k u p T a b l e� � � ! " # $ % & ' ( ) * + , - � . / � 0 1 � 2 �3

4 � � 5 6 � � � 78

� 9 : � � � ; < = , > ? � @ A B 4 * , C D E F " G l o o k u p H �7 9 : � I J � ; 0 1 , - � . � K L M � � �

� 0 1 N - � . O � c a s e � P � Q R� lo o k u p ! " # $�� case �# � � % & � �� n- ' ( # $�) * + l o o k u p ! " , � - . # / 0 ) 1 2n2


10.1.5 Lookup Table��

� Lookup Table�� ( � �� )18

function [7:0] data_line1;input [3:0] addr_in;

begincase(addr_in)

0 : data_line1 = 8'b0010_0000;1 : data_line1 = 8'b0100_0100;2 : data_line1 = 8'b0110_1001;3 : data_line1 = 8'b0110_0111;

. . . . . .14 : data_line1 = 8'b0110_1110;15 : data_line1 = 8'b0010_0000;

default : data_line1 = 8'b0000_0000;endcase

endendfunction @A@A@A@A 10.13


10.2 � � � � ��

� 4�� 4: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

�4S) 4 � � T U V " G � W � X Y � ; J U� i f � � � , c a s e � , � � � � � Z� � � ; @ A Bmodule mux41_if(sel, a, b, c, d, y);input [1:0] sel;input [3:0] a, b, c, d;output [3:0] y;reg [3:0] y;

always @(sel or a or b or c or d) beginif (sel == 2'b00) y = a;else if(sel == 2'b01) y = b;else if(sel == 2'b10) y = c;else if(sel == 2'b11) y = d;else y = 4'bx;

endendmodule @A@A@A@A 10.14

if �!��!��!��!�


10.2 � � � � ��

� 4�� 4: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

module mux41_case(sel, a, b, c, d, y);input [1:0] sel;input [3:0] a, b, c, d;output [3:0] y;reg [3:0] y;

always @(sel or a or b or c or d) begincase(sel)

0 : y = a;1 : y = b;2 : y = c;3 : y = d;

default : y = 4'bx;endcase


case ��


10.2 � � � � ��

� 4�� 4: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

module mux41_conop(sel, a, b, c, d, y);input [1:0] sel;input [3:0] a, b, c, d;output [3:0] y;

assign y =(sel == 0) ? a :(sel == 1) ? b :(sel == 2) ? c :(sel == 3) ? d : 4'bx;

endmodule @A@A@A@A 10.16

�!�!�!�! � � ��


10.2 � � � � ��

� 4�� 4: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

module tb_mux41;reg [3:0] a, b, c, d;reg [1:0] sel;wire [3:0] y;

mux41_if U0(sel, a, b, c, d, y);// mux41_case U0(sel, a, b, c, d, y);// mux41_conop U0(sel, a, b, c, d, y);

initial begina = 4'b0001; b = 4'b0010;c = 4'b0100; d = 4'b1000;

#80 a = 4'b1100; b = 4'b0011;c = 4'b0110; d = 4'b1001;

end

initial sel = 2'b00;always #20 sel = sel + 1;


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6


10.2 � � � � ��

� 4�� 4: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.2 � � � � ��

� 4�� 4: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

7 87 87 87 8 10.8 0 90 90 90 9 10.14 ~ 10.16�� :� :� :� : ( )( )( )( )


10.2 � � � � ��

� 8�� 8: 1 ' ( ) * +' ( ) * +' ( ) * +' ( ) * +

module mux81_case(sel, in_word, out_bit);input [2:0] sel;input [7:0] in_word;output out_bit;reg out_bit;

always @(sel or in_word) begincase(sel)

endcaseend


case ��

@A,@A,@A,@A, B 6 0 1B 6 0 1B 6 0 1B 6 0 1 .


10.3.1 2��

� n : m 2 � � � � � � � �

�n- ' ( # 34� m- ' ( # 5 4% & 6 7 (8 , n= 2 m)� i f � � � , case � , f o r 9 : � ; <= �� > ? % & � �

� �� ; �� /� � � � � � � � � � � � � ��

� @ � � A B C D 34� � E # F G A + 5 4A d o n’ t car e H � I J K< � � D L & � M N O � � P

C DC DC DC D a[3:0] E DE DE DE D y[1:0]

0001 00

0010 01

0100 10

1000 11

.... 10.4 4:2 22222 / 0 ; �/ 0 ; �/ 0 ; �/ 0 ; �2� .2� .2� .2� .


10.3.1 2��

� 4: 2 2 $$$$ , - ., - ., - ., - .

module enc_4to2_case(a, y);input [3:0] a;output [1:0] y;reg [1:0] y;

always @(a) begincasex(a)

4'b0001 : y = 0;4'b0010 : y = 1;4'b0100 : y = 2; 4'b1000 : y = 3;default : y = 2'bx;

endcaseend


case ��

module enc_4to2_if(a, y);input [3:0] a;output [1:0] y;reg [1:0] y;

always @(a) beginif (a == 4'b0001) y = 0;else if(a == 4'b0010) y = 1;else if(a == 4'b0100) y = 2;else if(a == 4'b1000) y = 3;else y = 2'bx;


if �!��!��!��!�


10.3.1 2��

� 4: 2 2 $$$$ , - ., - ., - ., - .

module enc_4to2_for(a, y);input [3:0] a;output [1:0] y;reg [1:0] y;reg [3:0] temp;integer n;

always @(a) begintemp = 4'b0001;y = 2'bx;for(n = 0; n < 4; n = n + 1) begin

if(a == temp)y = n;

temp = temp << 1;end


for , - �, - �, - �, - �


10.3.1 2��

� 4: 2 2 $$$$ , - ., - ., - ., - .

module tb_enc_4to2;reg [3:0] a;wire [1:0] y;

enc_4to2_case U0(a, y);// enc_4to2_if U0(a, y);// enc_4to2_for U0(a, y);

always begina = 4'b0001;

#20 a = 4'b0010;#20 a = 4'b0100;#20 a = 4'b1000;#20;

end


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6


10.3.1 2��

0 90 90 90 9 10.19�� : ( )� : ( )� : ( )� : ( )

0 90 90 90 9 10.20, 0 90 90 90 9 10.21�� : ( )� : ( )� : ( )� : ( )


10.3.1 2��

� e n a b l e / 0 / 0 / 0 / 0 1 21 21 21 2 433332 � $� $� $� $ , - . , - . , - . , - . 4 5 4 5 4 5 4 5 � 6 � �� 6 � �� 6 � �� 6 � � � � � ��

�� , 7 8 9 � : �7 8 9 � : �7 8 9 � : �7 8 9 � : � ; <; <; <; < � ��

� c a s e �� i f � � �� f o r � � ��


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

.... 10.5 4:2 < = > ?< = > ?< = > ?< = > ? / 0 ; �/ 0 ; �/ 0 ; �/ 0 ; �2� .2� .2� .2� .

� ��

a[3:0] y[1:0] valid

1xxx 11 1

01xx 10 1

001x 01 1

0001 00 1

0000 xx 0


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

module pri_enc_4to2_if(a, valid, y);input [3:0] a;output valid;output [1:0] y;reg valid;reg [1:0] y;

always @(a) beginvalid = 1;if (a[3]) y = 3;else if(a[2]) y = 2;else if(a[1]) y = 1;else if(a[0]) y = 0;else begin

valid = 0;y = 2'bx;

endend


if �!��!��!��!� � ��


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

module pri_enc_4to2_case(a, valid, y);input [3:0] a;output valid;output [1:0] y;reg valid;reg [1:0] y;

always @(a) beginvalid = 1;casex(a)

4'b1xxx : y = 3;4'b01xx : y = 2;4'b001x : y = 1;4'b0001 : y = 0;default : begin

valid = 0;y = 2'bx;

endendcase


casex ��


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

module pri_enc_4to2_for(a, valid, y);input [3:0] a;output valid;output [1:0] y;reg valid;reg [1:0] y;integer n;

always @(a) beginvalid = 0;y = 2'bx;for(n = 0; n < 4; n = n+1)

if(a[n]) beginvalid = 1;y = n;

endend


for ��


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

module tb_pri_enc;reg [3:0] a;wire valid;wire [1:0] y;

pri_enc_4to2_case U0(a, valid, y);// pri_enc_4to2_if U0(a, valid, y);// pri_enc_4to2_for U0(a, valid, y);


#20 a = 4'b0010;#20 a = 4'b0100;#20 a = 4'b1000;#20;


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� 4: 2 = > ? @= > ? @= > ? @= > ? @ , - ., - ., - ., - .

7 87 87 87 8 10.12 0 90 90 90 9 10.23 ~ 10.25�� :� :� :� : ( )( )( )( )


10.3.2 ! " # $! " # $! " # $! " # $ � � � � � � � �

� e n a b l e / 0 / 0 / 0 / 0 1 21 21 21 2 4: 2 = > ? @= > ? @= > ? @= > ? @ , - . , - . , - . , - . 4 5 4 5 4 5 4 5 � 6 � �� 6 � �� 6 � �� 6 � � � � ��

� �� , 7 8 9 � : �7 8 9 � : �7 8 9 � : �7 8 9 � : � ; <; <; <; < � ��

� c a s e �� i f � � �� f o r � � ��


10.3.3 % � % � % � % �

� m : n 2 $$$$ A - .A - .A - .A - .

�m- � � ) T U � n- � � ) J U P � [ \ (� , n= 2 m)�n: m 2 ] ^ E _ � ^ E ` , - � . � � a b c� i f � � � , c a s e � , f o r � � � Z ; d e f � P � @ A B

� 9 : � ; 34# ' ( Q � R F G S + 3/4 ' ( Q ) T U V 0 K< � � K + F G A W �

C DC DC DC D a[1:0] E DE DE DE D y[3:0]

00 0001

01 0010

10 0100

11 1000

.... 10.6 2:4 22222 @ 0 ; �@ 0 ; �@ 0 ; �@ 0 ; �2� .2� .2� .2� .


10.3.3 % � % � % � % �

� 2 : 4 � $� $� $� $ A - .A - .A - .A - .

module dec_2to4_if(a, y);input [1:0] a;output [3:0] y;reg [3:0] y;

always @(a) beginif(a == 0) y = 4'b0001;else if(a ==1) y = 4'b0010;else if(a ==2) y = 4'b0100;else y = 4'b1000;


if �!��!��!��!� � ��


10.3.3 % � % � % � % �

� 2 : 4 � $� $� $� $ A - .A - .A - .A - .

module dec_2to4_case(a, y);input [1:0] a;output [3:0] y;reg [3:0] y;

always @(a) begincase(a)

0 : y = 4'b0001;1 : y = 4'b0010;2 : y = 4'b0100;3 : y = 4'b1000;default: y = 4'bx;

endcaseend


case ��


10.3.3 % � % � % � % �

� 2 : 4 � $� $� $� $ A - .A - .A - .A - .

module dec_2to4_for(a, y);input [1:0] a;output [3:0] y;reg [3:0] y;integer n;

always @(a) beginfor(n = 0; n <= 3; n = n + 1)

if(a == n)y[n] = 1'b1;

elsey[n] = 1'b0;


for ��


10.3.3 % � % � % � % �

� 2 : 4 � $� $� $� $ A - .A - .A - .A - .

module tb_dec_2to4;reg [1:0] a;wire [3:0] y;

dec_2to4_case U0(a, y);// dec_2to4_if U0(a, y);// dec_2to4_for U0(a, y);


#20 a = 4'b01;#20 a = 4'b10;#20 a = 4'b11;#20;


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6


10.3.3 % � % � % � % �

� 2 : 4 � $� $� $� $ A - .A - .A - .A - .

$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.3.3 % � % � % � % �

� 2 : 4 � $� $� $� $ A - .A - .A - .A - .

7 87 87 87 8 10.14 0 90 90 90 9 10.27 ~ 10.29�� :� :� :� : ( )( )( )( )


10.3.3 % � % � % � % �

� A c t i v e-h i g h en able � � � � � � � � � �� 3��6 � � �� (�� 1 0 . 7 )�� , � � � � !� � � � !� � � � !� � � � ! " #" #" #" # $ %$ %$ %$ %

� i f � � � ! � � � " #� e n ab l e $ % & �� a� ' ( ) * + { } , - . c as e �� / , ! � � � " #

enable � �� a[2:0] � � � � y[5:0]

0 xxx 000000

1

000 000001

001 000010

010 000100

011 001000

100 010000

101 100000

110 000000

111 000000

.... 10.7


10.3.3 % � % � % � % �

� B C D E F GB C D E F GB C D E F GB C D E F G A - .A - .A - .A - .

module dec_param(en, a, y);parameter in_width = 3, out_width = 8;input en;input [in_width-1:0] a;output [out_width-1:0] y;reg [out_width-1:0] y;integer n;

always @(en or a) beginif(!en)

y = 0;else

if(a > out_width-1)for(n = 0; n <= out_width-1; n = n+1)

y[n] = 1'bx;else

for(n = 0; n <= out_width-1; n = n+1)if(a == n)

y[n] = 1'b1;else

y[n] = 1'b0;end



10.3.3 % � % � % � % �

� � H� H� H� H d e c _ p a r a m �� I J� I J� I J� I J 3: 6 A - .A - .A - .A - .

module dec_param_inst(en, addr, dec_addr);input en;input [2:0] addr;output [5:0] dec_addr;

// 3:6 ��

dec_param #(3, 6) decoder_3to6(en, addr, dec_addr);



10.4 � & � & � & � &

� �K ��K ��K ��K �

�g T U ) h i j ^ k 2 � � l

� m n � � � , i f � � � , f o r � � � Z ; d e f � P � @ A B

module comp_assign(a, b, agtb, altb, aeqb);input [3:0] a, b;output altb, agtb, aeqb;

assign altb =(a < b);assign agtb =(a > b);assign aeqb =(a == b);


� 4��

F � � G HF � � G HF � � G HF � � G H � ��


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

module comp_if(a, b, agtb, altb, aeqb);input [3:0] a, b;output altb, agtb, aeqb;reg altb, agtb, aeqb;

always @(a or b) beginaltb = 1'b0;agtb = 1'b0;aeqb = 1'b0;if(a == b) aeqb = 1'b1;else if(a > b) agtb = 1'b1;else altb = 1'b1;


if �!��!��!��!� � ��


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

module comp_for(a, b, agtb, altb, aeqb);parameter size=4;input [size-1:0] a, b;output altb, agtb, aeqb;reg altb, agtb, aeqb;integer i;

always @(a or b) beginaltb = 1'b0;agtb = 1'b0;aeqb = 1'b1;for(i = size-1; i > = 0; i=i-1) begin : comp_loop

if(a[i] != b[i]) beginagtb = a[i];altb = ~a[i];aeqb = 0;disable comp_loop;

endend


for ��


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

module tb_comp;reg [3:0] a, b;wire agtb, altb, aeqb;

// comp_assign Uo(a, b, agtb, altb, aeqb);// comp_if Uo(a, b, agtb, altb, aeqb);

comp_for Uo(a, b, agtb, altb, aeqb);

always begina = 4'b0001; b = 4'b1001;

#20 a = 4'b0010; b = 4'b0000;#20 a = 4'b1100; b = 4'b1101;#20 a = 4'b1001; b = 4'b1001;#20 a = 4'b0111; b = 4'b0100;#20 a = 4'b1111; b = 4'b1111;#20 a = 4'b1101; b = 4'b1001;#20 a = 4'b0000; b = 4'b0000;#20 a = 4'b1010; b = 4'b1010;#20 a = 4'b0001; b = 4'b1011;#20;


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

0 90 90 90 9 10.33�� :� :� :� : ( )( )( )( )


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

0 90 90 90 9 10.34�� :� :� :� : ( )( )( )( )


10.4 � & � & � & � &

� 4�� K ��K ��K ��K �

0 90 90 90 9 10.35�� :� :� :� : ( )( )( )( )


10.5 Tri-state ' (' (' (' (� 3 L ML ML ML M N �N �N �N � O C � NO C � NO C � NO C � N

� � � ) ; d o p " G q r , s I O � t u v D � u 3 � � ) w x

o p P � y z � 2 � 3

� X Y Z [ + / 0 ) \ � A ] ^ _ B S + / 0 �� ) \ � & ` 0

a � b c h i g h i mp ed ance d e & f g� � � � � � { � � � � � � � � � � � ; @ A B

CircuitBlock-B

enable_b

bus_data

CircuitBlock-A

enable_a

data_b

data_a



module tristate_conop(in, oe, out);input in, oe;output out;

assign out =(oe) ? in : 1'bz;endmodule @A@A@A@A 10.37

�!� � ��!� � ��!� � ��!� � � � ��

module tristate_gate(in, oe, out);input in, oe;output out;

bufif1 b1(out, in, oe); // Active-high oe


� � ��



`define PERIOD 20

module tb_tristate;reg in, oe;

// tristate_gate U0_tristate_1(in, oe, out);tristate_conop U0_tristate_2(in, oe, out);

initial begin#0 oe = 1'b0; in = 1'b1;#(`PERIOD) in = 1'b0; #(`PERIOD) in = 1'b1; oe = 1'b1;#(`PERIOD) in = 1'b0;#(`PERIOD*2) in = 1'b1;#(`PERIOD*3) in = 1'b0;#(`PERIOD) oe = 1'b0;#(`PERIOD*2) in = 1'b1;#(`PERIOD) in = 1'b1;#(`PERIOD*15) $stop;


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6



$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.5 Tri-state ' (' (' (' (� P � QP � QP � QP � Q N �N �N �N � O C � NO C � NO C � NO C � N

� | M 2 } ~ 2 � b " � �

CircuitBlock

send

bus_data

rcv

received_data

send_data



module bidir_bus(send, send_data, rcv, received_data, bus_data);input send, rcv;input [7:0] send_data;inout [7:0] bus_data;output [7:0] received_data;

assign received_data =(rcv) ? bus_data : 8'bz;assign bus_data =(send) ? send_data : bus_data;




‘define PERIOD 20module tb_bidir_bus;

reg send, rcv;reg [7:0] send_data;wire [7:0] received_data, bus_data;

bidir_bus U0(send, send_data, rcv, received_data, bus_data);

initial begin#0 send = 1'b0; rcv = 1'b0; send_data = 8'h00;#(‘PERIOD) send_data = 8'h07; #(‘PERIOD) send_data = 8'h15; send = 1'b1;#(‘PERIOD) send_data = 8'hAB; #(‘PERIOD) send_data = 8'h34; #(‘PERIOD) send_data = 8'h11; send = 1'b0; rcv = 1'b1;#(‘PERIOD*2) send_data = 8'h21; #(‘PERIOD) send_data = 8'h77;#(‘PERIOD*2) send_data = 8'h66; send = 1'b1; rcv = 1'b1;#(‘PERIOD) send_data = 8'h12; #(‘PERIOD) send_data = 8'hCF; send = 1'b0; rcv = 1'b0;#(‘PERIOD) send_data = 8'h89;#(‘PERIOD) send_data = 8'h65; #(‘PERIOD*15) $stop;


3 4 � 5 63 4 � 5 63 4 � 5 63 4 � 5 6



$ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.5 Tri-state ' (' (' (' (

� R SR SR SR S 1 0 . 2 1 N �N �N �N � O C � N O C � N O C � N O C � N T UT UT UT U V W X V W X V W X V W X Y I � �Y I � �Y I � �Y I � � � � � � �� , 7 8 9 � : �7 8 9 � : �7 8 9 � : �7 8 9 � : � ; <; <; <; < � �� (ZZZZ, [ � E 2[ � E 2[ � E 2[ � E 2 8�� \ ]\ ]\ ]\ ] )

CircuitBlock-B

enable_a

bus_data

CircuitBlock-A

data_b

data_a

MUX

enable_b

7 87 87 87 8 10.21


10.6 ) * +) * +) * +) * + , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� ^ � _^ � _^ � _^ � _ ` 2` 2` 2` 2 � � � � a �a �a �a �

� c a s e �" @� e � % case � � O � � 9 4 f � � � �

� i f � � � " G el se 7 8 � q � 4 � � �

�?#J?#J?#J?#J T a b % c � T a b % c � T a b % c � T a b % c � a �a �a �a �

�@� e � % T U � � O " i 3 J U / � � b j P � f +

� d ef au l t / � f +


10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� � �� a � d 2a � d 2a � d 2a � d 2 case e e e e ffff

module case_latch(sel, in1, in2, y_out);input [1:0] sel;input [3:0] in1, in2;output [3:0] y_out;reg [3:0] y_out;

always @(sel or in1 or in2) begincase(sel)

2'b10 : y_out = in1;2'b01 : y_out = in2;

endcaseend



10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0


09090909 10.42�� $ % & � '$ % & � '$ % & � '$ % & � ' ( )( )( )( )


10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0


09090909 10.42�� :� :� :� : ( )( )( )( )

A 6A 6A 6A 6


10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� � �� a � d 2a � d 2a � d 2a � d 2 i f e e e e ffff

module if_latch(a, b, y_out);input a, b;output [3:0] y_out;reg [3:0] y_out;

always @(a or b) beginif (({a, b}) == 2'b11) y_out = 5;else if(({a, b}) == 2'b10) y_out = 2;else if(({a, b}) == 2'b01) y_out = 3; // No else block



10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� � �� a � d 2a � d 2a � d 2a � d 2 i f e e e e ffff

09090909 10.43�� :� :� :� : ( )( )( )( )

A 6A 6A 6A 6


10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� case e ge ge ge g d ef au l t e �e �e �e � h " Gh " Gh " Gh " G i =i =i =i =

� � � e 5 r 4 f � �

module case_no_latch1(sel, in1, in2, y_out);input [1:0] sel, in1, in2;output [1:0] y_out;reg [1:0] y_out;

always @(sel or in1 or in2) begincase(sel)

2'b10 : y_out = in1;2'b01 : y_out = in2;default : y_out = 2'bx;

endcaseend



10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� case e ge ge ge g d ef au l t e �e �e �e � h " Gh " Gh " Gh " G i =i =i =i =

09090909 10.44�� :� :� :� : ( )( )( )( )


10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� case e �e �e �e � j � k �j � k �j � k �j � k � 1 21 21 21 2 i =i =i =i =

� � � e 5 r 4 f � �

module case_no_latch2(memce0, memce1, cs, en, addr);output memce0, memce1, cs;input en;input [31:30] addr;reg memce0, memce1, cs;

always @(addr or en) begin{memce0, memce1, cs} = 3'b0; // ��

casez({addr, en})3'b101: memce0 = 1'b1;3'b111: memce1 = 1'b1;3'b0?1: cs = 1'b1;

endcaseend



10.6 )*+)*+)*+)*+ , -, -, -, - . / �. / �. / �. / � � 0� 0� 0� 0

� case e �e �e �e � j � k �j � k �j � k �j � k � 1 21 21 21 2 i =i =i =i =

09090909 10.45�� :� :� :� : ( )( )( )( )

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