hardware and petri nets: application to asynchronous circuit design jordi cortadellauniversitat...
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![Page 1: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/1.jpg)
Hardware and Petri nets:application to asynchronous
circuit design
Jordi Cortadella Universitat Politècnica de Catalunya, Spain
Michael Kishinevsky Intel Corporation, USA
Alex Kondratyev Theseus Logic, USA
Luciano Lavagno Università di Udine, Italy
Alexander Yakovlev University of Newcastle upon Tyne, UK
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STATE
CombinationalLogic
Clock
Inputs Outputs
Current state Next state
f -1
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STATE
CombinationalLogic
Inputs Outputs
Current state Next state
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CombinationalLogic
Inputs Outputs
Current state Next state
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1
1
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0
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1
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01
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A circuit is a concurrent system
Gates ProcessesDelays Computation timesSignal transitions Events
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y-
a+ b+
x+ y+
c+
c-
a-
b-
x-
x+ y-
y+x-
a
b
xy
c
Specification(environment)
Implementation(circuit)
![Page 28: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/28.jpg)
Outline
• Synthesis flow– Specification– State graph and next-state functions– State encoding– Implementability conditions– Logic decomposition
• Backannotation (theory of regions)
• Formal verification
![Page 29: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/29.jpg)
x
y
z
Signal Transition Graph (STG)
xy
z
x+
x-
y+
y-
z+
z-
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x
y
z
x+
x-
y+
y-
z+
z-
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x+
x-
y+
y-
z+
z-
xyz000
x+
100y+z+
z+y+
101 110
111
x-
x-
001
011y+
z-
010
y-
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xyz000
x+
100y+z+
z+y+
101 110
111
x-
x-
001
011y+
z-
010
y-
Next-state functions
x z x y ( )
y z x
z x y z
![Page 33: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/33.jpg)
Next-state functions
x z x y ( )
y z x
z x y z
x
z
y
![Page 34: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/34.jpg)
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
![Page 35: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/35.jpg)
VME bus
DeviceLDS
LDTACK
D
DSr
DSw
DTACK
VME BusController
DataTransceiver
BusDSr
LDS
LDTACK
D
DTACK
Read Cycle
![Page 36: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/36.jpg)
STG for the READ cycle
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDS
LDTACK
D
DSr
DTACK
VME BusController
![Page 37: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/37.jpg)
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
![Page 38: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/38.jpg)
Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
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Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
10000
10010
10110 01110
01100
0011010110
(DSr , DTACK , LDTACK , LDS , D)
![Page 40: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/40.jpg)
QR (LDS+)QR (LDS+)
QR (LDS-)QR (LDS-)
Excitation / Quiescent Regions
ER (LDS+)ER (LDS+)
ER (LDS-)ER (LDS-)
LDS-LDS-
LDS+
LDS-
![Page 41: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/41.jpg)
Next-state function
0 1
LDS-LDS-
LDS+
LDS-
1 0
0 0
1 1
1011010110
![Page 42: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/42.jpg)
Karnaugh map for LDS
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
LDS = 0 LDS = 1
0 1-0
0 0 0 0 0 0/1?
1
111
-
-
-
---
- - - -
-
- ---
- - -
![Page 43: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/43.jpg)
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
![Page 44: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/44.jpg)
Concurrency reduction
LDS-LDS-
LDS+
LDS-
1011010110
DSr+
DSr+
DSr+
![Page 45: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/45.jpg)
Concurrency reduction
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
![Page 46: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/46.jpg)
State encoding conflicts
LDS-
LDTACK-
LDTACK+
LDS+
10110
10110
![Page 47: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/47.jpg)
Signal Insertion
LDS-
LDTACK-
D-
DSr-
LDTACK+
LDS+
CSC-
CSC+
101101
101100
![Page 48: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/48.jpg)
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
![Page 49: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/49.jpg)
Complex-gate implementation
)(csccsc
csc
csc
LDTACKDSr
LDTACKD
DDTACK
DLDS
![Page 50: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/50.jpg)
Implementability conditions
• Consistency + CSC + persistency
• There exists a speed-independent circuit that implements the behavior of the STG
(under the assumption that ay Boolean function can be implemented with one complex gate)
![Page 51: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/51.jpg)
Persistency
100 000 001a- c+
b+ b+
a
cb
a
c
b
is this a pulse ?
Speed independence glitch-free output behavior under any delay
![Page 52: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/52.jpg)
a+
b+
c+
d+
a-
b-
d-
a+
c-a-
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
![Page 53: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/53.jpg)
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
ER(d+)
ER(d-)
![Page 54: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/54.jpg)
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
adcd
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
ac
d
![Page 55: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/55.jpg)
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
![Page 56: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/56.jpg)
No Hazards
abc
x 0
abcx1000
1100
b+
0100
a-
0110
c+
1
1
0
0
1
1
0
1
0
1
0
0
![Page 57: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/57.jpg)
Decomposition May Lead to Hazards
abcx1000
1100
b+
0100
a-
0110
c+
a
bz
cx
1
0
0
0
0
1000
11001100
0100
0110
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
1
0
1
0
1
0
![Page 58: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/58.jpg)
y-
z- w-
y+ x+
z+
x-
w+
1001 1011
1000
1010
0001
0000 0101
0010 0100
0110 0111
0011
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
Decomposition example
![Page 59: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/59.jpg)
yz=1yz=0
1001 1011
1000
1010
0001
0000 0101
0010 0100
0110 0111
0011
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
1001 1011
1000
1010
0001
0000 0101
0010 0100
0110 0111
0011
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
C
C
x
y
x
y
w
z
xyz
y
zw
z
w
z
y
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s-
s+
s-
s-
s=1
s=0
1001 1011
1000
1010
0111
0011y+
x-
w+
z+
z-
0001
0000 0101
0010 0100
0110
x+
w-
w-
w-
z-
z-y+
y+
x+
x+
1001
1000
1010
y+
z-
0111
C
C
x
y
x
y
w
z
x
y
z
w
z
w
z
y
sy-
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y-
z- w-
y+ x+
z+
x-
w+
s-
s+
s-
s+
s-
s-
s=1
s=0
1001 1011
1000
1010
0111
0011y+
x-
w+
z+
z-
0001
0000 0101
0010 0100
0110
x+
w-
w-
w-
z-
z-y+
y+
x+
x+
1001
1000
1010
y+
z-
0111
y-
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Event insertion
a b c
![Page 63: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/63.jpg)
Event insertion
a b
ER(x)
c
![Page 64: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/64.jpg)
Event insertion
a b
ER(x)
cx x x x
b
SR(x)
![Page 65: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/65.jpg)
Event insertion
b
ER(x)
cx x x x
b
SR(x)
a
![Page 66: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/66.jpg)
Properties to preserve
a
a
b
b
a
a
b
b
a
a
b
b
xx
a
a
b
b
a
a
b
b
ba
a
b
b
xx
xx
a ispersistent
a is disabled by b
= hazards
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Interactive design flow
Petri Net
(STG)
Transition
System
Transition
System
Reachability analysis
Transformations + Synthesis
![Page 68: Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel](https://reader030.vdocuments.net/reader030/viewer/2022032704/56649d3a5503460f94a143df/html5/thumbnails/68.jpg)
Synthesis of Petri Nets
a
a
b
bb
c
c
c a
b c
Theory of regions (Ehrenfeucht, Rozenberg, 90)
a
b
bc
c
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b
bb
b
Label splitting
a
c c
d
d
d
d
a
b
b
c
d
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Formal verification
• Implementability properties– Consistency, persistency, state coding …
• Behavioral properties (safeness, liveness)– Mutual exclusion, “ack” after “req”, …
• Equivalence checking– Circuit Specification– Circuit < Specification
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Property verification: consistency
d+
a+
b+
c- a-
b- d-
c+
Specification
a+ a-
Property
Failure if a+ enabled in specification anda- enabled in property (or viceversa)
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Correctness: environment circuit
d+
a+
b+
c- a-
b- d-
c+a
b
c
d
Environment
Circuit
Failure: circuit produces anevent unexpected (not enabled)by the environment
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Fighting the state explosion
• Symbolic methods (BDDs)
• Partial order reductions
• Petri net unfoldings
• Structural theory (invariants)
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Fighting with state explosion
p1
p2
p3
p1 p2 p3
p1 p2 p3p1 p2 p3
p1
p2 p2
p3 p3
0 1
01
00
00
1
1
1 1
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Representing Markings
p1p2
p3
p4
p5 p0
p2 + p3 + p5 = 1p0 + p1 + p4 + p5 = 1
{ p0, p3 } v0 v1 v2 v3
p2 v0 v1
p3 v0 v1
p5 v0
p0 v2 v3
p1 v2 v3
p4 v2
Place encoding
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Conclusions
• The synthesis and formal verification of asynchronous control circuits can be totally automated
• Existing tools at academia(http://www.lsi.upc.es/~jordic/petrify)
• An asynchronous circuit is a concurrent system with processes (gates) and communication (wires)
• The theory of concurrency is crucial to formalize automatic synthesis and verification methods
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Food for theoreticians
• How to insert events (and signals) while preserving some properties (persistency, obs. equiv.) ?
• How to transform specifications and do incremental analysis ?. For example, recalculate– covers of S-components and T-components
– symbolic representations of the state space
• Can we go beyond Free-Choice PNs for structural derivation of the (approximate) state space ?
• How to transform an unbounded partial specification into a bounded (and highly concurrent) implementable specification ?
• How to verify huge timed systems ?