Hardware Connections for DAQ-FPGA Interface

Interface for Driver / Data Acquisition Board P09311

David Howe

DAQ Board

• 32-pins utilized for DAQ-FPGA and FPGA-DAQ traffic– Right-most row of pins on

J15 (as labeled on board)

• Left-most row grounded per P08311’s spec’s. Since P09311’s design does not incorporate these pins, they are left disconnected, with the ability to be used in future projects

Pins used for connection with

FPGA

DAQ Connector Pinout

• Only two rows of one set of pin headers utilized by P08311

– For purpose of P09311, ground pins (odd pins) are not currently used

• Even pins 2 through 48 are data lines for digital I/O interaction between DAQ board and FPGA

• Even pins 50 through 64 are used for data transfer to/from analog I/O as well as control for A/D and D/A conversion on DAQ board

Spartan-3 Starter Board

• FPGA board utilized by P09311

• Expansion Connectors A1 and A2 used for I/O traffic

– 2 Row x 20 pin female headers

Used Connectors

FPGA Connector PinoutsA1

A2

DLP USB-245M• USB FIFO: Reference

http://www.dlpdesign.com/usb/dlp-usb245mv15.pdf

• Pins 3, 10, 11, 12 connected together to provide power to the device via USB port

• Pins 13-24 used for communication with FPGA

1

12 13

24

Breakout Board• Consists of 3 Major

Components:– DAQ Pin Connectors– FPGA Pin Connectors– DLP-USP245M USB FIFO

Adapter– See Bill of Materials for

complete part information

• Connections are soldered from the USB device and the DAQ connector to the FPGA connectors

• Purpose of board is to provide intermediate stage between FPGA and peripheral interfaces

– Allows easy FPGA disconnect for testing / programming purposes

Top of Board

Bottom of Board

Breakout Board Pinout

A 1 -5

A 1 -6

A 2 -3 4

A 2 -2 2

A 2 -2 1

A 2 -2 5

A 2 -2 4

A 2 -2 3

A 2 -2 7

A 2 -2 6

A 2 -2 8

A 2 -5

A 2 -7

A 2 -6

A 2 -9

A 2 -8

A 2 -1 0

A 2 -1 2

A 2 -1 1

A 2 -1 3

A 2 -1 5

A 2 -1 4

A 2 -1 6

A 2 -1 8

A 2 -2 0

A 2 -1 9

A 2 -1 7D L P U S B -2 4 5 M

H E A D E R 1 2 X2

123456789

1 01 11 2

2 42 32 22 12 01 91 81 71 61 51 41 3

A 2

2468

1 01 21 41 61 82 02 22 42 62 83 03 23 43 63 84 0

135791 11 31 51 71 92 12 32 52 72 93 13 33 53 73 9

A 1

2468

1 01 21 41 61 82 02 22 42 62 83 03 23 43 63 84 0

135791 11 31 51 71 92 12 32 52 72 93 13 33 53 73 9

D A Q H E A D E R

H E A D E R 3 2

6 46 26 05 85 65 45 25 04 84 64 44 24 03 83 63 43 23 02 82 62 42 22 01 81 61 41 21 08642

A 1 -1 8

A 1 -1 7

A 1 -1 6

A 1 -1 5

A 1 -1 4

A 1 -1 3

A 1 -1 2

A 1 -1 1

A 1 -1 0

A 1 -9

A 1 -8

A 1 -7

A 2 -2 9

A 2 -3 0

A 2 -3 2

A 2 -3 3

A 2 -3 1

Digital I/O Connector

• ZIF socket connected to I/O Expansion Header A1 on 2nd Spartan-3 FPGA via ribbon cable

• This allows for testing of a multitude of IC’s through development on FPGA

• Using a 2nd FPGA will allow for the largest degree of system flexibility

J 1 0

Z I F S O C -2 4 x 2

123456789

1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 4

4 84 74 64 54 44 34 24 14 03 93 83 73 63 53 43 33 23 13 02 92 82 72 62 5

A 1 -1 3

A 1 -2 3

A 1 -2 9

A 1 -1 7A 1 -1 9

A 1 -1 5

A 1 -7A 1 -5

A 1 -9

A 1 -2 7

A 1 -6

A 1 -3 3A 1 -3 1

A 1 -2 5

A 1 -1 1

A 1 -2 1

A 1 -1 8

A 1 -8A 1 -1 0A 1 -1 2

A 1 -2 2A 1 -2 4

A 1 -1 6A 1 -1 4

A 1 -3 2A 1 -2 4

A 1 -2 0

A 1 -2 6A 1 -2 8A 1 -3 0