hardware-in-the-loop co-design testbed for flying...

Hardware-in-the-LoopCo-Design Testbed for Flying Capacitor

Multilevel Converters

Nathan Pallo

ECE 590i

02/13/2017

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Introduction: FCML Inverters for Electric Aircraft

High power inverter a key enabling technology Need: High Specific Power Need: High Efficiency

Flying capacitor multilevel topology a promising solution

Credit: NASA

Introduction: FCML Inverters for Electric Aircraft

Further investigation of low-level control needed Closed-loop control of capacitor voltage balancing Stable and robust control under transients and faults

System of systems Multiple phases for motor drive Paralleled converters to meet peak power requirement

320kW Inverter Module 200kW inverter

9-24X

Outline

Motivation for Hardware-in-the-Loop

FCML Model Development

Experimental Validation of FCML model DC-DC (steady state) DC-DC (transient) Inverter (steady state) Inverter (transient)

Conclusion & Future Work

4


5

Further investigation of low-level control needed Requires a working converter to test controller implementation Hardware bugs may compound controller debugging Controller bugs at rated power/voltage could be destructive

System of systems Testing system-level control requires multiple working inverters Collaboration is difficult

Requires multiple working testbeds or one shared testbed Not all control collaborators work with high power


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Low-level control Does not require a working

hardware prototype Testing is non-destructive

System of systems Multiple model instances Multiple emulators

Collaboration Does not require shared

hardware or bench equipment Digital models easily shared Low voltage I/O

High Throughput Fast iterations while testing on

actual controller hardware

FCML Model Development

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FCML Model – 3-level Example

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3 state variables can be identified

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1:

4 systems can be identified based on switch stateA1 B1


1:

2:


A2 B2


1:

2:

3:


A2 B2

A3 B3


13

1:

2:

3:

4:


A2 B2

A3 B3

A4 B4

FCML Model – Emulator Implementation

Example: Switch State 1 Switch State 2 PWM signal change occurs at tS1 between 500ns time-steps Oversampling provides 20 ns timing precision Change is reflected at output 2-3 time-steps (1-1.5µs) later

1: 2:

Experimental Validation of Model

DC-DC (steady state)

DC-DC (transient)

Inverter (steady state)

Inverter (transient)

fixed duty cycle easier to identify sources of error


Prior work: test simulator and hardware in tandem

Collect data for 3-, 5- and 7-Level Converters

Compare iL and vx waveforms iL captures sum of all currents vx captures capacitor voltages

Altera MAX10

Controller

13-Level FCML Testbed*

Typhoon HIL402 Emulator

*C. B. Barth, T. Foulkes, W. H. Chung, T. Modeer, P. Assem, P. Assem, Y. Lei, and R. C. N. Pilawa-Podgurski, “Design and control of a gan-based, 13-level, flying capacitor multilevel inverter,” in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), pp. 1–6, June 2016.

Experimental Validation: DC-DC Steady State

Test conditions:

5-Level, 12.5% Duty


Measurement of vx pulse width accuracy as a metric Most timing-sensitive at interleaved frequency of (N-1) x fsw:

3-Level: 49 kHz 5-Level: 98 kHz 7-Level: 147 kHz

S1A

S2A

vx

vx pulse width (effective vx duty ratio)


Measurement of vx pulse width accuracy as a metric Most timing-sensitive at interleaved frequency of (N-1) x fsw:

3-Level: 49 kHz 5-Level: 98 kHz 7-Level: 147 kHz

S1A

S2A

vx

vx pulse width (effective vx duty ratio)

σmax: 1.7%, σave: 1.3% σmax: 3.5%, σave: 3.0% σmax: 12.5%, σave: 4.0%


Peak cross-correlation as a metric Comparison of entire waveform Normalized to maximum of 1

Waveforms mostly agree (metric near 1) for each converter Worst performance when vx is minimum pulse width

Gate signal changes occur at extremes of emulator timing precision Typically when duty ratio is a multiple of the switch phase shift


Phase Shift

Duty Cycle

Second gate signal change not detected until next time step!

Worst performance when vx is minimum pulse width:

S1A

S2A

vx


Spectral Comparison: X

Oscillations near extremes of vx pulse width at output filter frequency (~5kHz)

5-Level iL Spectrogram

These oscillations modulate onto the switching frequency

and harmonics

Suspected cause are limit-cycles arising

from discrete timing resolution

Experimental Validation: DC-DC Transient

3-Level with duty cycle step: 37.5% 62.5% Duty

Cross-correlation metrics: iL – 0.988, vx – 0.978

7-Level also tested Similar peak and settling time fidelity for iL Indicates application for system level emulation

Experimental Validation: Inverter Steady State

Knowing potential error from dc-dc modulate duty

Test conditions:

7-Level also tested at increased switching frequency

Cross-correlation scores:

ConverterSwitchingFrequency

Effective (Interleaved)Switching Frequency

iL metric vx metric

5-Level 24.5 kHz 98.0 kHz 0.992 0.992

7-Level 24.5 kHz 147 kHz 0.995 0.995

7-Level 49.0 kHz 294 kHz 0.991 0.995

7-Level 98.0 kHz 588 kHz 0.977 0.979

Experimental Validation: Inverter Steady State

7-Level24.5 kHz

147 kHzInterleaved

7-Level49.0 kHz

294 kHzInterleaved

7-Level98.0 kHz

588 kHzInterleaved

Experimental Validation: Inverter Load Step

5-Level with load step: 41.7Ω 83.3Ω

Cross-correlation metrics: iL – 0.989, vx – 0.993

Zoomed view shows decent tracking of current

Error is due mainly to oscillations at output filter freq. (most likely the same oscillations occurring for dc-dc)

Conclusion

3-, 5-, 7-level FCML real-time models developed Tested with fast 500 ns time-step on Typhoon HIL402 Compared with hardware analog on 13-level testbed Several quantitative metrics were proposed: Simulation pulse width statistics Peak cross-correlation between simulation and hardware Spectral power comparison

Model fidelity demonstrated within certain limits May be acceptable for low-level control in some cases Adequate for system-level development

Future work Analyze and mitigate oscillations in model emulation Further refine comparison metrics

Acknowledgements NASA Fixed Wing research program: NASA-NNX14AL79A POETS NSF ERC: EEC-1449548 Collaborators at Typhoon HIL, Inc.

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