hardware reference guide - arm...

Open Access

Bet

a D

raft

ENGLANDARM 90 Fulbourn RoadCherry HintonCambridge CB1 4JNUKTelephone: +44 1223 400400Facsimile: +44 1223 400410Email: [email protected]

GERMANYARMOtto-Hahn Str. 13b85521 Ottobrunn-RiemerlingMunichGermanyTelephone: +49 89 608 75545Facsimile: +49 89 608 75599Email: [email protected]

JAPANARMKSP West Bldg, 3F 300D, 3-2-1 SakadoTakatsu-ku, Kawasaki-shiKanagawa213 JapanTelephone: +81 44 850 1301Facsimile: +81 44 850 1308Email: [email protected]

USAARMSuite 5985 University AvenueLos GatosCA 95030 USATelephone: +1 408 399 5199Facsimile: +1 408 399 8854Email: [email protected]

World Wide Web address: http://www.arm.com

ARM Development BoardARM7TDMI Version

Hardware Reference Guide

Document number: ARM DUI 0017C

Issued: March 1997

Copyright ARM Limited 1997

hrg.book Page i Wednesday, July 22, 1998 9:18 AM

Open Access

ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

ii

Bet

a D

raft

Proprietary NoticeNeither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.TrademarksARM, and the ARM Powered logo are registered trademarks of ARM Ltd.EmbeddedICE is a trademark of ARM Limited.Windows 95 is a registered trademark of Microsoft Corporation.

Windows NT is a trademark of Microsoft Corporation.

KeyDocument Number

This document has a number which identifies it uniquely. It is displayed on every page.

Document StatusThis describes the document’s confidentiality and information status, and is shown at the bottom of each page.

Confidentiality status is one of:ARM Confidential Distributable to ARM staff and NDA signatories onlyNamed Partner Confidential Distributable to the above and to the staff of named partner companies onlyPartner Confidential Distributable within ARM and to staff of all partner companiesOpen Access No restriction on distributionInformation status is one of:Advance Information on a potential productPreliminary Current information on a product under developmentFinal Complete information on a developed product

Change LogIssue Date By Change

ARM XXX 0000 X - 00

Two-digit draft number (on review drafts only) Release code in the range A-ZUnique four-digit number Document typeL

A June 96 KTB CreatedB Nov 96 LG UpdatedC March 97 BJH Updated to reflect creation

of TDS User Guide

hrg.book Page ii Wednesday, July 22, 1998 9:18 AM

Open Access

iiiARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

1 Introduction 1-11.1 Using this Manual 1-21.2 Conventions 1-21.3 Useful Contacts 1-31.4 Glossary 1-4

2 Board Overview 2-12.1 Overview of the ARM Development Board 2-22.2 An Overview of the Board 2-3

3 Circuit Descriptions 3-13.1 Overview of Schematics 3-23.2 ARM Development Board 3-43.3 ARM7TDMI Processor Daughter Board 3-26

4 Expanding and Monitoring the ASB 4-14.1 Expanding the ASB 4-24.2 Building an ASB Master Expansion Board 4-64.3 Building an ASB Slave Expansion Board 4-74.4 ASB Timing on the ARM Development Board 4-8

Contents

hrg.book Page iii Wednesday, July 22, 1998 9:18 AM

Contents

Open Access

iv ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

5 Expanding and Monitoring the APB 5-15.1 APB Expansion Interface 5-25.2 Building an APB Slave Expansion Board 5-55.3 APB Timing on the ARM Development Board 5-6

6 The EmbeddedICE Interface 6-16.1 EmbeddedICE Interface 6-2

7 The Logic Analyser Interface 7-17.1 ARM HP Inverse Assembler 7-2

8 The Test Interface 8-18.1 Introducing the Test Interface 8-28.2 Connecting External Equipment to the Test Bus 8-38.3 Test Interface Interconnections 8-4

9 Programming the APB FPGA 9-19.1 Introduction 9-29.2 Interrupt Controller 9-39.3 Using the APB FPGA in Your Own Designs 9-4

10 Programming the MACH and PAL Devices 10-110.1 Reprogramming a Device 10-2

A Board Schematics A-1A.1 Card Outline Drawing A-2A.2 Top-level Diagram A-3A.3 Power Supply A-4A.4 Crystal Oscillator and Clock Distribution A-5A.5 ASB Slaves A-6A.6 “On-chip” Memory (Synchronous SRAM) A-7A.7 EPROM/FLASH ASB Slave A-8A.8 DRAM ASB Slave A-9A.9 SRAM ASB Slave A-10A.10 APB and NISA Bridge A-11A.11 NISA Bus Peripherals A-12A.12 Serial and Parallel Ports A-13A.13 PC Card Interface A-14A.14 PC Card Connecters and Power Supply A-15A.15 APB Slaves A-16A.16 APB Expansion Connecters A-17A.17 APB Buffers A-18A.18 Memory Address and Data Buffers A-19

hrg.book Page iv Wednesday, July 22, 1998 9:18 AM

Contents

Open Access

vARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

A.19 Test Interface Controller and Connecters A-20A.20 Master Header Connecters and Level Converters A-21A.21 System Modules (Arbiter and Decoder) A-22A.22 ASB Expansion Connecters A-23

B Daughter Board Schematics B-1B.1 Card Outline Drawing B-2B.2 Top-level Diagram B-3B.3 Header Connecters B-4B.4 Logic Analyser Connecters B-5B.5 AMBA Bus Master Veneer B-6B.6 Processor in QFP Package B-7B.7 Processor in PGA Package B-8B.8 EmbeddedICE Interface B-9

C Summary of Programmable Devices C-1C.1 Programmable Devices C-2

D Summary of Jumpers and Links D-1D.1 Overview D-2D.2 Surface Mount Links D-2D.3 Standard 2-pin Links D-3D.4 Link Fields D-4D.5 DIP Switches D-5

E Mechanical Information E-1

hrg.book Page v Wednesday, July 22, 1998 9:18 AM

hrg.book Page vi Wednesday, July 22, 1998 9:18 AM

Open Access

1-1ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

This manual provides hardware reference information on the ARM Development Board.

For information on connecting the board to a host computer and using the software development tools, please refer to the companion manual Target Development System User Guide (ARM DUI 0061).

1.1 Using this Manual 1-21.2 Conventions 1-21.3 Useful Contacts 1-3

1.4 Glossary 1-4

Introduction1

hrg.book Page 1 Wednesday, July 22, 1998 9:18 AM

Open Access

Introduction

1-2 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

1.1 Using this ManualChapter 1 is this introduction

Chapter 2 introduces the ARM Development Card

Chapter 3 describes the circuits of the ARM Development Card

Chapter 4 describes how to expand the ASB

Chapter 5 describes how to expand the APB

Chapter 6 describes the EmbeddedICE interface

Chapter 7 describes the logic analyser interface

Chapter 8 describes the test interface

Chapter 9 describes how to program the APB FPGA

Chapter 10 describes how to program the MACH and PAL devices

Appendix A provides detailed circuit schematics of the board

Appendix B provides detailed circuit schematics of the daughter board

Appendix C is an index of the programmable devices

Appendix D is a summary of the switches, jumpers and links

Appendix E is a mechanical drawing of the ARM Development Card

1.1.1 Related Documentation

You may find it useful to refer to the following documents:

ARM IHI-0001 AMBA Specification

ARM DUI 0014 HP ARM Inverse Assembler User Guide

ARM DDI-0041 AMBA Arbiter

ARM DDI-0042 AMBA Decoder

ARM DDI-0043 AMBA Test Interface Controller

ARM DDI-0047 AMBA Interrupt Controller

ARM DDI-0048 AMBA Reset and Pause

ARM DDI-0049 AMBA Timer APB Peripheral

ARM DDI-0051 AMBA Reset Controller

ARM DUI 0061 Target Development System user Guide

ARM DDI 0062 Reference Peripherals Specification

1.2 ConventionsThis manual employs typographic conventions intended to improve its ease of use.

code code which you need to enter, or which is provided as an example


Open Access

Introduction


1.3 Useful Contacts

1.3.1 Contacting ARM

Further information is available from ARM.

All schematics (ORCAD), PLD and VHDL binary files and latest release notes are available from our world wide web servers at:

http://www.arm.com

If you require PDL descriptions or have difficulty accessing our web page, please email:

[email protected]

1.3.2 Component data sheets

Contact points for component data sheets are as follows:

XR16C552 Exar (Startech) serial and parallel port chip

UK distributor:

Farnell Electronic Components Ltd. Tel: +44 113 2310160

http://www.exar.com

MACH and PALCE AMD programmable logic devices

UK distributors:

Kudos Thame Ltd. Tel: +44 1734 351010

Avnet Access Ltd. Tel: +44 1462 480888

http://www.amd.com

XC4005 Xilinx FPGA

UK distributor:

Microcall Ltd. Tel: +44 1844 261939

Avnet Access Ltd. Tel: +44 1462 480888

http://www.xilinx.com

VG-468 Vadem PC card controller

UK distributor:

MMD Tel: +44 1734 633700

http://www.vadem.com

1.3.3 Information on chips

A useful site for chip information is:

http://www.xs4all.nl/~ganswijk/chipdir


Open Access

Introduction


ARM DUI 0017C

1.4 GlossarySome of the terms used in this manual may be unfamiliar to you. This section explains some of the more important ones.

ARM7TDMI The ARM7TDMI test chip is an example of an ARM processor macrocell that is suitable for use on the ARM Development Card. See the ARM7TDMI Data Sheet (ARM DDI 0029) for more information.

CPLD A complex programmable logic device (CPLD) is usually a collection of PAL-type devices in a single package. The AMD MACH device is an example of a CPLD.

EmbeddedICE This is the additional hardware that is provided by debuggable ARM processors to aid debugging. The EmbeddedICE macrocell is fully described in the ARM7TDMI Data Sheet (ARM DDI 0029). The EmbeddedICE macrocell is controlled via the JTAG test access port, using an EmbeddedICE interface. This is an extra piece of hardware that allows software tools to debug code running on a target processor.

FPGA A field-programmable gate array (FPGA) is a type of programmable logic device (PLD). The ARM Development Card is fitted with one FPGA manufactured by Xilinx. You can change the functionality of this device if the appropriate design tools are available. Xilinx sells an appropriate tool set which interfaces to a variety of front-end systems which may be based on schematics or hardware description languages such as VHDL. See also LCA.

ICE An in-circuit emulator (ICE), is a device that aids debugging of hardware and software. ARM debuggable processors such as the ARM7TDMI have extra hardware called EmbeddedICE to assist this process.

JTAG This is a serial-like test port provided on many large silicon chips such as the ARM7TDMI.

LCA A logic cell array (LCA) is a type of programmable logic device (PLD) also known as a field-programmable gate array (FPGA).

MACH A MACH device is a example of a complex programmable logic device (CPLD). The ARM Development Card uses a number of MACH210 and MACH230 devices. Based on electrically erasable (EE) technology, they are reprogrammable. Using appropriate software (such as PALASM), the function of these devices may be changed by reprogramming in a standard programmer.

NISA NISA (not-ISA) is ARM’s description of the bus that connects the Advanced System Bus (ASB) to some standard peripheral devices such as the serial/parallel ports and PC card controller. It is a subset of the Industry Standard Architecture (ISA) bus found in most IBM compatible PCs.


Open Access

Introduction


PAL A programmable array logic (PAL) device is a example of a programmable logic device (PLD). The PAL used on the ARM Development Card is a PALCE22V10. This has up to 22 inputs, ten outputs and ten programmable macrocells. As it is based on electrically erasable (EE) technology, it is reprogrammable. Using appropriate software (such as PALASM), the function of this device may be changed by reprogramming in a standard programmer.

PCMCIA The Personal Computer Memory Card Association (PCMCIA) produces a specification that details an interface suitable for connecting small boards (the size of credit cards) to larger host systems. The name PCMCIA is generally used to describe these cards, but its use has been superseded by the term PC card.

PLD A programmable logic device. See also PAL and FPGA.

PALASM A programmable array logic assembler (PALASM) is a low-cost, proprietary logic description language produced by Advanced Micro Devices (AMD) for their range of PLDs and CPLDs. It has been used extensively in the design of the ARM Development Card.

PLL A phase-locked loop (PLL) usually comprises a voltage controller oscillator, programmable divider, frequency comparator, and an integrator. These components allow a programmable frequency clock to be generated. This is locked to and stabilised by a reference clock input. On the ARM Development Card, a single component performs this function. A reference crystal at 14.318MHz is used, and with three programmable inputs, the device is able to generate 8 output frequencies from about 4–50MHz.

VHDL VHDL is a hardware description language suitable for the simulation and synthesis of logic circuits. The design for the FPGA on the ARM Development Card was completed using VHDL and synthesis tools from Compass. Xilinx tools were used to place and route the design.


Open Access


This chapter describes each of the main blocks of the ARM Development Board.

2.1 Overview of the ARM Development Board 2-2

2.2 An Overview of the Board 2-3

Board Overview2


Open Access

Board Overview


ARM DUI 0017C

2.1 Overview of the ARM Development BoardThe ARM Development Board is a platform that is suitable for code development and exploration of embedded ARM processors. It is a convenient means of evaluating the Advanced RISC Machines’ Thumb-aware (ARM7T) family of RISC processors.

The ARM Development Board has been designed to conform to the Advanced Microcontroller Bus Architecture (AMBA) specification. This specification defines an on-chip communications standard for designing high performance 32- and 16-bit embedded microcontrollers. A convenient way to view the ARM Development Board is as a microcontroller design in discrete components. This means that it is possible to observe bus transactions and peripheral accesses using standard test equipment. Thus, a typical microcontroller design can be easily observed and prototyped.

Because the processor in the system is little more than ARM core it is possible to use an in-circuit emulator (ICE). This enables a system design to be tested and debugged at the processor level. In addition processors with EmbeddedICE capabilities can be debugged directly using the EmbeddedICE interface. The ARM Development Board also has a parallel port and two serial ports that allow it to be connected to a variety of hosts. Using a monitor program supplied with the board, the user can download and run code in collaboration with the ARM Software Development Toolkit.

The ARM Development Board shows how to design a system based on the AMBA specification, comprising a multi-master system bus (ASB) and a low-power peripheral bus (APB). While on-chip techniques may differ, the main system modules and their interconnect have been preserved.

The following are useful reference documents. You should refer to these to understand the functionality of AMBA modules.

• AMBA Specification(ARM IHI 0001)

• Reference Peripherals Specification(ARM DDI 0062)

2.1.1 Using ARM resources in your design

This manual contains both the circuit description (and schematics) of the ARM Development Board and a description of programmable logic devices used.

The programmable logic equations and schematics can be obtained from ARM for use in your own designs. These are provided to help you design your prototype target hardware systems.

Both hardware and software are provided as tutorial aids and demonstrate techniques rather than an optimal implementation. Please feel free to use the schematics and programmable logic equations provided as a basis for your own system designs.


Open Access

Board Overview


2.2 An Overview of the BoardA typical AMBA system comprises a processor connected to an Advanced System Bus (ASB) with a bridge to the slower, low-power Advanced Peripheral Bus (APB). The main system blocks are shown in Figure 2-1: Overview of the ARM Development Board on page 2-4:

• AMBA bus master comprising an ARM processor and PLD

• AMBA system modules, arbiter and decoder

• On-chip (synchronous SRAM) memory

• SRAM block

• EPROM or FLASH block

• DRAM block

• Test interface

• APB bridge

• APB slaves, timer, interrupt controller

• ASB expansion connectors

• APB expansion connectors

• NISA bus bridge

• PC card (PCMCIA) block

• Serial and parallel port block

2.2.1 Board architecture

A convenient way to view the ARM Development Board is as a sample microcontroller with its support peripherals constructed from discrete devices. The bus master, system modules, APB bridge and peripherals, on-chip RAM and external bus interfaces form the heart of a microcontroller. Additional peripherals such as PC card (PCMCIA) and serial and parallel ports may also be incorporated or interfaced to externally.

Each functional block is constructed from separate programmable logic devices (PLDs). This enables you to observe the system interactions using standard test equipment such as a logic analyser. The expansion connectors provide a way of interfacing additional circuitry to the ARM Development Board and also provide convenient hook-up points for a logic analyser.

Refer to Chapter 4, Expanding and Monitoring the ASB and Chapter 5, Expanding and Monitoring the APB for further information.


Open Access

Board Overview


ARM DUI 0017C

Memory types

A typical system might provide some of the following memory types:

• SRAM

• EPROM

• FLASH

• DRAM

Examples of all of these can be found on the board.

Each memory type has its own controller. An ideal system might have a single external bus interface (EBI). In this implementation the EBI is distributed into separate memory controllers.

Figure 2-1: Overview of the ARM Development Board

External Bus I/F

ASBExpansion

AMBA Bus Master

ARMPLD

Arbiter

Decoder

“On-chip”SRAM

32K x 32

ROM SRAM DRAM I/O

TestI/F

3V-5V Level Shift

APBBridge

Timer

InterruptController

APBExpansion

512Kx 8

128Kx 32

0-8 MSIMM

PCMCIA

Parallel +Serial Port


Open Access


This chapter describes the circuits of the ARM Development Board.

3.1 Overview of Schematics 3-2

3.2 ARM Development Board 3-43.3 ARM7TDMI Processor Daughter Board 3-26

Circuit Descriptions3


Open Access

Circuit Descriptions


ARM DUI 0017C

3.1 Overview of SchematicsThe board has been designed to allow an AMBA bus master (such as an ARM7TDMI test chip) to be mounted on daughter board. The daughter board is an integral part of the ARM Development Board, although the daughter board supplied could be replaced with another AMBA master, such as an in-circuit emulator.

3.1.1 Master board circuits

The master board design comprises 22 schematics as listed below.

1 Board outline drawing DRAWING.SCH

2 Top-level diagram CHAMP.SCH

3 Power supply POWER.SCH

4 Crystal oscillator and clock distribution OSC.SCH

5 ASB slaves ASBSLAVE.SCH

6 “On-chip” memory (synchronous SRAM) ONCHIP.SCH

7 EPROM/FLASH ASB slave EPROM.SCH

8 DRAM ASB slave DRAM.SCH

9 SRAM ASB slave SRAM.SCH

10 APB and NISA bridge ASBNISA.SCH

11 NISA bus peripherals NISABUS.SCH

12 Serial and parallel ports SUPERIO.SCH

13 PC card interface PCMCIA.SCH

14 PC card connectors and power supply CARDCON.SCH

15 APB slaves APBSLAVE.SCH

16 APB expansion connectors APBEXP.SCH

17 APB buffers APBBUF.SCH

18 Memory address and data buffers MEMBUF.SCH

19 Test interface controller and connectors TIC.SCH

20 Master header connectors and level convertors MASTER.SCH

21 System modules (arbiter and decoder) SYSMODS.SCH

22 ASB expansion connector ASBEXP.SCH

3.1.2 Configuring the board

The board is configurable through the use of links, jumpers and switches. Each of these is described in detail in the following subsections. In addition, there is a summary of links and switches in Appendix D, Summary of Jumpers and Links. Also, the Target Development System User Guide (ARM DUI 0061) contains information on configuring the ARM Development Board.


Open Access



3.1.3 Daughter board circuits

The daughter board schematics for the supplied system are included in Appendix B, Daughter Board Schematics.

The daughter board (or header) is connected to the ARM Development Board by four 60-way connectors. This allows different bus masters to be connected, including in-circuit emulators.

The design comprises seven schematics as listed below.

Note There are two versions of the processor schematic depending upon whether you have a QFP or PGA packaged part on the board.

1 Board outline drawing DRAWING.SCH

2 Top-level diagram CHAMPQFP.SCH

3 Header connectors CPUHEAD.SCH

4 Logic analyser connectors LAPODS.SCH

5 AMBA bus master veneer AMBAPLD.SCH

6 Processor in QFP package PROCQFP.SCH

7 Processor in PGA package PROCPGA.SCH

8 EmbeddedICE interface EICE.SCH


Open Access



ARM DUI 0017C

3.2 ARM Development BoardThe top-level schematic is illustrated in A.1 Card Outline Drawing on page A-2, and shows the main blocks of the design. The blocks are interconnected by the ASB signals prefixed B_, such as B_A[31:0], B_D[31:0] and B_WAIT. There are two ASB bus masters, the ARM chip mounted on a header card and the test interface controller (TIC).

The ASB system modules (the system arbiter and decoder) can also be seen.

There is a block called ASB expansion which details the physical connectors. This allows the ASB to be monitored by a logic analyser, or allows external circuitry to be attached

The oscillator block describes the system clock generation and distribution, and the power supply block describes the power input and regulation.

There are a number of ASB slaves which are described in 3.2.3 ASB Slaves on page 3-7.

3.2.1 Power Supply

This schematic is shown in A.3 Power Supply on page A-4.

Two green LEDs marked (5V) and (3V3) light up when power is connected to the board.

Note Take care when connecting up power to this board as there is no protection for incorrectly wired supplies. If the LEDs fail to light, switch off immediately and check the connections.

The board is designed to function at 5V so that high-speed programmable logic devices can be used. The ARM processor is a 3.3V component and so needs to be protected from high logic levels. This is accomplished through use of level-convertor ICs. A 3.3V supply is generated on board from a 5V supply for use by the ARM processor and the synchronous SRAM (a 3.3V part with 5V tolerant I/O).

Power to the board is supplied through a PC-style 12-way connector. This allows a PC power supply to be connected directly, and this will provide all the requirements of the board. The board consumes 2–5A at 5V depending upon the amount of DRAM fitted and the clock frequency used. If preferred a bench power supply can be used instead.

Note Some PC power supplies can trip out if very low current is taken, so you can insert a load across the +12V supply has been made. If this is a requirement, connect a resistance across the pads marked (JP2).

The connector (J1) contacts are rated at 2A, so if current consumption is low, it is only necessary to connect to pin 2 (+5V) and pin 5 (GND). Pin 3 (+12V) need only be connected if the PC card (PCMCIA) interface is to be used.

An LM317 voltage regulator (U1) is used to generate the 3.3V supply required by the ARM processor. You can decouple this from the regulator by removing a wire link (JP1) if required.


Open Access



3.2.2 Crystal Oscillator and Clock Distribution

This schematic is shown in A.4 Crystal Oscillator and Clock Distribution on page A-5.

A standard 14.318MHz crystal oscillator (X1) is connected to a phase-locked loop (PLL) based clock-generation device (U5), which generates all the system clocks. These are:

SYSCLK distributed to system

SYSCLK2X double rate system clock

CLK32MHZ 32MHz clock for NISA bus (primary)

CLK24MHZ 24MHz clock for NISA bus (alternative to CLK32MHZ)

COMMCLK 1.843MHz for serial port UART

System clocks

The system clocks, either on-board or external, are distributed to the rest of the board via three low-skew clock buffer devices (U3,U4 and U6). Each clock output is serially terminated and drives one load only.

If other system clock frequencies are needed (up to a maximum of 25MHz), an external source can be applied in place of the SYSCLK and SYSCLK2X outputs from (U5). Both must be provided and they must be phase-aligned.

External clocks

The external clocks, EXTSCLK and EXTSCLK2X, should be connected to plugs (PL1 and PL2). Optional 47R resistors can be fitted (R36 and R37) to terminate the clock inputs if required. To select external clocks instead of the on-board clocks, you have to move the surface mount links (LK2 and LK3) to the B-C position.

Double-rate clock

The double-rate clock SYSCLK2X is used by the synchronous SRAM to allow single cycle memory accesses. This is a departure from the AMBA bus methodology, but used in order to simulate fast “on-chip” memory.

Serial port (UART)

The 1.843MHz COMMCLK drives the serial port (UART) baud rate generator directly. In addition, this clock is divided down by the PAL (U2) to provide a refresh signal (REFCLK) at 64kHz for the DRAM controller.

NISA bus devices

The NISACLK is used to drive the NISA bus devices. This is a 32MHz clock signal, derived from CLK32MHZ, selected by a surface mount link (LK1). The CLK24MHZ output from (U5) is not normally used.


Open Access



ARM DUI 0017C

Unused clock signals

Two clock signals are not used NISACLK1 and B_CLK8. These are available as monitor points (V1 and V2), as shown in A.2 Top-level Diagram on page A-3.

Clock frequencies

The frequency of SYSCLK and SYSCLK2X can be controlled by three inputs (CLKSEL[2:0]). A switch (S1) is used to control these select lines via a PAL (U2), which is used to prevent inappropriate clock frequencies being selected.

Ref Position Name Option Description

S1 1 SEL0 on/off see table below

2 SEL1 on/off see table below



Table 3-1: S1

Switch position Frequency (MHz

SEL3 SEL2 SEL1 SEL0 SYSCLK SYSCLK2X

on on on on 4 8

on on on off 8 16

on on off on 16 32

on on off off 20 40

Table 3-2: Switch positions


Open Access



3.2.3 ASB Slaves

This schematic is shown in A.5 ASB Slaves on page A-6, and shows the following ASB slaves and associated circuitry:

• DRAM controller

• Synchronous SRAM controller

• SRAM controller

• EPROM/FLASH controller

• Memory address and data buffers

• APB and NISA bus bridge

Each memory controller is described in the appropriate section. The memory address and data buffers are shared by the these controllers as follows:

• B_D is driven onto M_D when nOEMD is driven LOW

• M_D is driven onto B_D when nOEBD is driven LOW

The SRAM controller and the DRAM controller both drive nOEMD and nOEBD, which are implemented as open-collector active low signals.

M_A is generated by sampling B_A on the falling edge of B_CLK, and is used by the SRAM and EPROM slaves.

Address and data latches for the APB and NISA buses are implemented separately (see 3.2.15 APB Buffers on page 3-22).

Link (LK4) is used to select the endianism of the board. The default (link out) is little-endian. If the link is inserted the BIGEND signal goes high and this is used by the SRAM, synchronous SRAM and DRAM controllers to enable big-endian style writes. There is no support for EPROMs that have been programmed big-endian. The BIGEND signal is also routed to the ARM processor.


Open Access



ARM DUI 0017C

3.2.4 “On-Chip” Memory (Synchronous SRAM)

The “on-chip” memory (synchronous SRAM) schematic is shown in A.6 “On-chip” Memory (Synchronous SRAM) on page A-7.

A typical AMBA system might comprise some fast “on-chip” memory and various memory controllers for SRAM, DRAM and EPROM. On the board, a synchronous SRAM device has been used to simulate “on-chip” memory. By running the device with a double-rate clock, single-cycle memory access can be achieved.

The controller is implemented as an ASB slave in a fast PAL (U8). The memory device is a 32K x 32-bit pipelined synchronous SRAM capable of being clocked at up to 66MHz. Because it is a pipelined device, the data is available to be read two clock cycles after the address is latched. In an ARM system, the data needs to be available in the clock cycle following the address. Therefore, by running the device at twice the system clock frequency, the data is read out in the correct system cycle.

Figure 3-1: ASB Sync SRAM Timing Diagram shows the clock relationship and control signals.

Figure 3-1: ASB Sync SRAM Timing Diagram

READ DECODE1 WRITE DECODE2 READ MULTIPLE

HOLD READ IDLE IDLE HOLD WRITE IDLE IDLE HOLD READIDLE IDLE HOLD READ READHOLD

0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns

B_CLK

B_CLK2X

state

D_SEL

B_A

B_WRITE

ADSP

OE

WE

B_D read

B_D write


Open Access



3.2.5 EPROM/FLASH ASB Slave

This schematic is shown in A.7 EPROM/FLASH ASB Slave on page A-8.

The EPROM/FLASH subsystem is implemented in two devices:

• one drives the memory strobes and interfaces with ASB (U10)

• the other provides data path steering (U11)

The board contains two sockets:

• an 32-pin DIL socket (U12) into which EPROM or FLASH devices up to 512Kx8 (4MB) can be fitted

• a 44-pin PLCC socket (U13) into which EPROM or FLASH devices up to 256Kx16 (4MB) can be fitted

Therefore, there is one 8-bit wide and one 16-bit wide socket, but only one device may be driven at a time. Links on the board select:

• whether an 8- or 16-bit device is driven

• whether it is EPROM or FLASH

• the number of bus cycles required to access it

Link field LK6 has the following link positions:

Clock cycles

The number of cycles is either 2, 3, 4 or 5. The cycle time must be carefully selected, taking into account the system clock frequency and the device speed grade.

For example, for a system clock frequency of 20MHz, cycle time = 50ns. Table 3-4: Pulse widths for settings of CYC[1:0] on page 3-10 shows pulse widths for various settings of CYC[1:0].

Note The write-enable strobe length (for FLASH only), is always the number of cycles minus one.

Position Name Description Options Default

1 CYC1 Number of cycles see table below out

2 CYC0 Number of cycles see table below in

3 EPROM Selects EPROM or FLASH outin

==

EPROMFLASH

in

4 SEL8BIT Selects 8- or 16-bit device outin

==

8-bit16-bit

out

Table 3-3: LK6 link positions


Open Access



ARM DUI 0017C

For an ATMEL AT29C040A-15 (512K x 8) 5V only FLASH PEROM, tWP = 90ns, and tCE = 150ns, so select CYC[1:0] = [out,in] = 3cycles.

Connecting external peripherals to the EPROM/FLASH controller

As well as supporting EPROM and FLASH devices, you can use the controller to drive simple 8- or 16-bit peripherals that need memory type strobes such as:

• chip enable

• output enable

• write enable

To connect such a peripheral to the ARM Development Board, disconnect any EPROM or FLASH devices and wire up the peripheral to the appropriate socket using a transition header. If you need to support EPROM or FLASH and a peripheral, some modification of the controller may be necessary.

An alternative is to implement a similar controller and data-path router on a daughter card and attach it to the ASB using the 20-way headers provided. Refer to Chapter 4, Expanding and Monitoring the ASB for further information.

CYC1 CYC0 Cycles Pulse width(ns)

CE OE WE

in in 2 100ns 100ns 50ns

in out 3 150ns 150ns 100ns

out in 4 200ns 200ns 150ns

out out 5 250ns 250ns 200ns

Table 3-4: Pulse widths for settings of CYC[1:0]


Open Access



3.2.6 DRAM ASB Slave

This schematic is shown in A.8 DRAM ASB Slave on page A-9.

The DRAM subsystem comprises:

• an ASB slave controller (U14)

• two SIMM sockets (SK1 and SK2) which can be fitted with a variety of memory modules

The DRAM controller supports one or two 72-pin SIMM slots and uses automatic SIMM presence-detection for contiguous memory configuration. The DRAM controller provides:

• fast page-mode burst-mode sequential-access support

• byte, half-word and word transaction support

• 256-byte boundary page-mode cycle break-up

• DRAM refresh (using CAS-before-RAS Refresh mode)

• automatic module-size reconfiguration

• support for 4MB, 8MB and 16MB SIMM modules

Note Although up to 64MB of DRAM can be fitted, the default memory map allows for 16MB. If you require more DRAM, modify the system decoder to allow access to the range required.

The DRAM controller drives the address and control paths for the DRAM subsystem. The datapath is shared with the SRAM subsystem.

DRAM SIMMs supported

The DRAM controller supports 72-pin modules built of 4Mb and 16Mb technology DRAM devices, with a RAS Access Time specified at 70ns or faster.

Note Where two SIMM modules are fitted, these must be of the same size and configuration. Where only one SIMM is fitted then this should only be fitted to slot A.

The following size DRAM SIMM modules are supported:

These SIMMs are standard commodity parts for desktop computers and workstations, and byte parity is not required or used. The basic memory size for all these modules is determined by the two presence-detect bits (PD1, PD0) with the addition of two pull-up resistors on the board. Only Slot A presence-detect is used.

4MB 32x1M 72-pin 70ns (single-sided module, 8 x 1Mx4)4MB 36x1M 72-pin 70ns (single-sided module, 9 x 1Mx4)

8MB 32x2M 72-pin 70ns (double-sided module, 2 x 8 x 1Mx4)8MB 36x2M 72-pin 70ns (double-sided module, 2 x 9 x 1Mx4)16MB 32x4M 72-pin 70ns (single-sided module, 8 x 4Mx4)

16MB 36x4M 72-pin 70ns (single-sided module, 9 x 4Mx4)32MB 32x8M 72-pin 70ns (double-sided module, 2 x 8 x 4Mx4)32MB 36x8M 72-pin 70ns (double-sided module, 2 x 9x 4Mx4)


Open Access



ARM DUI 0017C

3.2.7 SRAM ASB Slave

This schematic is shown in A.9 SRAM ASB Slave on page A-10.

The SRAM subsystem comprises:

• an ASB slave controller (U16)

• four 20ns 128KBx8 SRAM devices (U15,U17,U18 and U19)

The controller uses this memory to emulate two logical banks of 8-, 16- or 32-bit wide SRAM. Although there is one 8-bit wide device connected to each byte lane, the controller simulates narrow memory systems by inserting the correct number of wait states.

DIP switches

Slow SRAM can also be simulated through the use of DIP switches to control the number of bus cycles required for a memory access. Two-, three-, four-, and five-cycle memory can be emulated. DIP switches are also used to determine the memory width.

The controller partitions the memory space into two logical banks of 256KB. The banks are called bank 0 and bank 1 and each has individual select lines for size and speed.

Switch Name Description Options Default

1 B0CYC0 Bank 0 number of cycles see table below on


3 B0SIZ0 Bank 0 size (8,16,32-bit) see table below on

4 B0SIZ1 Bank 0 size (8,16,32-bit) see table below off



7 B1SIZ0 Bank 1 size (8,16,32-bit) see table below on

8 B1SIZ1 Bank 1 size (8,16,32-bit) see table below off

Table 3-5: DIP switch positions


Open Access



DIP switch (S2) has the following positions, where # is the bank number, 0 or 1

The default configuration emulates 2-cycle 32-bit memory in both banks.

Many different configurations are possible. For example:

bank 0 8-bit 5 cycle (250ns @ 20MHz) memory (EPROM emulation)

bank 1 16-bit 2 cycle (100ns @ 20MHz) memory (standard SRAM).

B#CYC1 B#CYC0 Cycles B#SIZ1 B#SIZ0 Size

on on 2 on on 8-bit

on off 3 on off 16-bit

off on 4 off on 32-bit

off off 5 off off 32-bit

Table 3-6: S2 switch positions

Switch Name Position

1 B0CYC0 off

2 B0CYC1 off

3 B0SIZ0 on

4 B0SIZ1 on

5 B1CYC0 on

6 B1CYC1 on

7 B1SIZ0 off

8 B1SIZ1 on

Table 3-7: Switches


Open Access



ARM DUI 0017C

3.2.8 APB and NISA Bridge

This schematic is shown in A.10 APB and NISA Bridge on page A-11, and shows the following blocks:

• APB address and data buffers

• APB slave block

• NISA (not-ISA) bus peripherals block

• APB expansion block

• APB and NISA (not-ISA) bridge device

The Advanced Peripheral Bus (APB) connects to the ASB through the address and data buffers and the bridge which is implemented in (U20). In addition, this bridge generates signals required to interface to the ISA-type peripherals. This is not a full implementation of the ISA bus, hence not-ISA (NISA). The NISA bus peripherals comprise the PC card (PCMCIA) controller and the serial and parallel I/O device.

The bridge chip is responsible for generating all the APB control signals and enabling the address and data latches. The NISA bus shares the address and data latches with the APB bus. The bridge detects accesses to APB and NISA address space and acts accordingly.

Link (LK7) is used to select the width of the P_STB signal. The default (link out) is a strobe of two system clock cycles. If the link is inserted the P_STB signal is asserted for one system clock cycle only.

Note The APB peripherals are not guaranteed to function correctly if the link is inserted and the system clock frequency is above 20MHz. Use this link with care.

3.2.9 NISA Bus Peripherals

The NISA bus peripherals schematic is shown in A.11 NISA Bus Peripherals on page A-12, and shows the following blocks.

• serial and parallel I/O port block

• PC card (PCMCIA) interface block

Details of these blocks can be found in the following sections.


Open Access



3.2.10 Serial and Parallel Ports

The serial and parallel ports schematic is shown in A.12 Serial and Parallel Ports on page A-13.

The serial and parallel I/O subsystem is based around an ST16C552 device. This is a dual asynchronous receiver and transmitter with 16-byte transmit and receive FIFO and a bi-directional Centronics type parallel printer port. This device is pin and functionally compatible with the VL16C552 and the WD16C552. In order to program the device you are advised to obtain a data sheet for one of these devices. Please contact ARM if you have any problems obtaining the datasheet.

The XR16C552 (U21) drives two serial ports (A and B) through two RS232 level shifters (U22 and U23). To connect to the serial ports you will need a cable that terminates in a 9-pin D socket. The pinout is compatible with a standard PC serial port and is shown Table 3-8: Serial port pinout:

The ST16C552 also drives a Centronics-type parallel port. To connect to the parallel port you will need a cable that terminates in a 25-way D plug. The pinout is compatible with a standard PC parallel port and is shown in Table 3-9: Parallel port pinout on page 3-16.

Pin Function Direction

1 DCD in

2 RxD in

3 TxD out

4 DTR out

5 GND power

6 DSR in

7 RTS out

8 CTS in

9 RI in

Table 3-8: Serial port pinout


Open Access



ARM DUI 0017C

Pin Function Direction Pin Function Direction

1 STROBE i/o 14 AUTOFD i/o

2 DATA[0] i/o 15 ERROR in

3 DATA[1] i/o 16 INIT i/o

4 DATA[2] i/o 17 SLCTIN i/o

5 DATA[3] i/o 18 GND power





10 ACK in 23 GND power

11 BUSY in 24 GND power

12 PE in 25 GND power

13 SLCT in

Table 3-9: Parallel port pinout

Additional features

Some additional features have been added to the board to allow the parallel port to drive some LEDs and read switches.

DIP switch (S3) connects to bits 0-3 of the parallel port when the four lower bits of the link field (LK11) are jumpered.

Similarly the four yellow LEDs marked PP0–3 are connected to bits 4–7 of the parallel port when the upper four bits of the link field (LK11) are jumpered. This information is summarized in Table 3-10: LED’s and read switches t:

Position Bit Connects to

1-2 0 S3 switch 1

3-4 1 S3 switch 2

5-6 2 S3 switch 3

7-8 3 S3 switch 4

9-10 4 LED PP0

11-12 5 LED PP1

13-14 6 LED PP2

15-16 7 LED PP3

Table 3-10: LED’s and read switches


Open Access



Note When using the parallel port to connect to external devices, you are advised to remove all the jumpers of link field (LK11). If you need to drive some LEDs and use an external device, you should consider driving the LEDs connected to the PC card (PCMCIA) controller.

The ST16C552 can be configured through the use of two links:

• INT TYPE

• DIRN (LK8 and LK9)

LK8 selects the interrupt type, either latched mode (out) or ACK mode (in).

Latched mode A falling edge on the ACK pin is latched and causes a parallel port interrupt. This interrupt is cleared by reading the appropriate status register. Latched mode is the default.

ACK mode The ACK pin is connected directly to the parallel port interrupt line. If the parallel port ACK line is not connected externally, it is possible to make ACK pulse low by pressing the “momentary action” switch, SW1 (which has a black cap). To enable this function, the link ENABLE INT (LK10) must be inserted. If the link is out, pressing the switch has no effect.

Note When using the parallel port to connect to external devices, you are advised to remove the jumper from ENABLE INT (LK10).

L9 (The DIRN link) is connected to the BIDEN pin on the ST16C552. You can program the parallel port to be input or output under software control, but the method differs depending upon the state of the BIDEN pin. The default is link out which means that BIDEN is high and the direction is programmed by writing to the parallel port control register. Please refer to the 16C552 data sheet for further information.

Ref Name Description Options Default

LK8 INT TYPE latched or ACK mode outin

==

latchedACK

out

LK9 DIRN parallel port direction BIDEN select out

LK10 ENABLE INT enable switch interrupt outin

==

disabledenabled

out

Table 3-11: Link summary


Open Access



ARM DUI 0017C

3.2.11 PC Card Interface

This schematic is shown in A.13 PC Card Interface on page A-14.

The PC card (PCMCIA) I/O subsystem is based around a Vadem VG-468 (U25) device. This a PC card socket controller which is designed to connect to a PC ISA bus. In this case, it is driven by the APB and NISA bridge. The controller supports two PC card sockets and the associated voltage switching devices.

In order to program the controller, you are advised to obtain a data sheet from the manufacturer. Please contact ARM if you have any problems obtaining a data sheet. It is a complex device and a description of its internal function is outside the scope of this document.

In combination with the voltage switching devices described in the next section the ARM Development Board is able to support cards that require a +5V supply and a programming voltage (VPP) of +5V or +12V.

Note No support is provided for +3.3V PC cards.

There are two yellow LEDs (D11 and D12) attached to the VG-486 labelled PCA and PCB. Logically, one LED is associated with each of the PC card sockets A and B. These LEDs are connected to the GPIO pins of the controller and so can be switched on an off by writing to an appropriate register in the device.


Open Access



3.2.12 PC Card Connectors and Power Supply

The PC card connectors and power supply schematic is shown in A.14 PC Card Connecters and Power Supply on page A-15.

This schematic shows two voltage switching devices (U26 and U27) and two PC card socket connectors (SK4A and SK4B). The two socket connectors form one physical device, housing two card slots. The upper slot is A and the lower slot is B. The connectors are driven directly from the PC card controller, which is also responsible for determining the card voltage.

To function correctly, the MIC2560 (U26 and U27) requires supplies at +3.3V (VDD), +5V (VCC), and +12V (VPP). If any of these supplies are not connected, the supply presented to the card will be incorrect. The card VCC voltage depends upon two inputs, VCC5EN and VCC3EN. With VCC3EN tied HIGH through a surface mount link (LK12 and LK13), VCC5EN controls the supply.

The card VPP voltage depends upon two inputs:

Note The signal names for slot A are prefixed by A_.The signal names for slot B are prefixed by B_.

Driving this signal LOW sets the card VCC voltage at +5V. Driving the signal HIGH puts the power supply pins into a high impedance state, effectively cutting off the supply to the card.

VG-468 signal nameMIC2560-1 signal name

nVCCENVCC5EN

-VCC3EN

VCC Supply5V 0 1

HIGH Z 1 1

• EN0

• EN1

By driving these signals HIGH and LOW the supply can be switched between +5V, +12V, GND and high impedance. See the table on the right for more information.

VG-468 signal nameMIC2560-1 signal name

VPP1ENEN1

VPP2ENEN2

VPP Supply0V 0 0

5V 0 1

12V 1 0

HIGH Z 1 1


Open Access



ARM DUI 0017C

3.2.13 APB Slaves

This schematic is shown in A.15 APB Slaves on page A-16.

All the APB slaves are implemented in a single Xilinx field programmable gate array (FPGA). The XC4005 (U29) is programmed to provide the following functions:

• two 16-bit counter/timers with pre-scale

• interrupt controller

• reset and pause controller

Each of these functions is selected by accessing the appropriate address space. In addition to P_SELCT, P_SELIC and P_SELRPC, which are the select lines for the functions above, there is also a P_SELEX line which can be used to select user implemented functions. If you wish to reprogram the FPGA for your own use then contact ARM for VHDL descriptions of this device.

FPGA configuration

The FPGA is configured at power-up by a serial PROM (U28). The configuration can be downloaded from a workstation using a special download cable connected to header (J2). This procedure is detailed in Chapter 9, Programming the APB FPGA.

Link field (LK16) is used to tell the FPGA whether it is to be programmed from the serial PROM or by download cable.

When the FPGA is successfully configured, the green LED marked “FPGA OK” lights up. If it does not light up, check that:

• the serial PROM (U28) and the links MODE0–2 are inserted

• the device has been configured by download cable

FPGA functionality

You can program the FPGA to have different functionality by replacing the serial PROM (U28) with an alternative device.

Position Name Description Options Default

1 INIT not used do not connect out

2 MODE0 Number of cycles out = cable, in = PROM in

3 MODE1 Selects EPROM or FLASH out = cable, in = PROM in

4 MODE2 Selects 8 or 16-bit device out = cable, in = PROM in

Table 3-12: LK16


Open Access



Note The FPGA has just four outputs: ARMnFIQ, ARMnIRQ, STANDBY and REMAP. If you choose to change the function of the FPGA you must ensure that these outputs have the following default values:

See Target Development System User Guide (ARM DUI 0061) for further details on the REMAP signal.

Output Description Default

ARMnFIQ connects to nFIQ on processor HIGH

ARMnIRQ connects to nIRQ on processor HIGH

STANDBY puts system into standby state LOW

REMAP selects normal or reset memory map AS REQUIRED

Table 3-13: FPGA outputs


Open Access



ARM DUI 0017C

3.2.14 APB Expansion Connecters

This schematic is shown in A.16 APB Expansion Connecters on page A-17.

This schematic shows six 20-way box headers (POD1-6) which can be used to expand or monitor the APB. POD6 is spare and can be used to connect external devices to signals on the board.

For expansion devices, there are four interrupt pins available:

• nINTAPB[2:0]

• nFIQSRC

These are all active low inputs to the interrupt controller, with on-board pull-up resistors.

Note The nFIQSRC pin is also connected to the ASB expansion connectors, so in order to share the signal line, you must make drivers open-collector. To select external devices P_SELEX is available.

If you are planning to build external expansion devices for the APB, refer to Chapter 5, Expanding and Monitoring the APB for further details.

3.2.15 APB Buffers

The APB buffers schematic is shown in A.17 APB Buffers on page A-18.

This schematic shows two 16-bit address buffers(U32 and U33) and two 16-bit data buffers (U30 and U31) that are used to connect the ASB to the APB. These devices are controlled by the APB and NISA bridge.

3.2.16 Memory Address and Data Buffers

This schematic is shown in A.18 Memory Address and Data Buffers on page A-19.

The schematic shows one 16-bit address latch (U34) and two 16-bit data buffers (U35 and U36) that are used to connect the ASB to the memory devices. These devices are controlled by the SRAM and DRAM ASB slaves.


Open Access



3.2.17 Test Interface Controller and Connectors

This schematic is shown in A.19 Test Interface Controller and Connecters on page A-20.

The test interface comprises:

• a controller (U37), which is an ASB bus master

• four bi-directional transceivers (U38–41)

• two 20-way box headers (TEST1 and TEST2), which form the external connection.

Enabling the test interface

To enable the test interface, you must insert the link (LK17) marked “USE TIC”. If this link is inserted, it is important to drive the test bus signals T_REQA, T_REQB and T_CLK. Otherwise, the test interface controller may become the default bus master and the ARM processor will not be able to gain control of the ASB.

In normal operation the test interface is not used and LK17 should be left out.

For full details of the test interface refer to the AMBA Specification (ARM IHI 001).

3.2.18 Master Header Connectors and Level Convertors

This schematic is shown in A.20 Master Header Connecters and Level Converters on page A-21.

Master header connectors

The ARM processor, mounted on a daughter card, is connected to the board using four 60-way connectors (PL6–9), as shown on this schematic. A number of the connector pins are not used, as these are reserved for future expansion.

Level convertors

Because the board functions at 5V and the processor is a 3.3V component, level convertors (U42–53) are provided to prevent high signal levels causing damage. These level convertors are constructed from “Quickswitch” buffers. These devices have very low propagation delay (less than 250ps) and appear as a 5 ohm resistor when switched on.

The output voltage for an input voltage equal to the supply is approximately 1V below the supply. A resistor/diode network is used to provide a supply of 4.3V, so that high input levels are clamped to 3.3V when driven out of the device.


LK17 USETIC enable the TIC out=disable, in=enable out

Table 3-14: LK17


Open Access



ARM DUI 0017C

3.2.19 System Modules (Arbiter and Decoder)

This schematic is shown in A.21 System Modules (Arbiter and Decoder) on page A-22. The schematic shows the two ASB system modules:

• the arbiter

• the decoder

Arbiter

The arbiter (U54) is responsible for deciding which bus master gains control of the ASB. In addition, this device also controls the system reset B_RES[2:0] lines.

Two surface mount links (LK14 and LK15) are provided to enable the expansion bus request lines (A_REQ001 and A_REQ002). In normal operation these lines are tied LOW through the links, but if you connect a bus master to the ASB, you need to enable one or other of these request lines by moving the appropriate link to the A-C position.

Pressing SW2 (the switch with a red cap) causes a full system reset.

Decoder

The decoder (U55) is responsible for driving the ASB select lines (D_SELxxx) and is vital to the correct operation of the board. This device can be reprogrammed to implement alternative memory maps if required.

The decoder functions in two distinct states:

• normal

• reset

On power-up, the board is by default in the reset configuration. In this state the EPROM or FLASH can be found at the bottom of the address map. If the remap register is written to, the REMAP signal goes HIGH and the decoder switches to the normal memory map where there is SRAM at the bottom.

If you are bringing up a system where there is no EPROM or FLASH, you may want to disable this feature. Link (LK18) is provided for this purpose. In the default position (in), the REMAP input to the decoder is driven by the REMAP and pause controller implemented in the APB FPGA. If this link is removed, the REMAP signal is always high, and the board starts up with SRAM at the bottom of the address map.


LK18 REMAP driven or always high out=high, in=driven in

Table 3-15: LK18


Open Access



3.2.20 ASB Expansion Connectors

The ASB expansion connectors schematic is shown in A.22 ASB Expansion Connecters on page A-23.

This schematic shows six 20-way box headers (POD7–12) which can be used to expand or monitor the ASB.

For expansion devices there are three interrupt pins available nINTASB[1:0] and nFIQSRC. These are all active LOW inputs to the interrupt controller, with on-board pull-up resistors. Note however that nFIQSRC is also connected to the APB expansion connectors, so in order to share the signal line make drivers open-collector. To select external devices two signals D_SELASB[1:0] are available. To enable these lines drive the signals nENASB[1:0] LOW.

If you are planning to build external expansion devices for the ASB, refer to Chapter 4, Expanding and Monitoring the ASB for further details.


Open Access



ARM DUI 0017C

3.3 ARM7TDMI Processor Daughter BoardThis schematic is shown in B.2 Top-level Diagram on page B-3.

This AMBA bus master daughter card comprises an ARM7TDMI test chip and a PLD that converts it into an AMBA master. It is connected to the main board through four 60-way connectors and provides headers to which a logic analyser may be connected. The JTAG interface on the test chip is brought out to a header to which an EmbeddedICE interface may be connected.

The top-level schematic shows the following blocks:

• processor (QPF or PGA)

• header card connectors

• AMBA bus master veneer

• logic analyser connectors

• EmbeddedICE interface connector

3.3.1 Processor in QFP package

This schematic is shown in B.6 Processor in QFP Package on page B-7.

This schematic shows the ARM7TDMI test chip in a QFP package. A number of inputs are tied to default values through resistors.

To learn more about the ARM7TDMI refer to the documents:

• ARM7TDMI Data Sheet (ARM DDI 0029) and

• ARM7TDMI Test Chip Appendix (ARM DXI 0022).

3.3.2 Processor in PGA package

This schematic is shown in B.7 Processor in PGA Package on page B-8.

This schematic shows the ARM7TDMI test chip in a PGA package. It is identical in all other respects to the QFP packaged device.

3.3.3 Header card connectors

This schematic is shown in B.3 Header Connecters on page B-4.

This schematic shows four 60-way connectors (SK1–4) which are used to attach the daughter card to the main board. A number of the connector pins are not used, these are reserved for future expansion.

Refer to section 3.2.18 Master Header Connectors and Level Convertors to see which ASB signals the processor is connected to.


Open Access



3.3.4 AMBA bus master veneer

This schematic is shown in B.5 AMBA Bus Master Veneer on page B-6.

In order to turn an ARM processor (such as the ARM7TDMI test chip) into an AMBA bus master an AMBA veneer is required. This function is performed by the MACH215 device (U2). Because this is a 5V part it is necessary to level shift the outputs so that output high voltages do not damage the processor. The two level convertors (U3 and U4) are constructed from “Quickswitch” buffers. These devices have very low propagation delay (less than 250ps) and appear as a 5 ohm resistor when switched on. The output voltage for an input voltage equal to the supply is approximately 1V below the supply. A resistor/diode network (R32 and D1) is used to provide a supply of 4.3V, so that high input levels are clamped to 3.3V when driven out of the device.

There are four surface mount links (LK1–4) which operate as follows. BMEN0 (LK1) and BMEN1 (LK2) are configuration inputs to the processor and AMBA veneer device. These links should always be connected A–C as their functionality is reserved for future use.

OLDTC (LK3) allows older revisions of the ARM7TDMI test chip to be used in this system. Before revision 1 of the ARM7TDMI test chip some of the AMBA signals were not available. This link configures the AMBA veneer to provide these functions on behalf of the processor. By default this link is in the B–C position as all production headers will be fitted with revision 1 or higher ARM7TDMI devices.

The GRANT SELECT link (LK4) is used to configure the way in which the processor is granted and enabled onto ASB. By default this link is in position A–C and should not be moved.

3.3.5 Logic analyser connectors

This schematic is shown in B.4 Logic Analyser Connecters on page B-5.

Six 20-way box headers (POD1–6) are provided to allow connection of Hewlett Packard 20 pin (HP 01650-63203) pods suitable for use with HP1650B-series logic analysers. These connectors can also be used for expansion purposes. Using a logic analyser it is possible to observe the processor cycles and if required disassemble ARM instruction mnemonics to trace program execution. This procedure and the POD pin assignments are covered in detail in Chapter 7, The Logic Analyser Interface.

3.3.6 EmbeddedICE interface

This schematic is shown in B.8 EmbeddedICE Interface on page B-9.

This schematic shows the EmbeddedICE JTAG connector (PL1). It is a 14-way box header, compatible with the ARM EmbeddedICE interface. To connect this device to an EmbeddedICE unit you will need a short 14-way IDC cable which is supplied with that interface.

For further information on the EmbeddedICE interface refer to Chapter 6, The EmbeddedICE Interface.


Open Access


This chapter describes how to expand and monitor the ASB.

4.1 Expanding the ASB 4-2

4.2 Building an ASB Master Expansion Board 4-64.3 Building an ASB Slave Expansion Board 4-74.4 ASB Timing on the ARM Development Board 4-8

Expanding and Monitoringthe ASB4


Open Access

Expanding and Monitoring the ASB


ARM DUI 0017C

4.1 Expanding the ASBNote Please refer to the AMBA Specification (ARM IHI 0001) for a detailed description of the

signals mentioned in this section.

4.1.1 Headers and pinout

The ASB expansion interface comprises six 20-way box headers, horizontally mounted along the top edge of the development card. The headers are numbered POD7 to POD12.

Each header has a pinout that is compatible with Hewlett Packard HP1650B series logic analyser pods (HP01650-63203). Unconnected pins are labeled NC. These pins can be used to connect other signals to the header if required.

Note If the logic analyser pods described are used, they supply +5V on pin 1, so this should not be connected to any output on the board. The logic analyser pods have signal inputs on pins 4–19 and a trigger input on pin 3.

The pods are assigned as follows:

POD7: low ASB data bus B_D[15:0] trigger B_CLKPOD8: high ASB data bus B_D[31:16] no trigger inputPOD9: low ASB address bus B_A[15:0] trigger nB_CLKPOD10: high ASB address bus B_A[31:16] no trigger input

POD11: ASB control signals no trigger inputPOD12: ASB control signals no trigger input

Figure 4-1: Pods 7 and 8

POD7 POD8

NC 1 2 VCC NC 1 2 VCC

B_CLK 3 4 B_D[15] NC 3 4 B_D[31]

B_D[14] 5 6 B_D[13] B_D[30] 5 6 B_D[29]

B_D[12] 7 8 B_D[11] B_D[28] 7 8 B_D[27]

B_D[10] 9 10 B_D[9] B_D[26] 9 10 B_D[25]

B_D[8] 11 12 B_D[7] B_D[24] 11 12 B_D[23]

B_D[6] 13 14 B_D[5] B_D[22] 13 14 B_D[21]

B_D[4] 15 16 B_D[3] B_D[20] 15 16 B_D[19]

B_D[2] 17 18 B_D[1] B_D[18] 17 18 B_D[17]

B_D[0] 19 20 GND B_D[16] 19 20 GND


Open Access





POD9 POD10


nB_CLK 3 4 B_A[15] NC 3 4 B_A[31]

B_A[14] 5 6 B_A[13] B_A[30] 5 6 B_A[29]

B_A[12] 7 8 B_A[11] B_A[28] 7 8 B_A[27]

B_A[10] 9 10 B_A[9] B_A[26] 9 10 B_A[25]

B_A[8] 11 12 B_A[7] B_A[24] 11 12 B_A[23]

B_A[6] 13 14 B_A[5] B_A[22] 13 14 B_A[21]

B_A[4] 15 16 B_A[3] B_A[20] 15 16 B_A[19]

B_A[2] 17 18 B_A[1] B_A[18] 17 18 B_A[17]

B_A[0] 19 20 GND B_A[16] 19 20 GND

POD11 POD12


NC 3 4 D_SELASB[1] NC 3 4 NC

D_SELASB[0] 5 6 B_ERROR D_SELSRAM 5 6 D_SELSSRAM

B_LAST 7 8 B_WAIT D_SELROM 7 8 D_SELDRAM

B_LOCK 9 10 B_RES[2] D_SELNISA 9 10 D_SELAPB

B_RES[1] 11 12 B_RES[0] nFIQSRC 11 12 nENASB[1]

B_PROT[1] 13 14 B_PROT[0] nENASB[0] 13 14 nINTASB[1]

B_TRAN[1] 15 16 B_TRAN[0] nINTASB[0] 15 16 A_GNT002

B_SIZE[1] 17 18 B_SIZE[0] A_GNT001 17 18 A_REQ002

B_WRITE 19 20 GND A_REQ001 19 20 GND


Open Access



ARM DUI 0017C

4.1.2 List of signals

The following list describes each signal.

Signal Description

B_CLK AMBA system clock

nB_CLK AMBA system clock inverted

B_RES[2:0] AMBA reset signals

B_D[31:0] ASB data bus

B_A[31:0] ASB address bus

B_WAIT ASB wait response

B_LAST ASB last response

B_ERROR ASB error response

B_LOCK ASB locked transfers

B_PROT[1:0] ASB protection control

B_TRAN[1:0] ASB transfer type

B_SIZE[1:0] ASB transfer size

B_WRITE ASB transfer direction

D_SELASB[1:0] ASB expansion select signals

D_SELSSRAM ASB select SSRAM controller

D_SELSRAM ASB select SRAM controller

D_SELDRAM ASB select DRAM controller

D_SELROM ASB select EPROM/FLASH controller

D_SELAPB ASB select APB bridge

D_SELNISA ASB select NISA bridge

nINTASB[1:0] interrupt sources, active low, level sensitive

nFIQSRC fast interrupt source, active low, level sensitive

Table 4-1: ASB signals


Open Access



nENASB[1:0] enable ASB expansion slaves

A_REQ001 ASB expansion request signal 1

A_REQ002 ASB expansion request signal 2

A_GNT001 ASB expansion grant signal 1

A_GNT002 ASB expansion grant signal 2

Signal Description

Table 4-1: ASB signals (Continued)


Open Access



ARM DUI 0017C

4.2 Building an ASB Master Expansion BoardTo build an ASB master that connects to the motherboard, you need some or all of the signals listed in Table 4-1: ASB signals. The following are particularly important

A_REQ001 request to system arbiter for bus ownership

A_REQ002 request to system arbiter for bus ownership

A_GNT001 grant from system arbiter of bus ownership

A_GNT002 grant from system arbiter of bus ownership

4.2.1 Surface mount links

By default, A_REQ001 and A_REQ002 are tied LOW on the motherboard through surface mount links. When implementing expansion bus masters, the surface mount links must be moved to connect the arbiter request lines to the expansion header. Refer to section 3.2.19 System Modules (Arbiter and Decoder) on page 3-24 for more information on this.

4.2.2 Interrupts

A master can issue interrupts to the system CPU through the following:

nINTASB[1:0] interrupt sources

nFIQSRC fast interrupt source

Note An expansion master cannot receive interrupts from other devices in the system.


Open Access



4.3 Building an ASB Slave Expansion BoardTo build an ASB peripheral or slave that connects to the motherboard, you need some of the following signals.

B_CLK or nB_CLK if other clock edge is required

B_RES[2:0] only B_RES[1] is usually required

B_D a number of data bits

B_A a number of address bits

B_WRITE transfer direction

B_SIZE[1:0] transfer size

D_SELASB[1:0] select signal reserved for expansion slaves

4.3.1 Slaves

Normally the system decoder asserts B_WAIT, B_ERROR and B_LAST on behalf of the absent slaves. If the slave needs to drive these signals:

nENASB[1:0] must be driven or tied LOW

In this case, the slave must drive the following signals or the system cannot function correctly:

B_WAIT waits for the master

B_ERROR signals a slave error

B_LAST signals the last transfer in a burst

If the slave generates interrupts:

nINTASB[1:0] one or more of these IRQ sources

nFIQSRC possibly the FIQ source


Open Access



ARM DUI 0017C

4.4 ASB Timing on the ARM Development BoardThe AMBA specification does not specify bus timing, as this depends upon the technology used. For expansion on the ARM Development Board, it is important to have some timing guidelines. To assist with this, the following timings have been defined:

Figure 4-4: ASB timings on the ARM Development Board

Ttr

Taca

Tacw

Tacs

Tacp

Tsel

Tsrw

Tsrl

Tsre

Tdata

0ns 25ns 50ns 75ns 100ns 125ns 150ns

B_CLK

B_TRAN[1:0]

B_A[31:0]

B_WRITE

B_SIZE[1:0]

B_PROT[1:0]

D_SEL

B_WAIT

B_LAST

B_ERROR

B_D[31:0]


Open Access



Parameter Description Min Typ Max

Ttr B_TRAN setup to B_CLK falling 13.5

Taca B_A setup to B_CLK falling 5

Tacw B_WRITE setup to B_CLK falling 5

Tacs B_SIZE setup to B_CLK falling 5

Tacp B_PROT setup to B_CLK falling 5

Tsrw B_WAIT setup to B_CLK rising 8

Tsrl B_LAST setup to B_CLK rising 8

Tsre B_ERROR setup to B_CLK rising 8

Tdata B_D setup to B_CLK falling 5

Table 4-2: Sample timings


Open Access


The ARM Development Board implements an APB with full 32-bit address and data buses. In a typical system, these buses may well be narrower; the APB slaves only use 16 data lines and nine address lines. Full 32-bit support is provided for flexibility when expanding the APB.

This chapter describes how to expand and monitor the APB.

5.1 APB Expansion Interface 5-25.2 Building an APB Slave Expansion Board 5-55.3 APB Timing on the ARM Development Board 5-6

Expanding and Monitoringthe APB5


Open Access

Expanding and Monitoring the APB


ARM DUI 0017C

5.1 APB Expansion Interface Note Please refer to the AMBA Specification (ARM IHI 0001) for a detailed description of

the signals mentioned in this section.


The APB expansion interface comprises six 20-way box headers horizontally mounted along the bottom edge of the development card. The headers are numbered POD1 to POD6.

Each header has a pinout that is compatible with Hewlett Packard HP1650B series logic analyser pods (HP01650-63203). Unconnected pins are labelled NC. These pins can be used to connect other signals to the header if required.

Note If the logic analyser pods described are used, they supply +5V on pin 1, so this should not be connected to any output on the board. The logic analyser pods have signal inputs on pins 4–19 and a trigger input on pin 3.


POD1: low APB data bus P_D[15:0] trigger B_CLKPOD2: high APB data bus P_D[31:16] no trigger input POD3: low APB address bus P_A[15:0] trigger nB_CLKPOD4: high APB address bus P_A[31:16] no trigger input

POD5: APB control signals trigger P_STBPOD6: unassigned, for future expansion


POD1 POD2


B_CLK 3 4 P_D[15] NC 3 4 P_D[31]

P_D[14] 5 6 P_D[13] P_D[30] 5 6 P_D[29]

P_D[12] 7 8 P_D[11] P_D[28] 7 8 P_D[27]

P_D[10] 9 10 P_D[9] P_D[26] 9 10 P_D[25]

P_D[8] 11 12 P_D[7] P_D[24] 11 12 P_D[23]

P_D[6] 13 14 P_D[5] P_D[22] 13 14 P_D[21]

P_D[4] 15 16 P_D[3] P_D[20] 15 16 P_D[19]

P_D[2] 17 18 P_D[1] P_D[18] 17 18 P_D[17]

P_D[0] 19 20 GND P_D[16] 19 20 GND


Open Access





POD3 POD4


nB_CLK 3 4 P_A[15] NC 3 4 P_A[31]

P_A[14] 5 6 P_A[13] P_A[30] 5 6 P_A[29]

P_A[12] 7 8 P_A[11] P_A[28] 7 8 P_A[27]

P_A[10] 9 10 P_A[9] P_A[26] 9 10 P_A[25]

P_A[8] 11 12 P_A[7] P_A[24] 11 12 P_A[23]

P_A[6] 13 14 P_A[5] P_A[22] 13 14 P_A[21]

P_A[4] 15 16 P_A[3] P_A[20] 15 16 P_A[19]

P_A[2] 17 18 P_A[1] P_A[18] 17 18 P_A[17]

P_A[0] 19 20 GND P_A[16] 19 20 GND

POD5 POD6


P_STB 3 4 NC NC 3 4 NC

NC 5 6 NC NC 5 6 NC

NC 7 8 nINTAPB[2] NC 7 8 NC

nINTAPB[1] 9 10 nINTAPB[0] NC 9 10 NC

B_RES[1] 11 12 B_RES[2] NC 11 12 NC

nFIQSRC 13 14 B_RES[0] NC 13 14 NC

P_SELIC 15 16 P_SELRC NC 15 16 NC

P_SELCT 17 18 P_SELEX NC 17 18 NC

P_WRITE 19 20 GND NC 19 20 GND


Open Access



ARM DUI 0017C



Signal Description

B_CLK AMBA system clock

nB_CLK AMBA system clock inverted

B_RES[2:0] AMBA reset signals

P_D[31:0] APB data bus

P_A[31:0] APB address bus

P_STB APB strobe

nINTAPB[2:0] interrupt sources, active low, level sensitive

nFIQSRC fast interrupt source, active low, level sensitive

P_SELIC APB select signal for interrupt controller

P_SELRC APB select signal for reset/pause controller

P_SELCT APB select signal for counter/timers

P_SELEX APB select signal for expansion device

P_WRITE APB read/write signal

Table 5-1: APB signals


Open Access



5.2 Building an APB Slave Expansion BoardTo build an APB peripheral or slave that connects to the motherboard, you need the following signals:

P_D a number of data bits

P_A a number of address bits

P_STB strobe signal

P_WRITE read/write signal

P_SELEX select signal reserved for expansion devices

5.2.1 System clock and reset

If the application requires a system clock and reset:

B_RES[2:0] only B_RES[2] is usually required

B_CLK or nB_CLK if other clock edge is required

5.2.2 Interrupts

If the slave generates interrupts:

nINTAPB[2:0] one or more of these IRQ sources

nFIQSRC possibly the FIQ source


Open Access



ARM DUI 0017C

5.3 APB Timing on the ARM Development BoardThe AMBA specification does not specify bus timing, as this depends upon the technology used. For expansion on the ARM Development Board it is important to have some timing guidelines. To assist with this, the following timings have been defined:

Figure 5-4: APB timings on the ARM Development Board

This shows a read and write cycle, separated by an idle cycle. If multiple reads or writes occur, they are not separated by an idle cycle, and this gives the minimum Tpd of 40ns at 25MHz.

5.3.1 P_STB signal

Figure 5-4: APB timings on the ARM Development Board shows that the P_STB signal lasts for two B_CLK cycles. This is because the APB slaves are implemented in a Xilinx FPGA, which is a relatively slow device.

If the system clock frequency is set at 20MHz or below, P_STB need only last for one B_CLK cycle. By inserting a link the APB bridge is instructed to shorten the P_STB HIGH pulse to one B_CLK cycle. Refer to section 3.2.8 APB and NISA Bridge on page 3-14 for details.

To implement slower APB slaves, it is necessary to reprogram the APB bridge MACH chip so that additional wait states are inserted. Refer to Chapter 10, Programming the MACH and PAL Devices for further details of this procedure.

READ CYCLE IDLE WRITE CYCLE

TpeTpe TpdTpd

Tpss Tpsh

Tpas Tpah

Tpws Tpwh

Tpdr Tpdz Tpds Tpdh

Tpc Tpc

0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns

B_CLK

P_STB

P_SEL

P_A

P_WRITE

P_D


Open Access



Parameter Description Min Typ Max

Tpe P_STB high pulse width (enabled time @ 25MHz) 80

Tpd P_STB low pulse width (disabled time @ 25MHz) 40

Tpss P_SEL setup to P_STB rising 21

Tpas P_A setup to P_STB rising 21

Tpws P_WRITE setup to P_STB rising 21

Tpsh P_SEL hold from P_STB falling 19

Tpah P_A hold from P_STB falling 19

Tpwh P_WRITE hold from P_STB falling 19

Tpds P_D setup to P_STB rising (write) 19

Tpdh P_D hold from P_STB falling (write) 41

Tpdr P_D setup to P_STB falling (read) 54

Tpdz P_D hold from P_STB falling (read) 26

Tpc B_CLK falling to P_STB falling 6.5

Table 5-2: Sample timings


Open Access


This chapter describes how the EmbeddedICE interface connects to the ARM Development Board.

6.1 EmbeddedICE Interface 6-2

The EmbeddedICE Interface6


Open Access

The EmbeddedICE Interface


ARM DUI 0017C

6.1 EmbeddedICE InterfaceA debuggable ARM processor (such as ARM7TDMI) on the ARM Development Board can be controlled through its JTAG port using the EmbeddedICE interface.

The EmbeddedICE interface is packaged separately from the ARM Development Board. The host computer requires the ARM Software Development Toolkit to communicate with the EmbeddedICE interface: the ARM Software Development Toolkit Reference Manual (ARM DUI 0020) explains how to use the tools with the EmbeddedICE interface.

This chapter describes the physical connection between the EmbeddedICE interface and the ARM Development Board. For details on how to connect the system components together refer to the Target Development System User Guide (ARM DUI 0061).

If you have the Angel Debug Monitor resident in the on-board FLASH then you do not need to use the EmbeddedICE interface.

6.1.1 EmbeddedICE interface connector

The interface connector PL1 (shown below), is mounted on the header card. It is a 14-way box header as shown in Figure 6-1: EmbeddedICE interface connector PL1 (viewed from above) below.

This plug is connected to the EmbeddedICE interface module using a short 14-way IDC cable with IDC sockets at each end.

Note The signals on this interface are at 3.3V, so care should be taken if the JTAG port is connected to any 5V system.

Figure 6-1: EmbeddedICE interface connector PL1 (viewed from above)

The connector pins are shown in Table 6-1: EmbeddedICE interface connector pins.

● 2 ● 4 ● 6 ● 8 ● 10 ● 12 ● 14

● 1 ● 3 ● 5 ● 7 ● 9 ● 11 ● 13

PL1

VSS VSSnICERSTVSSVSSVSSVSS

SPU SPUTDOTCKTMSTDInTRST


Open Access

The EmbeddedICE Interface


Pin descriptions

The functions of the connector pins are summarised in the following table:

Pin Name Function

1 SPU System powered up, pin connected to Vdd through a 33R resistor

3 nTRST Test reset, active low

5 TDI Test data in

7 TMS Test mode select

9 TCK Test clock

11 TDO Test data out

12 nRSTOUT unused

13 SPU As pin 1

2, 4, 6, 8, 10, 14 VSS System ground

Table 6-1: EmbeddedICE interface connector pins


Open Access


This chapter describes the features of the ARM Development Card that facilitate code development and debugging.

In most cases, you can download code and debug it using the ARM toolkit, in combination with either a debug monitor resident on the board or an EmbeddedICE interface. However, you sometimes need to use a logic analyser so you can debug code in real time.

7.1 ARM HP Inverse Assembler 7-2

The Logic Analyser Interface7


Open Access

The Logic Analyser Interface


ARM DUI 0017C

7.1 ARM HP Inverse AssemblerARM have developed an inverse assembler for use with HP logic analyzers to enable disassembly of the code. A set of six 2-way box headers are provided on the ARM Development Board for this purpose (POD 7-12). A further set is mounted on the ARM TDMI Daughter Board. See the ARM HP Inverse Assembler User Guide (ARM DUI 0062) for more information on the inverse assembler.

7.1.1 Connector and pinout

To enable you to observe processor cycles and signals on the ASP or APB buses, a further six 20-way box headers are mounted along two sides of the AMBA master daughter card. The headers are numbered POD1 to POD6 and they connect directly to the ARM processor. Each header has a pinout that is compatible with Hewlett Packard HP1650B series logic analyser pods (HP01650-63203).


POD1: low data bus D[15:0] no trigger input POD2: high data bus D[31:16] no trigger input POD3: low address bus A[15:0] no trigger input

POD4: high address bus A[31:16] no trigger input POD5: bus control signals trigger MCLK POD6: bus control signals trigger ECLK


POD1 POD2

NC 1 2 VDD NC 1 2 VDD

NC 3 4 D[15] NC 3 4 D[31]

D[14] 5 6 D[13] D[30] 5 6 D[29]

D[12] 7 8 D[11] D[28] 7 8 D[27]

D[10] 9 10 D[9] D[26] 9 10 D[25]

D[8] 11 12 D[7] D[24] 11 12 D[23]

D[6] 13 14 D[5] D[22] 13 14 D[21]

D[4] 15 16 D[3] D[20] 15 16 D[19]

D[2] 17 18 D[1] D[18] 17 18 D[17]

D[0] 19 20 VSS D[16] 19 20 VSS


Open Access





POD3 POD4


NC 3 4 P_A[15] NC 3 4 A[31]

A[14] 5 6 P_A[13] A[30] 5 6 A[29]

A[12] 7 8 P_A[11] A[28] 7 8 A[27]

A[10] 9 10 P_A[9] A[26] 9 10 A[25]

A[8] 11 12 P_A[7] A[24] 11 12 A[23]

A[6] 13 14 P_A[5] A[22] 13 14 A[21]

A[4] 15 16 P_A[3] A[20] 15 16 A[19]

A[2] 17 18 P_A[1] A[18] 17 18 A[17]

A[0] 19 20 VSS A[16] 19 20 VSS

POD5 POD6


MCLK 3 4 nEXEC ECLK 3 4 NC

PIPEF 5 6 nM[1] NC 5 6 NC

nM[0] 7 8 nOPC NC 7 8 NC

MAS[1] 9 10 MAS[0] nM[4] 9 10 nM[3]

nRW 11 12 SEQ nM[2] 11 12 DBGACK

nMREQ 13 14 ABORT nTRANS 13 14 LOCK

nIRQ 15 16 nFIQ TRAN[1] 15 16 TRAN[0]

nRESET 17 18 PWAIT CPA 17 18 CPB

TBIT 19 20 VSS nCPI 19 20 VSS


Open Access



ARM DUI 0017C



Signal Description

D[31:0] data bus

A[31:0] APB address bus

MCLK system clock (equivalent to B_CLK)

PIPEF pipeline full

nM[4:0] processor mode

MAS[1:0] transfer size (equivalent to B_SIZE[1:0])

nRW read/write (equivalent to B_WRITE)

nMREQ memory request

nFIQ fast interrupt request

nIRQ interrupt request

nRESET processor reset (equivalent to B_RES[1])

TBIT Thumb bit

nEXEC instruction not executed

nOPC opcode fetch

SEQ sequential address

ABORT memory abort

PWAIT processor wait

ECLK external clock output

nTRANS processor user mode

TRAN[1:0] processor BC[1:0] (equivalent to B_TRAN[1:0])

CPA co-processor absent

CPB co-processor busy

nCPI co-processor instruction

VDD +3.3V

VSS system ground

Table 7-1: Logic analyser pod signals


Open Access


This chapter describes how to use the test interface.

8.1 Introducing the Test Interface 8-2

8.2 Connecting External Equipment to the Test Bus 8-38.3 Test Interface Interconnections 8-4

The Test Interface8


Open Access

The Test Interface


ARM DUI 0017C

8.1 Introducing the Test InterfaceThe test interface comprises:

• a controller

• a number of bidirectional latched transceivers that control flow between the test bus and ASB

The test interface is the default ASB master. This means that if no other master is requesting the bus, the arbiter grants access to the test interface controller (TIC).

Using the test bus interface, you can gain control of the ASB in real time and perform manufacturing test and in-circuit diagnostics. On a circuit board this is not usually a problem, but the ARM Development Board is a board-level implementation of a typical ASIC, where it would not be possible to examine the internal connections.

Note Refer to the AMBA Specification (ARM IHI 0001) for details of the test port provided.

8.1.1 External signals

The following external signals are defined:

T_CLK test clock input

T_REQA test bus request A inputT_REQB test bus request B inputT_ACK test acknowledge output

T_D[31:0] test bus bi-directionalB_D[31:0] ASB data bus bi-directionalB_A[31:0] ASB address bus bi-directional


Open Access

The Test Interface


8.2 Connecting External Equipment to the Test BusTo drive the test interface on the ARM Development Board some external equipment is required. This is typically a parallel I/O device offering 36 separate input/output lines.


The equipment is connected to the board via two 20-way box headers mounted on the right edge of the development card. These are called:

• TEST1

• TEST2

The connector pins are assigned as follows:

Figure 8-1: Connector pin assignments

8.2.2 Test vectors

ARM has code that runs on a host computer and drives an I/O board. This code requires a test vector file as input. The test vector file is written to provide stimulus and check data that is read back from the test bus.

The program has been written to be hardware-independent, so you only have to write a few functions to interface to your chosen system.

If you need to use the test interface and would like to take advantage of this code then please contact ARM for assistance.

TEST1 TEST2

T_CLK 1 2 VCC T_REQA 1 2 VCC

T_ACK 3 4 T_D[15] T_REQB 3 4 T_D[31]

T_D[14] 5 6 T_D[13] T_D[30] 5 6 T_D[29]

T_D[12] 7 8 T_D[11] T_D[28] 7 8 T_D[27]

T_D[10] 9 10 T_D[9] T_D[26] 9 10 T_D[25]

T_D[8] 11 12 T_D[7] T_D[24] 11 12 T_D[23]

T_D[6] 13 14 T_D[5] T_D[22] 13 14 T_D[21]

T_D[4] 15 16 T_D[3] T_D[20] 15 16 T_D[19]

T_D[2] 17 18 T_D[1] T_D[18] 17 18 T_D[17]

T_D[0] 19 20 GND T_D[16] 19 20 GND


Open Access

The Test Interface


ARM DUI 0017C

8.3 Test Interface InterconnectionsThe following diagram explains the interconnections:

Figure 8-2: Test interface interconnections

TIC

T_CLKT_REQAT_REQB ASB control

T_ACK

B_A[15:0]

B_D[15:0]

B_A[31:0]

B_D[31:0]

T_D[15:0]

T_D[31:16]


Open Access


This chapter describes how to program the field programmable gate array (FPGA) on the ARM Development Board.

9.1 Introduction 9-29.2 Interrupt Controller 9-3

9.3 Using the APB FPGA in Your Own Designs 9-4

Programming the APB FPGA9


Open Access

Programming the APB FPGA


ARM DUI 0017C

9.1 IntroductionThe ARM Development Board has one Xilinx 4000 series field programmable gate array (FPGA).

The FPGA is an array of configurable logic blocks (CLBs) and in/out blocks (IOBs). The interconnection between CLBs and IOBs, and their function is configured by programming SRAM cells.

Programming typically occurs on power-up and takes a few milliseconds. On power-up, the FPGA reads its mode pins (MODE[2:0]). These determine how the internal SRAM is to be programmed.

9.1.1 APB slaves and standard peripherals

The FPGA is used to implement a number of APB slaves. These are as follows:

• interrupt controller (11 IRQ sources and one FIQ source)

• two 16-bit counter/timers with 8 bit prescalers

• reset and pause (standby) controller

This is a set of standard peripherals common to most AMBA systems. These peripherals are mapped into the APB memory area, which is any address between 0x0A000000 and 0x0BFFFFFF.

Further information about these peripherals can be found in the Reference Peripherals Specification (ARM DDI 0062).

The base addresses shown in Table 9-1: Base addresses have been implemented on the board:

For a full system memory map, please refer to the Target Development System User Guide (ARM DUI 0061).

Address Name

0x0A000000 Interrupt Controller base (ICBase)

0x0A800000 Counter Timer base (CTBase)

0x0B000000 Reset and Pause Controller base (RPCBase)

0x0B800000 Expansion (spare for user functions)

Table 9-1: Base addresses


Open Access



9.2 Interrupt ControllerThe interrupt controller differs from the standard design in that it has an extra register which allows the source of the FIQ interrupt to be selected as any of the 15 IRQ sources (1–15) or an external FIQ source pin.

9.2.1 Selecting the FIQ source

To select the FIQ source, write to the following 4-bit register:

ICBase + 0x114 r/w FIQ_source_register

Program this register with any value from 0x0 to 0xF.

Source 0 is the external FIQ source which is an active low, level-sensitive input on the ASB and APB expansion connectors. This input is pulled up on the ARM Development Board.

9.2.2 Bit allocation

The table on the right shows the bit assignment in the IRQ interrupt controller:

Bit Interrupt Source

0 Unused

1 Soft interrupt

2 COMMRX from processor

3 COMMTX from processor

4 Timer 1 (internal)

5 Timer 2 (internal)

6 PC card slot A

7 PC card slot B

8 Serial port A

9 Serial port B

10 Parallel port

11 ASB expansion 0

12 ASB expansion 1

13 APB expansion 0

14 APB expansion 1

15 APB expansion 2


Open Access



ARM DUI 0017C

9.3 Using the APB FPGA in Your Own DesignsWith care, the APB FPGA can be used to implement additional logic. This section describes how to reprogram the device. Note that this is not a trivial task. You should adopt a VHDL design methodology and use the default configuration as a starting point.

VHDL for the default configuration is available; details can be found in Appendix C, Summary of Programmable Devices.

9.3.1 Configuring the FPGA

The mode pins of the FPGA can be individually set HIGH or LOW by inserting jumpers onto the MODE pins of link field (LK16). In the default configuration these pins are linked, pulling MODE[2:0] LOW and configuring the FPGA for serial master mode. In this mode, the FPGA reads its configuration from a serial PROM.

The serial PROM is an 8-pin DIL packaged device that can be programmed using a standard device programmer. The appropriate data file is generated using Xilinx proprietary tools.

MODE[2:0] Name Comment

000 master serial Default, use serial PROM

001 master parallel up not available on this board

010 reserved not available on this board

011 master parallel down not available on this board


101 peripheral not available on this board


111 slave serial Use download cable

Table 9-2: Configuring the FPGA


Open Access



9.3.2 Connecting the XChecker Cable

If the MODE[2:0] pins are not linked, the FPGA is in master-slave mode. In this mode the FPGA expects to be configured using the XChecker download cable.

The XChecker cable must be connected to the special 9-pin header provided on the ARM Development Board. The individual wires of the XChecker cable are labelled to aid the connection.

The pins are shown in Figure 9-1: Download cable pin connections:

Figure 9-1: Download cable pin connections

Preparing a Bit File

To configure an FPGA using the XChecker cable, a configuration bit file is required. This is generated by the Xilinx XACT place and route tools using the makebits program. This program can be run on any appropriate logic cell array (*.lca) file.

After you place and route the Xilinx tools, write a file with a *.lca extension. To generate a bit file type:

makebits -t filename.lca

where:

-t ties down unused interconnect internally

This generates a file called filename.bit.

1 VCC (+5V)

2 GND

X this pin is cut

4 CCLK

5 D/P

6 DIN

7 PROG

8 INIT

9 RST


Open Access



ARM DUI 0017C

9.3.3 Downloading a Configuration

To download a configuration:

1 Connect the XChecker download cable to a serial port on the host computer.

2 Connect the other end to the ARM Development Board (see 9.3.2 Connecting the XChecker Cable on page 9-5).

3 Send the bit file to the FPGA using the XChecker download cable by typing the following command on the host machine:

xchecker filename.bit

4 Follow the on screen prompts. If the program returns an error, check the power supply to the board and the integrity of the connectors.

When the download is successful the xchecker program reports:

DONE signal went high

and the LED marked “FPGA OK” lights up because it is connected to the FPGA DONE signal.

9.3.4 Configuration Using a Serial PROM

When a design has been tested—usually using the download cable—the configuration can be programmed into a PROM. A PROM inserted into the board initializes the FPGA on power-up.

To generate a PROM data file suitable for programming a device, use the Xilinx makeprom program. This is a graphical tool that allows PROM files to be generated in a variety of formats.

1 Select the format (for example, MCS) and PROM size required.

2 Using the menus, load the bit file from address 0 upwards. This can then be saved to disk.

3 Using a device programmer, load the PROM data file into memory. The serial PROMs required are Xilinx parts XC17128D–PD8C. These are 5V devices in an 8-pin DIL package.

Note This part has a programmable reset polarity bit. Various device programmers handle programming of this bit in different ways. Some manual intervention is required to ensure that the device has active low reset polarity. When these bits have been written to, the device can be programmed.

4 Program the PROM and insert it into the 8-pin DIL socket (U24) provided.

5 Ensure that the MODE[2:0] pins are connected using jumper sockets.

6 Power the board and observe the LED marked “FPGA OK”. If this LED does not light up, power down the board and recheck.


Open Access


This chapter briefly describes the methods for programming the MACH and PAL devices.

10.1 Reprogramming a Device 10-2

Programming the MACHand PAL Devices10


Open Access

Programming the MACH and PAL Devices


ARM DUI 0017C

10.1 Reprogramming a DeviceMuch of the programmable logic on the ARM Development Board is implemented in AMD MACH and PALCE type devices. These devices are based on electrically erasable (EE) technology so they can be reprogrammed to add or change functionality if required. This should only be attempted if you have a full and detailed understanding of the design.

There are many and varied reasons why you might want to make modifications. For example:

• One reason why you might want to do this is to change the address map. In this case, you program the decoder.

• Alternatively, you might want to change the priority of bus masters, in which case you alter the arbiter.

• If you want to fit slower SRAM, you need to modify the SRAM controller to prevent unsuitable switch positions crashing the system.

ARM can assist with making such modifications. See Appendix C, Summary of Programmable Devices for information on all the PLD filenames and how to obtain them from ARM.

10.1.1 Design files

Reprogramming a MACH or PALCE device on the ARM Development Board requires a design file. This design file comprises a list of logic equations in a hardware description language (HDL). Various tools are available for this, such as:

ABEL from Data I/O

PLDesigner from Minc

PALASM from AMD

All the designs for the ARM Development Board were completed using PALASM which is a low-cost proprietary tool from the device vendor AMD.

If you use a different PLD design tool then it should not be too difficult to modify the PALASM description to suit your front end. No special constructs have been used, so the process should be straightforward.

10.1.2 Preparing a .JED File and Programming a Device

A tool such as PALASM turns a design written in an HDL into a fuse map. This fuse map is described in a JEDEC standard file format. The file, usually called filename.jed, can be downloaded into the target device using a logic programmer.


Open Access

A-1ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

The board design comprises 22 schematics as listed below.

A.1 Card Outline Drawing A-2A.2 Top-level Diagram A-3A.3 Power Supply A-4A.4 Crystal Oscillator and Clock Distribution A-5A.5 ASB Slaves A-6A.6 “On-chip” Memory (Synchronous SRAM) A-7A.7 EPROM/FLASH ASB Slave A-8A.8 DRAM ASB Slave A-9A.9 SRAM ASB Slave A-10A.10 APB and NISA Bridge A-11A.11 NISA Bus Peripherals A-12A.12 Serial and Parallel Ports A-13A.13 PC Card Interface A-14A.14 PC Card Connecters and Power Supply A-15A.15 APB Slaves A-16A.16 APB Expansion Connecters A-17A.17 APB Buffers A-18A.18 Memory Address and Data Buffers A-19A.19 Test Interface Controller and Connecters A-20A.20 Master Header Connecters and Level Converters A-21A.21 System Modules (Arbiter and Decoder) A-22A.22 ASB Expansion Connecters A-23

Board SchematicsA

hrg.

book

Pag

e 1

Wed

nesd

ay, J

uly

22, 1

998

9:1

8 A

M

Open Access

A-2 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

Board SchematicsA.1 Card Outline Drawing

Date: March 8, 1996 Sheet

Size Document Number

B EOI-0011B (DRAWING.

Title

Card Outline Drawi

CB1 4JNCAMBRIDGECHERRY HINTONFULBOURN ROAD

(C) ADVANCED RISC MAC

TEST PORT

POD9 POD10 POD11 POD12

SRAM

SRAMS2

ASB EXPANSION

U17

U18

SRAM SEL

13.0

LK18

POD7 POD8

U55

DECODER

U8

SSRAM

U9

SSRAMTEST CHIP

3.6

8.7

4.5

U13

U10

U54

ARBITERRESETCONTROL

EPROM/FLASHCONTROL

LK6

CNTRL

S1

U2

CLKDIV

U20 U11

CLKSEL

LK17

TEST1SRAM

SRAM

U16

SRAMCONTROL

U1216_BIT8-BIT

EPROM/FLASHEPROM/FLASH

U14

U37

TESTINTERFACECONTROL

DRAM SIMM

B A

U19

U15

SK2SK1

SERIAL PORT B

SERIAL PORT A

TEST2

PARALLEL PORT

INTERRUPT SWITCH

RESET SWITCHLK9

S3

LK8LK10LK4

LK16

J2

DRAMCONTROLLER

U29

PERIPHERALSAPB

U21

SERIAL/PARALLELCONTROL

DOWNLOADCABLE

LK7

APB/NISABRIDGE

EPROM/FLASHDATA PATH

U25

PC-CARDCONTROLLER

HEATSINKPOWER CONNECTOR

PC-CARD SLOTS

ALL DIMENSIONS IN INCHES

SWITCHES--------

S1 CLOCK FREQUENCY SELECTS2 SRAM SELECTS3 PARALLEL PORT SWITCHES

POD1 POD2 POD3

APB EXPANSION

2-PIN LINKS

LK4 BIGENDLK7 P_STB WIDTH

-----------

LK8 INTERRUPT TYPELK9 DIRECTIONLK10 ENABLE INTERRUPTLK17 USE TEST INTERFACELK18 REMAP

POD4 POD5 POD6

LK11

LINK FIELDS-----------

LK6 EPROM/FLASH SELECTLK11 PARALLEL PORT LINKSLK16 FPGA LINKS


Open Access


ARM DUI 0017C

Board SchematicsA.2 Top-level Diagram



B ARM EOI-0011B (CHAMP

Title

ARM7T Development Board (

CB1 4JNCambridgeCherry HintonFulbourn Road

(c) ADVANCED RISC MACHIN

R

B

ASB SLAVES

ASBSLAVE.SCH

B_D[31..0]

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

ARMnFIQ

ARMnIRQ

REMAP

STANDBY

ARMCOMMTX

ARMCOMMRX

B_A[31..0]

B_WRITE

B_SIZE[1..0]

nB_CLK[6..0]

BIGEND

B_CLK2X[1..0]

REFCLK

NISARST

B_RES[2..0]

B_WAIT

B_LAST

COMMCLK

B_CLK[4..0]

nINTASB[1..0]

nFIQSRC

NISACLK0

REFCLK

B_RES[2..0]

B_WAIT

B_LAST

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

D_SELASB0

D_SELASB1 COMMCLK

ASB SYSTEM MODULES

SYSMODS.SCH

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

D_SELASB0

D_SELASB1

A_REQTIC

A_REQARM

A_REQ002

A_GNTTIC

A_GNTARM

A_GNT001

A_GNT002

STANDBY

REMAP

B_RES[2..0]

B_A[31..2]

B_TRAN[1..0]

nSYSRST

NISARST

A_REQ001

nENASB[1..0]

nJTRST

nB_CLK[8..7]

B_CLK5

B_CLK7

B_WAIT

B_LAST

B_ERROR

B_LOCK

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_RES[2..0]

B_PROT[1..0]

B_LOCK

B_WAIT

B_TRAN[1..0]

B_WAIT

B_LAST

B_ERROR

B_A[31..2]

nB_CLK[8..7]

B_CLK5

nENASB[1..0]

B_LOCK

ARM MASTER

MASTER.SCH

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_PROT[1..0]

B_LOCK

B_WAIT

B_LAST

B_ERROR

ARMnFIQ

ARMnIRQ

A_REQARM

A_GNTARM

A_GNT001

ARMCOMMRX

ARMCOMMTX

BIGEND

B_RES[2..0]

nSYSRST

A_REQ001

B_CLK6

nJTRST

ARMnFIQ

ARMnIRQ

A_GNTARM

A_REQARM

A_GNT001

A_REQ001

BIGEND

B_CLK6

nJTRST

TEST INTERFACE CONTROLLER

TIC.SCH

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

A_GNTTIC

B_PROT[1..0]

B_LOCK

B_WAIT

B_ERROR

B_LAST

A_REQTIC

B_CLK9

nB_CLK9

B_RES[1..0]

B_CLK9

nB_CLK9

B_LAST

B_ERROR

B_A[31..0]

B_D[31..0]

REMAP

STANDBY

A_REQTIC

A_REQARM

A_REQ001

A_REQ002

ARMCOMMRX

ARMCOMMTX

nSYSRST

nSYSRST

B_CLK7 B_RES[2..0]

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

A_GNTTIC

A_GNTARM

A_GNT001

A_GNT002

B_CLK[4..0]

nB_CLK[6..0]

B_CLK2X[1..0]NISARST

NISARST

nJTRST

NISACLK0

n

n

A

A

DISTRIBUTE TEST PINS OVER BOARD

POWER SUPPLY

POWER.SCH

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

ASB EXPANSION

ASBEXP.SCH

A_GNT001

A_GNT002

D_SELASB0

D_SELASB1

A_REQ002

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_RES[2..0]

B_PROT[1..0]

B_LOCK

B_WAIT

B_LAST

B_ERROR

nINTASB[1..0]

nFIQSRC

A_REQ001

nENASB[1..0]

B_CLK10

nB_CLK10

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_PROT[1..0]

B_LOCK

B_WAIT

A_REQTIC

B_TRAN[1..0]

B_RES[2..0]

B_PROT[1..0]

B_LOCK

B_WAIT

B_LAST

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_LAST

B_ERROR

A_GNTTIC

B_RES[1..0]

SPARE CLOCK POINTS

OSCILLATORS

OSC.SCH

REFCLK

B_CLK2X[1..0]

nB_CLK[10..0]

COMMCLK

NISACLK[1..0]

B_CLK[10..0]

1 V1

1 V2

B_CLK2X[1..0]

B_ERROR

D_SELASB0

D_SELASB1

A_GNT001

A_GNT002

REFCLK

nB_CLK10

nB_CLK[10..0]

COMMCLK

B_CLK[10..0]

NISACLK[1..0]

B_CLK10

B_CLK8

NISACLK1

1

TP1TESTPIN

A_REQ001

A_REQ002

nINTASB[1..0]

nFIQSRC

nENASB[1..0] GND

BOARD OUTLINE

DRAWING.SCH

1

TP2TESTPIN

1

TP3TESTPIN

1

TP4TESTPIN

1

TP5TESTP

GND GND GND GND


Open Access


ARM DUI 0017C

Board SchematicsA.3 Power Supply

Date: February 26, 1996 Sheet


B ARM EOI-0011B (POWER

Title

Power Supply



INSERT LOAD IF REQUIRED

JP2JUMPER

C310u

VPP

GND GND

BOARD GROUND

BOARD 5V

PCMCIA VPP SUPPLY (optional)

GND

VCC

VPP

DC_OK FROM PC PSU

P8

P9 -5V FROM PC PSU

-12V FROM PC PSU

123456789101112

J1

CON12

PSU5VPSU12V

PSUGNDPSUGNDPSUGNDPSUGND

PSU5VPSU5VPSU5V

PC STYLE POWER CONNECTOR

C410u

IN 3

OUT 2

ADJ 1

U1

LM317T

PSU5V HEADER POWER SUPPLY - VDD (3V3)D1

1N4001

C21u

JP1

JUMPERD21N4148

R2200R1206

POWER (3V3)

VPP IS REQUIRED WHEN USING PCMCIA

INTERFACE, EVEN IF 12V IS NOT

ACTUALLY REQUIRED BY THE CARD

R4470R

VDD

VDD

POWER (5V)

R1470R

VCC

D3LEDGREEN

GND

D4LEDGREEN

GND

GND

C110u

R3330R1206

Vout = 1.25(1 + (R3/R2)) + .00005.R3

VOLTAGE REGULATOR OUTPUT

PSUGND


Open Access


ARM DUI 0017C

Board SchematicsA.4 Crystal Oscillator and Clock Distribution



B ARM EOI-0011B (OSC.

Title

Crystal oscillator and clock



MONITOR POINTS

DRAM REFR

BAUD RATE

1 V12

1 V13 1 V14 1 V15 1 V16

C0C1C2

C3REFCLK

COMMCLK

I3 5

I4 6

I5 7

NC 8

I6 9

I7 10

I8 11

I9

12

I10

13

GND

14

NC15

I11

16

IO0

17

IO1

18

I02 19IO3 20IO4 21NC/GND 22IO5 23IO6 24IO7 25

IO8

26

IO9

27

VCC

28

NC

1

CLK/I0

2

I1

3

I2

4 U2

22V10PLCC-7

R4010K

R4110K

R4210K

R4310K

R4410K

R4510K

R4610K

R4710K

R4910K

COMMCLK

B_CLK2X2

VCC

SEL0SEL1SEL2SEL3

VCCREFRESH CLOCK DIVIDER

distributors belowConnect to clock

CLKSEL SYSCLK2 1 0 (MHz)

R6

10K

1 V3

1 2 3 4

8 7 6 5

S1

SW DIP-4

VCCPLL

CLKSEL0

CLKSEL2

CLKSEL1SYSCLK

GNDREF1

POWERDN

SYSCLK2X

VCC

PLL CLOCK GENERATOR

SPECIAL LAYOUT REQUIRED

X1

14.318MHz

1.8MHZ 1

X2 2

X1/CLK 3

VCC 4

GND 5

32MHZ 6

24MHZ 7

12MHZ 8

AGND 9

OE 10 S2 11PD 12REF0 13REF1 14GND 15VCC 162XCLK 17CLK 18S1 19S0 20U5

W48C55-62

R50

10K

VCCPLLGND

AGNDCLKOE

COMMCLK

CLK24MHZCLK32MHZ

VCC

Fit resistors toterminate alternate

12

PL1

EXTCLK R3647RDO NOT FIT

12

PL2

EXTCLK

R38

10RR39

10R

GNDAGND

VCCVCCPLL

EXTSCLK

EXTSCLK2X

GND

GND

---------------0 0 0 4

0 1 0 160 1 1 201 0 0 25

1 0 1 331 1 0 401 1 1 50

0 0 1 8

NOTE: NOT DESIGNED

ABOVE 25MHz

FOR OPERATION

SPARE INPUTS

---------------

open = 1, closed = 0

PAL WILL FILTER

INVALID SELECTIONS

GND

SERIES TERMINATION RESISTORS

1V7 1V8 1V9

1V10 1V11GND

SP4SP5SP6

SP7 GND

SP8

SPARE I/O

1 V17 1 V18

nB

GND

CCLK_RCCLK_R2

nB_CLK[10..0]

CLKSEL2

CLKSEL0CLKSEL1

B_

nB_CLK3nB_CLK4nB_CLK5nB_CLK6nB_CLK7nB_CLK8nB_CLK9

B_CLK0B_CLK1B_CLK2B_CLK3B_CLK4B_CLK5

nB_CLK10

nB_CLK0nB_CLK1nB_CLK2

B_CLK6B_CLK7B_CLK8B_CLK9

B_CLK[10..0]

R1033R R1133R R1233R R1333R R1433R R1533R R1633R R1733R R1833R R1933R R2033R

R2133R R2233R R2333R R2433R R2533R R2633R R2733R R2833R R2933R R3033R R3133R

VCC

VCC

GND

nB_C5nB_C6nB_C7

nB_C8nB_C9nB_C10

nB_C0nB_C1nB_C2nB_C3nB_C4nB_C5nB_C6nB_C7nB_C8nB_C9nB_C10

B_C0B_C1B_C2B_C3B_C4B_C5

GND

B_C6B_C7B_C8B_C9

B_C5B_C6

LOW-SKEW CLOCK DISTRIBUTION

VCCA 1

OA0 2

OA1 3

OA2 4

GNDA 5

OA3 6

OA4 7

GNDQ 8

OEA 9

INA 10 INB 11OEB 12MON 13OB4 14OB3 15GNDB 16OB2 17OB1 18OB0 19VCCB 20U3

FCT805T

VCCA 1

OA0 2

OA1 3

OA2 4

GNDA 5

OA3 6

OA4 7

GNDQ 8

OEA 9


FCT806T 1 V20 1 V21 1 V22

R3233R

VCC

VCC

GND

GND

nB_C0nB_C1nB_C2

nB_C3nB_C4

B_C0B_C1

GNDB_C2X0B_C2X1B_C2X2

VCC

GND

GND

B_CLK2X2

ALTERNATIVE CLOCK INPUTS

Must disable system

clock inputs.

links below.clock by moving

VCCA 1

OA0 2

OA1 3

OA2 4

GNDA 5

OA3 6

OA4 7

GNDQ 8

OEA 9


FCT805T

1V23 1V24

1V25

R3747RDO NOT FIT

VCC

GND

GNDGND

N_C0N_C1

GND

GND

Default A-C

SELECT NISA CLOCK SOURCE

Default A-C

Default A-C

A 1

C 2

B 3

LK1

SMLINKCLK24MHZ

CLK32MHZ

NCLK

DECOUPLING CAPACITORS

DISTRIBUTE SYSTEM CLOCKS

SELECT INTERNAL OR

EXTERNAL CLOCK SOURCESC82u2

C11100n

A 1

C 2

B 3

LK2

SMLINK

A 1

C 2

B 3

LK3

SMLINK

GND

GND

B_C2

B_C3B_C4

GND

SCLKSYSCLK

EXTSCLK

SCLK2XSYSCLK2X

EXTSCLK2X

VCCPLL

C6100n

C7100n

C9100n

C10100n

R3333R

R3433R R3533R

R4833R

VCC

GND

GND

GND

B_C10B_C7

B_C8B_C9B_C10

N_C0N_C1

B_C2X0B_C2X1

VCC

GND

NI

B_

B_CLK10

NISACLK0NISACLK1

B_CLK2X0B_CLK2X1

B_CLK2X[1..0]

NISACLK[1..0]


Open Access


ARM DUI 0017C

Board SchematicsA.5 ASB Slaves



B ARM EOI-0011B (ASBSLAV

Title

ASB Slaves



APB AND NISA BRID

APBNISA.SCH

B_D[31..0]

B_RES[2..0]

B_A[31..0]

B_WRITE

B_SIZE[1..0]

D_SELNISA

D_SELAPB

ARMCOMMTX

ARMCOMMRX

B_CLK[2..0]

ARMnFIQ

ARMnIRQ

STANDBY

REMAP

B_WAIT

NISARST

COMMCLK

nB_CLK[2..1]

nFIQSRC

nINTASB[1..0]

NISACLK0

B_D[31..0]

B_WRITE

B_SIZE[1..0]

D_SELNISA

B_A[31..0]

D_SELAPB

B_RES[2..0]

COMMCLK

ONCHIP (SYNC SRAM) SLAVE

ONCHIP.SCH

B_D[31..0]

B_WAIT

B_CLK2X[1..0]

D_SELSSRAM

BIGEND

B_RES0

B_WRITE

B_SIZE[1..0]

B_A[18..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_WAIT

B_A[18..0]

B_RES0

D_SELSSRAM

B_CLK2X[1..0]

DRAM SLAVE

DRAM.SCH

M_D[31..0]

B_WAIT

B_LAST

D_SELDRAM

BIGEND

B_RES0

B_A[25..0]

B_WRITE

B_SIZE[1..0]

REFCLK

nB_CLK0

nOEMD

nOEBD

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_RES[2..0]

B_WAIT

B_LAST

B_LAST

M_D[31..0]

B_WRITE

B_SIZE[1..0]

B_WAIT

B_A[25..0]

B_RES0

B_RES[2..0]

B_WAIT

B_LAST

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

nB_CLK0

D_SELNISA

B_CLK[4..0]

nINTASB[1..0]

nB_CLK[6..0]

D_SELROM

D_SELAPB

D_SELSSRAM

D_SELSRAM

D_SELDRAM

B_CLK2X[1..0]

BIGEND

D_SELDRAM

nOEMD

nOEBD

B_A[17..2]

B_D[31..0]

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

nINTASB[1..0]

B_CLK[4..0]

nB_CLK[6..0] REFCLK

nB_CLK6

B_CLK2X[1..0]

ADDRESS AND DATA BUFFERS

MEMBUF.SCH

B_D[31..0]

M_A[17..2]

B_A[17..2]

M_D[31..0]

nB_CLK6

nOEMD

nOEBD

nOEMD

nOEBD

M_D[31..0]

M_A[17..2]SIGNALS DRIVEN BY SRAM AND

DRAM CONTROLLERS

R511K

R521K

BIGEND

nOEMD nOEBD

VCC VCC

B_WAIT

nFIQSRC

nINTASB[1..0]

ARMCOMMTX

ARMCOMMRX

B_CLK[2..0]

nB_CLK[2..1]

ARMnFIQ

ARMnIRQ

STANDBY

NISARST

NISACLK0

12

LK4

LINK

R5310K

1 2

U24A

74HCT14

REMAP

BIGEND

VCC

GND

EPROM/FLASH SLAVE

EPROM.SCH

B_D[31..0]

B_WAIT

B_RES0

B_WRITE

B_SIZE[1..0]

M_A[17..2]

D_SELROM

B_A[1..0]

B_A18

B_CLK4

nB_CLK[5..4]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_WAIT

M_A[17..2]

B_RES0

SRAM SLAVE

SRAM.SCH

B_WRITE

B_SIZE[1..0]

M_A[17..2]

M_D[31..0]

B_RES0

B_WAIT

D_SELSRAM

B_A[1..0]

B_A18

BANKSEL

BIGEND

B_CLK3

nB_CLK3

nOEMD

nOEBD

nFIQSRC

ARMCOMMRX

ARMCOMMTX

REFCLK

ARMnFIQ

ARMnIRQ

REMAP

STANDBY

NISARST

COMMCLK

NISACLK0

M_D[31..0]

B_WRITE

B_SIZE[1..0]

B_WAIT

B_RES0

M_A[17..2]

REMAP

STANDBY

ARMnFIQ

ARMnIRQ

nFIQSRC

ARMCOMMRX

ARMCOMMTX

REFCLK

NISARST

COMMCLK

NISACLK0

BANKSEL PARTITIONS SRAM

INTO TWO LOGICAL BANKS

OF 256K BYTES EACH

BIGEND

D_SELSRAM

B_A18

B_A[1..0]

nB_CLK3

B_A18

B_CLK3

nOEMD

nOEBD

nB_CLK[5..4]

D_SELROM

B_A18

B_A[1..0]

B_CLK4

OUT - little endian (default)IN - big endian

SELECT BIG OR LITTLE ENDIAN


Open Access


ARM DUI 0017C

Board SchematicsA.6 “On-chip” Memory (Synchronous SRAM)



B EOI-0011B (ONCHIP.S

Title

’On chip’ (synchronous SRA



SYNCHRONOUS SRAM

R5810K

R5910K

nBW1

nBW2

nBW3

nBW4

nADSP

VDD

GND

GND

GND

nOE

nADSC

nADV

B_A10

B_A11

B_CLK2X1

nGW

VDD VDD

R5410K

nCE

CE2

B_A8

B_A9

VDD

SSRAM CONTROLLERMONITOR POINTS

1 V33

1 V34

B_WAITB_WAITB_D[31..0]

B_A[18..0]

B_RES0

D_SELSSRAM

B_SIZE[1..0]

B_WRITE

BIGEND

B_CLK2X[1..0]

B_D[31..0]

B_A[18..0]

B_RES0

B_SIZE[1..0]

D_SELSSRAM

B_WRITE

BIGEND

B_CLK2X[1..0]

B_A0B_A1

B_SIZE0

B_SIZE1

B_WRITEBIGEND

MONITOR POINT

I3 5

I4 6

I5 7

NC 8

I6 9

I7 10

I8 11

I9

12

I10

13

GND

14

NC15

I11

16

IO0

17

IO1

18

I02 19IO3 20IO4 21NC/GND 22IO5 23IO6 24IO7 25

IO8

26

IO9

27

VCC

28

NC

1

CLK/I0

2

I1

3

I2

4 U8

22V10PLCC-7

1 V32

B_RES0

nBW2nBW3nBW4GNDnOEnCEnADSP

STATE0

STATE1

VCC

D_SELSSRAM

B_CLK2X0

DQP3 1

DQ17 2

DQ18 3

VDDQ 4

VSSQ 5

DQ19 6

DQ20 7

DQ21 8

DQ22 9

VSSQ 10

VDDQ 11

DQ23 12

DQ24 13

PL 14

VDD 15

NC 16

VSS 17

DQ25 18

DQ26 19

VDDQ 20

VSSQ 21

DQ27 22

DQ28 23

DQ29 24

DQ30 25

VSSQ 26

VDDQ 27

DQ31 28

DQ32 29

DQP4 30

MODE

31

A5

32

A4

33

A3

34

A2

35

A1

36

A0

37

NC38NC39

VSS

40

VDD

41

NC42NC43

A10

44

A11

45

A12

46

A13

47

A14

48

NC/A15

49

NC/A16

50

DQP1 51DQ1 52DQ2 53VDDQ 54VSSQ 55DQ3 56DQ4 57DQ5 58DQ6 59VSSQ 60VDDQ 61DQ7 62DQ8 63ZZ 64VDD 65NC 66VSS 67DQ9 68DQ10 69VDDQ 70VSSQ 71DQ11 72DQ12 73DQ13 74DQ14 75VSSQ 76VDDQ 77DQ15 78DQ16 79DQP2 80

A9

81

A8

82

ADV*

83

ADSP*

84

ADSC*

85

OE*

86

BWE*

87

GW*

88

CLK

89

VSS

90

VDD

91

CE2*

92

BW1*

93

BW2*

94

BW3*

95

BW4*

96

CE2

97

CE*

98

A7

99

A6

100 U9

MT58LC

A 1

C 2

B 3

LK5

SMLINK

B_D16B_D17

B_D18B_D19B_D20B_D21

B_D22B_D23

VDDGND

VDDGND

VDDPIPELINED

VDD

B_B_

B_B_B_B_

B_B_

VDGN

VDGN

GN

B_B_

B_B_B_B_

B_B_

GND

VDD

VD

VDGN

VDGN

GN

B_A2

B_A3

B_A4

B_A12

B_A13

B_A14

B_A15

B_A16

B_A17

B_A18

Default A-C

SSRAM POWERED AT 3.3V

B_D24B_D25

B_D26B_D27B_D28B_D29

B_D30B_D31

GND

VDDGND

VDDGND

GND

B_A5

B_A6

B_A7

GND

B_WAIT

nBW1

GND

SPARE INPUTS

1V29 1V30

R5510K

R5610K

R5710K

1V31

VDD VDD VDD

C1210u

C17100n

VCC

GND

VCC

GND


WITH 5V TOLERANT I/O

C13100n

C14100n

C15100n

C16100n

VDD VDD

GND


Open Access


ARM DUI 0017C

Board SchematicsA.7 EPROM/FLASH ASB Slave



B EOI-0011B (EPROM.S

Title

EPROM/FLASH ASB Sla



8-BIT EPROM/FLASH

A18 1

A16 2

A15 3

A12 4

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15

GND 16 D3 17D4 18D5 19D6 20D7 21CE 22A10 23OE 24A11 25A9 26A8 27A13 28A14 29A17 30WE 31VCC 32U12

AT29C512/010/020/040

VCCnWE

nOEM_A2M_A3M_A4M_A5M_A6M_A7

M_A8M_A9

M_A10

M_A11

M_A12M_A13M_A14

M_A15M_A16

M_A17

M_A18

M_D4M_D5

GND

GND

VCC

OUTMD

M_D0

M_D1

M_D2

M_D3

M_D8

M_D9

M_D10

M_D11

SET LINKS TO SELEC

8 OR 16-BIT DEVICDATA PATH ROUTER

IO8 12

IO9 13

IO10 14

IO11 15

IO12 16

IO13 17

IO14 18

IO15 19

CLK0/I0 20

VCC 21

GND 22

CLK1/I1 23

IO16 24

IO17 25

IO18 26

IO19 27

IO20 28

IO21 29

IO22 30

IO23 31

GND 32

IO24

33

IO25

34

IO26

35

IO27

36

IO28

37

IO29

38

IO30

39

IO31

40

I2

41

VCC

42

GND

43

VCC

44

IO32

45

IO33

46

IO34

47

IO35

48

IO36

49

IO37

50

IO38

51

IO39

52

GND

53

IO40 54IO41 55IO42 56IO43 57IO44 58IO45 59IO46 60IO47 61CLK2/I3 62VCC 63GND 64CLK3/I4 65IO48 66IO49 67IO50 68IO51 69IO52 70IO53 71IO54 72IO55 73GND 74

IO56

75

IO57

76

IO58

77

IO59

78

IO60

79

IO61

80

IO62

81

IO63

82

I5

83

VCC

84

GND

1

VCC

2

IO0

3

IO1

4

IO2

5

IO3

6

IO4

7

IO5

8

IO6

9

IO7

10

GND

11 U11

MACH230-10

R6010K

R6110K

B_WAIT

B_D8B_D9B_D10

B_D0

B_D1

B_D2

B_D3

B_D4

B_D5

B_D6

B_D7

GND

VCC

B_WAIT

VCCVCC

B_D[31..0]

B_RES0

B_SIZE[1..0]

B_WRITE

nB_CLK[5..4]

D_SELROM

M_A[17..2]

B_A[1..0]

B_A18

B_CLK4

B_D[31..0]

B_RES0

B_SIZE[1..0]

B_WRITE

nB_CLK[5..4]

D_SELROM

M_A[17..2]

B_A[1..0]

B_A18

B_CLK4

EPROM/FLASH CONTROLLER

SPARE INPUTS

1V48

1V49

B_SIZE1

B_A0

B_A1

GND

VCC

SEL0

SEL1

HOLD0

HOLD1

B_A18

D_SELROM

B_D11B_D12B_D13B_D14B_D15

B_D16B_D17B_D18B_D19B_D20B_D21B_D22B_D23GND

GNDVCC

SPARE I/O

1 V41 1 V42 1 V43 1 V44 1 V45 1 V46 1 V47

M_D6M_D7M_D12M_D13M_D14M_D15

GNDVCCB_RES0

SEL8BIT

nB_CLK5

16-BIT EPROM/FLASH

D12 7

D11 8

D10 9

D9 10

D8 11

GND 12

NC 13

D7 14

D6 15

D5 16

D4 17

D3

18

D2

19

D1

20

D0

21

OE

22

NC23A0

24

A1

25

A2

26

A3

27

A4

28

A5 29A6 30A7 31A8 32NC 33GND 34A9 35A10 36A11 37A12 38A13 39

A14

40

A15

41

A16

42

WE

43

VCC

44

NC

1

A17

2

CE

3

D15

4

D14

5

D13

6 U1

AT

GND

M_A0M_A1

M_D0M_D1M_D2

M_D3M_D4M_D5M_D6M_D7

M_A15

M_A16

M_A17

M_A18

M_D13

M_D14

M_D15

nWE

VCC

nCS8

nCS16

nOE

M_A1

M_A2

M_A3

M_A4

M_A5

M_D0

M_D1

M_D2

M_D3

GND

VCC

SEL0

SEL1

HOLD0

HOLD1

HOLD2

TRANS0

TRANS1

TRANS2

GND

M_D4M_D5M_D6M_D7


GND

SPARE I/O 1 V50

R6210K

R6310K

R6410K

R6510K

HOLD2TRANS0TRANS1TRANS2

GNDEPROMSEL8BIT

B_D24

B_D25

B_D26

B_D27

B_D28

B_D29

B_D30

B_D31

OUTBD

VCC

M_A18

nB_CLK4

nCS16VCC

CYCLE COUNTER

IO5 7

IO6 8

IO7 9

I0 10

I1 11

GND 12

CLK0/I2 13

IO8 14

IO9 15

IO10 16

IO11 17

IO12

18

IO13

19

IO14

20

IO15

21

VCC

22

GND

23

IO16

24

IO17

25

IO18

26

IO19

27

IO20

28

IO21 29IO22 30IO23 31I3 32I4 33GND 34CLK1/I5 35IO24 36IO25 37IO26 38IO27 39

IO28

40

IO29

41

IO30

42

IO31

43

VCC

44

GND

1

IO0

2

IO1

3

IO2

4

IO3

5

IO4

6 U10

MACH210A-7

1V35 1V36

B_WAITB_WRITEB_SIZE0

CYC1CYC0GND

OUTBDOUTMDCCNT0CCNT1

B_CLK4


MONITOR POINTS

TICK COUNTER

C1810u

C19100n

C20100n

C21100n

C22100n

C23100n

1V37 1V38 1V39

TCNT0

TCNT1

TCNT2

VCC

GND

nOE

nWE

M_A0

M_A1

B_RES0

nCS8

C24100n

C25100n

C26100n

+ 1

+ 3

+ 5

+ 7

+ 2

+ 4

+ 6

+ 8

LK6

LINK-4

VCC

GND

GND

VCC

GND

open = EPROM, closed = FLASHopen = 8 bit, closed = 16-bit

00 2

CYC No. of cycles

10 4 01 3

11 5

cycle information, see below

EPROMSEL8BIT

CYC1CYC0

WHEN EPROM IS SELECTED

WE IS CONNECTED TO A18


Open Access


ARM DUI 0017C

Board SchematicsA.8 DRAM ASB Slave



B ARM EOI-0011B (DRAM.

Title

DRAM ASB Slave



1 2 3 4 5 6 7 8 9 10 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2 30 31 32 33 34 35 36

37 38 39 40 41 42 43 44 45 4 47 4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 6 67 68 6 7 7 72

GND 1

D[00] 2

D[16] 3

D[01] 4

D[17] 5

D[02] 6

D[18] 7

D[03] 8

D[19] 9

VCC 10

NC 11

RA[00] 12

RA[01] 13

RA[02] 14

RA[03] 15

RA[04] 16

RA[05] 17

RA[06] 18

RA[10] 19

D[04] 20

D[20] 21

D[05] 22

D[21] 23

D[06] 24

D[22] 25

D[07] 26

D[23] 27

RA[07] 28

NC 29

VCC 30

RA[8] 31

RA[9] 32

RAS1 33

RAS0 34

PUDP2 35

PUDP0 36

PUDP1 37

PUDP3 38

GND 39

CAS0 40

CAS2 41

CAS3 42

CAS1 43

RAS0 44

RAS1 45

NC 46

WE 47

NC 48

D[08] 49

D[24] 50

D[09] 51

D[25] 52

D[10] 53

D[26] 54

D[11] 55

D[27] 56

D[12] 57

D[28] 58

VCC 59

D[29] 60

D[13] 61

D[30] 62

D[14] 63

D[31] 64

D[15] 65

NC 66

PD0 67

PD1 68

NC 69

NC 70

NC 71

GND 72

SK2

DRAM SIMM

RAMVCC

M_D0

M_D1

M_D2

M_D3

M_D4

M_D16

M_D17

M_D18

M_D19

M_D20

GND

RA0RA1RA2RA3RA4RA5RA6RA10

C2810u

C2910u

C4410u

C4510u

RAMVCC

M_D0

M_D1

M_D2

M_D3

M_D4

M_D16

M_D17

M_D18

M_D19

M_D20

GNDRAMVCC

RAMVCC

RAMVCC

RA0RA1RA2RA3RA4RA5RA6RA10

GND

GND

SEPARATE VCC FOR DRAM

COUPLED TO VCC WITH

2 PARALLEL INDUCTORS

EACH SIMM DECOUPLED WITH:

3 10u TANTS

2 10n DEC CAPS

C2710u

C4310u

L1

22uH

L2

22uH

RAMVCC

RAMVCC

VCC

VCC

M_D[31..0]

B_SIZE[1..0]

B_WRITE

B_WAIT

B_RES0

D_SELDRAM

BIGEND

nOEMD

nOEBD

B_A[25..0]

B_LAST

REFCLK

nB_CLK0

M_D[31..0]

B_SIZE[1..0]

B_WRITE

B_RES0

D_SELDRAM

BIGEND

B_WAIT

nOEMD

nOEBD

B_A[25..0]

B_LAST

REFCLK

nB_CLK0

DRAM CONTROLLER

1V51

IO8 12

IO9 13

IO10 14

IO11 15

IO12 16

IO13 17

IO14 18

IO15 19

CLK0/I0 20

VCC 21

GND 22

CLK1/I1 23

IO16 24

IO17 25

IO18 26

IO19 27

IO20 28

IO21 29

IO22 30

IO23 31

GND 32

IO24

33

IO25

34

IO26

35

IO27

36

IO28

37

IO29

38

IO30

39

IO31

40

I2

41

VCC

42

GND

43

VCC

44

IO32

45

IO33

46

IO34

47

IO35

48

IO36

49

IO37

50

IO38

51

IO39

52

GND

53


IO56

75

IO57

76

IO58

77

IO59

78

IO60

79

IO61

80

IO62

81

IO63

82

I5

83

VCC

84

GND

1

VCC

2

IO0

3

IO1

4

IO2

5

IO3

6

IO4

7

IO5

8

IO6

9

IO7

10

GND

11 U14

MACH231-7

B_A4

B_A5

B_A6

B_A7

B_A12

B_A13

B_A14B_A15B_A16

GND

M_A2

M_A3

M_A4M_A5

nWE

B_LAST

B_WRITE

VCC

GND

VCC

2 100n DEC CAPS

MONITOR POINTS

SERIAL TERMINATION RESISTORS

C3510n

C3610n

C39100n

C40100n

1 V57

1 V58

1 V59

1 V60COLMUXCASENCOLADDRnCAS3

nCAS0nCAS1nCAS2

GND

B_A0

B_A1

B_A2

B_A3

B_A10

B_A11

M_A0

M_A1

C3710n

C3810n

C41100n

C42100n

R6633R R6733R R6833R R6933R

R7233R

R7333R

RAMVCC

M_D5

M_D6

M_D7

M_D21

M_D22

M_D23

GND

PUDUPA0

PUDUPA1

PUDUPA2

PUDUPA3

RAMVCC

RnCAS0RnCAS2RnCAS3RnCAS1RnRAS0

RnRAS1RnRAS0

RA0RA1RA2RA3RA4

RA8RA9

M_A0M_A1M_A2M_A3M_A4

RA7GND

GND

RAMVCC

M_D5

M_D6

M_D7

M_D21

M_D22

M_D23

GND

PUDUPB0

PUDUPB1

PUDUPB2

PUDUPB3

RnRAS2

RnRAS3RnRAS2

RnCAS0RnCAS2RnCAS3RnCAS1

RA7

RA8RA9

RAMVCC

M_D8

M_D9

M_D10

M_D11

M_D12

M_D13

M_D14

M_D15

M_D24

M_D25

M_D26

M_D27

M_D28

M_D29

M_D30

M_D31

RnRAS3

RnWER70

33R R7133R R7433R R7533R R7633R

R7733R R7833R R7933R R8033R R8133R R8233R

R8333R

R8433R

R8533R

R954K7

RAMVCC

M_D8

M_D9

M_D10

M_D11

M_D12

M_D13

M_D14

M_D15

M_D24

M_D25

M_D26

M_D27

M_D28

M_D29

M_D30

M_D31

PD0PD1

nCAS3

nCAS0nCAS1nCAS2

nRAS0nRAS1nRAS2nRAS3

RnCAS0RnCAS1RnCAS2RnCAS3

RnRAS0RnRAS1RnRAS2RnRAS3

RnRAS1

M_A8M_A9

nWE

RA5RA6RA7RA8RA9

RnWE

RnWE

M_A5M_A6M_A7

M_A10 RA10

VCC

PLACE NEAR TO SIGNAL SOURCE

1 V55

1 V56

CASSSTART

GNDVCCD_SELDRAM

nRAS0nRAS1nRAS2nRAS3

REFCYCMEMCYC

B_A24B_A25

nOEBD

REFCLK

REFREQ

B_SIZE0

B_SIZE1

BIGEND

GND

nB_CLK0

SPARE I/O

1V52

B_A8B_A9B_A17B_A18

B_A19

B_A20

B_A21

B_A22

B_A23

M_A6M_A7

M_A8

M_A9

M_A10

PD0

PD1B_WAIT

B_RES0

nOEMD

VCCGND

GND

VCC

GND

VCC


C3010u

C31100n

C32100n

C33100n

C34100n

VCC

GND

VCC

GND

SPARE I/O

MONITOR POINT

USE IDENTICAL SIMMS IF BOTH SLOTS USED

1 V53

1 V54

PULLUP RESISTORS

R864K7 R874K7 R884K7 R894K7 R904K7 R914K7 R924K7 R934K7

R944K7

GND

PUDUPA0PUDUPA1PUDUPA2PUDUPA3PUDUPB0PUDUPB1PUDUPB2PUDUPB3

PD0PD1

SLOT A

GND


Open Access


ARM DUI 0017C

Board SchematicsA.9 SRAM ASB Slave



B ARM EOI-0011B (SRAM.

Title

SRAM ASB Slave



R96

10K

VCC

FAST SRAM BANK

NC 1

A16 2

A14 3

A12 4

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15

GND 16 D3 17D4 18D5 19D6 20D7 21CE1 22A10 23OE 24A11 25A9 26A8 27A13 28WE 29CE2 30A15 31VCC 32U15

SRAM128K8-20

M_A2M_A3M_A4M_A5M_A6M_A7M_A8M_A9

M_A10M_A11

M_A12

M_A13

M_A14M_A15

M_A16M_A17M_A18

nCS

VCC

nOE

nWE3

M_D24M_D25M_D26 M_D28

M_D29M_D30M_D31

B_WAIT

nOEMD

nOEBD

nWE1

nWE2

nWE3

VCC

GND

BANKSEL

nWE0

SRAM CONTROLLER

M_A[17..2]

M_D[31..0]

B_A[1..0]

B_A18

B_SIZE[1..0]

B_WRITE

B_RES0

D_SELSRAM

nB_CLK3

B_CLK3

B_WAIT

B_WRITE

B_SIZE0

B_A18

M_A[17..2]

M_D[31..0]

B_A[1..0]

B_SIZE[1..0]

B_WRITE

B_RES0

D_SELSRAM

B_WAIT

nOEMD

nOEBD

B_CLK3

nB_CLK3

B_A18

IO5 7

IO6 8

IO7 9

I0 10

I1 11

GND 12

CLK0/I2 13

IO8 14

IO9 15

IO10 16

IO11 17

IO12

18

IO13

19

IO14

20

IO15

21

VCC

22

GND

23

IO16

24

IO17

25

IO18

26

IO19

27

IO20

28


IO28

40

IO29

41

IO30

42

IO31

43

VCC

44

GND

1

IO0

2

IO1

3

IO2

4

IO3

5

IO4

6 U16

MACH210A-7

1V63 1V64

BANKSEL

BIGEND

B_SIZE1B_A0B_A1

B_RES0GND

nOEBDnOEMD

D_SELSRAM

BANKSEL

BIGEND

B_CLK3

CCNT0CCNT1

SPARE I/O

R10010K

1 V61

1 V62

1 V65 1 V66

1 V67 1 V68

nCS

GND

M_A18BIGEND

nB_CLK3

TCNT2TCNT1

nOE

VCC

NC 1

A16 2

A14 3

A12 4

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15


SRAM128K8-20

GND


M_A10M_A11

M_A12

M_A13

M_A14M_A15

M_A16M_A17M_A18

nCS

GND

VCC

nOE

nWE2

M_D16M_D17M_D18


M_D27

R97

10K

VCC

R98

10K

VCC

NC 1

A16 2

A14 3

A12 4

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15


SRAM128K8-20

NC 1

A16 2

A14 3

A12 4

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15


SRAM128K8-20


M_A10M_A11

M_A12

M_A13

M_A14M_A15

M_A16M_A17M_A18

nCS

GND

VCC

nOE

nWE1

M_D8M_D9M_D10


00 2

CYC No. of cycles

10 4 01 3

11 5

MONITOR POINTS

B1CYC0

B1CYC1

B1SIZ0

B1SIZ1

GND

VCC

TCNT0

BANK0

MONITOR POINTS

1 2 3 4 5 6 7 8

16151413121110 9

S2

SW DIP-8

R10110K

R10210K

R10310K

R10410K

R10510K

R10610K

R10710K

R10810K

B0CYC0B0CYC1B0SIZ0B0SIZ1

B0CYC0

B0CYC1

B0SIZ0

B0SIZ1

VCC

SELECT CYCLES AND WIDTH OF BANK

BANK 1

OPEN = 1, CLOSED = 0

C4610u

C47100n

C48100n

C49100n

C50100n

C51100n

B1CYC0B1CYC1B1SIZ0B1SIZ1

GND

SIZ Width of bank

00 8 bit01 16 bit10 32 bit11 reserved

C52100n

VCC

GND

VCC

GND


M_A10M_A11

M_A12

M_A13

M_A14M_A15

M_A16M_A17M_A18

nCS

GND

VCC

nOE

nWE0

M_D0M_D1M_D2


R99

10K

VCC


Open Access


ARM DUI 0017C

Board SchematicsA.10 APB and NISA Bridge



B EOI-011B (ASBNISA.S

Title

APB and NISA Bridg



APB EXP

APBEXP

P_WRIT

P_STB

P_A[31

P_D[31

P_SELE

B_RES

P_SELI

P_SELC

P_SELR

nB_CLK

B_CLK1

nINTAP

nFIQSR

P_A[31..0]

P_D[31..0]

P_WRITE

P_STB

P_SELEX

B_RES[2..0]

INTPCA

INTPCB

INTSPA

INTSPB

nINTPP

P_SELIC

P_SELCT

P_SELRC

ARMCOMMTX

ARMCOMMRX

APB SLAVES

APBSLAVE.SCH

P_WRITE

P_STB

P_SELIC

P_SELCT

P_SELRC

P_A[31..0]

P_D[31..0]

B_RES[2..0]

P_SELEX

nINTPP

INTPCB

INTSPA

INTSPB

INTPCA

ARMCOMMRX

ARMCOMMTX

ARMnFIQ

STANDBY

REMAP

ARMnIRQ

B_CLK0

nINTAPB[2..0]

nINTASB[1..0]

nFIQSRC

P_A[31..0]

P_D[31..0]

P_WRITE

P_STB

P_SELIC

P_SELCT

P_SELRC

P_SELEX

B_RES[2..0]

APB BUFFERS

APBBUF.SCH

nB_DEN

nB_DLEN

nP_DEN

nP_DLEN

P_D[31..0]

B_A[31..0]

B_D[31..0]

nP_ALENP_A[31..26]

P_A[22..9]

P_A[1..0]

P_A[31..26]

P_A[1..0]

P_A[22..9]

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_RES[2..0]

D_SELNISA

D_SELAPB

B_CLK[2..0]

COMMCLK

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_RES[2..0]

B_CLK[2..0]

D_SELAPB

D_SELNISA

nB_DEN

nB_DLEN

nP_DEN

nP_DLEN

nP_ALEN

COMMCLK

SPARE I/O

1V77

B_WAIT

nFIQSRC

nINTASB[1..0]

ARMCOMMRX

ARMCOMMTX

nB_CLK[2..1]

ARMnFIQ

ARMnIRQ

STANDBY

NISARST

NISACLK0

B_WAIT

nFIQSRC

nINTASB[1..0]

ARMCOMMRX

ARMCOMMTX

nB_CLK[2..1]

ARMnFIQ

ARMnIRQ

STANDBY

NISARST

NISACLK0

APB AND NISA BRIDGE

MONITOR POINTS

1 V69 1 V70 1 V71 1 V72 1 V73 1 V74 1 V81

VCC

GND

VCC

GND

B_A8

Q0

Q2

Q3Q4

SSTATE0

B_WRITE

B_WAIT

nIOR

nIOW

nMEMR

nMEMW

nSBHE

BALE

SAPBACK

PCCLK

NISA BUS PERIPHERALS

NISABUS.SCH

nCSA

nCSB

nCSP

BALE

RDY

INTPCA

INTPCB

INTSPA

INTSPB

nINTPP

nSBHE

nMEMR

nMEMW

nIOR

nIOW

nRESET

NISARST

P_D[15..0]

P_A[24..0]

nM16

nIO16

nZWS

COMMCLK

PCCLK

P_A[24..0]

P_D[15..0]

nCSA

B_CLK0

ARMnFIQ

ARMnIRQ

STANDBY

REMAP

nINTAPB[2..0]

nFIQSRC

nINTASB[1..0]

INTPCA

INTPCB

INTSPA

nB_CLK1

B_CLK1

INTSPB

nINTPP

nCSB

nCSP

BALE

nM16

nIO16

nZWS

nSBHE

nMEMR

nMEMW

nIOR

nIOW

COMMCLK

GNDVCC

B_CLK2

nB_CLK2

P_A23

B_A5

B_A23

B_A24

B_A25

B_RES0

B_RES1

GND

STROBE2

nP_DLEN

nP_ALENnB_DEN

MONITOR POINTS

1V75

1V78

1V79

1V80

IO8 12

IO9 13

IO10 14

IO11 15

IO12 16

IO13 17

IO14 18

IO15 19

CLK0/I0 20

VCC 21

GND 22

CLK1/I1 23

IO16 24

IO17 25

IO18 26

IO19 27

IO20 28

IO21 29

IO22 30

IO23 31

GND 32

IO24

33

IO25

34

IO26

35

IO27

36

IO28

37

IO29

38

IO30

39

IO31

40

I2

41

VCC

42

GND

43

VCC

44

IO32

45

IO33

46

IO34

47

IO35

48

IO36

49

IO37

50

IO38

51

IO39

52

GND

53


IO56

75

IO57

76

IO58

77

IO59

78

IO60

79

IO61

80

IO62

81

IO63

82

I5

83

VCC

84

GND

1

VCC

2

IO0

3

IO1

4

IO2

5

IO3

6

IO4

7

IO5

8

IO6

9

IO7

10

GND

11 U20

MACH231-7

REMAPREMAP

SNM16P_SELEXP_SELCTP_SELRCSNZWSSRDYSNIO16P_SELIC

D_SELNISAP_A5P_A6

B_A7P_STB

VCCGND

NISACLK0

SELECT STROBE WIDTH

OUT - 2 cycle (default)IN - 1 cycle

MONITOR POINT

12

LK7

LINK

R10910K

1V76

B_A6

GNDP_A0B_SIZE0B_SIZE1

STROBE2

VCC

GND DECOUPLING CAPACITORS

C5310u

P_A2

P_A3

P_A4

P_A7

P_A8

P_A24P_A25

B_A2

B_A3

B_A4

nM16nIO16RDY

nP_DEN

GND

VCC

GND

VCC

nB_DLEN

P_WRITE

D_SELAPB

nZWS

nCSA

nCSB

nCSP

SDSELNISA

C54100n

C55100n

C56100n

C57100n

B_RES0

RDY

VCC

GND

NISARST

PCCLK

VCC

GND


Open Access


ARM DUI 0017C

Board SchematicsA.11 NISA Bus Peripherals



B EOI-0011B (NISABUS.

Title

NISA Bus Periphera



INTPCA

INTPCB

nM16

INTPCA

INTPCB

nM16

PC-CARD INTERFACE

PCMCIA.SCH

BALE

INTPCA

INTPCB

nSBHE

nMEMR

nMEMW

nIOR

nIOW

NISARST

nM16

nIO16

RDY

nZWS

P_A[24..0]

P_D[15..0]

PCCLK

P_D[15..0]

BALE

nSBHE

NISARST

P_A[24..0]

PCCLK

P_A[24..0]

P_D[15..0]

BALE

nSBHE

NISARST

PCCLK

nMEMR

nMEMW

nIOR

nIOW

SERIAL AND PARALLEL PORTS

SUPERIO.SCH

P_D[7..0]

nCSA

nCSB

nCSP

nRESET

nIOR

nIOW

INTSPA

INTSPB

nINTPP

COMMCLK

P_A[4..2]

nMEMR

nMEMW

nIOR

nIOW

nIO16

RDY

nZWS

nIO16

RDY

nZWS

INTSPA

INTSPB

nINTPP

INTSPA

INTSPB

nINTPPnCSA

nCSB

nCSP

P_D[7..0]

nRESET

nIOR

nIOW

P_A[4..2]

COMMCLK

nCSA

nCSB

nCSP

nRESET

COMMCLK


Open Access


ARM DUI 0017C

Board SchematicsA.12 Serial and Parallel Ports



B EOI-0010B (SUPERIO.

Title

Serial and Parallel P



13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1

R11433R

R11533R

R11633R

R11733R

R11833R

R11933R

nACK

BUSY

PE

SLCT

nSLCTIN

GND

GND

GND

GND

GND

GND

GND

GNDnSLCTIN

INIT

nAUTOFD

nACK

IO3

IO4

IO5

IO6

IO7

SWITCH

CLOSED - read 0OPEN - read 1

LEDPP0

LEDPP1

R1214K7

R1224K7

R1234K7

R1244K7

R1254K7

R126

470R

R127

470R

1 2 3 4

8 7 6 5

S3

SW DIP-4

R13010K

R13110K

D7

LEDYELLOW

D8

LEDYELLOW

1 2

U7A

74HCT14

3 4

U7B

74HCT14

PD3

PD4

PD5

PD6

PD7

VCC

VCC

VCC

VCC

GND

Insert links toconnect LEDs andswitches toparallel port

R13210K

R13310K

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

LK11

LINK-8

R20510K R20610K R20710K

INTSPA

INTSPB

nINTPP

IO0IO1IO2IO3IO4IO5IO6IO7

LED0LED1

LED0

LED1

VCCSELECT PARALLEL PORT DIRECTION

OUT - I/O (default)

R11110K

12

LK9

LINK

nCSA

nCSB

nCSP

P_D[7..0]

nRESET

nIOR

nIOW

P_A[4..2]

COMMCLK

nCSA

nCSB

nCSP

P_D[7..0]

nRESET

nIOR

nIOW

P_A[4..2]

INTSPA

INTSPB

nINTPP

COMMCLK

VCC

GND

SERIAL/PARALLEL CONTROLLER

MONITOR POINT

IN - output only

TXB 10

DTRB* 11

RTSB* 12

CTSB* 13

D0 14

D1 15

D2 16

D3 17

D4 18

D5 19

D6 20

D7 21

TXRDYA* 22

VCC 23

RTSA* 24

DTRA* 25

TXA 26

GND

27

CTSA*

28

CDA*

29

RIA*

30

DSRA*

31

CSA*

32

A2

33

A1

34

A0

35

IOW*

36

IOR*

37

CSP*

38

RESET*

39

VCC

40

RXA

41

TXRDYB*

42

INTSEL*

43

RDOUT 44INTA 45PD7 46PD6 47PD5 48PD4 49PD3 50PD2 51PD1 52PD0 53GND 54STROBE* 55AUTOFDXT* 56INIT 57SLCTIN* 58INTP* 59INTB 60

RXRDYB*

61

RXB

62

ERROR*

63

VCC

64

SLCT

65

BUSY

66

PE

67

ACK*

68

BIDEN

1

GND

2

CSB*

3

CLK

4

DSRB*

5

RIB*

6

GND

7

CDB*

8

RXRDYA*

9 U21

ST16C552

1V82

TXBnDTRBnRTSBnCTSBP_D0P_D1

nRXRDYA

GND

nRIB

nDSRB

nCSB

GND

BIDEN

nACK

COMMCLK

nDCDB

OUT - disable (default)PUSH BUTTON INTERRUPT

1V85R208

10K

nSLCTININIT

nSTROBE

PEBUSY

SLCT

VCC

nERROR

RXB

nRXRDYB

nAUTOFD

INTSPBnINTPP

PBINT

LED2LED3

LED2

LED3LEVEL SHIFTERS

LEDPP2

LEDPP3

T3O 1

T1O 2

T2O 3

R2I 4

R2O 5

T2I 6

T1I 7

R1O 8

R1I 9

GND 10

VCC 11

C1+ 12

V+ 13

C1- 14 C2+ 15C2- 16V- 17R5I 18R5O 19T3I 20T4I 21R4O 22R4I 23EN 24SHDN 25R3O 26R3I 27T4O 28U22

MAX211E

R128

470R

R129

470R

D9

LEDYELLOW

D10

LEDYELLOW

+ 1 + 2LK10

LINK

5 6

U7C

74HCT14

9 8

U7D

74HCT14

11 10

U7E

74HCT14

SA_TXSA_DTR

SA_RTS

SA_DCD

SA_RXRXAnDTRATXAnDCDA

nSTROBE

PD0

PD1

PD2

nACK

VCC

VCC

PAR

5 9 4 8 3 7 2 6 1

R11233R

R11333R

R12033R

C742200p

SA_DCD

SA_RXSA_DSR

SA_RTS

SA_DSR

SA_CTS

GNDnRTSA

nCTSA

GNDGNDnDSRA

nAUTOFD

nERROR

INIT

IO0

IO1

IO2

GND

SER

5 9 4 8 3 7 2 6 1

SA_TX

SA_DTR

GND

SA_CTS

SA_RI

SB_DCDSB_DSRSB_RXSB_RTSSB_TXSB_CTSSB_DTRSB_RIGND

SA_RInRIA

SA_VNSA_C2NSA_C2P

SB_DSR

SB_CTS

SB_RI

GND

nRIBnRTSB

nCTSB

GNDGNDnDSRB

SB_VNSB_C2NSB_C2P

T3O 1

T1O 2

T2O 3

R2I 4

R2O 5

T2I 6

T1I 7

R1O 8

R1I 9

GND 10

VCC 11

C1+ 12

V+ 13

C1- 14 C2+ 15C2- 16V- 17R5I 18R5O 19T3I 20T4I 21R4O 22R4I 23EN 24SHDN 25R3O 26R3I 27T4O 28U23

MAX211E

C73470n

13 12

U7F

74HCT14

GNDVCCSA_C1PSA_VPSA_C1N

SB_TXSB_DTR

SB_RTS

SB_DCD

SB_RXRXBnDTRBTXBnDCDB

GNDVCCSB_C1PSB_VPSB_C1N

GND

VCC

Push button to causeparallel port interrupt

IN - enable

R11010K

D61N4148

R13410K

GNDPD0PD1PD2PD3PD4PD5PD6PD7

RDOUT

nIOR

nCSP

nRESET

VCC

nINTSEL

RXA

nTXRDYB

INTSPA

VCC

SW1SW PUSHBUTTONBLACK CAP

MONITOR POINTS

1V83

1V86

nTXRDYA

P_D3P_D2

P_D4P_D5P_D6P_D7

VCCnRTSAnDTRATXA

GND

nCTSA

nRIA

nDSRA

nCSA

nIOW

RDOUT

P_A2

P_A3

P_A4

nDCDA


SELECT INTERRUPT TYPE

OUT - latched mode (default)IN - ACK mode

MONITOR POINT

C5810u

C59100n

C60100n

C61100n

C63100n

C64100n

1V84 CAPACITORS FOR LEVEL SHIFTERS

MUST INSERT LINK

C62100n

C650u1

C660u1

12

LK8

LINK

VCC

GND

SA_C1P

SA_C1N

SA_C2P

SA_C2N

GND

VCC

GND

C670u1

C680u1

C690u1

C700u1

C710u1

C720u1

SA_VP

VCC

GND

SA_VN

SB_C1P

SB_C1N

SB_C2P

SB_C2N

SB_VP

VCC

GND

SB_VN

SER


Open Access


ARM DUI 0017C

Board SchematicsA.13 PC Card Interface



B EOI-0011B (PCMCIA.S

Title

PC-Card (PCMCIA) Interface an



PC-CARD CONNECTOR

CARDCON.SCH

A_D[15..0]

A_CA[25..0]

A_nCE[2..1]

A_nIORDA_nIOWRA_RESET

A_nOEA_nWE

A_nVCCENA_VPP2ENA_VPP1EN

B_D[15..0]

B_CA[25..0]

B_nCE[2..1]

B_nIOWRB_RESET

B_nOEB_nWE

B_nVCCENB_VPP2ENB_VPP1EN

A_nCD[2..1]

A_nWAITA_nINPACKA_nREG

A_WP

B_nCD[2..1]

B_nWAITB_nINPACKB_nREG

B_WP

B_nIORD

B_RDY

B_BVD[2..1]

A_RDY

A_BVD[2..1]

A_nREG

A_nIORDA_nIOWRA_RESETA_nWAITA_nINPACK

A_D[15..0]

A_CA[25..0]

A_nCE[2..1]

A_nCD[2..1]

A_BVD[2..1]

P_D0

P_D1

P_D2

P_D3

P_D4

P_D5

P_D6

P_D7

P_D8

P_D9

P_D10

P_D11

P_D12

P_D13

P_D14P_D15

VCC

GND

GND

nSPKROUTnINTR

P_A0

P_A2

P_A3

P_A4

P_A5

P_A6

P_A7

P_A8

P_A9

P_A10

P_A11

P_A12

P_A13

P_A14

P_A15

P_A16

P_A17

P_A18

P_A19

P_A20

P_A21

P_A22

P_A23

GND

VCC

nIOW

nIOR

BALE

AEN

nSBHE

nMEMR

nMEMW

PWRGOOD

NISARST

P_A24

PCCLK

A_*REG 1

A_D3 2

A_*CD1 3

A_D4 4

A_D11 5

A_D5 6

A_D6 7

A_D12 8

A_D13 9

A_D7 10

A_*CE1 11

A_D14 12

A_D15 13

GND 14

A_CA10 15

A_*OE 16

VCC 17

A_*CE2 18

A_CA11 19

A_*IORD 20

A_CA9 21

A_*IOWR 22

A_CA8 23

A_CA17 24

A_CA13 25

A_CA18 26

GND 27

A_CA14 28

A_CA19 29

A_*WE 30

A_CA20 31

A_RDY 32

A_CA21 33

A_CA16 34

A_CA22 35

A_CA15 36

A_CA23 37

A_CA12 38

A_CA24 39

A_CA7 40

A_CA25 41

GND 42

A_CA6 43

A_CA5 44

A_RESET 45

A_CA4 46

A_*WAIT 47

A_CA3 48

A_*INPACK 49

A_CA2 50

A_CA1 51

A_BVD2 52

A_CA0

53

A_BVD1

54

A_D0

55

A_D8

56

A_D1

57

A_D9

58

VCC

59

A_D2

60

A_WP

61

A_D10

62

A_*CD2

63

A_VPP2EN1

64

A_VPP1EN1

65

A_*VCCEN

66

A_GPIO

67

B_GPIO

68

B_*VCCEN

69

B_VPP1EN1

70

B_VPP2EN1

71

B_*REG

72

B_D3

73

B_*CD1

74

GND

75

B_D4

76

B_D11

77

B_D5

78

B_D6

79

B_D12

80

B_D13

81

B_D7

82

B_*CE1

83

B_D14

84

B_D15

85

B_CA10

86

B_*OE

87

VCC

88

B_*CE2

89

B_CA11

90

B_*IORD

91

B_CA9

92

B_*IOWR

93

B_CA8

94

B_CA17

95

B_CA13

96

B_CA18

97

B_CA14

98

B_CA19

99

B_*WE

100

GND

101

B_CA20

102

B_RDY

103

B_CA21

104

B_CA16 105B_CA22 106B_CA15 107VCC 108B_CA23 109B_CA12 110B_CA24 111B_CA7 112B_CA25 113B_CA6 114B_CA5 115B_RESET 116B_CA4 117B_*WAIT 118B_CA3 119B_*INPACK 120B_CA2 121B_CA1 122B_BVD2 123B_CA0 124B_BVD1 125B_D0 126B_D8 127B_D1 128B_D9 129B_D2 130GND 131B_WP 132B_D10 133B_*CD2 134GND 135IRQ15 136IRQ14 137IRQ12 138IRQ11 139IRQ10 140VCC 141IRQ3 142IRQ4 143IRQ5 144IRQ7 145IRQ9 146*ZWS 147*IOCS16 148*MEMCS16 149IOCHRDY 150*RIO 151*INTR 152*SPKROUT 153GND 154SD15 155SD14 156

SD13

157

SD12

158

SD11

159

SD10

160

SD9

161

SD8

162

SD0

163

SD1

164

SD2

165

VCC

166

SD3

167

SD4

168

GND

169

SD5

170

SD6

171

SD7

172

*MEMW

173

*MEMR

174

LA17

175

LA18

176

LA19

177

LA20

178

LA21

179

LA22

180

LA23

181

*SBHE

182

SA0

183

SA1

184

SA2

185

SA3

186

CLK

187

GND

188

RESETDRV

189

SA4

190

VCC

191

SA5

192

SA6

193

SA7

194

SA8

195

SA9

196

SA10

197

SA11

198

SA12

199

SA13

200

SA14

201

SA15

202

SA16

203

AEN

204

BALE

205

*SIOR

206

*SIOW

207

PWRGOOD

208 U25

VG-468

R137100R

R138100R

nIOR

nIOW

BALE

nSBHE

nMEMR

P_A[24..0]

P_D[15..0]

NISARST

PCCLKA_D3

A_D4A_D11

A_nCD1

A_nREG

nIOW

nIOR

BALE

nSBHE

nMEMR

P_A[24..0]

P_D[15..0]

NISARST

PCCLK

GNDGND

R1394K7 R1404K7

nMEMW

INTPCA

INTPCB

RDY

nM16

nIO16

nZWS

A_D5A_D6

A_D7

A_D12A_D13

A_D14A_D15

A_CA8

A_CA9

A_CA10

A_CA11

A_CA13

A_CA14

A_CA17

A_CA18

A_CA19

A_nCE1

A_nCE2

GND

VCCA_nOE

A_nIORD

A_nIOWR

GND

nMEMW

RDY

nM16

nIO16

nZWS

nSPKROUT

INTPCA

INTPCB

VCC

B_D1

B_D2B_D9

B_D10B_nCD2

GNDB_WP

GND

INTPCAINTPCBVCC

RDYnM16nIO16nZWS

nRIO A_nOEA_nWEA_RDYA_WP

A_VPP1ENA_VPP2ENA_nVCCEN

B_nIORDB_nIOWR

B_D[15..0]

B_CA[25..0]

B_nCE[2..1]

B_nCD[2..1]

B_BVD[2..1]

B_nREG

B_RESETB_nWAITB_nINPACK

B_nWEB_RDYB_WP

B_nOE

B_VPP1ENB_VPP2ENB_nVCCEN

B_D0B_D8

B_CA0

B_CA1B_CA2

B_CA3

B_CA4

B_CA5B_CA6

B_CA7

B_CA12

B_CA15

B_CA16B_CA22

B_CA23

B_CA24

B_CA25

VCC

B_RESET

B_nWAIT

B_nINPACK

B_BVD1

B_BVD2

R1414K7 R1424K7 R1434K7 R1444K7 R1454K7

A_CA1A_CA2

A_CA3

A_CA4

A_CA5A_CA6

A_CA7

A_CA12

A_CA16

A_CA20

A_CA21

A_CA22

A_CA23

A_CA24

A_CA25

A_CA15

A_nWE

A_RDY

GND

A_RESET

A_nWAIT

A_nINPACK

A_BVD2

RDYnM16nIO16nZWS

nINTRnRIO

LEDPCA

LEDPCB

R135

470R

R136

470R

D11

LEDYELLOW

D12

LEDYELLOW

3 4

U24B

74HCT14

5 6

U24C

74HCT14

A_GPIO

B_GPIO VCC

VCC

A_D0

A_D1

A_D2

A_D8

A_D9

A_D10

A_CA0

A_nCD2

A_WP

A_BVD1

VCC

A_VPP2EN

A_VPP1EN

A_nVCCEN

A_GPIO

B_GPIO

B_D3

B_D4

B_D5

B_D6

B_D7

B_D11

B_D12

B_D13

B_D14

B_D15

B_CA10

B_nVCCEN

B_VPP1EN

B_VPP2EN

B_nREG

B_nCD1

GND

B_nCE1

B_nOE

VCC

B_CA8

B_CA9

B_CA11

B_CA13

B_CA14

B_CA17

B_CA18

B_CA19

B_CA20

B_CA21

B_nCE2

B_nIORD

B_nIOWR

B_nWE

GND

B_RDY

C7510u

C76100n

C77100n

C78100n


Open Access


ARM DUI 0017C

Board SchematicsA.14 PC Card Connecters and Power Supply



B EOI-0011B (CARDCON.

Title

PC-Card Connector and Powe



R157100K

VCC

PC-CARD SLOT A

GND 1

D3 2

D4 3

D5 4

D6 5

D7 6

*CE1 7

A10 8

*OE 9

A11 10

A9 11

A8 12

A13 13

A14 14

*WE/PGM 15

RDY/*BSY 16

VCC 17

VPP1 18

A16 19

A15 20

A12 21

A7 22

A6 23

A5 24

A4 25

A3 26

A2 27

A1 28

A0 29

D0 30

D1 31

D2 32

WP 33

GND 34

GND 35

*CD1 36

D11 37

D12 38

D13 39

D14 40

D15 41

*CE2 42

NC 43

*IORD 44

*IOWR 45

A17 46

A18 47

A19 48

A20 49

A21 50

VCC 51

VPP2 52

A22 53

A23 54

A24 55

A25 56

NC 57

RESET 58

*WAIT 59

*INPACK 60

*REG 61

BVD2 62

BVD1 63

D8 64

D9 65

D10 66

*CD2 67

GND 68

SK4A

PCMCIA CONNECTOR

A_D3A_D4A_D5A_D6A_D7

A_D11A_D12A_D13A_D14A_D15

A_CA8A_CA9

A_CA10

A_CA11

A_CA13A_CA14

A_CA17A_CA18A_CA19A_CA20A_CA21

GND GNDA_nCD1

A_nCE1A_nCE2

A_nOEA_nIORDA_nIOWR

A_nWEA_RDYA_VCC A_VCCA_VPP A_VPP

POWER SUPPLY CARD A

1 V87

VCC3IN 1

VCCOUT 2

VCC3IN 3

GND 4

VCC5EN 5

VCC3EN 6

EN0 7

EN1 8 FLAG 9NC 10NC 11VPPIN 12VPPOUT 13VCCOUT 14VCC5IN 15VCCOUT 16U26

MIC2560-1BWM

R15910K

A 1

C 2

B 3

LK13

SMLINK

A_VPP1ENA_VPP2EN

A_nVCCEN

A_VCC

GND

VCC

VPPA_VCC3EN

A_VCC

A_VCCA_VPP

A_VCCA_VCC3EN

VCC

GND

A_D[15..0]

A_CA[25..0]

A_nCE[2..1]

A_nIORD

A_nIOWR

A_RESET

A_nOE

A_nWE

A_nVCCEN

A_VPP2EN

A_nOE

A_nIORD

A_nIOWR

A_nWE

A_RESET

A_VPP2EN

A_nVCCEN

A_D[15..0]

A_CA[25..0]

A_nCE[2..1] VDD

A_VPP1EN

B_D[15..0]

B_CA[25..0]

B_nCE[2..1]

A_nCD[2..1]

A_nWAIT

A_nINPACK

A_nREG

A_WP

A_BVD[2..1]

A_RDY

A_nREG

A_RDY

A_nWAIT

A_nINPACK

A_WP

A_VPP1EN

B_D[15..0]

B_CA[25..0]

A_nCD[2..1]

A_BVD[2..1]

B_nCE[2..1]

POWER SUPPLY DECODING

0 5V

nVCCEN A/B_VCC

1 HIGH Z

----------------

VPP1EN VPP2EN A/B_VPP

0 0 0V-------------------------

0 1 5V1 0 12V1 1 HIGH Z

Default to A-C

PC-CARD SLOT B

GND 69

D3 70

D4 71

D5 72

D6 73

D7 74

*CE1 75

A10 76

*OE 77

A11 78

A9 79

A8 80

A13 81

A14 82

*WE/PGM 83

RDY/*BSY 84

VCC 85

VPP1 86

A16 87

A15 88

A12 89

A7 90

A6 91

A5 92

A4 93

A3 94

A2 95

A1 96

A0 97

D0 98

D1 99

D2100

WP101

GND102

GND 103

*CD1 104

D11 105

D12 106

D13 107

D14 108

D15 109

*CE2 110

NC 111

*IORD 112

*IOWR 113

A17 114

A18 115

A19 116

A20 117

A21 118

VCC 119

VPP2 120

A22 121

A23 122

A24 123

A25 124

NC 125

RESET 126

*WAIT 127

*INPACK 128

*REG 129

BVD2 130

BVD1 131

D8 132

D9 133

D10 134

*CD2 135

GND 136

SK4B

PCMCIA CONNECTOR

A_D0A_D1A_D2

A_D8A_D9A_D10

A_CA0A_CA1A_CA2A_CA3A_CA4A_CA5A_CA6A_CA7A_CA12A_CA15A_CA16 A_CA22

A_CA23A_CA24A_CA25

GND GNDA_nCD2

A_nREG

A_RESETA_nWAITA_nINPACK

A_WP

A_BVD1A_BVD2

B_D3GND GND

B_nCD1

R14610K R14710K

R14810K R14910K

R155100K

R156100K

A_VCC

VCC

VCC

R15010K R15110K

B_VCC

B_D4B_D5B_D6B_D7


B_CA3B_CA4B_CA5B_CA6B_CA7

B_CA8B_CA9

B_CA10

B_CA11

B_CA12

B_CA13B_CA14

B_CA15B_CA16

B_CA17B_CA18B_CA19B_CA20B_CA21

B_CA22B_CA23B_CA24B_CA25

B_RESETB_nWAITB_nINPACK

B_nCE2

B_nIORDB_nIOWR

B_nWEB_RDYB_VCC

B_nCE1

B_nOE

B_VCCB_VPPB_VPP

Default to A-C

POWER SUPPLY CARD B

MUST USE MIC2560-1 not -0 or -2

A 1

C 2

B 3

LK12

SMLINK

VCC3IN 1

VCCOUT 2

VCC3IN 3

GND 4

VCC5EN 5

VCC3EN 6

EN0 7

EN1 8 FLAG 9NC 10NC 11VPPIN 12VPPOUT 13VCCOUT 14VCC5IN 15VCCOUT 16U27

MIC2560-1BWM

R15810K

B_VCC3ENB_VCC

VCC

GND

B_nCD[2..1]

B_nIORD

B_nIOWR

B_RESET

B_nWAIT

B_nOE

B_nWE

B_nVCCEN

B_VPP2EN

B_VPP1EN

B_BVD[2..1]

B_RESET

B_nWAIT

B_nIORD

B_nIOWR

B_nWE

B_nOE

B_VPP1EN

B_VPP2EN

B_nVCCEN

B_nCD[2..1]

B_BVD[2..1]

C8010u

C81100n

C82100n

C83100n

C84100n

B_nINPACK

B_nREG

B_WP

B_RDY

B_nREG

B_nINPACK

B_RDY

B_WP

VCC

VDD

VCC

1 V88

C85100n

C86100n

C87100n

C88100n

B_VPP1ENB_VPP2EN

B_nVCCEN

B_VCC

GND

VCC

VPPB_VCC3EN

B_VCC

B_VCCB_VPP

A_VCC B_VCCVPP VPP

C89100n

C90100n

B_D0B_D1B_D2

B_D8B_D9B_D10

B_CA0B_CA1B_CA2 B_nREG

B_BVD1B_BVD2

GNDB_WP

GNDB_nCD2

A_VPP B_VPP

GND GND

R15210K R15310K

R154100K

VCC


Open Access


ARM DUI 0017C

Board SchematicsA.15 APB Slaves



B ARM EOI-0011B (APBSLAV

Title

APB Slaves



R1611K

ARMnFARMnFIQ

VCC

SPARE I/O 1 V96 1 V97

VCC

P_A16

P_A17

P_A18

P_A19

P_A20

P_A21

P_A22

P_A23

CCLK

GND

GND

GND 1

A16+ 2

A17+ 3

P4 4

P5 5

P6 6

P7 7

NC 8

NC 9

GND 10

P11 11

P12 12

P13 13

P14 14

P15 15

P16 16

P17 17

P18 18

GND 19

VCC 20

P21 21

P22 22

P23 23

P24 24

P25 25

P26 26

P27 27

P28 28

GND 29

NC 30

NC 31

P32 32

P33 33

P34 34

P35 35

P36 36

P37 37

M1 38

GND 39

M0 40

VCC

41

M2

42

P43

43

HDC

44

P45

45

P46

46

P47

47

LDC

48

NC49NC50

GND

51

P52

52

P53

53

P54

54

P55

55

P56

56

P57

57

P58

58

INIT

59

VCC

60

GND

61

P62

62

P63

63

P64

64

P65

65

P66

66

P67

67

P68

68

P69

69

GND

70

NC71NC72

P73

73

P74

74

P75

75

P76

76

P77

77

P78

78

GND

79

DONE

80

VCC 81PROG 82D7+ 83P84 84P85 85P86 86D6+ 87P88 88NC 89NC 90GND 91P92 92P93 93D5+ 94CSO+ 95P96 96P97 97D4+ 98P99 99VCC 100GND 101D3+ 102RS+ 103P104 104P105 105D2+ 106P107 107P108 108P109 109GND 110NC 111NC 112D1+ 113RCLK+ 114P115 115P116 116D0/DIN 117DOUT+ 118CCLK 119VCC 120

TDO

121

GND

122

A0/WS+

123

A1+

124

P125

125

P126

126

A2/CS1+

127

A3+

128

NC

129

NC

130

GND

131

P132

132

P133

133

A4+

134

A5+

135

NC

136

P137

137

P138

138

A6+

139

A7+

140

GND

141

VCC

142

A8+

143

A9+

144

P145

145

P146

146

A10+

147

A11+

148

P149

149

P150

150

GND

151

NC

152

NC

153

A12+

154

A13+

155

P156

156

P157

157

A14+

158

A15+

159

VCC

160 U29

XC4005PQ160-4PC

P_A0

P_A1

P_A2

P_A3

P_A4

P_A5

P_A6

P_A7

P_A8

P_A9

P_A10

P_A11

P_A12

P_A13

P_A14

P_A15

VCC

VCC

GND

GND

SPARE I/O

APB SIGNALS

1V92

1V94 1V95

P_D[31..0]

P_A[31..0]

P_WRITE

P_STB

P_SELIC

P_SELCT

P_SELRC

P_SELEX

B_RES[2..0]

B_CLK0

GND

P_A[31..0]

P_D[31..0]

P_WRITE

P_STB

P_SELIC

P_SELCT

P_SELRC

P_SELEX

B_RES[2..0]

B_CLK0B_CLK0

INTERRUPT SOURCES

INTPCA

INTPCB

INTSPA

INTSPB

nINTPP

nFIQSRC

nINTAPB[2..0]

nINTASB[1..0]

ARMCOMMRX

ARMCOMMTX

P_D1P_D2P_D3P_D4P_D5P_D6P_D7

P_D8P_D9P_D10P_D11P_D12P_D13P_D14P_D15

P_D16P_D17P_D18P_D19

VCCGND

GND

nINTAPB[2..0]

nFIQSRC

INTPCA

INTPCB

INTSPA

INTSPB

nINTPP

nINTASB[1..0]

ARMCOMMRX

ARMCOMMTX

SPARE I/O 1 V89

P_D20P_D21P_D22P_D23

P_D24P_D25P_D26P_D27P_D28P_D29P_D30P_D31

GND

GNDVCC

INTSPAINTSPBINTPCAINTPCB

DIN

ARMCOMMTXARMCOMMRX

STANDBY =

R1661K

REMAP

ARMnI

STANDBY

REMAP

ARMnIRQ

STANDBY

VCC

VCC

FPGA CONF

SERIAL P

DATA 1

CLK 2

OE 3

CE 4 GNDCEOVPPVCC

U28

XC17128D

9 8

U24D

74HCT14

R1991K

DONE

DINCCLKnPROG

GND

VCC

GND

DONE

GND

P_A24

P_A25

P_A26

P_A27

nFIQSRC

nINTPPnINTASB0nINTASB1

nINTAPB2

nINTAPB0nINTAPB1

nPROG

GND

VCC

GND

VCC

MODE2

P_A28

P_A29

P_A30

P_A31

P_STB

P_WRITE

P_SELIC

P_SELCT

P_SELRC

P_SELEX

INIT

REMAP

STANDBY

ARMnFIQ

ARMnIRQ

SPARE I/O

DOWNLOAD CABLE

CONNECTOR

1V90 1V91

1V93

R1624K71

23456789

J2

CON9

R1674K7

R1684K7

P_D0

MODE0

MODE1

B_RES0B_RES1B_RES2

GND

GND

CCLK

VCCGND

DONE

VCC VCC VCC

Insert links 3-4, 5-6, 7-8to enable serial PROM

Cut pin 3

R1634K7

R1644K7

R1654K7

1 V107

+ 1

+ 3

+ 5

+ 7

+ 2

+ 4

+ 6

+ 8

LK16

LINK-4

INIT

MODE0MODE1MODE2

DINnPROG

RST

INIT

VCC VCC VCC

GND

SPARE I/O

C91100n

C92100n

C93100n

C9510u

1V104 1V105 1V106SPARE I/O

C94100n

1 V98 1 V99 1 V100 1 V101 1 V102 1 V103

VCC

GND

DONE

VCC

GND

R160

470R

D13

LEDGREE


Open Access


ARM DUI 0017C

Board SchematicsA.16 APB Expansion Connecters



B EOI-0011B (APBEXP.S

Title

APB Expansion Connec



+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD5

CON20AP

1V114

1V128

1 V130 1 V131

VCCP_STB

VCC

LOGIC ANALYSER PODS

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD1

CON20AP

1V108 VCC

P_D13P_D14P_D15B_CLK1

VCC

P_A[31..0] P_A[31..0]

P_D[31..0]

P_WRITE

P_STB

P_SELIC

P_SELCT

P_SELRC

P_SELEX

B_RES[2..0]

nFIQSRC

nB_CLK1

B_CLK1

P_D[31..0]

P_WRITE

P_STB

P_SELEX

B_RES[2..0]

nFIQSRC

P_SELIC

P_SELCT

P_SELRC

nB_CLK1

B_CLK1

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD2

CON20AP

1V109 1V111

GND

GND

VCC

P_D0P_D1P_D2P_D3P_D4P_D5P_D6P_D7P_D8P_D9P_D10P_D11P_D12

P_D16P_D17P_D18P_D19P_D20P_D21P_D22P_D23P_D24P_D25P_D26P_D27P_D28P_D29P_D30P_D31

GND

VCC

GND

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD6

CON20AP

1V115

1V116 1V117 1V118 1V119 1V120 1V121

1 V122 1 V123 1 V124 1 V125 1 V126 1 V127

1V129

1 V132 1 V133 1V134 1V135

1V136

GND

GND

VCC

B_RES0B_RES1 B_RES2

P_WRITEP_SELEXP_SELRC

P_SELCTP_SELICnFIQSRC

nINTAPB0nINTAPB1nINTAPB2

GND

VCC

GND

NOTE: PIN 1 OF ALL

5V ON ANALYSER

PODS CONNECTS TO

PIN 2 IS TRIGGER

R1691K

R1721K

nFIQSRC nINTAPB2

VCC VCC

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD3

CON20AP

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD4

CON20AP

1V110

1V112 1V113

GND

VCC

VCC

P_A0P_A1P_A2P_A3P_A4P_A5P_A6P_A7P_A8P_A9P_A10P_A11P_A12P_A13P_A14P_A15

P_A17P_A18P_A19P_A20P_A21P_A22P_A23P_A24P_A25P_A26P_A27P_A28P_A29P_A30P_A31

nB_CLK1VCC

GND

VCC

nINTAPB[2..0]nINTAPB[2..0]

GNDP_A16 GND

PULLUPS ON INTERRUPTS

R1701K

R1711K

nINTAPB0 nINTAPB1

VCC VCC


Open Access


ARM DUI 0017C

Board SchematicsA.17 APB Buffers



B EOI-0011B (APBBUF.S

Title

APB Buffers



1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27

2OEAB 28 2OEBA 292LEBA 302CEBA 31GND 322B7 332B6 34VCC 352B5 362B4 372B3 38GND 392B2 402B1 412B0 421B7 431B6 441B5 45GND 461B4 471B3 481B2 49VCC 501B1 511B0 52GND 531CEBA 541LEBA 551OEBA 56U32

FCT16543

R173

10KGNDGNDnP_ALEN

GND

GND

B_A0B_A1 P_A1

P_A0

VCC

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

P_D[31..0]

P_A[31..26]

P_A[22..9]

P_A[1..0]

nB_DENnP_DLENGNDGNDP_D0P_D1

nB_DEN

nB_DLEN

nP_DEN

nP_DLEN

B_D[31..0]

B_A[31..0]

nP_ALEN

B_D0B_D1

GNDGND

nP_DENnB_DLEN

nB_DEN

nB_DLEN

nP_DEN

nP_DLEN

B_D[31..0]

B_A[31..0]

P_D[31..0]

nP_ALEN

P_A[31..26]

P_A[22..9]

P_A[1..0]

B_D2B_D3B_D4

B_D5B_D6B_D7B_D8B_D9B_D10

B_D11B_D12B_D13

B_D14B_D15

VCC

GND

GND

VCC

GNDGNDnB_DLENnP_DEN

VCC

GND

VCC

GND

GND

GND

nB_DENnP_DLEN

P_D2P_D3P_D4

P_D5P_D6P_D7P_D8P_D9P_D10

P_D11P_D12P_D13

P_D14P_D15

R174

10K

1 V137 1 V138 1 V139

1 V140 1 V141 1 V142 1 V143

VCC

GND

GND

VCC

GNDGND

VCC

GND

VCC

GND

GND

nP_ALENGND

B_A2B_A3B_A4

B_A5B_A6B_A7B_A8B_A9B_A10

B_A11B_A12B_A13

B_A14B_A15

P_A10

P_A11P_A12P_A13

P_A14P_A15

P_A9

VCC

GENERATED IN APB BRIDGE

P_A 25..23, 8..2 ARE ALL

GENERATED IN APB BRIDGE

P_A 25..23, 8..2 ARE ALL

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

R175

10K

1 V144 1 V145 1 V146

GND

VCC

GND

GND

GNDnP_ALEN

GND

VCC

GND

GND

GND

B_A16B_A17

B_A18B_A19B_A20


B_A27B_A28

P_A16P_A17

P_A18P_A19P_A20

P_A21P_A22

P_A26

P_A27P_A28

VCC

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

nB_DENnP_DLENGNDGND

VCC

GND

GND

P_D16P_D17

P_D18P_D19P_D20

P_D21P_D22P_D23P_D24P_D25P_D26

P_D27P_D28

GND

VCC

GND

GND

GND

nP_DENnB_DLEN

B_D16B_D17

B_D18B_D19B_D20


B_D27B_D28

C110100n

C111100n

C114100n

C115100n

C116100n

C117100n

VCC

GNDGNDnB_DLENnP_DEN

B_D29

B_D30B_D31

C112100n

C113100n

VCC

GNDGND

nB_DENnP_DLEN

P_D29

P_D30P_D31

VCC

GND

VCC

GND

R176

10K

VCC

GNDGND

VCC

GND

nP_ALENGND

B_A29

B_A30B_A31

P_A29

P_A30P_A31

VCC


Open Access


ARM DUI 0017C

Board SchematicsA.18 Memory Address and Data Buffers



B EOI-0011B (MEMBUF.S

Title

Address and Data Buf



M_D[31..0

M_A[17..2]

M_D[31..0]

M_A[17..2]

ADDRESS REGISTER

1OE 1

1O0 2

1O1 3

GND 4

1O2 5

1O3 6

VCC 7

1O4 8

1O5 9

GND 10

1O6 11

1O7 12

2O0 13

2O1 14

GND 15

2O2 16

2O3 17

VCC 18

2O4 19

2O5 20

GND 21

2O6 22

2O7 23

2OE 24 2CLK 252D7 262D6 27GND 282D5 292D4 30VCC 312D3 322D2 33GND 342D1 352D0 361D7 371D6 38GND 391D5 401D4 41VCC 421D3 431D2 44GND 451D1 461D0 471CLK 48U34

FCT16374

GNDM_A2M_A3

B_A2B_A3

nB_CLK6

DATA BUFFERS

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

GNDGNDGND

GND

nOEMD nOEBD

B_A[17..2]

B_D[31..0]

nOEMD

nOEBD

nB_CLK6

B_A[17..2]

B_D[31..0]

nOEMD

nOEBD

nB_CLK6

M_D0M_D1

M_D2M_D3M_D4


M_D11M_D12M_D13

M_D14M_D15

B_D0B_D1

B_D2B_D3B_D4


B_D11B_D12B_D13

B_D14B_D15

GND

GND

GND

GNDGND GND

GNDGND

GND

GND

GND

GND

VCC

VCC

VCC

VCC

GND

VCC

GND

GND

GND

GND

GND

GND

GND

GND

VCC

VCC

VCC

M_A4M_A5

M_A6M_A7

M_A8M_A9M_A10M_A11

M_A12M_A13

M_A14M_A15

B_A4B_A5

B_A6B_A7

B_A8B_A9B_A10B_A11

B_A12B_A13

B_A14B_A15

M_A16M_A17

B_A16B_A17nB_CLK6

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

nOEMD nOEBD

GND

GND

GND

GNDGNDGND

GNDGND

GND

GND

VCC VCC

nOEMD nOEBD

B_D16B_D17

B_D18B_D19B_D20


M_D16M_D17

M_D18M_D19M_D20


C118100n

C119100n

C120100n

C121100n

C122100n

C123100n

VCC

GND

GNDGND GND

GNDGND

GND

VCC VCC

nOEMD nOEBD

B_D27B_D28B_D29

B_D30B_D31

M_D27M_D28M_D29

M_D30M_D31

VCC

GND


Open Access


ARM DUI 0017C

Board SchematicsA.19 Test Interface Controller and Connecters



B ARM EOI-0011B (TIC.

Title

Test Interface Controller an



1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

GND

GND

GND

VCC

B_D16B_D17

B_D18B_D19B_D20


B_D27

nTICEN

nT_DENGND

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

GND

GND

GND

VCC

GND

GND

GND

VCC

GND

GND

GND

VCC

T_D0T_D1

T_D2T_D3T_D4

T_D5T_D6T_D7T_D8T_D9T_D10

T_D11

T_D16T_D17

T_D18T_D19T_D20


T_D27

B_D0B_D1

B_D2B_D3B_D4


B_D11

nB_DENnB_DLENnTICEN

nB_DENnB_DLENnTICEN

nT_DENGNDnTICEN

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

R181

10KGND

GND

GND

VCC

GND

GND

GND

VCC

T_D16T_D17

T_D18T_D19T_D20


T_D27

B_A16B_A17

B_A18B_A19B_A20


B_A27

nB_AENnB_ALENnTICEN

VCC VCC

1OEAB 1

1LEAB 2

1CEAB 3

GND 4

1A0 5

1A1 6

VCC 7

1A2 8

1A3 9

1A4 10

GND 11

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

GND 18

2A3 19

2A4 20

2A5 21

VCC 22

2A6 23

2A7 24

GND 25

2CEAB 26

2LEAB 27


FCT16543

R180

10KGND

GND

GND

VCC

GND

GND

GND

VCC

T_D0T_D1

T_D2T_D3T_D4


T_D11

B_A0B_A1

B_A2B_A3B_A4


B_A11

nB_AENnB_ALENnTICEN

ADDRESS TRANSCEIVERS

R183

10K

A_GNTTIC

nB_CLK9

B_CLK9

B_RES[1..0]

VCC

GND

VCC

GND

T_D12T_D13

T_D14T_D15

B_A12B_A13

B_A14B_A15

nTICENnB_ALENnB_AEN

A_GNTTIC

B_CLK9

nB_CLK9

B_RES[1..0]

TEST INTERFACE CONTROLLER

R182

10K

1V168

1V170

1V169

1V171

VCC

GND

VCC

GND

T_D28T_D29

T_D30T_D31

B_A28B_A29

B_A30B_A31

nTICENnB_ALENnB_AEN

VCCVCCDATA TRANSCEIVERS

VCC

GND

VCC

GND

VCC

GND

T_D12T_D13

T_D14T_D15

T_D28T_D29

T_D30T_D31

B_D12B_D13

B_D14B_D15

nTICENnB_DLENnB_DEN

nTICENnB_DLENnB_DEN

nTICEN

nT_DENGND

TEST INTERFACE HEADER

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

TEST1

CON20AP

VCC

VCC

GND

B_D28B_D29

B_D30B_D31

nTICEN

nT_DENGND

T_CLK

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

TEST2

CON20AP

GND

GND

VCC

T_D0T_D1T_D2T_D3T_D4T_D5T_D6T_D7T_D8T_D9T_D10T_D1T_D12T_D1T_D14T_D1

T_D16T_D1T_D18T_D1T_D20T_D2T_D22T_D2T_D24T_D2T_D26T_D2T_D28T_D2T_D30T_D3

T_REQAT_REQB

T_ACK

ENABLE TRANSCEIVERS

SPARE I/O

nTICEN IS DRIVEN LOW TO

INSERT LINK TO USE TIC

1 V167

R17910K

1 V175

VCC

MONITOR POINTS

IO5 7

IO6 8

IO7 9

I0 10

I1 11

GND 12

CLK0/I2 13

IO8 14

IO9 15

IO10 16

IO11 17

IO12

18

IO13

19

IO14

20

IO15

21

VCC

22

GND

23

IO16

24

IO17

25

IO18

26

IO19

27

IO20

28


IO28

40

IO29

41

IO30

42

IO31

43

VCC

44

GND

1

IO0

2

IO1

3

IO2

4

IO3

5

IO4

6 U37

MACH210A-7

1V172 1V173 1V174 ADDRV

GRANTED

B_ERRORB_LASTB_WAITT_REQAT_REQBGND

T_ACK B_RES0

GND

WRITE

READ

VCC

GNDQ

0Q1

Q2

A_REQTIC

A_GNTTIC

nTICEN

B_CLK9

nB_CLK9

B_RES1

T_CLACK

nUSETIC

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_PROT[1..0]

B_LOCK

B_WAIT

A_REQTIC

B_LAST

B_ERROR

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_PROT[1..0]

B_LOCK

B_WAIT

A_REQTIC

B_ERROR

B_LAST

MONITOR POINT

1V176

C12410u

C125100n

C126100n

C127100n

C128100n

C129100n

C130100n

VCC

GND

B_WRITE

B_PROT0

B_PROT1

B_SIZE0

B_SIZE1

B_LOCKB_TRAN0B_TRAN1

nB_DLEN

nT_DEN

nB_AEN

nB_ALEN

nB_DEN

TESTMODET_CLK

VCC

GND

VCC

GND

OUT = TIC disabled (default)IN = TIC enabled

R19410K

12

LK17

LINK

nUSETIC

VCC

GND

DO NOT CONNECT LOGIC AN

TO THESE HEADERS


Open Access


ARM DUI 0017C

Board SchematicsA.20 Master Header Connecters and Level Converters



B ARM EOI-0011B (MASTER

Title

ARM Master Header and Level



+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

PL9

CON60AP

GND

GND

CPBCPAGND

GND

COMMTX

TRAN0

nCPI

ERRORMCLK

nIRQ

COMM

TRAN

WAIT

nFIQ

LAST

RES1RES0

RES2

BENDnICE

ISYNC

HEADER CONNECTORS

(TDO)(TMS)(TDI)

(TCK)

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

PL8

CON60AP

D0D2D3

D11D12

D15D17D18D20D21

D5D6D8D9

D14

GND

GND

GND

EXTERN1EXTERN0

REQARMGNTARMREQ001GNT001

nTRST

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

PL6

CON60AP

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

PL7

CON60AP

A0A2A3A5A6A8A9A11A12A14A15A17A18A20A21A23A24A26A27

GND

GNDD1

GND

D10GNDD13

D16GNDD19

D4

D7

B_WRITE

B_TRAN[1..0]

B_LOCK

B_SIZE[1..0]

B_PROT[1..0]

A_GNTARM

A_GNT001

B_A[31..0]

B_D[31..0]

B_RES[2..0]

B_CLK6

A_GNTARM

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_RES[2..0]

B_PROT[1..0]

B_LOCK

GNDA1

A4GNDA7

A10GNDA13

A16GNDA19

A22GNDA25

A_GNT001

B_CLK6

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9

GND 10 B7 11B6 12B5 13B4 14B3 15B2 16B1 17B0 18OE 19VCC 20U44

QS3245

B_WAIT

B_LAST

B_ERROR

ARMnFIQ

ARMnIRQ

BIGEND

nJTRST

ARMnFIQ

ARMnIRQ

B_WAIT

B_LAST

B_ERROR

A28GNDA31

SIZE1GNDPROT0

GNDA0A1A2A3A4A5A6A7

B_A0B_A1B_A2B_A3B_A4B_A5B_A6

BIGEND

VLL1 VLL1

nJTRST

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

A29A30WRITESIZE0PROT1LOCKVDD

D22GNDD25

GNDD28

D31

GNDA16A17A18A19A20A21A22A23


D0D1D2D3D4D5D6D7

VLL2 VLL2 VLL3 OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

D23D24

VDD

D26D27D29D30

VDD

GND

GND D16D17D18D19D20D21D22D23

B_D0B_D1B_D2B_D3B_D4B_D5B_D6

VLL3 VLL4

MONI

VDD

ISYN

GND

VCC

GNDB_D16B_D17B_D18B_D19

B_D21B_D22

B_D20

CPAnCPI

CPBEXTEEXTE

VLL4

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

1

1 1

A_REQARM

A_REQ001GND

B_D23

B_D24B_D25B_D26B_D27B_D28B_D29B_D30B_D31

ARMCOMMT

ARMCOMMR

GNDnSYSRST

nSYSRST

VLL4

VLL8

nTRST

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

1V191 1V192 1V193 1V194

GND

GND

GND

D24D25D26D27D28D29D30D31

B_D7

B_D8B_D9B_D10B_D11B_D12B_D13B_D14B_D15

GNDB_RES0B_RES1B_RES2B_WAITB_ERROR

nICERST

VLL3 VLL4

VLL7VLL8

nJTRST

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

GND

GND


B_A23

B_A24B_A25B_A26B_A27B_A28B_A29B_A30B_A31

GND

GND

D8D9D10D11D12D13D14D15

GNDREQARMGNTARMREQ001GNT001

A_REQARMA_GNTARMA_REQ001A_GNT001nFIQ

nIRQ ARMnFIQ

RES0RES1RES2WAITERRORLAST

VLL2 VLL2 VLL3

VLL6 VLL6 VLL7

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

GND

GND


B_A7


GNDSIZE0SIZE1PROT0PROT1WRITELOCK

B_SIZE0B_SIZE1B_PROT0B_PROT1B_WRITE

VLL1 VLL1

VLL5 VLL5

C9610n

R1842K2

D14

1N4001

C9710n

R1852K2

D15

1N4001

C9810n

D16

1N4001

GND

B_LOCKTRAN0TRAN1 B_TRAN0

B_TRAN1

VLL1 VLL2 VLL3

VCC VCC VCC

GND GND

LEVEL SHIFTER INDIVIDUAL POWER SUPPLIES

LEVEL SHIFTERS 5V -> 4.3V

R1862K2

C9910n

R1872K2

D17

1N4001

C10010n

R1882K2

D18

1N4001

C10110n

D19

1N4001

GND GND

COMMRXCOMMTX ARMCOMMRX

ARMCOMMTX

ARMnIRQ MCLKBEND

VLL4 VLL5 VLL6

VCC VCC VCC

GND GND GND

R1892K2

C10210n

R1902K2

D20

1N4001

C10310n

R1912K2

D21

1N4001

1V195 1V196

B_LAST

BIGENDGND

B_CLK6

VLL7 VLL8

VCC VCC

GND GND GND

SPARE LEVEL SHIFTERS

1 1

1


Open Access


ARM DUI 0017C

Board SchematicsA.21 System Modules (Arbiter and Decoder)



B EOI-0011B (SYSMODS.

Title

System Modules



GND

VCC

A_GNTTIC

A_GNTARM

A_GNT001

A_GNT002

B_ERROR

nJTRST

ARBITER AND RESET CONTROLLER

IO5 7

IO6 8

IO7 9

I0 10

I1 11

GND 12

CLK0/I2 13

IO8 14

IO9 15

IO10 16

IO11 17

IO12

18

IO13

19

IO14

20

IO15

21

VCC

22

GND

23

IO16

24

IO17

25

IO18

26

IO19

27

IO20

28


IO28

40

IO29

41

IO30

42

IO31

43

VCC

44

GND

1

IO0

2

IO1

3

IO2

4

IO3

5

IO4

6 U54

MACH210A-7

EXTPOR

A_REQTIC

A_REQARM

AREQ1

AREQ2

GND

Default B-C Default B-C

TIE REQUEST LOW, MOVE IF USED

A 1

C 2

B 3

LK14

SMLINK

A 1

C 2

B 3

LK15

SMLINK

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

D_SELASB0

D_SELASB1

A_REQ001AREQ1

A_REQ002AREQ2

GND

B_A[31..2]

B_TRAN[1..0]

B_WAIT

B_LAST

B_ERROR

nB_CLK[8..7]

nENASB[1..0]

B_LOCK

B_TRAN[1..0]

B_WAIT

B_LAST

B_ERROR

B_A[31..2] D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

D_SELASB0

D_SELASB1nB_CLK[8..7]

nENASB[1..0]

B_LOCK

DECODER

REMAP

STANDBY

A_REQTIC

A_REQARM

A_REQ001

A_REQ002

nSYSRST

B_CLK5

B_CLK7

B_RES[2..0]

REMAP

STANDBY

A_REQTIC

A_REQARM

A_REQ001

A_REQ002

A_GNTTIC

A_GNTARM

A_GNT001

A_GNT002

nSYSRST NISARST

B_CLK5

nJTRST

B_CLK7

A_GNTTIC

A_GNTARM

A_GNT001

A_GNT002

B_RES[2..0]

NISARST

nJTRST

VCC

REMAP12

LK18

LINK

R21010K

OUT - always remappedIN - remap enabled (default)

REMAPPED

GND

B_A7

B_A8

B_A9

B_A10

B_A11B_A12

BOUNDARYSTANDBY

nB_CLK8

nSYSRSTD_SELASB0

B_WAITB_LAST

GND

VCC

GND

B_RES0B_RES1B_RES2

B_A2

B_A3

B_A4

B_A5

B_A6

D_SELASB1nENASB0

nENASB1

B_CLK7

B_LOCK

NISARST

RESET MONITOR POINT

1 V207

1 V208

EXTPOR

nEXTPOR

D221N4148

R196100K

C1094u7

11 10

U24E

74HCT14

13 12

U24F

74HCT14

SPARE GATE

VCC

THESE SERIES RESISTORS

ARE AN ATTEMPT TO DAMP

REFLECTIONS AND INCREASE

OVERALL SYSTEM SPEED

SW2SW PUSHBUTTONRED CAP

R200

33R

R201

33R

B_A15B_A16B_A17B_A18

GNDnB_CLK7

D_SELASB0

D_SELASB1

SELASB0

SELASB1

IO5 7

IO6 8

IO7 9

I0 10

I1 11

GND 12

CLK0/I2 13

IO8 14

IO9 15

IO10 16

IO11 17

IO12

18

IO13

19

IO14

20

IO15

21

VCC

22

GND

23

IO16

24

IO17

25

IO18

26

IO19

27

IO20

28


IO28

40

IO29

41

IO30

42

IO31

43

VCC

44

GND

1

IO0

2

IO1

3

IO2

4

IO3

5

IO4

6 U55

MACH210A-7

D_SELAPB

D_SELDRAM

D_SELSRAM

GND

VCC

B_A13

B_A14

GNDB_TRAN0B_TRAN1D_SELROM

D_SELSSRAMD_SELNISA

SELASB1

SELASB0

WAIT

LAST

BOUNDARY

B_A22

B_A23

B_A24

B_A25

B_A26

B_A27

B_A28

B_A29B_A30B_A31

VCC

GND

B_CLK5

ERROR

REMAPPED

C10410u

R202

33R

R203

33R

R204

33R

B_A19B_A20B_A21

B_RES0B_RES1

B_WAIT

B_LAST

B_ERROR

WAIT

LAST

ERROR


C105100n

C106100n

C107100n

C108100n

VCC

GND

GND

VCC

GND


Open Access


ARM DUI 0017C

Board SchematicsA.22 ASB Expansion Connecters



B EOI-0011B (ASBEXP.S

Title

ASB Expansion Connec



VCC

B_PROT0B_RES0B_RES2B_WAITB_ERRORD_SELASB1

VCC+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD11

CON20AP

1V148

1V155

B_PROT1B_RES1B_LOCKB_LASTD_SELASB0

VCC

LOGIC ANALYSER PODS

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD7

CON20AP

1V147 VCC

B_D5B_D6B_D7B_D8B_D9B_D10B_D11B_D12B_D13B_D14B_D15B_CLK10

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_RES[2..0]

B_WAIT

B_LOCK

B_PROT[1..0]

B_TRAN[1..0]

B_LAST

B_ERROR

D_SELASB0

B_A[31..0]

B_D[31..0]

B_WRITE

B_SIZE[1..0]

B_TRAN[1..0]

B_RES[2..0]

B_PROT[1..0]

B_LOCK

B_WAIT

B_LAST

B_ERROR

D_SELASB0

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD8

CON20AP

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD9

CON20AP

1V149 1V150

1V151 VCC

GND

GND

VCC


B_D16B_D17B_D18B_D19B_D20B_D21B_D22B_D23B_D24B_D25B_D26B_D27B_D28B_D29B_D30B_D31

B_A13B_A14B_A15nB_CLK10 NOTE: PIN 1 OF ALL

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD12

CON20AP

1V152

1V156

B_WRITEB_SIZE1B_TRAN1

A_REQ001A_GNT001nINTASB0

nFIQSRCnENASB0

D_SELSRAMD_SELROMD_SELNISA

VCC

GND

VCC

GND

1 V161

GND

GND

VCC

B_SIZE0B_TRAN0

A_REQ002A_GNT002

nENASB1nINTASB1

D_SELSSRAMD_SELDRAMD_SELAPB

GND

VCC

GND

PULL nENASB[1

R1781K

nINTASB1

VCC

VCC

5V ON ANALYSER

PODS CONNECTS TO

PIN 2 IS TRIGGER

R1771K

nINTASB0

VCC

VCC

GND

VCC

GND

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD10

CON20AP

1V153 1V154

GNDB_A0B_A1B_A2B_A3B_A4B_A5B_A6B_A7B_A8B_A9B_A10B_A11B_A12

GND

VCC

B_A16B_A17B_A18B_A19B_A20B_A21B_A22B_A23B_A24B_A25B_A26B_A27B_A28B_A29B_A30B_A31

A_GNT001

A_GNT002

D_SELASB1

B_CLK10

nB_CLK10

D_SELSSRAM

D_SELSRAM

D_SELROM

D_SELDRAM

D_SELAPB

D_SELNISA

A_GNT001

A_GNT002

D_SELASB1

B_CLK10

nB_CLK10

D_SELSSRAM

D_SELSRAM

D_SELDRAM

D_SELROM

D_SELAPB

D_SELNISA

nINTASB[1..0]

nFIQSRC

A_REQ001

A_REQ002

nENASB[1..0]

A_REQ001

A_REQ002

nINTASB[1..0]

nFIQSRC

nENASB[1..0]

R19310K

nENASB0

WHEN USING AS

DEVICES

R19210K

nENASB1


Open Access

B-1ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

The daughter board design comprises the seven schematics as listed below. There are two versions of the processor schematic according to whether you have a QFP or PGA packaged part on the board.

B.1 Card Outline Drawing B-2B.2 Top-level Diagram B-3

B.3 Header Connecters B-4B.4 Logic Analyser Connecters B-5B.5 AMBA Bus Master Veneer B-6

B.6 Processor in QFP Package B-7B.7 Processor in PGA Package B-8B.8 EmbeddedICE Interface B-9

Daughter Board SchematicsB

hrg.

book

Pag

e 1

Wed

nesd

ay, J

uly

22, 1

998

9:1

8 A

M

Open Access

B-2 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

Daughter Board SchematicsB.1 Card Outline Drawing

Date: June 14, 1996 Sheet


B EOI-0016B (DRAWING.

Title

Header Card Outline Dr



EMB ICE

HEADER CONNECTORS EMBEDDED ICE INTERFACE

3.6

2.40.6

0.6

1.6

4.5

2.4

1.3

1.3

0.3

1.6 TEST CHIP

POD5

POD6

SK4

SK3

U5 U6 U7 U8

U9

1

1

1 POD1

POD2

SK2

1

POD4

QS3245

QS3245

MACH215POD3

SURFACE MOUNT LINKS

LK2 LK3

SK1

LK1

LK4

1

1.3

0.3

ALL DIMENSIONS IN INCHES


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.2 Top-level Diagram



B ARM EOI-0016B (CHAMPQF

Title

ARM7T Development Board He



LOGIC ANALYSER PODS BLOCK

LAPODS.SCH

nIRQ

A[31..0]

MCLK

D[31..0]

nFIQ

SIZE[1..0]

PROT[1..0]

WRITE

LOCK

PIPEF

nEXEC

nMREQ

SEQ

RES1

nCPI

ABORT

nM[4..0]

DBGACK

TBIT

ECLK

CPA

CPB

TRAN[1..0]

nPWAIT

A[31..0]

D[31..0]

WRITE

SIZE[1..0]

PROT[1..0]

LOCK

MCLK

nFIQ

nIRQ

PIPEF

RES[1..0]

WAIT

MCLK

LAST

ERROR

BIGEND

ISYNC

RES1

nPWAIT

HEADER CARD CONNECTOR BLOCK

HDRCONN.SCH

TRAN[1..0]

A[31..0]

WRITE

SIZE[1..0]

PROT[1..0]

LOCK

RES[1..0]

MCLK

WAIT

LAST

ERROR

nFIQ

nIRQ

BIGEND

ISYNC

REQARM

nCPI

COMMTX

COMMRX

CPA

CPB

GNTARM

EXTERN[1..0]

nICERST

D[31..0]

nTRSTnMABE

A[31..0]

D[31..0]

WRITE

SIZE[1..0]

TRAN[1..0]

PROT[1..0]

LOCK

SEQ

nMREQ

A[31..0]

D[31..0]

WRITE

SIZE[1..0]

TRAN[1..0]

PROT[1..0]

LOCK

nICERST

PROCESSOR BLOCK

PROCQFP.SCH

D[31..0]

A[31..0]

WRITE

SIZE[1..0]

PROT[1..0]

LOCK

nMREQ

SEQ

nM[4..0]

nEXEC

TBIT

DBGACK

ECLK

COMMTX

COMMRX

TDOTDI

TMS

TCK

nTRST

MCLK

WAIT

nWAIT

WSEL

MTBE

MDBE

BIGEND

ISYNC

nFIQ

nIRQ

ABORT

RES1

TMUX[1..0]

CPA

CPB

EXTERN[1..0]

nCPI

BMEN[1..0]

TRAN[1..0]

MTBE

MDBE

WSEL

WAIT

MCLK

nWAIT

ABORT

RES1

TDI

TCK

TMS

nTRST

BIGEND

ISYNC

nFIQ

nIRQ

TMUX[1..0]

AMBA VENEER BLOCK

AMBAPLD.SCH

MCLK

MTBE

MDBEWAIT

WSEL

nWAIT

PIPEF

ABORT

TMUX[1..0]

REQARM

BMEN[1..0]

SEQ

nMREQ

LOCK

WRITE

PROT[1..0]

RES[1..0]

LAST

ERROR

GNTARMTRAN[1..0]

nMABE

nPWAIT

TDO

nM[4..0]

nEXEC

TBIT

ECLK

DBGACK

COMMRX

COMMTX

COMMRX

COMMTX

nCPI

REQARM

nMABEnM[4..0]

DBGACK

ABORT

nFIQ

nIRQ

nEXEC

nTRST

EXTERN[1..0]

CPB

CPA

GNTARM

TBIT

ECLK

nMREQ

SEQ

nCPI

CPA

EMBEDDED ICE CONNECTOR

EICE.SCH

TDO TDI

TMS

TCK

nICERST

TDI

TCK

TMS

nICE

MTBE

MDBE

WSEL

nWAIT

ABORT

PIPEF

TDO

TMUX[1..0]

CPB

TRAN[1..0]nMABE

nPWAIT

CAPACITORS

WRITE

MCLK

WAIT

LOCK

nMREQ

SEQ

nCPIRES[1..0]

ERROR

LAST

PROT[1..0]

5V DECOUPLINGC110u

C2100n

C3100n

EXTERN[1..0]

CPB

CPA

BMEN[1..0]

VCC

3V3 DECOUPLING

VCC is system 5V

VDD is system 3V3

VSS is system ground

BOARD OUTLINE

DRAWING.SCH

C610u

C7100n

C8100n

C9100n

C10100n

VDD

VSS

VSS

CAPACITORS

GNTARM

GROUND TEST PINS

TRAN[1..0]

REQARM

BMEN[1..0]

1

TP1TESTPIN

1

TP2TESTPIN

1

TP3TESTP

VSS VSS VSS


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.3 Header Connecters



B ARM EOI-0016B (CPUHEA

Title

Processor and header con



VSSCOMMTX

TRAN0

CO

TR

WA

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

SK4

CON60APSK

CAPACITORS

3V3 DECOUPLING

VDD

VSS

C17100n

FOR BUFFERS

D0D2D3

VSS

VSS

REQARMGNTARMREQ001GNT001

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

SK3

CON60APSKT

C1210u

C13100n

C14100n

C15100n

C16100n

VSS

VSSD1

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

SK1

CON60APSKT

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 21

+ 23

+ 25

+ 27

+ 29

+ 31

+ 33

+ 35

+ 37

+ 39

+ 41

+ 43

+ 45

+ 47

+ 49

+ 51

+ 53

+ 55

+ 57

+ 59

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

+ 22

+ 24

+ 26

+ 28

+ 30

+ 32

+ 34

+ 36

+ 38

+ 40

+ 42

+ 44

+ 46

+ 48

+ 50

+ 52

+ 54

+ 56

+ 58

+ 60

SK2

CON60APSKT


A[31..0]

TRAN[1..0]TRAN[1..0]

A[31..0]

VSS

VSS

B_A1

B_A4

B_A7

COMMRX

COMMTX

D[31..0]

WRITE

SIZE[1..0]

PROT[1..0]

LOCK

WRITE

SIZE[1..0]

PROT[1..0]

LOCK

COMMTX

COMMRX

VSS

VSS

VSS

VSS

VSSnCPI

D[31..0]

nCPI

REQARMREQARM

nICERSTnICERST

B_A10

B_A13

B_A16

B_A19

B_A22

B_A25

B_A28

B_A31

B_PROT0

B_SIZE1

VDD

VSS

D10VSSD13

D16VSSD19

D22VSSD25

VSS

D4

D7

D28

D31

B_A11B_A12B_A14B_A15B_A17B_A18B_A20B_A21B_A23B_A24B_A26B_A27B_A29B_A30

B_PROT1B_SIZE0B_WRITE

B_LOCK

D11D12

D15D17D18D20D21D23D24

VDD

D5D6D8D9

D14

D26D27D29D30

VDD

VSS

EXTERN1

VSS

EXTERN0

TCKTDOTMSTDI

nTRST VSS

CP

VD

CPAVSS

VSS

nCPI

ERRORMCLKISYNCnIRQ

nFBI

VS

VC

RERE

RE

nI

LA

VSS

VDDVSSB_A24B_A25B_A26B_A27B_A28B_A29B_A30B_A31

A24A25A26A27A28A29A30A31

DIR 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


LVT245T

nMABVDD

VSS

VDDVSS

A8A9A10A11A12A13A14A15


A16A17A18A19A20A21A22A23

DIR 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


LVT245T

nMABE nMABEA0A1A2A3A4A5A6A7VSS

VDDVSS DIR 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


LVT245T

VSS

VSSB_A0B_A1B_A2B_A3B_A4B_A5B_A6B_A7


DIR 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


LVT245T

nMABEWAIT

MCLK

ERROR

nFIQ

nIRQ

MCLK

WAIT

ERROR

nFIQ

nIRQ

RES[1..0] RES[1..0]

LAST LAST

nMABE nMABE

ISYNC

BIGEND

CPA

CPB CPB

CPA

BIGEND

ISYNC

GNTARM GNTARM

EXTERN[1..0]EXTERN[1..0]

nTRSTnTRST

DIRECTION IS B->A SO DIR IS LOW

OUTPUT ENABLED BY nMABE

BUFFERS ON ADDRESS AND CONTROL LINES

VSS

VSS

B_SIZE0B_SIZE1

B_PROT0

B_PROT1

B_WRITE

B_LOCK

DIR 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


LVT245T

VDDnMABE

SIZE0SIZE1

PROT0

PROT1

WRITE

LOCK

VSSVSS

R34560RDO NOT FIT

R35220RDO NOT FIT

VDD

VSS

WAIT

OPTIONAL TERMINATION RESISTORS


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.4 Logic Analyser Connecters



B ARM EOI-0016B (LAPODS

Title

Logic Analyser connec



VDD

(nOPC)

LOGIC ANALYSER PODS

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD5

CON20AP

1V72 VDDMCLK

nM1PIPEFnEXEC

VDD

nM0 PROT0

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD1

CON20AP

1V64 1V65D14D12

D15D13D11

VDDA[31..0] A[31..0]

D[31..0]D[31..0]

MCLK

TRAN[1..0]

WRITE

SIZE[1..0]

PROT[1..0]

LOCK

PIPEF

nEXEC

WRITE

SIZE[1..0]

TRAN[1..0]

PROT[1..0]

LOCK

MCLK

PIPEF

nEXEC

nMREQ

SEQ

nMREQ

SEQ

nPWAITnPWAIT

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD2

CON20AP

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD3

CON20AP

1V66 1V67D30D28D26D24D22D20D18D16

D31D29D27D25D23D21D19D17VSS

VDD

D10D8D6D4D2D0

D9D7D5D3D1VSS

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD6

CON20AP

1V76

VSS

TRAN1

SIZE1

PROT1

WRITE

LOCK

SIZE0

TRAN0

nIRQ nFIQ

DBGACK

VSS

VDDECLK

RES1

nM2nM3nM4

VSS

VDD

VSS

SEQABORTnMREQ

(MAS1)(nRW)

(nRESET)TBIT

nCPICPA CPB

1V78 1V77

nPWAIT

1 V84 1 V85 1 V86

VSS

VDD

VSS

(MAS0)

NOTE: PIN 1 OF ALL

5V ON ANALYSER

PODS CONNECTS TO

VDD

VSS

VDD

VSS

+ 1

+ 3

+ 5

+ 7

+ 9

+ 11

+ 13

+ 15

+ 17

+ 19

+ 2

+ 4

+ 6

+ 8

+ 10

+ 12

+ 14

+ 16

+ 18

+ 20

POD4

CON20AP

1V68 1V69

1V70 1V71

A15A13A11A9A7A5A3A1

A14A12A10A8A6A4A2A0 VSS

VDD

A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31

VSS

VDD

nFIQ

ABORT

DBGACK

nM[4..0]

nIRQ

TBIT

ECLK

RES1

nFIQ

ABORT

nIRQ

nM[4..0]

DBGACK

TBIT

ECLK

RES1

nCPI nCPI

CPA

CPB

CPA

CPB


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.5 AMBA Bus Master Veneer



B ARM EOI-0016B (AMBAPL

Title

AMBA Bus Master Ven



WSEL

ABORT

VLLGND

VLL

GND

PIPEF

TMUX1TMUX0

nWAIT

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

nMABE

nPWAIT

GND

VCC

RES1

PROT1

ARE NOT USED

RES1 AND PROT1

IN INITIAL REVISION 1V50 1V51

MABE changed to nMABE

PWAIT changed to nPWAIT

WRITE

MCLK

ERROR

WAIT

LOCK

nMREQ

SEQ

MCLK

WAIT

ERROR

WRITE

LOCK

nMREQ

SEQ

RES[1..0] RES[1..0]

PROT[1..0] PROT[1..0]

LASTLAST

LOCKMCLKGND

nMREQSEQ

1V52 1V53 1V54

1V55 1V56 1V57

PROT0RES0GND

WRITEERROR

LAST

BMEN0

IO5 7

IO6 8

IO7 9

I0 10

I1 11

GND 12

CLK0/I2 13

IO8 14

IO9 15

IO10 16

IO11 17

IO12

18

IO13

19

IO14

20

IO15

21

VCC

22

GND

23

IO16

24

IO17

25

IO18

26

IO19

27

IO20

28


IO28

40

IO29

41

IO30

42

IO31

43

VCC

44

GND

1

IO0

2

IO1

3

IO2

4

IO3

5

IO4

6 U2

MACH215-12SOCKET PLCC44

VSS

VLL

VCC

D11N4001

R322K2

C11100n

MTBE

MDBE

WSEL

nWAIT

MTBE

MDBE

WSEL

nWAIT

ABORT ABORT

TMUX[1..0]TMUX[

REQARM REQAR

nMABE nMABE

PIPEF PIPEF

TRAN[1..0] TRAN

BMEN[1..0]BMEN[

FOR REV 1 TEST CHIP AN

TRAN[1:0] IS NOT GENER

BY MACH CHIP. IF REV0

TRAN[1:0] IS OUTPUT FR

nPWAIT nPWAI

VLLGND

VLL

GND

MDBE

TRAN1TRAN0

REQARM

OE 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9


QS3245

1 V89 1 V90 1 V91

1V93 1V94 1V95

LEVEL CONVERTOR

POWER SUPPLY

TRANBE

VCC

GND

WAIT

OLDTC

GNTARM

GNTARMGNTARM

1V58 1V59

BMEN0A 1

C 2

B 3

LK1

SMLINK

VDD

VSS

A 1

C 2

B 3

LK2

SMLINK

Default A-C

BUS MASTER ENABLE 0 BUS MASTER ENABLE 1

Default A-C

BMEN1 OLDTCA 1

C 2

B 3

LK3

SMLINK

Default B-C

SELECT TEST CHIP REVISION

VDD VCC

VSS VSS

VCCVCC

GND VSS

Default A-C

A 1

C 2

B 3

LK4

SMLINK

MTBE

GRANT SELECT

GNTARM

TRANBE


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.6 Processor in QFP Package



B ARM EOI-0016B (PROCQF

Title

Processor in QFP pac



VDDM

VDDFS

VDD

VDD

VSS

VDD

TEST3

APE

nENIN

DBGEN

DBGRQ

BREAKPT

1 V10

1 V11

1 V12

1 V13

1 V19

1 V20

1 V21

1 V22

R16

0R

R17

0R

R18

0R

R19

0R

VDD

VDD

VDD

VDDBL3

BL0

BL1

BL2

1 V1

1 V2

1 V3

1 V4

1 V27

R6

0R

R7

0R

R8

0R

R9

0R

BMEN1

BMEN0R15

0R

nFIQ

ISYNC

VDD

MCLK

nWAIT

ABORT

VSS

EEBE

CPA

CPB

nCPI

VDD

BL3

BL2

BL1

BL0

VSS

WAIT

WSEL

TRAN1

TRAN0

VDD

MTBE

VSS

COMMRX

COMMTX

TMUX1

TMUX0

RES1

R14

0R

VDD

TEST3

TEST2

TBIT

VSS

nM4

nM3

nM2

nM1

nM0

VDD

nEXEC

SEQ

VDDM

VDDM

nMREQ

ECLK

VSS

BIGEND

nIRQ

1V25

VSS 1

A0 2

A1 3

A2 4

VDD 5

A3 6

A4 7

A5 8

VSS 9

A6 10

A7 11

A8 12

VDD 13

A9 14

A10 15

A11 16

VSS 17

A12 18

A13 19

A14 20

VDD 21

A15 22

A16 23

A17 24

VSS 25

A18 26

A19 27

A20 28

VDD 29

A21 30

A22 31

A23 32

VSS 33

A24 34

A25 35

A26 36

VDD 37

A27 38

A28 39

A29 40

VSS 41

A30 42

A31 43

NRW 44

VDD 45

MAS0 46

MAS1 47

NTRANS 48

VSS 49

LOCK 50

NOPC 51

VDD 52

VSS

53

EABE

54

ABE

55

ALE

56

VDD

57

APE

58

DBE

59

TEST0

60

VSS

61

D0

62

D1

63

D2

64

VDD

65

D3

66

D4

67

D5

68

VSS

69

D6

70

D7

71

D8

72

VDD

73

D9

74

D10

75

D11

76

VSS

77

D12

78

D13

79

D14

80

VDD

81

D15

82

D16

83

D17

84

VSS

85

D18

86

D19

87

D20

88

VDD

89

D21

90

D22

91

D23

92

VSS

93

D24

94

D25

95

D26

96

VDD

97

D27

98

D28

99

D29

100

VSS

101

D30

102

D31

103

VDD

104

VSS 105TEST1 106NENOUTI 107NENOUT 108NENIN 109VDD 110EDBE 111SEL1 112SEL0 113BUSEN 114VSS 115TBE 116HIGHZ 117NTDOEN 118NTRST 119VDD 120TDO 121VDDFS 122TMS 123TCK 124TDI 125VSS 126DBGACK 127BREAKPT 128DBGRQ 129DBGEN 130VDD 131EXTERN0 132EXTERN1 133DBGRQI 134VDDM 135VDDM 136TCK1 137TCK2 138VSS 139TAPSM0 140TAPSM1 141TAPSM2 142TAPSM3 143VDD 144IR0 145IR1 146IR2 147IR3 148VSS 149RANGEOUT1 150RANGEOUT0 151SCREG3 152SCREG2 153SCREG1 154SCREG0 155VDD 156

VSS

157

COMMRX

158

COMMTX

159

NC

160

NC

161

NC

162

BCE

163

VDD

164

BC0

165

BC1

166

F0

167

F1

168

WAITSEL

169

WAIT2

170

VSS

171

BL0

172

BL1

173

BL2

174

BL3

175

VDD

176

NCPI

177

CPB

178

CPA

179

EEBE

180

VSS

181

NRESET

182

ABORT

183

NWAIT

184

MCLK

185

VDD

186

ISYNC

187

NFIQ

188

NIRQ

189

BIGEND

190

VSS

191

ECLK

192

NMREQ

193

VDDM

194

VDDM

195

SEQ

196

NEXEC

197

VDD

198

NM0

199

NM1

200

NM2

201

NM3

202

NM4

203

VSS

204

TBIT

205

TEST2

206

TEST3

207

VDD

208 U1

ARM7TDMIB2-QFP

VSS

A1A2VDDA3A4A5VSSA6A7A8VDDA9A10A11VSSA12A13A14VDDA15A16A17

A0VDD

VSS

VDD

VSS

VDDMVDDM

EXTERN1

VSS

SEL0

SEL1

BUSEN

SCREG0SCREG1SCREG2SCREG3RNGOUT0RNGOUT1

IR3IR2IR1IR0

TAPSM2TAPSM3

TAPSM1TAPSM0

TCK2TCK1

DBGRQI

VSS

VSS

CPA

D[31..0]

VDD

1 V5

1 V6

1 V7

1 V8

1 V28 1 V29 1 V30 1 V31 1 V32 1 V33

1 V34 1 V35 1 V36 1 V37

1 V38 1 V39 1 V40 1 V41

1 V42 1 V43

1 V44

R10

0R

R11

0R

R12

0R

RES1 RES1

R13

10K

D[31..0] A[31..0

VDD

VDD

VDD

ALE

ABE

DBE

EEBE

EXTERN0

EXTERN1

CPB

TBE

A[31..0]

TRAN[1..0]TRAN[1

VDD

1 V9

1 V14

1 V15

1 V16 1 V17

1 V18

1 V23

1 V24

R20

0R

R21

0R

R22

0R

R23

10K

WRITE

TDO

WRITE

SIZE[1..0]

PROT[1..0]PROT[1

SIZE[1

LOCK LOCK

TDO

nM[4..0] nM[4..0

nEXEC nEXEC

TBITTBIT

DBGACK DBGACK

nMREQ

SEQSEQ

nMREQ

nCPInCPI

VDD

VSS

VDDFS

VSS

VDD

SEL0SEL1MDBE

nENIN

BUSEN

TDITCKTMS

TDOVDDnTRST

TBE

DBGACKBREAKPTDBGRQDBGEN

EXTERN0

NTDOENHIGHZ

MTBE

BIGEND

ISYNC

nFIQ

BIGEND

ISYNC

nFIQ

MDBE MDBE

WSEL

WAIT

WSEL

WAIT

MCLK MCLK

nWAIT

ABORTABORT

nWAIT

MTBE

1 V45 1 V46

1 V47

TMUX[1..0] TMUX[1..0]

BMEN[1..0] BMEN[1..0]

VSSA18A19A20VDDA21A22A23VSSA24A25A26VDDA27A28A29VSSA30A31

VDDWRITE

SIZE0SIZE1PROT1VSS

VDD

VSS

VSS

VDD

D6D7D8

VSS

LOCKPROT0

D0D1D2

D3D4D5

MABE

ABE

ALE

VDD

APE

DBE

TEST0

1V26

VDDMABER36

0R 1 V97D9

VDD

D10

D11

VSS

D12

D13

D14

VDD

D16

D17

VSS

D18

D15

D19

D20

VDD

D21

D22

D23

VSS

D24

D25

D26

VDD

D27

D28

D29

VSS

D30

D31

VDD

VSSTEST1

nENOUTnENOUTI

TDI

TCK

TMS

nTRST

TDI

TCK

TMS

nTRST

nIRQ nIRQ 1 V48 1 V49

CPACPA

CPB CPB

EXTERN[1..0] EXTERN[1..0]

ECLKECLK

COMMRX

COMMTX COMMTX

COMMRX


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.7 Processor in PGA Package

Date: September 13, 1996 Sheet


B ARM EOI-0012 (PROCPGA

Title

Processor in PGA pac



VDDM

VDDFS

VDD

VDD

VSS

VDD

TEST3

APE

nENIN

DBGEN

DBGRQ

BREAKPT

1 V10

1 V11

1 V12

1 V13

1 V19

1 V20

1 V21

1 V22

R16

0R

R17

0R

R18

0R

R19

0R

VDD

VDD

VDD

VDDBL3

BL0

BL1

BL2

1 V1

1 V2

1 V3

1 V4

1 V27

R6

0R

R7

0R

R8

0R

R9

0R

BMEN1

BMEN0R15

0R

nFIQ

ISYNC

VDD

MCLK

nWAIT

ABORT

VSS

EEBE

CPA

CPB

nCPI

VDD

BL3

BL2

BL1

BL0

VSS

WAIT

WSEL

TRAN1

TRAN0

VDD

MTBE

VSS

COMMRX

COMMTX

TMUX1

TMUX0

RES1

R14

0R

VDD

TEST3

TEST2

TBIT

VSS

nM4

nM3

nM2

nM1

nM0

VDD

nEXEC

SEQ

VDDM

VDDM

nMREQ

ECLK

VSS

BIGEND

nIRQ

1V25

VSSB2

A0D3

A1B1

A2E4

VDDC2

A3E3

A4C1

A5F4

VSSD2

A6F3

A7D1

A8G4

VDDE2

A9G3

A10E1

A11H3

VSSF2

A12H4

A13F1

A14H2

VDDG2

A15J2

A16G1

A17J3

VSSH1

A18J4

A19J1

A20K2

VDDK1

A21K3

A22L1

A23K4

VSSM1

A24L2

A25N1

A26L3

VDDM2

A27L4

A28P1

A29M3

VSSN2

A30M4

A31R1

NRWN3

VDDP2

MAS0N4

MAS1T1

NTRANSP3

VSSR2

LOCKP4

NOPCU1

VDDR3

VSS

T2

EABE

R4

ABE

U2

ALE

P5

VDD

T3

APE

R5

DBE

U3

TEST0

P6

VSS

T4

D0

R6

D1

U4

D2

P7

VDD

T5

D3

R7

D4

U5

D5

R8

VSS

T6

D6

P8

D7

U6

D8

T8

VDD

T7

D9

T9

D10

U7

D11

R9

VSS

U8

D12

P9

D13

U9

D14

T10

VDD

U10

D15

R10

D16

U11

D17

P10

VSS

U12

D18

T11

D19

U13

D20

R11

VDD

T12

D21

P11

D22

U14

D23

R12

VSS

T13

D24

P12

D25

U15

D26

R13

VDD

T14

D27

P13

D28

U16

D29

R14

VSS

T15

D30

P14

D31

U17

VDD

R15

VSS T16TEST1 P15NENOUTI T17NENOUT N14NENIN R16VDD N15EDBE R17SEL1 M14SEL0 P16BUSEN M15VSS P17TBE L14HIGHZ N16NTDOEN L15NTRST N17VDD K15TDO M16VDDFS K14TMS M17TCK K16TDI L16VSS J16DBGACK L17BREAKPT J15DBGRQ K17DBGEN J14VDD J17EXTERN0 H16EXTERN1 H17DBGRQI H15VDDM G17VDDM H14TCK1 F17TCK2 G16VSS E17TAPSM0 G15TAPSM1 F16TAPSM2 G14TAPSM3 D17VDD F15IR0 E16IR1 F14IR2 C17IR3 E15VSS D16RANGEOUT1 E14RANGEOUT0 B17SCREG3 D15SCREG2 C16SCREG1 D14SCREG0 A17VDD C15

VSS

B16

COMMRX

C14

COMMTX

A16

NC

D13

NC

B15

NC

C13

BCE

A15

VDD

D12

BC0

B14

BC1

C12

F0

A14

F1

D11

WAITSEL

B13

WAIT2

C11

VSS

A13

BL0

C10

BL1

B12

BL2

D10

BL3

A12

VDD

B10

NCPI

B11

CPB

B9

CPA

A11

EEBE

C9

VSS

A10

NRESET

D9

ABORT

A9

NWAIT

B8

MCLK

A8

VDD

C8

ISYNC

A7

NFIQ

D8

NIRQ

A6

BIGEND

B7

VSS

A5

ECLK

C7

NMREQ

B6

VDDM

D7

VDDM

A4

SEQ

C6

NEXEC

B5

VDD

D6

NM0

A3

NM1

C5

NM2

B4

NM3

D5

NM4

A2

VSS

C4

TBIT

B3

TEST2

D4

TEST3

A1

VDD

C3 U1

ARM7TDMIB2-PGASOCKET PGA240

3045

VSS

A1A2VDDA3A4A5VSSA6A7A8VDDA9A10A11VSSA12A13A14VDDA15A16A17

A0VDD

VSS

VDD

VSS

VDDMVDDM

EXTERN1

VSS

SEL0

SEL1

BUSEN

SCREG0SCREG1SCREG2SCREG3RNGOUT0RNGOUT1

IR3IR2IR1IR0

TAPSM2TAPSM3

TAPSM1TAPSM0

TCK2TCK1

DBGRQI

VSS

VSS

CPA

D[31..0]

VDD

1 V5

1 V6

1 V7

1 V8

1 V28 1 V29 1 V30 1 V31 1 V32 1 V33

1 V34 1 V35 1 V36 1 V37

1 V38 1 V39 1 V40 1 V41

1 V42 1 V43

1 V44

R10

0R

R11

0R

R12

0R

RES1 RES1

R13

10K

D[31..0] A[31..0

VDD

VDD

VDD

ALE

ABE

DBE

EEBE

EXTERN0

EXTERN1

CPB

TBE

A[31..0]

TRAN[1..0]TRAN[1

VDD

1 V9

1 V14

1 V15

1 V16 1 V17

1 V18

1 V23

1 V24

R20

0R

R21

0R

R22

0R

R23

10K

WRITE

TDO

WRITE

SIZE[1..0]

PROT[1..0]PROT[1

SIZE[1

LOCK LOCK

TDO

nM[4..0] nM[4..0

nEXEC nEXEC

TBITTBIT

DBGACK DBGACK

nMREQ

SEQSEQ

nMREQ

nCPInCPI

VDD

VSS

VDDFS

VSS

VDD

SEL0SEL1MDBE

nENIN

BUSEN

TDITCKTMS

TDOVDDnTRST

TBE

DBGACKBREAKPTDBGRQDBGEN

EXTERN0

NTDOENHIGHZ

MTBE

BIGEND

ISYNC

nFIQ

BIGEND

ISYNC

nFIQ

MDBE MDBE

WSEL

WAIT

WSEL

WAIT

MCLK MCLK

nWAIT

ABORTABORT

nWAIT

MTBE

1 V45 1 V46

1 V47

TMUX[1..0] TMUX[1..0]

BMEN[1..0] BMEN[1..0]

VSSA18A19A20VDDA21A22A23VSSA24A25A26VDDA27A28A29VSSA30A31

VDDWRITE

SIZE0SIZE1PROT1VSS

VDD

VSS

VSS

VDD

D6D7D8

VSS

LOCKPROT0

D0D1D2

D3D4D5

MABE

ABE

ALE

VDD

APE

DBE

TEST0

1V26

VDDMABER36

0R 1 V97D9

VDD

D10

D11

VSS

D12

D13

D14

VDD

D16

D17

VSS

D18

D15

D19

D20

VDD

D21

D22

D23

VSS

D24

D25

D26

VDD

D27

D28

D29

VSS

D30

D31

VDD

VSSTEST1

nENOUTnENOUTI

TDI

TCK

TMS

nTRST

TDI

TCK

TMS

nTRST

nIRQ nIRQ 1 V48 1 V49

CPACPA

CPB CPB

EXTERN[1..0] EXTERN[1..0]

ECLKECLK

COMMRX

COMMTX COMMTX

COMMRX


Open Access


ARM DUI 0017C

Daughter Board SchematicsB.8 EmbeddedICE Interface



B ARM EOI-0016B (EICE.

Title

EmbeddedICE Interfa



VDD

R210K

R310K

R410K

R510K EmbeddedICE Interface

135791113

2468101214

PL1

CON14A

VDD

TDITMSTCKTDO

nTRST

nICERST

SPU

VSS

nICERST

R3310K

TCKTMSTDI

TDO

SPU

VDDR1

33R

1V96

nTRST is driven by the system at power up only.

To reset the TAP controller hold TMS high for

5 TCK cycles. To cause a full system reset drive

nICERST low.


Open Access

C-1ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

This appendix summarizes the available programmable devices.

C.1 Programmable Devices C-2

Summary ofProgrammable DevicesC


Open Access

Summary of Programmable Devices

C-2 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

C.1 Programmable DevicesThis appendix lists the available programmable devices. If you would like to use these designs, contact ARM for help.

C.1.1 Board devicesThe board contains twelve programmable devices.

Note 1 U28 is not re-programmable.

Ref ARM Name Ident. Device

U2 CLKDIV EFI-0017 PALCE22V10-7

U8 SSRAMC EFI-0018 PALCE22V10-7

U10 EPROMC EFI-0019 MACH210A-7

U11 EPROMDP EFI-0020 MACH230-10

U12 ANGELDM EFI-0021 8-bit EPROM/FLASH

U13 not fitted EFI-0022 16-bit EPROM/FLASH

U14 DRAMC EFI-0023 MACH231-7

U16 SRAMC EFI-0024 MACH210A-7

U20 APBIF EFI-0025 MACH231-7

U28 APBPER1 EFI-0026 XC17128D serial PROM

U37 TIC EFI-0027 MACH210A-7

U54 ARBRES8 EFI-0028 MACH210A-7

U55 DECODER EFI-0029 MACH210A-7

Table C-1: Programmable devices


Open Access

Summary of Programmable Devices

C-3ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

C.1.2 Daughter board deviceThe daughter board contains one programmable device.

C.1.3 MACH and PALCEAll MACH and PALCE devices can be reprogrammed. The functionality of these devices was designed using PALASM.

The PALASM source is available from ARM, as described in 1.3 Useful Contacts on page 1-3.

C.1.4 FPGAThe FPGA is programmed by serial PROM (U28). To reprogram the device you need to replace this PROM with a new one.

The FPGA design was completed using VHDL and synthesised using the Compass synthesizer. The VHDL source is also available from ARM.

Ref ARM Name Ident. Device

U2 CPU4 EFI-0030 MACH215-12

Table C-2: The daughter board programmable device


Open Access

D-1ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

This appendix summarises the jumpers and links.

D.1 Overview D-2

D.2 Surface Mount Links D-2D.3 Standard 2-pin Links D-3D.4 Link Fields D-4

D.5 DIP Switches D-5

Summary of Jumpersand LinksD


Open Access

Summary of Jumpers and Links

D-2 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

D.1 OverviewThe ARM Development Card is configurable through the use of links, jumpers and switches. Each of these is described in detail in Chapter 3, Circuit Descriptions. This section summarises that information.

Surface mount links are used where an option should only be changed for a special purpose. You may need to move these links if you are modifying the ARM Development Card to add additional hardware.

Standard 2-pin links are used for infrequently used options. You should only insert or remove the jumpers if you are sure of the effect.

DIP switches are used where the you may frequently want to make changes. You cannot stop the ARM Development Card functioning by altering the switch positions.

The default positions are denoted by a *.

D.2 Surface Mount Links

Ref Name Position Description

LK1 NISA clock select AC

* 32MHz24MHz

LK2 SYSCLK source AC

* internalexternal

LK3 SYSCLK2X source AC

* internalexternal

LK5 pipelined SSRAM AC

* pipelinednon-pipelined

LK12 PC card B VCC3EN AC

* highlow

LK13 PC card A VCC3EN AC

* highlow

LK14 AREQ1 select AC *

A_REQ001low

LK15 AREQ2 select AC *

A_REQ002low

Table D-1: Surface mount links


Open Access



D.3 Standard 2-pin Links

Ref Name Position Description

LK4 BIGEND outin

* little-endianbig-endian

LK7 P_STB WIDTH outin

* 2-cycle P_STB1-cycle P_STB

LK8 INT TYPE outin

* latched modeACK mode

LK9 DIRN outin

* BIDEN=1BIDEN=0

LK10 ENABLE INT outin

* disable switch interruptenable switch interrupt

LK17 USETIC outin

* disable test interfaceenable test interface

LK18 REMAP outin *

REMAP highREMAP driven

Table D-2: Standard 2-pin links


Open Access


D-4 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

D.4 Link Fields

CYC1 CYC0 Cycles Ref Position Name Option Description

in in 2 LK6 1 CYC1 outin

**

see Table D-3see Table D-3in out 3

out in 4 2 CYC0 outin

* see Table D-3see Table D-3out out 5

Table D-3: Cycle selection 3 EPROM outin *

select EPROMselect FLASH

4 SEL8BIT outin

* 8-bit device16-bit device

LK11 1 outin

* use parallel portPP bit0 to S3-1

2 outin


3 outin


4 outin


5 outin

* use parallel portPP bit4 to LED PP0

6 outin


7 outin


8 outin


LK16 1 INIT outin

* no functiondo not connect

2 MODE0 outin *

use download cableuse serial PROM

3 MODE1 outin *


4 MODE2 outin *


Table D-4: LK6, LK11, and LK16


Open Access



D.5 DIP Switches

.

B#CYC1 1 B#CYC0 1 Cycles Ref Position Name Option Description

on on 2 * S1 1 SEL0 on/off see Table D-8

on off 3 2 SEL1 on/off see Table D-8

off on 4 3 SEL2 on/off see Table D-8

off off 5 4 SEL3 on/off see Table D-8

Table D-5: S2 Switch positions S2 1 B0CYC0 on/off see Table D-5

2 B0CYC1 on/off see Table D-5

3 B0SIZ0 on/off see Table D-6

B#SIZ11 B#SIZ01 Size 4 B0SIZ1 on/off see Table D-6

on on 8-bit 5 B1CYC0 on/off see Table D-5

on off 16-bit 6 B1CYC1 on/off see Table D-5

off on 32-bit * 7 B1SIZ0 on/off see Table D-6

off off 32-bit 8 B1SIZ1 on/off see Table D-6

Table D-6: S2 Switch positions S3 1 S3-1 on/off toggle parallel port bit 0

2 S3-2 on/off toggle parallel port bit 1

1. # is the bank number: 0 or 1 3 S3-3 on/off toggle parallel port bit 2

4 S3-4 on/off toggle parallel port bit 3

Table D-7: S!, S2, and S3

Switch position Frequency (MHz)

SEL3 SEL2 SEL1 SEL0 SYSCLK SYSCLK2X

on on on on 4 8

on on on off 8 16

on on off on 16 32

on on off off 20 40

Table D-8: S1 switch positions


Open Access

E-1ARM Development Board (ARM7TDMI Version) Hardware Reference GuideARM DUI 0017C

This appendix shows a mechanical drawing of the ARM Development Card with dimensions to help you to build add-on hardware.

Mechanical InformationE


Open Access

Mechanical Information

E-2 ARM Development Board (ARM7TDMI Version)Hardware Reference Guide

ARM DUI 0017C

hrg.book Page 2 Wednesday, July 22, 1998 9:18 A

M

hardware reference guide - arm...

Documents