hardware testing

8/3/2019 Hardware Testing

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HARDWARE TESTING


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HARDWARE TESTING

Introduces digital system testing that makes the systems easier to test

Testing of a system is an experiment in which the system is exercised and its

resulting experience is analyzed to ascertain whether it behaved correctly.

If incorrect behavior is detected locate the cause of the misbehavior or failure

Problem: Normally we have access only to the inputs and outputs of the circuit

Testing levels:

VHDL test benches: to verify the overall design and algorithms used are correct

Simulation at the logic level : to verify that a design is logically correct

Hardware testing: to verify that the manufactured digital system functions properly


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TOPICS COVERED

Testing of combinational logic

Testing of sequential logic

Using distinguishing sequence

Using scan testing

Boundary scan testing

Built in self test


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TESTING OF COMBINATIONAL CIRCUITS

Common faults: short circuits & Open circuits

Fault model : Stuck at faults( s-a-f causes a line inthe circuit to behave as if it is permanently at logic

0 or logic 1) Stuck at 0 faults(s-a-0)

Stuck at 1 faults(s-a-1)

To test a gate input for s-a-0 the gate input must be 1 so achange to 0 can be detected.

To test a gate input for s-a-1 the gate input must be 0 so achange to 1 can be detected


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TESTING AND & OR GATES FOR STUCK AT

FAULTS


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TESTING OF COMBINATIONAL LOGIC (EXAMPLE 1)

1. Stuck at 0 fault


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TESTING OF COMBINATIONAL LOGIC (EXAMPLE 1)

Stuck-at-1 test


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Test Vectors


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FAULT DETECTION USING PATH SENSITIZATION-

TESTING MULTILEVEL NETWORKS

Path sensitization- Choose some path from the

origin of the fault to the circuit output

Choose a set of inputs that will excite that fault

And then propagate the effect of that fault to

the network output

Forward trace: from fault to output and

backward trace: back to input from fault


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FAULT DETECTION USING PATH SENSITIZATION-

TESTING MULTILEVEL NETWORKS- EXAMPLE 2


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FAULT DETECTION USING PATH

SENSITIZATION- EXAMPLE 3-HW


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MINIMAL TEST SET


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DETERMINE A MINIMUM SET OF TEST VECTORS

TO TEST THE NETWORK- EXAMPLE 4

*TEST INPUT FOR P S-A-1 :

1. path A-a-p-v-f-F

2. ABCD =0101 will test for faults a1, p1, v1, f1 and c1.


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Assume that we can apply inputs to A,B,C,D

and observe output at F

And internal gate inputs and outputs cannot be

accessed


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1. Test input for p s-a-12. Choose A,B,C,D such that p=0

3. And if p is s-a-1 ,we must propagate this fault to the output F

so it can be observed.

4. To propagate this fault ,Make c=0 and w=1 : C=0

5. We can make w=1 ,by making t=1 or u= 1

6. To make u=1 ,we must have d=1 and r=1 : D=1 and C= 0

( c=0 makes r=1)

7. To make p=0 ,we choose A=0

8. By choosing B=1 ,we can sensitize the path A-a-p-v-f-F

9. ABCD =0101 will test for faults a1, p1, v1, f1 and c1.


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TEST INPUT FOR P S-A-0

1. path A-a-p-v-f-F

2. ABCD = 1101 will test for faults a0,b0, p0,q1, r0 ,d0 , u0, v0, w0, f0


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TEST INPUT FOR S S-A-1

1. path B-b-s-t-w-f-F

2. ABCD = 1011 will test for faults b1 , c0, s1, t0, v0, w0, f0


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Test Vectors


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EXAMPLE 5 - HWA)DETERMINE THE NECESSARY INPUTS TO THE FOLLOWING NETWORK TO TEST FOR V STUCK AT 0.

B)FOR THIS SET OF INPUTS DETERMINE WHICH OTHER STUCK AT FAULTS CAN BE TESTED.

C)REPEAT (A) AND ( B) FOR R STUCK AT 1.


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EXAMPLE 6- HW

Find the test sequences for C s-a-1 and D s-a-0


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EXAMPLE 7- HW

Find the test sequences for G s-a-1 and L s-a-0


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TESTING SEQUENTIAL LOGIC

Difficult than testing combinational logic

Uses test sequences ( sequences of inputs for

testing)

Comparing the circuit to be tested with the

correctly functioning network


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X(t) sequence of inputs in time

Z(t)- output sequence

X,Z,Q can be single variable or

vector

I.One way to derive test sequences for a sequential network is to convert it into

an iterative network

Iterative network is a combinational network , we could then derive the test vectors for

the iterative network using any standard methods for combinational networks

Standard mealy sequential network


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Iterative network, k identical copies

K-length of sequence used to test the sequential network

X(t)

x(0),x(1),x(k)Z(t)->z(0),z(1),z(2).z(k)

After the test vector have been derived for the iterative network ,these vectors

become the input sequences used to test the original sequential network


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Take 2 different state graphs for testing

testing state graph

correct state graph/ correct state diagram

Given state diagram should be strongly connected

(ie., other states can be reached from every state)

Test strategy for strongly connected state diagram Find an input sequence that will distinguish each state from

the other states

1 Find distinguishing sequence (i/p sequence


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EXAMPLE 1

fig:State graph for test example

1.Find distinguishing sequence (i/p sequence

which distinguishes each state : finding by

iteration)

2. Verify each entry using distinguishing

sequence

3. Verify each transition given in the statediagram

4. aim: to verify the transition what should be

the test sequences?

State table

Distinguishing Sequence =11

o/p for DS: s0=01,

s1=11, s2=10, s3=00

Assume that the sequential network being tested has a reset input so we can reset it


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Assume that the sequential network being tested has a reset input so we can reset it

to a known initial state, then apply the test sequence and observe the output sequence

Test procedure: reset the network to initial state, apply a test sequence and observe the

output sequence

Reset ,test input, distinguishing sequence: test vector

Last 2 bits of o/p are equal to corresponding states o/p. Hence the transition is verified


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EXAMPLE 2:

The state diagram consists of two

sequential network

1st indicated with bold line

2nd indicated by dashed line


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Correct state diagram-correctly

functioning networkTesting state diagram-same m/c with

malfunction

Determine the shortest input sequence that will distinguish the two sequences


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Find the distinguishing sequence of the

following state table

EXAMPLE 3


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For each state of the flip flops and for each i/p

combination , we need to verify that the

network o/p s are correct & that the network

o/p goes correct, n/w goes to correct next state

possible way:

to connect the o/p of each f/f within the IC being tested,

to one of the IC pinsBut number of pins on IC is limited, not practical

II. SCAN TESTING TESTING SEQUENTIAL LOGIC


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Scan path test circuit using two port flip flops

Can observe state

of all flip flops

Concept: flip flops are

arranged to form a shift

register

We can shift out the

state of the flip flops bit by bit

using a single serial output

pin on the IC

2 D inputs D1,D2

2 clock inputs-C1,C2

When C1 is pulsed ,D1 is

stored in the flip flop

When C2 is pulsed D2 is

stored in the flip flop

APPROACHSCAN TESTING


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Sequential n/w is splitted into

a combinational logic part and

a state register composed of f/fs

Each f/f have two D i/p s and two clk i/ps


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NORMAL MODE

When the n/w is not being testedthe SCK is used ie.,C1

A set of i/ps X1,X2,. Xn is applied and the outputsz1,z2,..zm are generated

When SCK/C1 is pulsed , the D1 i/p is stored in the f/f

The next state (Q1+ , Q2+ , Q3+.. QK+ ) generated by thecombinational logic, is loaded into f/fs when C1 is pulsed ,

the new states Q1, Q2,Q3,.Qk feeds back intocombinational logic


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TEST MODE

When the n/w is being tested, the f/fs are set to a specified state by

shifting the state code into the register using the scan data i/p (SDI)and the test clock(TCK)

The Q o/p of each f/f connected to D2 i/p of the next f/f to form

shift register

The test vector x1,x2,xn is applied , the o/ps z1,z2,zm areverified & SCK is pulsed to take the n/w to the next state

The next state is then verified by pulsing TCK to shift the state codeout of the scan data register via the scan data o/p


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TEST PROCEDURE


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EXAMPLE

Present state Next state outputQ1 Q2Q3 Q1+ Q2+Q3+

X=00 01 11 10

Z1 Z2

X=00 01 11 10

1 0 1 010 110 011 111 10 11 00 01

Seq n/w : 2 i/ps -> x1,x2

f/fs ->Q1, Q2, Q3

o/ps -> z1,z2

101 shifted in using TCK

Then x1,x2 = 00 is applied

Apply SCK pulses: Z1,z2 read as 10

Next state 010

010 shifted out using TCK


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BOUNDARY SCAN TEST

BST is a method of testing PCBs

Standard for BST is introduced by Joint Test ActionGroup(JTAG)- ieee standard 1149.1, standardtest access port and boundary scan architecture

BST is intended to check for shorts or opens b/nICs mounted on a board

Include BST on ASIC

Core logic + Boundary scan logic


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BOUNDARY SCAN

Functions of TAP pins are:

Introduced to test complex

PC boards


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One boundary scan cell is placed between each i/p or o/p pin & theinternal core logic

Tap controller and BSR is added to the core logic

To include BST on an ASIC , we add a special logic cell to each ASICI/O pad

These cells are joined together to form a chain & create a boundaryscan shift register that extends around each ASIC

The i/p to a boundary scan shift register is the test data input(TDI)

The o/p of a bdry scan shift register is TDO


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TD1, TD0, TCK, TMS are connected to TAP

controller

TAP controller is a state machine clocked on

the rising edge of the TCK ,

with state transitions controlled by the TMS signal

TRST optional pin, to reset the controller


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TYPICAL BOUNDARY SCAN CELL


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When in normal mode , data from the i/p pin isrouted to the internal core logic in the IC, or datafrom core logic routed to the o/p pin

When in the shift mode , serial data from theprevious cell is clocked into f/f Q1, at the same

time as the data stored in Q1 is clocked in to the

next boundary scan cell .After Q2 is updated , testdata can be supplied to the internal logic or to theo/p pin

PC BOARD WITH SEVERAL BOUNDARY SCAN ICS


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PC BOARD WITH SEVERAL BOUNDARY SCAN ICS

Boundary scan registers linked together serially in a single chain with i/p TD1 and o/p TD0

TCK,TMS, TRST are connected parallel to all of the ICs

Using these signals test instructions and test data can be supplied to the internal logic or to

o/p pin


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BUILT IN SELF TEST (BIST) Built in self test (BIST) is a design technique in which parts of a circuit are

used to test the circuit itself

BIST is a design for testability methodology aimed at detecting faulty

components in a system by incorporating test logic on chip

Built in self test, is a set of structured test techniques for combinational and

sequential logic, memories, multipliers and other embedded logic blocks

In each case the principle is to generate test vectors apply them to the

circuit under test and then check the response

The resulting output is observed by the response monitor, which produces

an error signal if an incorrect output pattern is observed


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BUILT IN SELF TEST

GENERIC BIST SCHEME

Application: Testing memory


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REFERENCE

C H Roth , Digital System Design Using VHDL,

chapter 10


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THANK YOU

hardware testing

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