hardware verification using dft & tetramax · hardware verification using dft & tetramax...
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Hardware Verification using DFT & TetraMaxCS 6745 - Testing and Verification of Digital Circuits
Anh Luong & Andrzej Forys
1 ObjectiveThis project′s goal was to combine our new knowledge of hardware verification with our previous VLSI experiencesincluding fabrication and post silicon testing. Throughout the Testing and Verification of Digital Circuits course, welearned the algorithms for fault detection and what happens behind the scenes of test pattern generators and verifiers.Given the Synopsys tools designed for this type of testing, Design for Test (DFT) Compiler and TetraMAX, our goalwas to learn about the tools, determine the additional hardware and software needed for functionality, and apply themto previously designed hardware in Verilog.
2 IntroductionDFT and TetraMAX tools are useful for testing and verification of pre and post silicon digital circuits, includingfinding errors in logic and fabrication. Although these can be used for both sequential and combinational circuits,the verification of sequential systems requires the use of Scan Flip-Flops (FF). In this report we will cover the basicdesigns of Scan FFs, scan chain insertion using DFT, and preparing library files and verilog files for Automatic TestPattern Generation (ATPG) with TetraMAX.
The referenced report by Edwin Jose covers the basics of using DFT and TetraMAX to perform Full Scan versusPartial Scan Analysis [1]. The tools and commands used in that report have since been updated several versions and itis no longer up to date. The workflows have also slightly changed. This report will also provide new library files andscripts to use the latest versions of the tools.
3 BackgroundPart of the verification process requires the use of the Synopsys Design Compiler (DC). Although our scripts andlibrary can be used to first synthesize the design, we will not cover the DC details because we assume the user hascommon knowledge of this tool. This also applies to the process of creating cells that are used to generate the library.Refer to ”Digital VLSI Chip Design with Cadence and Synopsys CAD Tools” for more information about these pro-cedures [2].
These are the versions of the tools we have been using for this project:
DC and DFT Compiler Versions D-2010.03-SP2TetraMax Version F-2011.09-SP4 (S13 Directory, script updated for new installation)TetraMax Version W-2004.12-SP4 (S12 Directory)
4 Synopsys ToolsSynopsys has two main tools used for this type of testing: the DFT Compiler and TetraMAX. These tools can testfaults in both combinational and sequential logic [3]. In the case of sequential logic that uses FFs, a special ScanFF needs to be developed. This gives the tools or users direct control over the values inside registers. It allows forpropagating values into and out of the data path [4].
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4.1 DFT CompilerThe DFT Compiler uses additional features on top of the standard DC to regenerate the netlist with Scan FFs. Itmodifies the structural Verilog produced through DC by replacing standard FFs with Scan FFs. The tool is smartenough to update all the cells and nets associated with the new design. It runs its own test design rule checking(DRC) and is able to fix several clock, reset, and scan signal routing errors with AutoFix. The DFT tool has accessto DFTMAX which allows it to create the ATPG test protocol and compressed netlist for the entire design, which isused by TetraMAX. Along with providing circuit size, number of nets, and timing delay analysis before and after scaninsertion, the tool provides scan coverage details such as how many faults are testable and what types of faults areencountered [3]. Figure 1 shows the procedure flow used by the DFT Compiler.
Figure 1: Design procedure in DFT Compiler [5].
4.2 Design Vision (DV)Synopsys also has a GUI based DFT tool called Design Vision which lets the designer view a full schematic of his orher structural Verilog before and after Scan FF replacement. It can be used as an interactive command window and aschematic viewer. This can be useful in finding DRC errors, because the tool can show specific failure locations in theschematic. When using the tool to only view schematics of the netlists generated by DFT, a structural Verilog file isneeded along with the test protocol defining STIL file (.spf) [3]. Figure 2 shows a section of our scan inserted design.
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Figure 2: Scan chain in processor controller.
4.3 TetraMAX ATPGAnother Synopsys tool, called TetraMax ATPG, is used to generate the test patterns for fault analysis. This tool willdetermine all testable faults along with those that are unreachable or untestable due to issues like redundancy. It willgenerate a testbench compatible file corresponding to all the generated patterns. Although in some cases similar tothe fault analysis done by the DFT Compiler, its main difference is the ability to generate test patterns for the entiredesign, test individual faults, and show the propagation results to the user [4]. Figure 3 shows the TetraMAX ATPGprocess flow.
Figure 3: Process of TetraMAX ATPG [6].
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5 Verification Procedures
5.1 Scan Flip-Flop DesignThe difference between ordinary FFs and Scan FFs is that the latter has more than one data input pin which is activatedduring test modes. There are two types of Scan FFs we considered: the kind that share a clock with the rest of theintegrated circuit (IC) while utilizing a ′scan enable′ signal to activate the ′scan input′ and the kinds that use a separate′scan clock′ to switch between data sources [3]. Our implementation is based on the design using the scan enablesignal.
The simplest way of designing Scan FFs like this is to add a multiplexer (MUX) on the data input line. The scanenable signal is the select bit on the MUX and it controls whether the FF receives its input from the data path orscan input. We designed 3 slightly different Scan FFs for this project. The first used a FF and a MUX from our owncell library. The second used cells from the UofUDigital v 2 library accessible to VLSI students [2]. The third wasmodeled after a standard design found in [7].
The schematic, layout, and analog extracted views need to be created for the scan cell before starting library gen-eration. Figure 4 shows the schematic for the standard design from [7]. When finished simulating the schematic,it′s useful to independently test a behavioral view to verify a properly working Scan FF. Next, once Layout VersusSchematic Checking (LVS) shows that netlists match between the schematic and layout, the analog extracted view canbe generated [2]. This will later be used to generate the cell library file. The layout based on our own library can beseen in Figure 5.
Figure 4: Schematic of Scan FF based on design in [7].
Figure 5: Scan FF layout based on our library.
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5.2 Library ModificationsThere are a few additions that need to be made to the Scan FF cell in the library before the .db file is produced. Thesewill occur after the ′cad-alf2lib′ command when following the Encounter Library Characterization (ELC) process in[2].
A special test cell() needs to be defined in the scan cell to let the tools know how to use it. It′s inserted betweenthe initial ff() declaration and the first pin() declaration. It needs to contain all the cell pins and their correspondingdirection and signal type. The direction indicates input/output/tri-state while the signal type is used for the test scansignals. Notice that the ff() declaration is also included with its next state and clock signals. The function designationrefers to the generated IQ and IQN signal names for the output of the FF. Below is a snippet of the library showing theadditional test cell() information.
t e s t c e l l ( ) {p i n (D) {d i r e c t i o n : i n p u t ;}p i n (CLK) {d i r e c t i o n : i n p u t ;}p i n ( SI ) {d i r e c t i o n : i n p u t ;s i g n a l t y p e : t e s t s c a n i n ;}p i n ( SE ) {d i r e c t i o n : i n p u t ;s i g n a l t y p e : t e s t s c a n e n a b l e ;}f f ( IQ , IQN ) {n e x t s t a t e : ”D” ;c l o c k e d o n : ”CLK” ;}p i n (Q) {d i r e c t i o n : o u t p u t ;f u n c t i o n : ” IQ ” ;s i g n a l t y p e : t e s t s c a n o u t ;}p i n (QB) {d i r e c t i o n : o u t p u t ;f u n c t i o n : IQN ;s i g n a l t y p e : t e s t s c a n o u t i n v e r t e d ;}
}Another addition to the cell is a nextstate designation for pins associated with ′scan in′ and ′scan enable.′ See theformat below:
. . .p i n ( SI ) {n e x t s t a t e t y p e : ” s c a n i n ” ;d i r e c t i o n : i n p u t ;. . .p i n ( SE ) {n e x t s t a t e t y p e : ” s c a n e n a b l e ” ;d i r e c t i o n : i n p u t ;. . .
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5.3 Behavioral Verilog Design ModificationsThe Verilog design needs additional signals before it can be synthesized. These signals are only required for sequentialcircuits, where FFs reside. The Scan FF will be inserted during the compilation process to create a scan chain. Becausethe Scan FF contains additional signals that will need to be routed, the netlist needs inputs and outputs to allow ATPGto control the input sequence and to validate the output sequence. For this reason, the circuit needs the following pinscreated in the top module: test mode, scan input, scan output, and scan enable. Below is a snippet of the top moduledeclaration.
module c o n t r o l l e r ( i n p u t c lk , r e s e t ,i n p u t [ 5 : 0 ] op ,i n p u t zero ,i n p u t s i , se , t e s t m o d e , / / s can in , s can enab le , t e s t m o d eo u t p u t so , / / s can o u to u t p u t r e g memread , memwrite , a l u s r c a , memtoreg , i o r d ,o u t p u t pcen ,o u t p u t r e g r e g w r i t e , r e g d s t ,o u t p u t r e g [ 1 : 0 ] pc sou rce , a l u s r c b , a luop ,o u t p u t r e g [ 3 : 0 ] i r w r i t e ) ;
p a r a m e t e r FETCH1 = 4 ’ b0001 ;p a r a m e t e r FETCH2 = 4 ’ b0010 ;
. . .
6 Verification Procedures
6.1 DC and DFT SetupIn our setup, the DC and DFT are run together using a single script. They could be run as two separate scripts, butproblems might arise during the file export and import process from DC to DFT respectively. Therefore, we assumedthat the design is already imported and ready for scan insertion. When reading the script, the breakpoint between thetwo compilers occurs at the ”Insert Test Structures” comment. For the rest of the setup information, we will not gointo each instruction in detail. This is because the ”man” command can be used to view the manual entries of DC tofind out functionality and usage of unclear commands. Instead we will cover a high level description of the design flow.
The DC script starts with updating the target libraries for both standard cells and the Scan FF. In our process, wedifferentiate between the standard cells library and the scan library but they do not necessarily need to be separated.The scan cell style is then set up. There are several designs to choose here including multiplexed FF, clocked scan,level-sensitive scan design (lssd), auxiliary clock lssd, combinational, or none. Based on our Scan FF design, onlymultiplexed scan flip-flop is used. We then set up the AutoFix feature for clock and reset signals. This allows thecompiler to fix any test DRC errors at gate level logic introduced by the additional nets.
During the next process, we set up the test protocol, including all the parameters for clock, reset, and test mode ifthey are used. Once the test protocol is created, we check the current design against the test design rules. Any majorviolation in this step could cause the flow to continue incorrectly and ultimately fail in the TetraMAX tool. If errorsoccur, the ”man” command can be used with the error number in parentheses to find out more information about theviolation.
Assuming errors have not occurred, we create the input signal delays. The delay allows the circuit to be fully re-set before a certain input is applied. At this step, we can choose between Full Scan or Partial Scan. With Partial Scan,the commented command, ”set scan element false {...},” blocks certain registers from being replaced with the ScanFF. Otherwise, Full Scan is assumed and the script will continue with the compilation process. This process replacesall sequential elements during optimization. This allows the design to be compiled in the future without the need ofreoptimization.
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Once the compilation process is completed, we can start on setting up the scan chain. This process is not neededfor combinational designs because there will be no replacements. This section sets up what each signal does in thescan chain design. We also include a memory wrapper section, which is used specifically for designs with memory.Here the Scan FFs will be inserted before and after the memory block instead of replacing each individual FF cell. Thisallows the memory block to be tested as a single module. Next, we preview the design before the scan chain insertionprocess begins. We also update the design state to reflect the inserted scan chain. The test design rules are checkedagain to ensure no major errors occurred during the scan insertion process. Finally, we create all output reports, thenew structural design with inserted scan chains, and the test protocol (STIL) file. A similar process can be done withDesign Vision, while viewing the physical modifications in the schematic.
6.2 TetraMAXThe process for TetraMAX starts with importing the following: the complete netlist including scan inserted structuralVerilog, the cell library (behavioral Verilog) and the scan cell library (behavioral Verilog). The design then buildsand checks for synthesized violations of the testing rules. Once completed successfully, TetraMAX can generate testpatterns and coverage reports. TetraMAX also allows faults to be analyzed and simulated individually. Although wedid not experiment with all of the features available in TetraMAX due to conflicting version installations, our scriptwill now work with the recently installed F-2011.09-SP4 version, assuming proper Scan FFs have been designed.
7 ResultsThe following results will include output information from verifying sequential or combinational Verilog designs.Due to an unresolved issue with our main Scan FF chain, our sequential design could not pass the TetraMAX DRC.Whether this was caused by tool installation issues or the scan chain itself, part of our Future Work will be to determinethe root cause. We were, however, able to test combinational designs using TetraMAX and included a section of thegenerated test patterns. The scan cell library file (.lib) and the behavioral library file (.v) are included in Appendix Aand B respectively.
The next comparison shows the size differences between our synthesized sequential controller using DC and thescan inserted version using DFT. These results show our best case Scan FF, which turned out the be the one built fromthe UofU Digital v1 2 library cells. Appendix C shows our script for running the DC and DFT Compiler.
From Size (µm square) Number of Nets (wires with same label)DC: 384 90DFT: 424 102
The next important piece of data is a high percentage of fault coverage. This means that if a fault occurs in thefabricated model, there′s a large chance the test patterns can pinpoint the exact area of failure. Below we outline thetypes of faults detected during the DFT Compiler process on our sequential controller.
Fault Type # of faultsDetected 568Undetectable 1ATPG untestable 5Not detected 0total faults 574test coverage 99.13%
The last snippet of output is from the TetraMAX process using our combinational adder circuit. Here we show 2 outof 15 test patterns generated by TetraMAX. This particular circuit has a total of 268 detected faults. These 15 patternsgive us a test coverage of 100%, not including 14 undetectable faults for this particular circuit. Appendix D shows thescript for TetraMax.
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p a t t e r n = 0 ; / / 200#0 PI = 23 ’ b11110100110000110001001 ;# 0 ;XPCT = 8 ’ b10110111 ;MASK = 8 ’ b11111111 ;#0 −>measurePO defaul t WFT ;#100 ; / / 300
p a t t e r n = 1 ; / / 300#0 PI = 23 ’ b01011100011111101010110 ;# 0 ;XPCT = 8 ’ b11011010 ;MASK = 8 ’ b11111111 ;#0 −>measurePO defaul t WFT ;#100 ; / / 400
The behavioral Verilog code for the sequential controller and combinational adder can be found in Appendix E and F,respectively.
8 Future WorkThe first part will be to determine what causes our scan chain to fail the TetraMAX DRC. The newer version of Tetra-MAX has been installed recently so we have not been able to retest our sequential designs. Another issue could be adiscrepancy between the DFT Compiler and the setup files used by TetraMAX.
The next part would be getting the sequential ATPG to work so full test vectors can be generated for the controllermodule. We would also apply this tool flow to our entire processor design. Once completed, fabrication and actualtesting of our scan enabled design is desired to validate the patterns generated by TetraMax for fault detection.
9 ConclusionBased on what we have learned about the Synopsys testing and verification tools, along with the scripts we havedeveloped, and the experience designing Scan FFs, we will be able to test our combinational and sequential Verilogdesigns. Currently we are able complete scan insertion and get a coverage analysis on our sequential designs using theDFT Compiler, although we might need slight modifications to the scan chain to complete the TetraMax process. Asfor combinational designs, there is no scan insertion process in the DFT Compiler, but we can still achieve an ATPGcoverage and the test patterns from TetraMAX. The complete combinational output file, called expAdd tb patterns.v,from TetraMAX is included in the source folder.
Only the main library files and scripts have been included in the Appendix. For a complete set of source files, re-fer to the zipped source folder included with this report. The files step0, step1, and step2 are used to quickly run thescripts.
step0 - sources the Synopsys environment setup file.step1 - runs through the DC and DFT Compiler script.step2 - runs through the TetraMAX script.
Note that modifications to the scripts are required depending on what type of Verilog design is being used.
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References[1] E. Jose, “Scan insertion and atpg using synopsys & full scan v/s partial scan analysis,” 2006.
[2] Digital VLSI Chip Design with Cadence and Synopsys CAD Tools. Pearson Education Inc., 2010.
[3] Synopsys DFT Compiler User Guide.
[4] Synopsys TetraMax User Guide.
[5] Synopsys, Synopsys DFT Compiler.
[6] Synopsys, Synopsys TetraMAX ATPG.
[7] V. S. Ashok Kumar Suhag, “Delay testable enhanced scan flip-flop: Dft for high fault coverage,” 2011 Interna-tional Symposium on Electronic System Design, 2011.
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10 Appendix
A foo.lib
/∗d e l a y model : t y pcheck model : t y ppower model : t y pc a p a c i t a n c e model : t y po t h e r model : t y p∗ /l i b r a r y ( foo ) {
d e l a y m o d e l : t a b l e l o o k u p ;i n p l a c e s w a p m o d e : m a t c h f o o t p r i n t ;
/∗ u n i t a t t r i b u t e s ∗ /t i m e u n i t : ”1 ns ” ;v o l t a g e u n i t : ”1V” ;c u r r e n t u n i t : ”1mA” ;p u l l i n g r e s i s t a n c e u n i t : ”1kohm ” ;l e a k a g e p o w e r u n i t : ”1nW” ;c a p a c i t i v e l o a d u n i t ( 1 , p f ) ;
p o w e r s u p p l y ( ) {d e f a u l t p o w e r r a i l : RAIL VDD ;p o w e r r a i l ( RAIL GND , 0 ) ;p o w e r r a i l ( RAIL VDD , 5 ) ;
}
/∗ D e f a u l t a t t r i b u t e s ∗ //∗ Fanou t ( i n t e r m s of c a p a c i t i v e l o a d u n i t s ) ∗ /d e f a u l t f a n o u t l o a d : 0 . 3 ; d e f a u l t m a x f a n o u t : 1 0 . 0 ;/∗ Pin C a p a c i t a n c e ∗ /d e f a u l t i n o u t p i n c a p : 0 .00675 ;d e f a u l t i n p u t p i n c a p : 0 .00675 ;d e f a u l t o u t p u t p i n c a p : 0 . 0 ;/∗ l e a k a g e power ∗ /d e f a u l t c e l l l e a k a g e p o w e r : 0 . 0 ;d e f a u l t l e a k a g e p o w e r d e n s i t y : 0 . 0 ;
s l e w u p p e r t h r e s h o l d p c t r i s e : 8 0 ;s l e w l o w e r t h r e s h o l d p c t r i s e : 2 0 ;s l e w u p p e r t h r e s h o l d p c t f a l l : 8 0 ;s l e w l o w e r t h r e s h o l d p c t f a l l : 2 0 ;i n p u t t h r e s h o l d p c t r i s e : 3 0 ;i n p u t t h r e s h o l d p c t f a l l : 7 0 ;o u t p u t t h r e s h o l d p c t r i s e : 7 0 ;o u t p u t t h r e s h o l d p c t f a l l : 3 0 ;nom proces s : 1 ;n o m v o l t a g e : 5 ;n o m t e m p e r a t u r e : 2 5 ;o p e r a t i n g c o n d i t i o n s ( t y p i c a l ) {
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p r o c e s s : 1 ;v o l t a g e : 5 ;t e m p e r a t u r e : 2 5 ;p o w e r r a i l ( RAIL GND , 0 ) ;p o w e r r a i l ( RAIL VDD , 5 ) ;
}d e f a u l t o p e r a t i n g c o n d i t i o n s : t y p i c a l ;
l u t a b l e t e m p l a t e ( d e l a y t e m p l a t e 5 x 5 ) {v a r i a b l e 1 : i n p u t n e t t r a n s i t i o n ;v a r i a b l e 2 : t o t a l o u t p u t n e t c a p a c i t a n c e ;i n d e x 1 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;i n d e x 2 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;
}p o w e r l u t t e m p l a t e ( e n e r g y t e m p l a t e 5 x 5 ) {
v a r i a b l e 1 : i n p u t t r a n s i t i o n t i m e ;v a r i a b l e 2 : t o t a l o u t p u t n e t c a p a c i t a n c e ;i n d e x 1 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;i n d e x 2 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;
}l u t a b l e t e m p l a t e ( h o l d t e m p l a t e 5 x 3 ) {
v a r i a b l e 1 : c o n s t r a i n e d p i n t r a n s i t i o n ;v a r i a b l e 2 : r e l a t e d p i n t r a n s i t i o n ;i n d e x 1 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;i n d e x 2 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 ” ) ;
}p o w e r l u t t e m p l a t e ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {
v a r i a b l e 1 : i n p u t t r a n s i t i o n t i m e ;i n d e x 1 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;
}l u t a b l e t e m p l a t e ( s e t u p t e m p l a t e 5 x 3 ) {
v a r i a b l e 1 : c o n s t r a i n e d p i n t r a n s i t i o n ;v a r i a b l e 2 : r e l a t e d p i n t r a n s i t i o n ;i n d e x 1 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;i n d e x 2 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 ” ) ;
}l u t a b l e t e m p l a t e ( w i d t h t e m p l a t e 5 x 1 ) {
v a r i a b l e 1 : r e l a t e d p i n t r a n s i t i o n ;i n d e x 1 ( ” 1 0 0 0 . 0 , 1 0 0 1 . 0 , 1 0 0 2 . 0 , 1 0 0 3 . 0 , 1 0 0 4 . 0 ” ) ;
}
/∗ −−−−−−−−−−−−− ∗∗ Design : SDFF ∗∗ −−−−−−−−−−−−− ∗ /c e l l ( SDFF ) {a r e a : 4500 ;c e l l l e a k a g e p o w e r : 0 . 6 7 9 2 8 4 ;r a i l c o n n e c t i o n ( GND, RAIL GND ) ;r a i l c o n n e c t i o n ( VDD, RAIL VDD ) ;p i n o p p o s i t e ( ”Q” , ”QB” ) ;f f ( IQ , IQN ) {
n e x t s t a t e : ” ( ( SE SI ) + ( ! SE D ) ) ” ;c l o c k e d o n : ” ( ! ( ! CLK ) ) ” ;
}
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t e s t c e l l ( ) {p i n (D) {d i r e c t i o n : i n p u t ;}p i n (CLK) {d i r e c t i o n : i n p u t ;}p i n ( SI ) {d i r e c t i o n : i n p u t ;s i g n a l t y p e : t e s t s c a n i n ;}p i n ( SE ) {d i r e c t i o n : i n p u t ;s i g n a l t y p e : t e s t s c a n e n a b l e ;}
f f ( IQ , IQN ) {n e x t s t a t e : ”D” ;c l o c k e d o n : ”CLK” ;
}p i n (Q) {
d i r e c t i o n : o u t p u t ;f u n c t i o n : ” IQ ” ;s i g n a l t y p e : t e s t s c a n o u t ;
}p i n (QB) {
d i r e c t i o n : o u t p u t ;f u n c t i o n : IQN ;s i g n a l t y p e : t e s t s c a n o u t i n v e r t e d ;
}}p i n (CLK) {
d i r e c t i o n : i n p u t ;i n p u t s i g n a l l e v e l : RAIL VDD ;c a p a c i t a n c e : 0 . 0 1 7 2 9 1 9 ;r i s e c a p a c i t a n c e : 0 . 0 1 7 2 6 8 6 ;f a l l c a p a c i t a n c e : 0 . 0 1 7 2 9 1 9 ;r i s e c a p a c i t a n c e r a n g e ( 0 .0172252 , 0 . 0 1 7 2 8 8 9 ) ;f a l l c a p a c i t a n c e r a n g e ( 0 .0172693 , 0 . 0 1 7 3 1 2 1 ) ;c l o c k : t r u e ;m a x t r a n s i t i o n : 1 . 2 ;i n t e r n a l p o w e r ( ) {r i s e p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 1 . 8 4 6 3 8 , 1 . 8 7 5 2 5 , 2 . 0 3 3 4 5 , 2 . 1 8 0 1 7 , 2 . 7 4 5 6 8 ” ) ;}f a l l p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 3 . 2 1 3 1 4 , 3 . 2 5 6 1 7 , 3 . 4 2 4 4 , 3 . 5 8 1 7 7 , 4 . 1 4 9 0 5 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : m i n p u l s e w i d t h ;when : ” !D&!SE&! SI ” ;
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s d f c o n d : ” D EQ 0 AN SE EQ 0 AN SI EQ 0 == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( w i d t h t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 0 . 7 6 3 7 0 2 , 0 . 8 2 8 2 0 1 , 0 . 9 7 0 0 8 6 , 1 . 0 7 3 0 3 , 1 . 3 8 6 9 1 ” ) ;}f a l l c o n s t r a i n t ( w i d t h t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 0 . 8 9 2 9 6 8 , 0 . 9 6 7 0 4 6 , 1 . 1 1 5 3 3 , 1 . 2 2 0 0 8 , 1 . 5 3 8 7 7 ” ) ;}}
}p i n (D) {
d i r e c t i o n : i n p u t ;i n p u t s i g n a l l e v e l : RAIL VDD ;c a p a c i t a n c e : 0 . 0 2 0 2 5 1 7 ;r i s e c a p a c i t a n c e : 0 . 0 1 9 6 4 7 ;f a l l c a p a c i t a n c e : 0 . 0 2 0 2 5 1 7 ;r i s e c a p a c i t a n c e r a n g e ( 0 .0196047 , 0 . 0 2 9 0 4 8 5 ) ;f a l l c a p a c i t a n c e r a n g e ( 0 . 0 2 0 2 4 1 , 0 . 0 2 9 0 3 1 4 ) ;m a x t r a n s i t i o n : 1 . 2 ;i n t e r n a l p o w e r ( ) {r i s e p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 1 . 8 5 9 2 7 , 1 . 8 8 6 0 6 , 2 . 0 2 5 4 6 , 2 . 1 4 0 5 9 , 2 . 5 9 2 2 ” ) ;}f a l l p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 2 . 5 8 9 0 5 , 2 . 6 2 0 0 6 , 2 . 7 7 4 2 6 , 2 . 9 0 7 6 1 , 3 . 3 8 8 5 8 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : h o l d r i s i n g ;when : ” ! SE ” ;s d f c o n d : ”SE == 1 ’ b0 ” ;r i s e c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}f a l l c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 4 8 7 5 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;
13
}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : s e t u p r i s i n g ;when : ” ! SE ” ;s d f c o n d : ”SE == 1 ’ b0 ” ;r i s e c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 3 1 8 7 5 , 0 . 2 1 3 7 5 , 0 . 0 8 2 5 ” , \” 0 . 3 7 1 2 5 , 0 . 2 6 6 2 5 , 0 . 1 3 5 ” , \” 0 . 5 3 2 5 , 0 . 3 7 1 2 5 , 0 . 2 4 ” , \” 0 . 5 5 5 , 0 . 4 5 , 0 . 3 1 8 7 5 ” , \” 0 . 8 1 7 5 , 0 . 6 5 6 2 5 , 0 . 5 2 5 ” ) ;}f a l l c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 6 5 6 2 5 , 0 . 4 9 5 , 0 . 3 6 3 7 5 ” , \” 0 . 7 0 8 7 5 , 0 . 6 0 3 7 5 , 0 . 4 1 6 2 5 ” , \” 0 . 8 7 , 0 . 7 6 5 , 0 . 5 7 7 5 ” , \” 1 . 0 0 5 , 0 . 8 4 3 7 5 , 0 . 7 1 2 5 ” , \” 1 . 3 8 , 1 . 2 1 8 7 5 , 1 . 0 8 7 5 ” ) ;}}
}p i n (Q) {
d i r e c t i o n : o u t p u t ;o u t p u t s i g n a l l e v e l : RAIL VDD ;c a p a c i t a n c e : 0 ;r i s e c a p a c i t a n c e : 0 ;f a l l c a p a c i t a n c e : 0 ;r i s e c a p a c i t a n c e r a n g e ( 0 , 0 ) ;f a l l c a p a c i t a n c e r a n g e ( 0 , 0 ) ;m a x c a p a c i t a n c e : 0 . 3 6 2 9 4 7 ;m a x t r a n s i t i o n : 1 . 9 0 1 6 2 ;f u n c t i o n : ” IQ ” ;t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g s e n s e : n o n u n a t e ;t i m i n g t y p e : r i s i n g e d g e ;c e l l r i s e ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 7 9 4 6 4 2 , 0 . 8 5 8 4 3 , 0 . 9 8 3 4 1 1 , 1 . 4 7 7 4 9 , 2 . 2 1 6 ” , \” 0 . 8 5 9 7 5 3 , 0 . 9 2 3 5 6 , 1 . 0 4 8 6 9 , 1 . 5 4 2 7 4 , 2 . 2 8 1 4 ” , \” 0 . 9 9 9 2 1 5 , 1 . 0 6 3 4 7 , 1 . 1 8 8 4 8 , 1 . 6 8 2 5 1 , 2 . 4 2 1 3 3 ” , \” 1 . 0 9 9 1 , 1 . 1 6 2 8 7 , 1 . 2 8 7 8 7 , 1 . 7 8 1 9 9 , 2 . 5 2 0 7 5 ” , \” 1 . 4 0 1 0 3 , 1 . 4 6 5 1 2 , 1 . 5 8 9 6 8 , 2 . 0 8 3 7 2 , 2 . 8 2 2 4 ” ) ;}
14
r i s e t r a n s i t i o n ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 2 1 2 0 4 9 , 0 . 2 7 0 2 5 , 0 . 3 8 8 7 3 5 , 0 . 8 7 3 4 2 9 , 1 . 6 0 6 0 9 ” , \” 0 . 2 1 2 0 6 2 , 0 . 2 7 0 2 6 1 , 0 . 3 8 8 7 5 2 , 0 . 8 7 3 4 2 , 1 . 6 0 6 2 8 ” , \” 0 . 2 1 2 0 5 6 , 0 . 2 7 0 2 4 9 , 0 . 3 8 8 7 3 1 , 0 . 8 7 3 3 8 3 , 1 . 6 0 6 3 8 ” , \” 0 . 2 1 1 9 1 9 , 0 . 2 7 0 2 0 4 , 0 . 3 8 8 7 5 2 , 0 . 8 7 3 3 9 7 , 1 . 6 0 6 3 1 ” , \” 0 . 2 1 2 0 3 5 , 0 . 2 7 0 6 8 9 , 0 . 3 8 8 8 7 8 , 0 . 8 7 3 4 9 3 , 1 . 6 0 6 3 1 ” ) ;}c e l l f a l l ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 7 6 3 7 0 2 , 0 . 8 4 7 6 8 8 , 1 . 0 1 2 0 5 , 1 . 6 5 8 4 9 , 2 . 6 2 1 9 4 ” , \” 0 . 8 2 8 2 0 1 , 0 . 9 1 2 7 0 9 , 1 . 0 7 7 0 3 , 1 . 7 2 3 5 6 , 2 . 6 8 6 8 6 ” , \” 0 . 9 7 0 0 8 6 , 1 . 0 5 4 1 6 , 1 . 2 1 8 5 4 , 1 . 8 6 4 6 , 2 . 8 2 8 5 8 ” , \” 1 . 0 7 3 0 3 , 1 . 1 5 6 8 , 1 . 3 2 0 9 8 , 1 . 9 6 6 6 5 , 2 . 9 3 0 5 9 ” , \” 1 . 3 8 6 9 1 , 1 . 4 7 0 5 5 , 1 . 6 3 4 3 6 , 2 . 2 8 0 5 2 , 3 . 2 4 4 1 2 ” ) ;}f a l l t r a n s i t i o n ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 2 3 9 4 8 6 , 0 . 3 0 8 9 1 , 0 . 4 4 9 6 6 2 , 1 . 0 2 5 8 6 , 1 . 9 0 1 6 2 ” , \” 0 . 2 3 9 4 9 7 , 0 . 3 0 8 9 1 1 , 0 . 4 4 9 6 4 1 , 1 . 0 2 5 8 7 , 1 . 9 0 0 9 6 ” , \” 0 . 2 3 9 5 9 3 , 0 . 3 0 8 9 9 7 , 0 . 4 4 9 6 8 , 1 . 0 2 6 , 1 . 9 0 1 1 1 ” , \” 0 . 2 3 9 9 9 7 , 0 . 3 0 9 3 7 7 , 0 . 4 5 0 0 0 7 , 1 . 0 2 6 0 8 , 1 . 9 0 1 6 2 ” , \” 0 . 2 4 1 4 2 5 , 0 . 3 1 0 2 5 3 , 0 . 4 5 0 4 0 2 , 1 . 0 2 6 1 7 , 1 . 9 0 1 1 8 ” ) ;}}i n t e r n a l p o w e r ( ) {r e l a t e d p i n : ”CLK” ;r i s e p o w e r ( e n e r g y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 3 . 8 5 9 0 1 , 4 . 1 6 8 0 8 , 4 . 7 8 9 8 8 , 7 . 2 8 8 , 1 1 . 0 3 8 9 ” , \” 3 . 8 8 1 4 9 , 4 . 1 9 0 6 3 , 4 . 8 1 2 6 7 , 7 . 3 1 0 8 6 , 1 1 . 0 6 1 6 ” , \” 4 . 0 2 7 9 8 , 4 . 3 3 8 1 4 , 4 . 9 6 0 0 1 , 7 . 4 5 8 0 7 , 1 1 . 2 0 8 8 ” , \” 4 . 1 8 4 4 , 4 . 4 9 3 9 , 5 . 1 1 6 0 3 , 7 . 6 1 4 5 2 , 1 1 . 3 6 5 4 ” , \” 4 . 7 4 2 5 6 , 5 . 0 5 2 4 2 , 5 . 6 6 4 9 7 , 8 . 1 6 2 6 , 1 1 . 9 1 3 2 ” ) ;}f a l l p o w e r ( e n e r g y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 3 . 1 5 3 7 4 , 2 . 8 4 6 5 6 , 2 . 2 3 1 4 , 0 . 2 4 7 6 1 7 , 3 . 9 8 6 7 7 ” , \” 3 . 1 7 0 8 2 , 2 . 8 7 1 6 3 , 2 . 2 5 6 4 9 , 0 . 2 2 2 2 1 6 , 3 . 9 6 1 4 6 ” , \” 3 . 3 6 1 9 8 , 3 . 0 5 4 7 5 , 2 . 4 3 9 8 3 , 0 . 0 3 8 0 5 1 , 3 . 7 7 6 4 4 ” , \” 3 . 5 6 5 3 9 , 3 . 2 5 6 9 9 , 2 . 6 4 0 7 4 , 0 . 1 6 1 0 1 3 , 3 . 5 7 7 5 8 ” , \” 4 . 2 8 2 2 4 , 3 . 9 7 2 0 3 , 3 . 3 5 2 7 3 , 0 . 8 7 2 7 5 6 , 2 . 8 6 4 8 4 ” ) ;}}
15
}p i n (QB) {
d i r e c t i o n : o u t p u t ;o u t p u t s i g n a l l e v e l : RAIL VDD ;c a p a c i t a n c e : 0 ;r i s e c a p a c i t a n c e : 0 ;f a l l c a p a c i t a n c e : 0 ;r i s e c a p a c i t a n c e r a n g e ( 0 , 0 ) ;f a l l c a p a c i t a n c e r a n g e ( 0 , 0 ) ;m a x c a p a c i t a n c e : 0 . 2 5 5 9 3 1 ;m a x t r a n s i t i o n : 2 . 2 3 0 8 4 ;f u n c t i o n : ”IQN ” ;t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g s e n s e : n o n u n a t e ;t i m i n g t y p e : r i s i n g e d g e ;c e l l r i s e ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 5 7 8 6 3 4 , 0 . 6 6 5 8 0 1 , 0 . 8 3 7 7 7 6 , 1 . 5 1 4 4 , 2 . 5 2 2 ” , \” 0 . 6 4 3 4 7 5 , 0 . 7 3 0 4 3 4 , 0 . 9 0 2 7 7 4 , 1 . 5 7 8 2 7 , 2 . 5 8 7 0 6 ” , \” 0 . 7 8 4 6 3 , 0 . 8 7 0 5 2 , 1 . 0 4 0 9 6 , 1 . 7 1 5 0 3 , 2 . 7 2 2 6 2 ” , \” 0 . 8 8 7 7 7 1 , 0 . 9 7 2 9 8 4 , 1 . 1 4 2 9 1 , 1 . 8 1 4 1 6 , 2 . 8 2 0 3 1 ” , \” 1 . 2 0 1 7 3 , 1 . 2 8 5 0 4 , 1 . 4 5 2 4 9 , 2 . 1 1 7 4 3 , 3 . 1 1 9 2 1 ” ) ;}r i s e t r a n s i t i o n ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 3 0 0 9 3 3 , 0 . 3 8 6 8 7 4 , 0 . 5 6 2 8 4 8 , 1 . 2 4 0 2 5 , 2 . 2 3 0 5 3 ” , \” 0 . 3 0 1 3 7 4 , 0 . 3 8 6 8 5 3 , 0 . 5 6 2 9 4 9 , 1 . 2 4 0 2 6 , 2 . 2 3 0 8 4 ” , \” 0 . 3 0 2 0 7 3 , 0 . 3 8 7 5 9 2 , 0 . 5 6 3 1 8 5 , 1 . 2 4 0 3 , 2 . 2 3 0 5 5 ” , \” 0 . 3 0 5 8 0 2 , 0 . 3 8 9 8 5 , 0 . 5 6 4 3 5 9 , 1 . 2 4 0 4 9 , 2 . 2 3 0 6 3 ” , \” 0 . 3 1 8 6 6 5 , 0 . 4 0 0 0 0 4 , 0 . 5 7 1 8 6 8 , 1 . 2 4 2 5 7 , 2 . 2 3 0 7 5 ” ) ;}c e l l f a l l ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 6 5 7 9 0 2 , 0 . 7 1 5 8 3 5 , 0 . 8 2 7 3 0 2 , 1 . 2 6 8 2 3 , 1 . 9 3 0 4 3 ” , \” 0 . 7 2 3 3 9 2 , 0 . 7 8 0 4 5 1 , 0 . 8 9 2 2 9 3 , 1 . 3 3 3 2 1 , 1 . 9 9 5 6 2 ” , \” 0 . 8 6 3 3 4 4 , 0 . 9 2 0 5 5 1 , 1 . 0 3 2 4 5 , 1 . 4 7 3 3 1 , 2 . 1 3 5 3 9 ” , \” 0 . 9 6 2 7 9 , 1 . 0 2 0 4 8 , 1 . 1 3 1 7 , 1 . 5 7 2 6 , 2 . 2 3 4 5 7 ” , \” 1 . 2 6 5 5 9 , 1 . 3 2 3 3 7 , 1 . 4 3 4 5 5 , 1 . 8 7 5 3 8 , 2 . 5 3 7 1 7 ” ) ;}f a l l t r a n s i t i o n ( d e l a y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 2 1 8 2 4 9 , 0 . 2 7 0 3 8 , 0 . 3 7 6 1 8 7 , 0 . 8 0 0 0 5 3 , 1 . 4 2 6 4 6 ” , \” 0 . 2 1 8 3 6 9 , 0 . 2 6 9 7 4 8 , 0 . 3 7 6 1 5 5 , 0 . 8 0 0 0 6 9 , 1 . 4 2 6 6 8 ” , \” 0 . 2 1 8 3 1 7 , 0 . 2 6 9 8 5 9 , 0 . 3 7 6 0 1 4 , 0 . 8 0 0 1 0 5 , 1 . 4 2 6 4 6 ” , \” 0 . 2 1 8 6 7 1 , 0 . 2 7 0 5 9 6 , 0 . 3 7 6 2 5 9 , 0 . 8 0 0 1 7 , 1 . 4 2 6 5 1 ” , \
16
” 0 . 2 2 0 1 0 8 , 0 . 2 7 1 4 7 , 0 . 3 7 6 7 5 6 , 0 . 8 0 0 2 5 , 1 . 4 2 6 4 7 ” ) ;}}i n t e r n a l p o w e r ( ) {r e l a t e d p i n : ”CLK” ;r i s e p o w e r ( e n e r g y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 3 . 7 8 9 1 , 4 . 1 4 9 3 6 , 4 . 8 9 6 4 9 , 8 . 0 0 7 9 4 , 1 2 . 7 4 5 5 ” , \” 3 . 8 1 1 5 3 , 4 . 1 6 7 1 3 , 4 . 9 1 7 4 2 , 8 . 0 3 0 1 2 , 1 2 . 7 6 3 ” , \” 3 . 9 9 9 2 1 , 4 . 3 5 0 4 2 , 5 . 0 8 9 5 4 , 8 . 1 8 4 8 3 , 1 2 . 9 1 7 1 ” , \” 4 . 1 9 4 3 1 , 4 . 5 4 0 4 5 , 5 . 2 7 3 9 5 , 8 . 3 5 5 1 1 , 1 3 . 0 8 1 3 ” , \” 4 . 9 0 3 1 4 , 5 . 2 2 9 6 3 , 5 . 9 4 1 9 7 , 8 . 9 7 8 2 6 , 1 3 . 6 8 0 2 ” ) ;}f a l l p o w e r ( e n e r g y t e m p l a t e 5 x 5 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 2 5 , 0 . 0 5 , 0 . 1 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 3 . 2 4 1 6 , 2 . 9 4 5 3 , 2 . 3 7 2 7 7 , 0 . 1 9 5 6 1 5 , 2 . 9 6 5 0 4 ” , \” 3 . 2 6 6 5 2 , 2 . 9 7 2 4 8 , 2 . 3 9 7 4 6 , 0 . 2 2 2 4 1 7 , 2 . 9 4 2 0 6 ” , \” 3 . 4 1 3 9 7 , 3 . 1 2 0 5 3 , 2 . 5 4 6 2 6 , 0 . 3 6 8 2 6 1 , 2 . 7 9 3 6 4 ” , \” 3 . 5 7 0 4 6 , 3 . 2 7 6 3 , 2 . 7 0 3 3 , 0 . 5 2 3 6 9 9 , 2 . 6 3 9 9 7 ” , \” 4 . 1 1 9 2 7 , 3 . 8 2 4 8 3 , 3 . 2 4 7 9 9 , 1 . 0 6 8 1 5 , 2 . 0 9 7 6 2 ” ) ;}}
}p i n ( SE ) {n e x t s t a t e t y p e : ” s c a n e n a b l e ” ;
d i r e c t i o n : i n p u t ;i n p u t s i g n a l l e v e l : RAIL VDD ;c a p a c i t a n c e : 0 . 0 4 7 4 8 7 ;r i s e c a p a c i t a n c e : 0 . 0 4 7 4 8 7 ;f a l l c a p a c i t a n c e : 0 . 0 4 7 1 5 3 3 ;r i s e c a p a c i t a n c e r a n g e ( 0 .0463496 , 0 . 0 5 0 4 4 3 5 ) ;f a l l c a p a c i t a n c e r a n g e ( 0 .0466062 , 0 . 0 5 0 4 9 5 ) ;m a x t r a n s i t i o n : 1 . 2 ;i n t e r n a l p o w e r ( ) {r i s e p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 2 . 3 1 8 6 , 2 . 3 4 5 5 2 , 2 . 5 0 6 , 2 . 6 5 1 3 4 , 3 . 5 7 6 1 3 ” ) ;}f a l l p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 3 . 4 7 2 7 5 , 3 . 5 3 4 0 7 , 3 . 8 7 0 6 5 , 4 . 1 8 2 4 4 , 5 . 3 1 6 3 7 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : h o l d r i s i n g ;when : ” !D&SI ” ;s d f c o n d : ” D EQ 0 AN SI EQ 1 == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;
17
i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}f a l l c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 4 8 7 5 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : h o l d r i s i n g ;when : ”D&! SI ” ;s d f c o n d : ” D EQ 1 AN SI EQ 0 == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}f a l l c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : s e t u p r i s i n g ;when : ” !D&SI ” ;s d f c o n d : ” D EQ 0 AN SI EQ 1 == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \
18
” 0 . 3 1 8 7 5 , 0 . 2 1 3 7 5 , 0 . 0 8 2 5 ” , \” 0 . 3 7 1 2 5 , 0 . 2 6 6 2 5 , 0 . 1 3 5 ” , \” 0 . 4 7 6 2 5 , 0 . 3 7 1 2 5 , 0 . 1 8 3 7 5 ” , \” 0 . 5 5 5 , 0 . 3 9 3 7 5 , 0 . 2 6 2 5 ” , \” 0 . 7 0 5 , 0 . 6 , 0 . 4 6 8 7 5 ” ) ;}f a l l c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 6 5 6 2 5 , 0 . 5 5 1 2 5 , 0 . 3 6 3 7 5 ” , \” 0 . 7 0 8 7 5 , 0 . 6 0 3 7 5 , 0 . 4 1 6 2 5 ” , \” 0 . 8 7 , 0 . 7 0 8 7 5 , 0 . 5 7 7 5 ” , \” 0 . 9 4 8 7 5 , 0 . 8 4 3 7 5 , 0 . 6 5 6 2 5 ” , \” 1 . 3 2 3 7 5 , 1 . 1 6 2 5 , 0 . 9 7 5 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : s e t u p r i s i n g ;when : ”D&! SI ” ;s d f c o n d : ” D EQ 1 AN SI EQ 0 == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 8 2 5 , 0 . 6 6 3 7 5 , 0 . 4 7 6 2 5 ” , \” 0 . 8 7 7 5 , 0 . 7 1 6 2 5 , 0 . 5 8 5 ” , \” 0 . 9 8 2 5 , 0 . 8 7 7 5 , 0 . 6 9 ” , \” 1 . 1 1 7 5 , 0 . 9 5 6 2 5 , 0 . 7 6 8 7 5 ” , \” 1 . 3 8 , 1 . 2 1 8 7 5 , 1 . 0 8 7 5 ” ) ;}f a l l c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 4 3 1 2 5 , 0 . 3 2 6 2 5 , 0 . 1 9 5 ” , \” 0 . 5 4 , 0 . 3 7 8 7 5 , 0 . 2 4 7 5 ” , \” 0 . 6 4 5 , 0 . 5 4 , 0 . 4 0 8 7 5 ” , \” 0 . 7 2 3 7 5 , 0 . 6 1 8 7 5 , 0 . 4 8 7 5 ” , \” 1 . 0 4 2 5 , 0 . 8 8 1 2 5 , 0 . 7 5 ” ) ;}}
}p i n ( SI ) {n e x t s t a t e t y p e : ” s c a n i n ” ;
d i r e c t i o n : i n p u t ;i n p u t s i g n a l l e v e l : RAIL VDD ;c a p a c i t a n c e : 0 . 0 2 0 8 0 4 7 ;r i s e c a p a c i t a n c e : 0 . 0 2 0 2 0 6 6 ;f a l l c a p a c i t a n c e : 0 . 0 2 0 8 0 4 7 ;r i s e c a p a c i t a n c e r a n g e ( 0 .0201587 , 0 . 0 2 9 9 6 5 6 ) ;f a l l c a p a c i t a n c e r a n g e ( 0 .0207946 , 0 . 0 2 9 9 5 6 4 ) ;m a x t r a n s i t i o n : 1 . 2 ;
19
i n t e r n a l p o w e r ( ) {r i s e p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 1 . 8 5 1 2 2 , 1 . 8 7 9 0 5 , 2 . 0 1 4 7 7 , 2 . 1 2 9 7 1 , 2 . 5 7 9 8 7 ” ) ;}f a l l p o w e r ( p a s s i v e e n e r g y t e m p l a t e 5 x 1 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;v a l u e s ( ” 2 . 6 3 5 9 7 , 2 . 6 6 6 7 3 , 2 . 8 2 2 , 2 . 9 5 4 2 5 , 3 . 4 3 9 4 6 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : h o l d r i s i n g ;when : ”SE ” ;s d f c o n d : ”SE == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}f a l l c o n s t r a i n t ( h o l d t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 0 , 0 . 0 , 0 . 0 4 8 7 5 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” , \” 0 . 0 , 0 . 0 , 0 . 0 ” ) ;}}t i m i n g ( ) {r e l a t e d p i n : ”CLK” ;t i m i n g t y p e : s e t u p r i s i n g ;when : ”SE ” ;s d f c o n d : ”SE == 1 ’ b1 ” ;r i s e c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;v a l u e s ( \” 0 . 3 1 8 7 5 , 0 . 2 1 3 7 5 , 0 . 0 8 2 5 ” , \” 0 . 3 7 1 2 5 , 0 . 2 6 6 2 5 , 0 . 1 3 5 ” , \” 0 . 5 3 2 5 , 0 . 3 7 1 2 5 , 0 . 2 4 ” , \” 0 . 5 5 5 , 0 . 4 5 , 0 . 3 1 8 7 5 ” , \” 0 . 8 1 7 5 , 0 . 6 5 6 2 5 , 0 . 5 2 5 ” ) ;}f a l l c o n s t r a i n t ( s e t u p t e m p l a t e 5 x 3 ) {i n d e x 1 ( ” 0 . 0 6 , 0 . 1 8 , 0 . 4 2 , 0 . 6 , 1 . 2 ” ) ;i n d e x 2 ( ” 0 . 0 6 , 0 . 3 , 0 . 6 ” ) ;
20
v a l u e s ( \” 0 . 6 5 6 2 5 , 0 . 4 9 5 , 0 . 3 6 3 7 5 ” , \” 0 . 7 0 8 7 5 , 0 . 6 0 3 7 5 , 0 . 4 1 6 2 5 ” , \” 0 . 8 7 , 0 . 7 6 5 , 0 . 5 7 7 5 ” , \” 1 . 0 0 5 , 0 . 8 4 3 7 5 , 0 . 7 1 2 5 ” , \” 1 . 3 8 , 1 . 2 1 8 7 5 , 1 . 0 8 7 5 ” ) ;}}
}}
}
B foo.v
module SDFF (CLK, D, Q, QB, SE , SI ) ;i n p u t CLK, D, SE , SI ;o u t p u t Q,QB;n o t ( n3 ,CLK ) ;n o t (Q,QB ) ;mux ( n2 , SE , SI ,D ) ;mux ( n1 , n3 , n2 , n1 ) ;imux (QB, n3 , Q, n1 ) ;
endmodule
C Script for DFT
# ∗ Modi f i ed by Anh Luong & Andrze j Forys# ∗ FALL 2012# ∗# ∗ Author : E r i k Brunvand , U n i v e r s i t y o f Utah# ∗# ∗ G e n e r a l s y n t h e s i s s c r i p t f o r Synopsys . There s h o u l d be# ∗ some g e n e r a l s w i t c h e s and p a r a m e t e r s s e t i n . s y n o p s y s d c . s e t u p# ∗ b u t o t h e r des ign−s p e c i f i c t h i n g s a r e s e t h e r e .# ∗ You s h o u l d look c a r e f u l l y a t e v e r y t h i n g above t h e# ∗ ” below h e r e shou ldn ’ t need t o be changed ” l i n e .# ∗# ∗ Note t h a t l i s t s t h a t c o n t i n u e a c r o s s a l i n e need a b a c k s l a s h# ∗ t o c o n t i n u e t o t h e n e x t l i n e ( i f you have a bunch of# ∗ d i f f e r e n t v e r i l o g f i l e s , one p e r l i n e , f o r example , o r a bunch# ∗ of t a r g e t l i b r a r y f i l e s ) . Make SURE t h e r e i s n ’ t a s p a c e a f t e r# ∗ t h e \ b e c a u s e t h a t can c a u s e Synopsys t o compla in . . .# ∗# ∗ Once you ’ ve m o d i f i e d t h i n g s t o your p r o j e c t , i n vo ke wi th :# ∗# ∗ syn−dc −f syn−s c r i p t# ∗# ∗
# Th i s s c r i p t assumes t h a t t h e f o l l o w i n g v a r i a b l e s a r e d e f i n e d# i n t h e . s y n o p s y s d c . s e t u p f i l e . You s h o u l d make s u r e t h a t# your . s y n o p s y s d c . s e t u p f i l e i s c o n f i g u r e d f o r your# c e l l l i b r a r y ! I f you want t o o v e r r i d e o r
21
# add t o t h o s e s e a r c h p a t h s , you can do t h a t h e r e . . .## S y n o p s y s I n s t a l l = p a t h t o s y n o p s ys i n s t a l l a t i o n d i r e c t o r y# s y n t h e t i c l i b r a r y = d e s i g n w a r e f i l e s# s y m b o l l i b r a r y = l o g i c symbols f o r making s c h e m a t i c s#
# s e a r c h p a t h s h o u l d i n c l u d e d i r e c t o r i e s wi th memory . db f i l e s# as w e l l a s t h e s t a n d a r d c e l l s# Your l i b r a r y p a t h may be empty i f your l i b r a r y w i l l be i n# your s y n t h e s i s d i r e c t o r y b e c a u s e ” . ” i s a l r e a d y on t h e p a t h .# s e t s e a r c h p a t h [ l i s t . \#[ f o r m a t ”%s%s ” $ S y n o p s y s I n s t a l l / l i b r a r i e s / syn ] \#[ f o r m a t ”%s%s ” $ S y n o p s y s I n s t a l l / dw / s i m v e r ] \# / uusoc / f a c i l i t y / cad common / l o c a l / Cadence / l i b /OA/ U o f U D i g i t a l v 1 2 ]
# t a r g e t l i b r a r y l i s t s h o u l d i n c l u d e a l l t a r g e t . db f i l e ss e t t a r g e t l i b r a r y [ l i s t U o f U D i g i t a l v 1 2 . db ]
# s y n t h e t i c l i b r a r y i s s e t i n . s y n o p s y s d c . s e t u p t o be# t h e d w f o u n d a t i o n l i b r a r y .s e t l i n k l i b r a r y [ c o n c a t [ c o n c a t ”∗” $ t a r g e t l i b r a r y ] $ s y n t h e t i c l i b r a r y ]
##################################### P r i n t t o s c r e e n o p t i o n s #####################################s e t v e r b o s e 1 ; # 1 Wr i t e r e p o r t s t o s c r e e n , 0 do n o t w r i t e r e p o r t s t o s c r e e ns e t v e r b o s e d f t 1 ; # 1 Wr i t e r e p o r t s t o s c r e e n , 0 do n o t w r i t e r e p o r t s t o s c r e e n
##################################### S y n t h e s i s #####################################
# below a r e p a r a m e t e r s t h a t you w i l l want t o s e t f o r each d e s i g n
# l i s t o f a l l HDL f i l e s i n t h e d e s i g ns e t myFi l e s [ l i s t c o n t r o l l e r . v ]s e t f i l e F o r m a t v e r i l o g ; # v e r i l o g o r VHDLs e t basename c o n t r o l l e r ; # Top− l e v e l module names e t myClk c l k ; # The name of your c l o c ks e t v i r t u a l 0 ; # 1 i f v i r t u a l c lock , 0 i f r e a l c l o c k
# c o m p i l e r s w i t c h e s . . .# s e t o p t i m i z e A r e a 0 ; # 1 f o r a r ea , 0 f o r speeds e t u s e U l t r a 1 ; # 1 f o r c o m p i l e u l t r a , 0 f o r compi l e
# mapEf fo r t , useUngroup a r e f o r# non−u l t r a compi l e . . .
s e t m a p E f f o r t 1 medium ; # F i r s t p a s s − low , medium , o r h ighs e t m a p E f f o r t 2 medium ; # second p a s s − low , medium , o r h ighs e t useUngroup 1 ; # 0 i f no f l a t t e n , 1 i f f l a t t e n
# Timing and l o a d i n g i n f o r m a t i o ns e t myPer iod ns 25 ; # d e s i r e d c l o c k p e r i o d ( s e t s speed g o a l )s e t myClkLatency ns 0 . 3 ; # c l o c k ne twork l a t e n c y
22
s e t myInDelay ns 0 . 2 5 ; # d e l a y from c l o c k t o i n p u t s v a l i ds e t myOutDelay ns 0 . 2 5 ; # d e l a y from c l o c k t o o u t p u t v a l i ds e t myInputBuf INVX4 ; # name of c e l l d r i v i n g t h e i n p u t ss e t myLoadLibrary U o f U D i g i t a l v 1 2 ; # name of l i b r a r y t h e c e l l comes froms e t myLoadPin Y ; # name of p i n t h a t o u t p u t s d r i v e
# C o n t r o l t h e w r i t i n g o f r e s u l t f i l e ss e t runname s t r u c t ; # Name appended t o o u t p u t f i l e s
# t h e f o l l o w i n g c o n t r o l which o u t p u t f i l e s you want . They# s h o u l d be s e t t o 1 i f you want t h e f i l e , 0 i f n o ts e t w r i t e v 1 ; # compi l ed s t r u c t u r a l V e r i l o g f i l es e t w r i t e d d c 0 ; # compi l ed f i l e i n ddc f o r m a t (XG−mode )s e t w r i t e s d f 1 ; # s d f f i l e f o r back−a n n o t a t e d t i m i n g sims e t w r i t e s d c 1 ; # sdc c o n s t r a i n t f i l e f o r p l a c e and r o u t es e t w r i t e r e p 0 ; # r e p o r t f i l e from c o m p i l a t i o ns e t w r i t e p o w 0 ; # r e p o r t f i l e f o r power e s t i m a t e
##################################### DFT S w i t c h e s #####################################s e t d f t r u n n a m e scan ; # name appended t o o u t p u t f i l e ss e t s c a n l i b r a r y [ l i s t foo . db ] ; # L i b r a r y wi th scan c h a i n c e l l s# s e t s c a n c e l l SCANFF ; # Name of ScanFF C e l l
# Se tup t i m i n g v a r i a b l e s f o r d f t d r c commands e t t e s t d e f a u l t d e l a y 0 ; # d e f i n e t ime when v a l u e s a r e a p p l i e d t o i n p u t p o r t ss e t t e s t d e f a u l t b i d i r d e l a y 0 ; # D e f i n e s t h e d e f a u l t s w i t c h i n g t ime of b i d i r e c t i o n a l p o r t s i n a t e s t e r c y c l e .s e t t e s t d e f a u l t s t r o b e 40 ; # d e f a u l t s t r o b e t ime i n a t e s t c y c l e f o r o u t p u t p o r t s and b i d i r e c t i o n a l p o r t s i n o u t p u t modes e t t e s t d e f a u l t p e r i o d 100 ; # D e f i n e s t h e d e f a u l t l e n g t h o f a t e s t v e c t o r c y c l e
# Se tup scan c h a i n f o r i n s e r t d f t# s e t t e s t d e f a u l t s c a n s t y l e m u l t i p l e x e d f l i p f l o p ; # D e f i n e s t h e d e f a u l t s can s t y l e f o r t h e i n s e r t d f t command . t y p e ”man t e s t d e f a u l t s c a n s t y l e ” f o r more i n f o r m a t i o n
#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗#∗ below h e r e shouldn ’ t need t o be changed . . . ∗#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
##################################### remove any o t h e r d e s i g n s from d e s i g n compi l e r ’ s memory####################################r e m o v e d e s i g n − a l l# IMPORTING DESIGN
# a n a l y z e and e l a b o r a t e t h e f i l e sa n a l y z e −f o r m a t $ f i l e F o r m a t − l i b WORK $myFi l e se l a b o r a t e $basename − l i b WORK −u p d a t ec u r r e n t d e s i g n $basename
# The l i n k command makes s u r e t h a t a l l t h e r e q u i r e d d e s i g n# p a r t s a r e l i n k e d t o g e t h e r .# The u n i q u i f y command makes un iqu e c o p i e s o f r e p l i c a t e d# modules .
23
l i n ku n i q u i f y
# SETUP CONSTRAINTS
# now you can c r e a t e c l o c k s f o r t h e d e s i g n# and s e t o t h e r c o n s t r a i n t si f { $ v i r t u a l == 0 } {
c r e a t e c l o c k −p e r i o d $myPer iod ns $myClk} e l s e {
c r e a t e c l o c k −p e r i o d $myPer iod ns −name $myClk}#∗∗∗ add t h i s s h i ts e t c l o c k l a t e n c y $myClkLatency ns $myClk
# S e t t h e d r i v i n g c e l l f o r a l l i n p u t s e x c e p t t h e c l o c k# The c l o c k has i n f i n t e d r i v e by d e f a u l t . Th i s i s u s u a l l y# what you want f o r s y n t h e s i s b e c a u s e you w i l l use o t h e r# t o o l s ( l i k e SOC E n c o u n t e r ) t o b u i l d t h e c l o c k t r e e# ( o r d e f i n e i t by hand ) .i f { $ v i r t u a l == 0 } {
s e t d r i v i n g c e l l − l i b r a r y $myLoadLibrary − l i b c e l l $myInputBuf [ a l l i n p u t s ] \} e l s e {
s e t d r i v i n g c e l l − l i b r a r y $myLoadLibrary − l i b c e l l $myInputBuf \[ r e m o v e f r o m c o l l e c t i o n [ a l l i n p u t s ] $myClk ]
}
# s e t t h e i n p u t and o u t p u t d e l a y r e l a t i v e t o myClki f { $ v i r t u a l == 0 } {
s e t i n p u t d e l a y $myInDelay ns −c l o c k $myClk [ a l l i n p u t s ] \} e l s e {
s e t i n p u t d e l a y $myInDelay ns −c l o c k $myClk \[ r e m o v e f r o m c o l l e c t i o n [ a l l i n p u t s ] $myClk ]
}s e t o u t p u t d e l a y $myOutDelay ns −c l o c k $myClk [ a l l o u t p u t s ]
# s e t t h e l o a d o f t h e c i r c u i t o u t p u t s i n t e r m s of t h e l o a d# of t h e n e x t c e l l t h a t t h e y w i l l d r i v e , a l s o t r y t o f i x# ho ld t ime i s s u e ss e t l o a d [ l o a d o f [ f o r m a t ”%s%s%s%s%s ” $myLoadLibrary ” / ” $myInputBuf ” / ” $myLoadPin ] ] [ a l l o u t p u t s ]s e t f i x h o l d $myClk
# FINISH SETUP CONSTRAINTS
# Th i s command w i l l f i x t h e problem of ha v i ng# a s s i g n s t a t e m e n t s l e f t i n your s t r u c t u r a l f i l e .# But , i t w i l l i n s e r t p a i r s o f i n v e r t e r s f o r f e e d t h r o u g h s !s e t f i x m u l t i p l e p o r t n e t s − a l l −b u f f e r c o n s t a n t s
# COMPILING DESIGN
# now compi l e t h e d e s i g n wi th g i v e n mapping e f f o r t# and do a second compi l e wi th i n c r e m e n t a l mapping# or use t h e c o m p i l e u l t r a meta−command
24
i f { $ u s e U l t r a == 1 } {c o m p i l e u l t r a
} e l s e {i f { $useUngroup == 1 } {
compi l e −u n g o u p a l l −m a p e f f o r t $mapEf fo r t1compi l e −i n c r e m e n t a l m a p p i n g −m a p e f f o r t $mapEf fo r t2
} e l s e {compi l e −m a p e f f o r t $mapEf fo r t1compi l e −i n c r e m e n t a l m a p p i n g −m a p e f f o r t $mapEf fo r t2
}}
#c h e c k d e s i g n# VIOLATIONSr e p o r t c o n s t r a i n t − a l l v i o l a t o r s
#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗#∗ now w r i t e o u t t h e r e s u l t s ∗#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
s e t f i l e b a s e [ f o r m a t ”%s%s ” [ f o r m a t ”%s%s ” $basename ” ” ] $runname ]
# s t r u c t u r a l ( s y n t h e s i z e d ) f i l e a s v e r i l o gi f { $ w r i t e v == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . v ” ]r e d i r e c t change names \{ change names − r u l e s v e r i l o g −h i e r a r c h y −v e r b o s e }
w r i t e −f o r m a t v e r i l o g −h i e r a r c h y −o u t p u t $ f i l e n a m e}
# w r i t e o u t t h e s d f f i l e f o r back−a n n o t a t e d v e r i l o g sim# Th i s f i l e can be l a r g e !i f { $ w r i t e s d f == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . s d f ” ]w r i t e s d f −v e r s i o n 1 . 0 $ f i l e n a m e
}
# t h i s i s t h e t i m i n g c o n s t r a i n t s f i l e g e n e r a t e d from t h e# c o n d i t i o n s above − used i n t h e p l a c e and r o u t e programi f { $ w r i t e s d c == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . sdc ” ]w r i t e s d c $ f i l e n a m e
}
# s y n o ps y s d a t a b a s e f o r m a t i n c a s e you want t o r e a d t h i s# s y n t h e s i z e d r e s u l t back i n t o s y n o p s ys l a t e r i n XG mode ( ddc f o r m a t )i f { $ w r i t e d d c == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . ddc ” ]w r i t e −f o r m a t ddc −h i e r a r c h y −o $ f i l e n a m e
}
# r e p o r t on t h e r e s u l t s from s y n t h e s i s
25
# n o t e t h a t > makes a new f i l e and >> appends t o a f i l ei f { $ w r i t e r e p == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . r e p ” ]r e d i r e c t $ f i l e n a m e { r e p o r t t i m i n g }r e d i r e c t −append $ f i l e n a m e { r e p o r t a r e a }
}
# r e p o r t t h e power e s t i m a t e from s y n t h e s i s .i f { $wr i t e pow == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . pow ” ]r e d i r e c t $ f i l e n a m e { r e p o r t p o w e r }
}
# p r i n t r e p o r t t o t h e s c r e e ni f { $ v e r b o s e == 1 } {
r e p o r t d e s i g nr e p o r t h i e r a r c h yr e p o r t t i m i n g −p a t h f u l l −d e l a y max −nw or s t 3 − s i g n i f i c a n t d i g i t s 2 −s o r t b y groupr e p o r t t i m i n g −p a t h f u l l −d e l a y min −nw or s t 3 − s i g n i f i c a n t d i g i t s 2 −s o r t b y groupr e p o r t a r e ar e p o r t c e l lr e p o r t n e tr e p o r t p o r t −vr e p o r t p o w e r − a n a l y s i s e f f o r t low
}
# Design r e p o r t ss e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . d e s i g n ” ]r e d i r e c t $ f i l e n a m e { r e p o r t d e s i g n }
# H i e r a r c h y r e p o r t ss e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . d e s i g n ” ]r e d i r e c t −append $ f i l e n a m e { r e p o r t h i e r a r c h y }
# Timing r e p o r t ss e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . t i m i n g ” ]r e d i r e c t $ f i l e n a m e { r e p o r t t i m i n g −p a t h f u l l −d e l a y max −nw or s t 5 − s i g n i f i c a n t d i g i t s 2 −s o r t b y group }
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . t i m i n g ” ]r e d i r e c t −append $ f i l e n a m e { r e p o r t t i m i n g −p a t h f u l l −d e l a y min −nw or s t 5 − s i g n i f i c a n t d i g i t s 2 −s o r t b y group }
# R e p o r t c e l ls e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . a r e a ” ]r e d i r e c t $ f i l e n a m e { r e p o r t a r e a }
# R e p o r t a r e as e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . a r e a ” ]r e d i r e c t −append $ f i l e n a m e { r e p o r t c e l l }
# R ep or t p o r ts e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . p o r t s ” ]r e d i r e c t $ f i l e n a m e { r e p o r t p o r t −v}
# R ep or t n e t
26
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . n e t ” ]r e d i r e c t $ f i l e n a m e { r e p o r t n e t }
# R ep or t powers e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . pow ” ]r e d i r e c t $ f i l e n a m e { r e p o r t p o w e r − a n a l y s i s e f f o r t low }
############################################## I n s e r t T e s t S t r u c t u r e s ############################################## Update f i l e b a s es e t f i l e b a s e [ f o r m a t ”%s%s ” [ f o r m a t ”%s%s ” $basename ” ” ] $ d f t r u n n a m e ]
# Update t a r g e t l i b r a r ys e t t a r g e t l i b r a r y [ l i s t $ t a r g e t l i b r a r y $ s c a n l i b r a r y ]
# S e t Scan Chain Types e t s c a n c o n f i g u r a t i o n − s t y l e m u l t i p l e x e d f l i p f l o p
# AutoFix f o r R e s e t and Clocks e t d f t c o n f i g u r a t i o n − f i x r e s e t e n a b l e − f i x c l o c k e n a b l e
# S e t T e s t P r o t o c o ls e t t e s t d e f a u l t p e r i o d 100s e t d f t s i g n a l −view e x i s t i n g d f t −t y p e ScanClock −t i m i n g {45 55} −p o r t c l ks e t d f t s i g n a l −view e x i s t i n g d f t −t y p e R e s e t − a c t i v e s t a t e 1 −p o r t r e s e ts e t d f t s i g n a l −view e x i s t i n g d f t −t y p e C o n s t a n t − a c t i v e s t a t e 1 −p o r t t e s t m o d ec r e a t e t e s t p r o t o c o l
# DFT Checkd f t d r c −v e r b o s e
# Add d e l a y i n g e n e r a t e d c l o c k sc r e a t e c l o c k c l k −p e r i o d 1000s e t i n p u t d e l a y 250 s i −c l o c k c l ks e t i n p u t d e l a y 150 se −c l o c k c l k
# P a r t i a l Scan# s e t s c a n e l e m e n t f a l s e { s t a t e r e g 3 }# s e t s c a n e l e m e n t f a l s e { s t a t e r e g 2 }# s e t s c a n e l e m e n t f a l s e { s t a t e r e g 1 }# s e t s c a n e l e m e n t f a l s e { s t a t e r e g 0 }
# Tes t−Ready S y n t h e s i scompi l e −s can
# Read Design & T e s t P r o t o c o l# Wr i t e o u t t h e t e s t p r o t o c o l and scan−r e a d y d e s i g n# w r i t e t e s t p r o t o c o l −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . s p f ” ]# w r i t e −f o r m a t ddc −h i e r a r c h y −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ]
# Read d e s i g n and t e s t p r o t o c o l# r e a d f i l e −f o r m a t ddc [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ]# c u r r e n t d e s i g n [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ] : $basename
27
# l i n k# r e a d t e s t p r o t o c o l [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . s p f ” ]
# S p e c i f y Scan Chains e t s c a n c o n f i g u r a t i o n −c h a i n c o u n t 1s e t s c a n c o n f i g u r a t i o n −c l o c k m i x i n g no mixs e t d f t s i g n a l −view spec −t y p e ScanDa ta In −p o r t s is e t d f t s i g n a l −view spec −t y p e ScanDataOut −p o r t sos e t d f t s i g n a l −view spec −t y p e ScanEnab le −p o r t s e − a c t i v e s t a t e 1s e t s c a n p a t h c h a i n 1 −s c a n d a t a i n s i −s c a n d a t a o u t so
# Memory Wrapper# s e t t e s t p o i n t e l e m e n t −t y p e o b s e r v e [ g e t o b j e c t n a m e [ g e t p i n s RAM 64B /D∗ ] ] −c l o c k s i g n a l c l k# s e t t e s t p o i n t e l e m e n t −t y p e o b s e r v e [ g e t o b j e c t n a m e [ g e t p i n s RAM 64B /A∗ ] ] −c l o c k s i g n a l c l k# s e t t e s t p o i n t e l e m e n t −t y p e c o n t r o l 0 1 [ g e t o b j e c t n a m e [ g e t p i n s RAM 64B /Q∗ ] ] −c l o c k s i g n a l c l k# r e p o r t t e s t p o i n t e l e m e n t
# Scan Prev iewp r e v i e w d f t −show a l lp r e v i e w d f t − t e s t p o i n t s a l l
# Scan Chain S y n t h e s i si n s e r t d f t
# Scan Chain I d e n t i f i c a t i o ns e t s c a n s t a t e s c a n e x i s t i n g
# DRC & Coveraged f t d r c −c o v e r a g e e s t i m a t e
# R ep or t Scan I n f o r m a t i o nr e p o r t s c a n p a t h −view e x i s t i n g d f t −c h a i n a l lr e p o r t s c a n p a t h −view e x i s t i n g d f t −c e l l a l l
# P r e p a r e TetraMax s c r i p tchange names −h i e r a r c h y − r u l e v e r i l o gw r i t e −f o r m a t v e r i l o g −h i e r a r c h y −o u t [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . v ” ]w r i t e −f o r m a t ddc −h i e r a r c h y −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ]w r i t e s c a n d e f −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . d e f ” ]s e t t e s t s t i l n e t l i s t f o r m a t v e r i l o gw r i t e t e s t p r o t o c o l −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . s p f ” ]
##################################### Qui t dc####################################q u i t
D Script for TetraMax
########################################################################## Modi f i ed by Anh Luong & Andrze j Forys#### U n i v e r s i t y o f Utah#### F a l l 2012
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######## TetraMax S c r i p t f o r ECE 128#### P e r f o r m s ATPG P a t t e r n G e n e r a t i o n f o r Synopsys G e n e r i c f i l e s#### a u t h o r : t j f#### u p d a t e : wgibb , s p r i n g 2010
#### n o t e : t h i s s c r i p t w i l l on ly run i n TMAX TCL mode#### s t a r t tmax l i k e t h i s : tmax − t c l#### s o u r c e t m a x a t p g . t c l##################################################################
################################################################ l o c a l v a r i a b l e s , d e s i g n e r must change t h e s e v a l u e s ################################################################s e t t op modu le c o n t r o l l e rs e t s y n t h e s i z e d f i l e s [ l i s t . / s r c / ${ t op modu le } s c a n . v ]s e t c e l l l i b . / U o f U D i g i t a l v 1 2 . vs e t s c a n l i b . / foo . vs e t s t i l f i l e [ l i s t . / r e p o r t s / ${ t op modu le } s c a n . s p f ]
# C o n t in u e e x e c u t i o n when command r e t u r n s an e r r o r# set command n o a b o r t
b u i l d −f o r c e
##################################################### r e a d i n s t a n d a r d c e l l s and use r ’ s d e s i g n ##################################################### remove any o t h e r d e s i g n s from d e s i g n compi l e r ’ s memoryr e a d n e t l i s t −d e l e t e# r e a d i n s t a n d a r d c e l l l i b r a r yr e a d n e t l i s t $ c e l l l i b − l i b r a r y# r e a d i n scan c e l l l i b r a r yr e a d n e t l i s t $ s c a n l i b − l i b r a r y# r e a d i n use r ’ s s y n t h e s i z e d v e r i l o g coder e a d n e t l i s t $ s y n t h e s i z e d f i l e s
##################################################### BUILD and DRC t e s t model#################################################r e p o r t m o d u l e s − a l lr u n b u i l d m o d e l $ top modu le# i g n o r i n g w a r n i n g s l i k e N20 or B10# S e t STIL f i l e from DFT Compi le rs e t d r c $ s t i l f i l e# run check t o s e e i f s y n t h e s i z e d code v i o l a t e s any t e s t i n g r u l e sr u n d r c
##################################################### G e n e r a t e ATPG ( p a t t e r n s )− f u l l s e q u e n t i a l################################################## c a p t u r e a l l f a u l t s , 9 c a p t u r e c y c l e s# s e t a t p g −c a p t u r e c y c l e s 9 − f u l l s e q a t p g# r e m o v e f a u l t s − a l l
29
r e p o r t s u m m a r i e s f a u l t s p a t t e r n sa d d f a u l t s − a l l# run a t p g i n f u l l s e q u e n t i a l mode f o r b e t t e r f a u l t c o v e r a g er e p o r t s u m m a r i e s f a u l t s p a t t e r n sr u n a t p g f u l l s e q u e n t i a l o n l y# w r i t e o u t p a t t e r n s ( o v e r w r i t e o l d f i l e s )r e p o r t s u m m a r i e s f a u l t s p a t t e r n sw r i t e p a t t e r n s . / s r c / ${ t op modu le } t b p a t t e r n s . v − r e p l a c e − i n t e r n a l −f o r m a t v e r i l o g s i n g l e f i l e −p a r a l l e l 0
##################################################### Outpu t r e p o r t s#################################################r e p o r t p a t t e r n s − a l l >> . / r e p o r t s / ${ t op modu le } . tmax . p a t t e r n sr e p o r t v i o l a t i o n s − a l l >> . / r e p o r t s / ${ t op modu le } . tmax . v i o l a t i o n sr e p o r t f a u l t s −summary −c o l l a p s e d >> . / r e p o r t s / ${ t op modu le } . tmax . c o v e r a g e
##################################################### Analyze F a u l t s################################################## up t o u s e r t o run t h e s e commands , t h e y can i n s p e c t t h e f a u l t s and v a r i o u s r e a s o n s f o r them :# a n a l y z e f a u l t s −c l a s s an# a n a l y z e f a u l t s −c l a s s an −v e r b o s e −max 3# a n a l y z e f a u l t s i n a r e g r e g / p d r e g s c a n 0 / q −s t u c k 1
# E x i t t h e programq u i t
E controller.v
module main ( i n p u t c lk , r e s e t ,i n p u t [ 5 : 0 ] op / / ,/ / i n p u t zero ,/ / o u t p u t r e g memread , memwrite , a l u s r c a , memtoreg , i o r d ,/ / o u t p u t pcen ,/ / o u t p u t r e g r e g w r i t e , r e g d s t ,/ / o u t p u t r e g [ 1 : 0 ] pcsou rce , a l u s r c b , a luop ,) ; / / o u t p u t r e g [ 3 : 0 ] i r w r i t e ) ;
p a r a m e t e r FETCH1 = 4 ’ b0001 ;p a r a m e t e r FETCH2 = 4 ’ b0010 ;p a r a m e t e r FETCH3 = 4 ’ b0011 ;p a r a m e t e r FETCH4 = 4 ’ b0100 ;p a r a m e t e r DECODE = 4 ’ b0101 ;p a r a m e t e r MEMADR = 4 ’ b0110 ;p a r a m e t e r LBRD = 4 ’ b0111 ;p a r a m e t e r LBWR = 4 ’ b1000 ;p a r a m e t e r SBWR = 4 ’ b1001 ;p a r a m e t e r RTYPEEX = 4 ’ b1010 ;p a r a m e t e r RTYPEWR = 4 ’ b1011 ;p a r a m e t e r BEQEX = 4 ’ b1100 ;p a r a m e t e r JEX = 4 ’ b1101 ;p a r a m e t e r ADDIWR = 4 ’ b1110 ; / / added f o r ADDI
p a r a m e t e r LB = 6 ’ b100000 ;
30
p a r a m e t e r SB = 6 ’ b101000 ;p a r a m e t e r RTYPE = 6 ’ b0 ;p a r a m e t e r BEQ = 6 ’ b000100 ;p a r a m e t e r J = 6 ’ b000010 ;p a r a m e t e r ADDI = 6 ’ b001000 ; / / / added f o r ADDI
r e g [ 3 : 0 ] s t a t e , n e x t s t a t e ;/ / r e g p c w r i t e , p c w r i t e c o n d ;
/ / s t a t e r e g i s t e ra lways @( posedge c l k )
i f ( r e s e t ) s t a t e <= FETCH1 ;e l s e s t a t e <= n e x t s t a t e ;
/ / n e x t s t a t e l o g i ca lways @( ∗ )
b e g i nc a s e ( s t a t e )
FETCH1 : n e x t s t a t e <= FETCH2 ;FETCH2 : n e x t s t a t e <= FETCH3 ;FETCH3 : n e x t s t a t e <= FETCH4 ;FETCH4 : n e x t s t a t e <= DECODE;DECODE: c a s e ( op )
LB : n e x t s t a t e <= MEMADR;SB : n e x t s t a t e <= MEMADR;ADDI : n e x t s t a t e <= MEMADR; / / added f o r ADDIRTYPE : n e x t s t a t e <= RTYPEEX;BEQ: n e x t s t a t e <= BEQEX;J : n e x t s t a t e <= JEX ;d e f a u l t : n e x t s t a t e <= FETCH1 ; / / s h o u l d n e v e r happen
e n d c a s eMEMADR: c a s e ( op )
LB : n e x t s t a t e <= LBRD;SB : n e x t s t a t e <= SBWR;
ADDI : n e x t s t a t e <= ADDIWR; / / added f o r ADDDId e f a u l t : n e x t s t a t e <= FETCH1 ; / / s h o u l d n e v e r happen
e n d c a s eLBRD: n e x t s t a t e <= LBWR;LBWR: n e x t s t a t e <= FETCH1 ;SBWR: n e x t s t a t e <= FETCH1 ;RTYPEEX: n e x t s t a t e <= RTYPEWR;RTYPEWR: n e x t s t a t e <= FETCH1 ;BEQEX: n e x t s t a t e <= FETCH1 ;JEX : n e x t s t a t e <= FETCH1 ;
ADDIWR: n e x t s t a t e <= FETCH1 ; / / added f o r ADDId e f a u l t : n e x t s t a t e <= FETCH1 ; / / s h o u l d n e v e r happen
e n d c a s eend
a lways @( ∗ )b e g i n
/ / s e t a l l o u t p u t s t o zero , t h e n c o n d i t i o n a l l y a s s e r t j u s t t h e a p p r o p r i a t e onesi r w r i t e <= 4 ’ b0000 ;p c w r i t e <= 0 ; p c w r i t e c o n d <= 0 ;
31
r e g w r i t e <= 0 ; r e g d s t <= 0 ;memread <= 0 ; memwrite <= 0 ;a l u s r c a <= 0 ; a l u s r c b <= 2 ’ b00 ; a l u o p <= 2 ’ b00 ;p c s o u r c e <= 2 ’ b00 ;i o r d <= 0 ; memtoreg <= 0 ;c a s e ( s t a t e )
FETCH1 :b e g i n
memread <= 1 ;i r w r i t e <= 4 ’ b0001 ; / / change t o r e f l e c t new memorya l u s r c b <= 2 ’ b01 ; / / g e t t h e IR b i t s i n t h e r i g h t s p o t sp c w r i t e <= 1 ; / / FETCH 2 ,3 ,4 a l s o changed . . .
endFETCH2 :
b e g i nmemread <= 1 ;i r w r i t e <= 4 ’ b0010 ;a l u s r c b <= 2 ’ b01 ;p c w r i t e <= 1 ;
endFETCH3 :
b e g i nmemread <= 1 ;i r w r i t e <= 4 ’ b0100 ;a l u s r c b <= 2 ’ b01 ;p c w r i t e <= 1 ;
endFETCH4 :
b e g i nmemread <= 1 ;i r w r i t e <= 4 ’ b1000 ;a l u s r c b <= 2 ’ b01 ;p c w r i t e <= 1 ;
endDECODE: a l u s r c b <= 2 ’ b11 ;MEMADR:
b e g i na l u s r c a <= 1 ;a l u s r c b <= 2 ’ b10 ;
endLBRD:
b e g i nmemread <= 1 ;i o r d <= 1 ;
endLBWR:
b e g i nr e g w r i t e <= 1 ;memtoreg <= 1 ;
endSBWR:
b e g i nmemwrite <= 1 ;i o r d <= 1 ;
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endRTYPEEX:
b e g i na l u s r c a <= 1 ;a l u o p <= 2 ’ b10 ;
endRTYPEWR:
b e g i nr e g d s t <= 1 ;r e g w r i t e <= 1 ;
endBEQEX:
b e g i na l u s r c a <= 1 ;a l u o p <= 2 ’ b01 ;p c w r i t e c o n d <= 1 ;p c s o u r c e <= 2 ’ b01 ;
endJEX :
b e g i np c w r i t e <= 1 ;p c s o u r c e <= 2 ’ b10 ;
endADDIWR: / / new s t a t e f o r a d d i w r i t e b a c k
b e g i nr e g w r i t e <= 1 ;
ende n d c a s e
enda s s i g n pcen = p c w r i t e | ( p c w r i t e c o n d & z e r o ) ; / / program c o u n t e r e n a b l e
endmodule
F expAdd.v
module expAdd ( Ex , Ey , Ez , B ) ;i n p u t [ 7 : 0 ] Ex , Ey ;i n p u t [ 6 : 0 ] B ;o u t p u t [ 7 : 0 ] Ez ;
a s s i g n Ez = Ex + Ey − B ;
endmodule
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