[harvard cs264] 03 - introduction to gpu computing, cuda basics

Lecture #3: GPU Programming with CUDA | February 8th, 2011

Nicolas Pinto (MIT, Harvard) [email protected]

Massively Parallel ComputingCS 264 / CSCI E-292

Administrivia• New here? Welcome!

• HW0: Forum, RSS, Survey

• Lecture 1 & 2 slides posted

• Project teams allowed (up to 2 students)

• innocentive-like / challenge-driven ?

• HW1: out tonight/tomorrow, due Fri 2/18/11

• New guest lecturers!

• Wen-mei Hwu (UIUC/NCSA), Cyrus Omar (CMU), Cliff Wooley (NVIDIA), Richard Lethin (Reservoir Labs), James Malcom (Accelereyes), David Cox (Harvard)

During this course,

we’ll try to

and use existing material ;-)

“ ”

adapted for CS264

Todayyey!!

Objectives

• Get your started with GPU Programming

• Introduce CUDA

• “20,000 foot view”

• Get used to the jargon...

• ...with just enough details

• Point to relevant external resources

Outline

• Thinking Parallel (review)

• Why GPUs ?

• CUDA Overview

• Programming Model

• Threading/Execution Hierarchy

• Memory/Communication Hierarchy

• CUDA Programming

Outline

• Why GPUs ?

• CUDA Overview

Thinking Parallel(last week)

Review

Getting your feet wet

• Common scenario: “I want to make the algorithm X run faster, help me!”

• Q: How do you approach the problem?

• Option 1: wait

• Option 2: gcc -O3 -msse4.2

• Option 3: xlc -O5

• Option 4: use parallel libraries (e.g. (cu)blas)

• Option 5: hand-optimize everything!

• Option 6: wait more

What else ?

How about analysis ?

load_data() foo() bar() yey()

Algorithm X v1.0 Profiling Analysis on Input 10x10x10

sequential in nature

100% parallelizable

Q: What is the maximum speed up ?

load_data() foo() bar() yey()

Algorithm X v1.0 Profiling Analysis on Input 10x10x10

sequential in nature

100% parallelizable

A: 2X ! :-(

You need to...

• ... understand the problem (duh!)

• ... study the current (sequential?) solutions and their constraints

• ... know the input domain

• ... profile accordingly

• ... “refactor” based on new constraints (hw/sw)

9 Some Perspective

Technical Problem to be Analyzed

Direct elimination equation solver

Discretization "A"

Scientific Model "A"

Sequential implementationParallel implementation

Iterative equation solver

Discretization "B"

Consultation with experts

Model "B"

Experiments

Theoretical analysis

Figure 11: The “problem tree” for scientific problem solving. There are many

options to try to achieve the same goal.

from Scott et al. “Scientific Parallel Computing” (2005)

Some PerspectiveThe “problem tree” for scientific problem solving

There are many options to try to achieve the same goal.

Computational Thinking

• translate/formulate domain problems into computational models that can be solved efficiently by available computing resources

• requires a deep understanding of their relationships

adapted from Hwu & Kirk (PASI 2011)

Architecture Algorithms

ParallelComputing

Languages

APPLICATIONS

Figure 3: Knowledge of algorithms, architecture, and languages contributes to ef-

fective use of parallel computers in practical applications.

adapted from Scott et al. “Scientific Parallel Computing” (2005)

Getting ready...

CompilersPatterns

Programming Models

Parallel Thinking

You can do it!

• thinking parallel is not as hard as you may think

• many techniques have been thoroughly explained...

• ... and are now “accessible” to non-experts !

Outline

• Why GPUs ?

• CUDA Overview

Why GPUs?

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slide by Matthew Bolitho

Motivation

Motivation?

Motivation

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Fact: nobody cares about theoretical peak

Challenge: harness GPU power for real application performance

Motivation

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Motivation

Task vs Data ParallelismCPUs vs GPUs

Task parallelism

• Distribute the tasks across processors based on dependency

• Coarse-grain parallelism

Task 1Task 2

Task 4Task 5 Task 6

Task 7 Task 8Task 9

Task 3

Task dependency graph

Task assignment across 3 processors

Task 1

Task 4

Task 7

Task 5

Task 8

Task 2

Task 6

Task 3

Task 9

Data parallelism

• Run a single kernel over many elements–Each element is independently updated–Same operation is applied on each element

• Fine-grain parallelism–Many lightweight threads, easy to switch context–Maps well to ALU heavy architecture : GPU

Kernel P1 P2 P3 P4 P5 Pn…….

…….Data

Task vs. Data parallelismTask vs. Data parallelism

• Task parallel

– Independent processes with little communication

– Easy to use

• “Free” on modern operating systems with SMP

• Data parallel

– Lots of data on which the same computation is being

executed

– No dependencies between data elements in each

step in the computation

– Can saturate many ALUs

– But often requires redesign of traditional algorithms

slide by Mike Houston

CPU vs. GPUCPU vs. GPU

• CPU

– Really fast caches (great for data reuse)

– Fine branching granularity

– Lots of different processes/threads

– High performance on a single thread of execution

• GPU

– Lots of math units

– Fast access to onboard memory

– Run a program on each fragment/vertex

– High throughput on parallel tasks

• CPUs are great for task parallelism

• GPUs are great for data parallelismslide by Mike Houston

GPU Computing?

• Design target for CPUs:• Make a single thread very fast• Take control away from

programmer

• GPU Computing takes adifferent approach:

• Throughput matters—single threads do not

• Give explicit control toprogrammer

Discuss HW1 Intro to GPU Computing

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GPUs ?

From CPUs to GPUs(how did we end up there?)

Intro PyOpenCL What and Why? OpenCL

“CPU-style” Cores

SIGGRAPH 2009: Beyond Programmable Shading: http://s09.idav.ucdavis.edu/

CPU-“style” cores

ALU (Execute)

Fetch/ Decode

Execution Context

Out-of-order control logic

Fancy branch predictor

Memory pre-fetcher

Data cache (A big one)

Credit: Kayvon Fatahalian (Stanford)

Andreas Klockner GPU-Python with PyOpenCL and PyCUDA

Slimming down

ALU (Execute)

Fetch/ Decode

Execution Context

Idea #1:

Remove components that help a single instruction stream run fast

Andreas Klockner GPU-Python with PyOpenCL and PyCUDAslide by

More Space: Double the Number of Cores

Two cores (two fragments in parallel)

ALU (Execute)

Fetch/ Decode

Execution Context

ALU (Execute)

Fetch/ Decode

Execution Context

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Four cores (four fragments in parallel)

ALU (Execute)

Fetch/ Decode

Execution Context

ALU (Execute)

Fetch/ Decode

Execution Context

ALU (Execute)

Fetch/ Decode

Execution Context

ALU (Execute)

Fetch/ Decode

Execution Context

. . . and again

Sixteen cores (sixteen fragments in parallel)

ALU ALU

16 cores = 16 simultaneous instruction streams 17 Credit: Kayvon Fatahalian (Stanford)

→ 16 independent instruction streams

Reality: instruction streams not actuallyvery different/independent

. . . and again

Sixteen cores (sixteen fragments in parallel)

ALU ALU

16 cores = 16 simultaneous instruction streams 17 Credit: Kayvon Fatahalian (Stanford)

→ 16 independent instruction streams

Reality: instruction streams not actuallyvery different/independent

Saving Yet More Space

Recall: simple processing core

Fetch/ Decode

ALU (Execute)

Execution Context

19 SIGGRAPH 2009: Beyond Programmable Shading: http://s09.idav.ucdavis.edu/

Fetch/ Decode

ALU (Execute)

Execution Context

Idea #2

Amortize cost/complexity ofmanaging an instruction streamacross many ALUs

→ SIMD

Fetch/ Decode

ALU (Execute)

Execution Context

Fetch/ Decode

ALU (Execute)

Execution Context

Idea #2

→ SIMD

Add ALUs

Fetch/ Decode

Idea #2:

Amortize cost/complexity of managing an instruction stream across many ALUs

ALU 1 ALU 2 ALU 3 ALU 4

SIMD processing Ctx Ctx Ctx Ctx

Ctx Ctx Ctx Ctx

Shared Ctx Data

Fetch/ Decode

ALU (Execute)

Execution Context

Idea #2

→ SIMD

Add ALUs

Fetch/ Decode

Idea #2:

Ctx Ctx Ctx Ctx

Shared Ctx Data

Add ALUs

Fetch/ Decode

Idea #2:

Ctx Ctx Ctx Ctx

Shared Ctx Data

Idea #2

→ SIMD

Gratuitous Amounts of Parallelism!

128 fragments in parallel

= 16 simultaneous instruction streams 16 cores = 128 ALUs

24 Credit: Kayvon Fatahalian (Stanford)

Example:

128 instruction streams in parallel16 independent groups of 8 synchronized streams

http://www.youtube.com/watch?v=1yH_j8-VVLo

Gratuitous Amounts of Parallelism!

128 fragments in parallel

= 16 simultaneous instruction streams 16 cores = 128 ALUs

24 Credit: Kayvon Fatahalian (Stanford)

Example:

128 instruction streams in parallel16 independent groups of 8 synchronized streams

Andreas Klockner GPU-Python with PyOpenCL and PyCUDA

slide by

Remaining Problem: Slow Memory

Problem

Memory still has very high latency. . .. . . but we’ve removed most of thehardware that helps us deal with that.

We’ve removed

caches

branch prediction

out-of-order execution

So what now?

Idea #3

Even more parallelism+ Some extra memory= A solution!

Problem

We’ve removed

caches

branch prediction

So what now?SIGGRAPH 2009: Beyond Programmable Shading: http://s09.idav.ucdavis.edu/

Hiding shader stalls Time

(clocks) Frag 1 … 8

Fetch/ Decode

Ctx Ctx Ctx Ctx

Shared Ctx Data

ALU ALU ALU ALU

Idea #3

Problem

We’ve removed

caches

branch prediction

So what now?SIGGRAPH 2009: Beyond Programmable Shading: http://s09.idav.ucdavis.edu/

(clocks)

Fetch/ Decode

ALU ALU ALU ALU

1 2 3 4

Frag 1 … 8 Frag 9… 16 Frag 17 … 24 Frag 25 … 32

Idea #3

Hiding Memory Latency

(clocks)

Fetch/ Decode

ALU ALU ALU ALU

1 2 3 4

(clocks)

Runnable

1 2 3 4

(clocks)

Runnable

1 2 3 4

(clocks)

1 2 3 4

Runnable

GPU Architecture Summary

Core Ideas:

1 Many slimmed down cores→ lots of parallelism

2 More ALUs, Fewer Control Units

3 Avoid memory stalls by interleavingexecution of SIMD groups(“warps”)

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Is it free?

Outline

• Why GPUs ?

• CUDA Overview

CUDA Overview

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GPGPU...

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CUDA Advantages over Legacy GPGPU

Random access to memoryThread can access any memory location

Unlimited access to memory

Thread can read/write as many locations as needed

User-managed cache (per block)

Threads can cooperatively load data into SMEM

Any thread can then access any SMEM location

Low learning curve

Just a few extensions to C

No knowledge of graphics is required

No graphics API overhead

NVIDIA Confidential

CUDA Parallel Paradigm

Scale to 100s of cores, 1000s of parallel threadsTransparently with one source and same binary

Let programmers focus on parallel algorithmsNot mechanics of a parallel programming language

Enable CPU+GPU Co-ProcessingCPU & GPU are separate devices with separate memories

NVIDIA Confidential

C with CUDA Extensions: C with a few keywords

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Standard C Code

Parallel C Code

NVIDIA Confidential

Compiling C with CUDA Applications

#$%&'$()*+,-./0(%$/1%/('!!!'2'3

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NVCC(Open64) CPU Compiler

C CUDAKey Kernels

CUDA objectfiles

Rest of CApplication

CPU objectfilesLinker

CPU-GPUExecutable

Modify into Parallel

CUDA code

Compiling CUDA Code

C/C++ CUDAApplication

PTX to Target

Compiler

G80 … GPU

Target code

PTX Code Virtual

Physical

CPU Code

CUDA Software Development

NVIDIA C Compiler

NVIDIA Assemblyfor Computing (PTX)

CPU Host Code

Integrated CPU + GPUC Source Code

CUDA Optimized Libraries:math.h, FFT, BLAS, …

CUDADriver

Profiler Standard C Compiler

GPU CPU

CUDA-gdb

Integrated into gdbSupports CUDA CSeamless CPU+GPU development experienceEnabled on all CUDA supported 32/64bit Linux distrosSet breakpoint and single step any source line Access and print all CUDA memory allocs, local, global, constant and shared vars.

CUDA Development Tools: cuda-gdb

CUDA-GDB in emacs

Parallel Source Debugging

CUDA-gdb in emacs

Parallel Source Debugging

CUDA-gdb in DDD

CUDA-MemCheck

Coming with CUDA 3.0 Release

Track out of bounds and misaligned accesses

Supports CUDA C

Integrated into the CUDA-GDB debugger

Available as standalone tool on all OS platforms.

CUDA Development Tools: cuda-memcheck

Parallel Source Memory CheckerCUDA-

MemCheck

CUDA Visual ProfilerCUDA Development Tools: (Visual) Profiler

Outline

• Why GPUs ?

• CUDA Overview

Programming Model

GPU Architecture

CUDA Programming Model

Connection: Hardware ↔ Programming Model

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Who cares ho

manycore

Program as if there were“infinitely” many cores

Program as if there were“infinitely” many ALUs percore

Consider: Which is easy to do automatically?

Parallel program → sequential hardware

Sequential program → parallel hardware?

Axis 0

HardwareSoftware representation

Really: Group providespool of parallelism to drawfrom.

X,Y,Z order within groupmatters. (Not amonggroups, though.)

Grids can be 1,2,3-dimensional.

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manycore

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

(Kernel: Func-

tion on Grid)

(Work) Group

(Work) Item

or “Block”

or “Thread”

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manycore

Axis 0

(Kernel: Func-

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manycore

Axis 0

(Kernel: Func-

tion on Grid)

(Work) Group

or “Block”

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manycore

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manycore

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

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manycore

Axis 0

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Who cares ho

manycore

Axis 0

Need a pause?

Outline

• Why GPUs ?

• CUDA Overview

Threading Hierarchy

• Kernel– GPU program that runs on a thread grid

• Thread hierarchy– Grid : a set of blocks– Block : a set of warps– Warp : a SIMD group of 32 threads– Grid size * block size = total # of threads

Block 1 Block 2 Block n<diffuseShader>:

sample r0, v4, t0, s0

mul r3, v0, cb0[0]

madd r3, v1, cb0[1], r3

madd r3, v2, cb0[2], r3

clmp r3, r3, l(0.0), l(1.0)

mul o0, r0, r3

mul o1, r1, r3

mul o2, r2, r3

mov o3, l(1.0)

Kernelwarp

. . . . .

warp warp warp warp warp

Some definitions

CUDA Kernels and Threads

Parallel portions of an application are executed on the device as kernels

One kernel is executed at a time

Many threads execute each kernel

Differences between CUDA and CPU threads CUDA threads are extremely lightweight

Very little creation overhead

Instant switching

CUDA uses 1000s of threads to achieve efficiencyMulti-core CPUs can use only a few

Definitions Device = GPU

Host = CPU

Kernel = function that runs on the device

Arrays of Parallel Threads

A CUDA kernel is executed by an array of threadsAll threads run the same code

Each thread has an ID that it uses to compute memory addresses and make control decisions

0 1 2 3 4 5 6 7

float x = input[threadID];

float y = func(x);

output[threadID] = y;

threadID

Thread Batching

Kernel launches a grid of thread blocksThreads within a block cooperate via shared memory

Threads within a block can synchronize

Threads in different blocks cannot cooperate

Allows programs to transparently scale to different GPUs

Thread Block 0

Shared Memory

Thread Block 1

Shared Memory

Thread Block N-1

Shared Memory

Transparent Scalability

Kernel grid

Block 2 Block 3

Block 4 Block 5

Block 6 Block 7

Device Device

Block 0 Block 1 Block 2 Block 3

Block 0 Block 1

Block 2 Block 3

Block 4 Block 5

Block 6 Block 7

Block 0 Block 1

Hardware is free to schedule thread blocks on any processor

A kernel scales across parallel multiprocessors

Kernel grid

Block 2 Block 3

Block 4 Block 5

Block 6 Block 7

Device Device

Block 0 Block 1

Block 2 Block 3

Block 4 Block 5

Block 6 Block 7

Block 0 Block 1

Gratuitous amount of parallelism !

Wake up call !

http://www.youtube.com/watch?v=qRuNxHqwazs

Kernel grid

Block 2 Block 3

Block 4 Block 5

Block 6 Block 7

Device Device

Block 0 Block 1

Block 2 Block 3

Block 4 Block 5

Block 6 Block 7

Block 0 Block 1

8-Series Architecture (G80)

128 thread processors execute kernel threads

16 multiprocessors, each contains

8 thread processors

Shared memory enables thread cooperation

SharedMemory

Multiprocessor

Thread

Processors

SharedMemory

10-Series Architecture

240 thread processors execute kernel threads

30 multiprocessors, each contains

8 thread processors

One double-precision unit

Shared memory enables thread cooperation

ThreadProcessors

Multiprocessor

SharedMemory

Double

• !"#$%&'()*$+',-(..,'.$/',0+(*$12%,$34$.%'()512/$506%1+',-(..,'.$789.:$,;$<=$-,'(.$()-&

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Fermi Architecture

e.g. GTX 480:

Note: GTX 580 has now 512 processors!

39M02: High Performance Computing with CUDA

Hardware MultithreadingHardware Multithreading

Hardware allocates resources to blocks

blocks need: thread slots, registers, shared

memory

blocks don’t run until resources are available

Hardware schedules threads

threads have their own registers

any thread not waiting for something can run

context switching is free – every cycle

Hardware relies on threads to hide latency

i.e., parallelism is necessary for performance

SharedMemory

Hardware Multithreading

memory

SharedMemory

memory

SharedMemory

memory

(clocks)

1 2 3 4

Runnable

Execution Model

Software Hardware

Threads are executed by thread processors

Thread

Thread Processor

Thread Block Multiprocessor

Thread blocks are executed on multiprocessors

Thread blocks do not migrate

Several concurrent thread blocks can reside on one multiprocessor - limited by multiprocessor resources (shared memory and register file)

Grid Device

A kernel is launched as a grid of thread blocks

Only one kernel can execute on a device at one time

Summary

Outline

• Why GPUs ?

• CUDA Overview

Memory/Communication Hierarchy

Example...

The Memory Hierarchy

Hierarchy of increasingly bigger, slower memories:

Registers

L1 Cache

L2 Cache

Virtual Memory

(hard drive)

1 kB, 1 cycle

10 kB, 10 cycles

1 MB, 100 cycles

1 GB, 1000 cycles

1 TB, 1 M cycles

How might data localityfactor into this?

What is a working set?

Intro Basics Assembly Memory Pipelinesadapted from Berger & Klöckner (NYU 2010)

faster

bigger

Example

GPU in PC Architecture

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3+ Gb/s

8 GB/s

25+ GB/s

160+ GB/sto

PC Architecture

modified from Matthew Bolitho

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modified from Matthew Bolitho

PCI not-so-Express Bus

Back to the GPU...

Multiple Memory ScopesPer-thread private memory

Each thread has its own local memoryStacks, other private data

Per-thread-block shared memory

Small memory close to the processor, low latencyAllocated per thread block

Main memoryGPU frame bufferCan be accessed by any thread in any thread block

Thread

Per-threadLocal Memory

Per-blockSharedMemory

Kernel 0

.Per-device

GlobalMemory

Kernel 1

SequentialBlocks

Thread

Kernel 0

.Per-device

GlobalMemory

Kernel 1

SequentialBlocks

Thread Cooperation

The Missing Piece: threads may need to cooperate

Thread cooperation is valuable

Share results to avoid redundant computation

Share memory accesses

Drastic bandwidth reduction

Thread cooperation is a powerful feature of CUDA

Cooperation between a monolithic array of threads is not scalable

Cooperation within smaller batches of threads is scalable

Thread

Kernel 0

.Per-device

GlobalMemory

Kernel 1

SequentialBlocks

Thread

Kernel 0

.Per-device

GlobalMemory

Kernel 1

SequentialBlocks

Per-thread private memoryEach thread has its own local memoryStacks, other private data

Thread

Kernel 0

.Per-device

GlobalMemory

Kernel 1

SequentialBlocks

Per-thread private memoryEach thread has its own local memoryStacks, other private data

Thread

Kernel 0

.Per-device

GlobalMemory

Kernel 1

SequentialBlocks

Kernel Memory Access

Per-thread

Per-block

Per-device

ThreadRegisters

Local Memory

SharedMemory

...Kernel 0

...Kernel 1

GlobalMemory

On-chip

Off-chip, uncached

• On-chip, small

• Fast

• Off-chip, large

• Uncached

• Persistent across kernel launches

• Kernel I/O

Per-thread

Per-block

Per-device

ThreadRegisters

Local Memory

SharedMemory

...Kernel 0

...Kernel 1

GlobalMemory

On-chip

Off-chip, uncached

• On-chip, small

• Fast

• Off-chip, large

• Uncached

• Kernel I/O

Global Memory

Per-thread

Per-block

Per-device

ThreadRegisters

Local Memory

SharedMemory

...Kernel 0

...Kernel 1

GlobalMemory

On-chip

Off-chip, uncached

• On-chip, small

• Fast

• Off-chip, large

• Uncached

• Kernel I/O

Per-thread

Per-block

Per-device

ThreadRegisters

Local Memory

SharedMemory

...Kernel 0

...Kernel 1

GlobalMemory

On-chip

Off-chip, uncached

• On-chip, small

• Fast

• Off-chip, large

• Uncached

• Kernel I/O

Global Memory

Per-device

...Kernel 0

...Kernel 1

GlobalMemory

• Off-chip, large

• Uncached

• Kernel I/O

• Different types of “global memory”

• Linear Memory

• Texture Memory

• Constant Memory

Memory Architecture

Memory Location Cached Access Scope Lifetime

Register On-chip N/A R/W One thread Thread

Local Off-chip No R/W One thread Thread

Shared On-chip N/A R/W All threads in a block Block

Global Off-chip No R/W All threads + host Application

Constant Off-chip Yes R All threads + host Application

Texture Off-chip Yes R All threads + host Application

Managing Memory

CPU and GPU have separate memory spaces

Host (CPU) code manages device (GPU) memory:Allocate / free

Copy data to and from device

Applies to global device memory (DRAM)

Multiprocessor

ChipsetDRAM

Device

Local Memory

GlobalMemory

Multiprocessor

Registers

Shared Memory

Caches

Configurable L1 cache per SM16KB L1$ / 48KB Shared Memory48KB L1$ / 16KB Shared Memory

Shared 768KB L2 cache

Compute motivation:Caching captures locality, amplifies bandwidthCaching more effective than Shared Memory RAM for irregular or unpredictable access

Ray tracing, sparse matrix

Caching helps latency sensitive cases

Register File

Thread

Register File

Thread

L1 Cache / Shared Memory

L2 Cache

Tesla Memory Hiearchy

Fermi Memory Hiearchy

... how do I program these &#*@ GPUs ??

Outline

• Why GPUs ?

• CUDA Overview

CUDA Programming

Managing Memory in CUDA

Per-thread

Per-block

Per-device

ThreadRegisters

Local Memory

SharedMemory

...Kernel 0

...Kernel 1

GlobalMemory

On-chip

Off-chip, uncached

• On-chip, small

• Fast

• Off-chip, large

• Uncached

• Kernel I/O

Kernel Memory AccessReview

Per-thread

Per-block

Per-device

ThreadRegisters

Local Memory

SharedMemory

...Kernel 0

...Kernel 1

GlobalMemory

On-chip

Off-chip, uncached

• On-chip, small

• Fast

• Off-chip, large

• Uncached

• Kernel I/O

Global Memory

Per-device

...Kernel 0

...Kernel 1

GlobalMemory

• Off-chip, large

• Uncached

• Kernel I/O

• Different types of “global memory”

• Linear Memory

• Texture Memory

• Constant Memory

Review

Managing Memory

CPU and GPU have separate memory spaces

Host (CPU) code manages device (GPU) memory:Allocate / free

Copy data to and from device

Applies to global device memory (DRAM)

Multiprocessor

ChipsetDRAM

Device

Local Memory

GlobalMemory

Multiprocessor

Registers

Shared Memory

Review

CUDA Variable Type Qualifiers

!   “automatic” scalar variables without qualifier reside in a register !   compiler will spill to thread local memory

!   “automatic” array variables without qualifier reside in thread-local memory

Variable declaration Memory Scope Lifetime int var; register thread thread

int array_var[10]; local thread thread

__shared__ int shared_var; shared block block

__device__ int global_var; global grid application

__constant__ int constant_var; constant grid application

CUDA Variable Type Performance

!   scalar variables reside in fast, on-chip registers !   shared variables reside in fast, on-chip memories !   thread-local arrays & global variables reside in

uncached off-chip memory !   constant variables reside in cached off-chip memory

Variable declaration Memory Penalty int var; register 1x

int array_var[10]; local 100x

__shared__ int shared_var; shared 1x

__device__ int global_var; global 100x

__constant__ int constant_var; constant 1x

CUDA Variable Type Scale

!   100Ks per-thread variables, R/W by 1 thread !   100s shared variables, each R/W by 100s of threads !   1 global variable is R/W by 100Ks threads !   1 constant variable is readable by 100Ks threads

Variable declaration Instances Visibility int var; 100,000s 1

int array_var[10]; 100,000s 1

__shared__ int shared_var; 100s 100s

__device__ int global_var; 1 100,000s

__constant__ int constant_var; 1 100,000s

GPU Memory Allocation / Release

cudaMalloc(void ** pointer, size_t nbytes)

cudaMemset(void * pointer, int value, size_t count)

cudaFree(void* pointer)

int n = 1024;

int nbytes = 1024*sizeof(int);

int *a_d = 0;

cudaMalloc( (void**)&a_d, nbytes );

cudaMemset( a_d, 0, nbytes);

cudaFree(a_d);

Data Copies

cudaMemcpy(void *dst, void *src, size_t nbytes, enum cudaMemcpyKind direction);

direction specifies locations (host or device) of src and dst

Blocks CPU thread: returns after the copy is complete

Doesn’t start copying until previous CUDA calls complete

enum cudaMemcpyKindcudaMemcpyHostToDevice

cudaMemcpyDeviceToHost

cudaMemcpyDeviceToDevice

Data Movement Example

int main(void)

float *a_h, *b_h; // host data

float *a_d, *b_d; // device data

int N = 14, nBytes, i ;

nBytes = N*sizeof(float);

a_h = (float *)malloc(nBytes);

b_h = (float *)malloc(nBytes);

cudaMalloc((void **) &a_d, nBytes);

cudaMalloc((void **) &b_d, nBytes);

for (i=0, i<N; i++) a_h[i] = 100.f + i;

cudaMemcpy(a_d, a_h, nBytes, cudaMemcpyHostToDevice);

cudaMemcpy(b_d, a_d, nBytes, cudaMemcpyDeviceToDevice);

cudaMemcpy(b_h, b_d, nBytes, cudaMemcpyDeviceToHost);

for (i=0; i< N; i++) assert( a_h[i] == b_h[i] );

free(a_h); free(b_h); cudaFree(a_d); cudaFree(b_d);

return 0;

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

int main(void)

for (i=0, i<N; i++) a_h[i] = 100.f + i;

return 0;

Host Device

Execution in CUDA

Executing Code on the GPU

Kernels are C functions with some restrictions

Cannot access host memoryMust have void return type

No variable number of arguments (“varargs”)Not recursiveNo static variables

Function arguments automatically copied from host to device

Function Qualifiers

Kernels designated by function qualifier:__global__

Function called from host and executed on deviceMust return void

Other CUDA function qualifiers__device__

Function called from device and run on deviceCannot be called from host code

__host__

Function called from host and executed on host (default)__host__ and __device__ qualifiers can be combined to generate both CPU and GPU code

CUDA Built-in Device Variables

All __global__ and __device__ functions have access to these automatically defined variables

dim3 gridDim;

Dimensions of the grid in blocks (at most 2D)

dim3 blockDim;

Dimensions of the block in threads

dim3 blockIdx;

Block index within the grid

dim3 threadIdx;

Thread index within the block

Launching Kernels

Modified C function call syntax:

kernel<<<dim3 dG, dim3 dB>>>(…)

Execution Configuration (“<<< >>>”)

dG - dimension and size of grid in blocks

Two-dimensional: x and y

Blocks launched in the grid: dG.x * dG.y

dB - dimension and size of blocks in threads:

Three-dimensional: x, y, and z

Threads per block: dB.x * dB.y * dB.z

Unspecified dim3 fields initialize to 1

Execution Configuration Examples

kernel<<<32,512>>>(...);

dim3 grid, block;grid.x = 2; grid.y = 4;block.x = 8; block.y = 16;

kernel<<<grid, block>>>(...);

dim3 grid(2, 4), block(8,16);

kernel<<<grid, block>>>(...);

Equivalent assignment using constructor functions

Unique Thread IDs

Built-in variables are used to determine unique thread IDs

Map from local thread ID (threadIdx) to a global ID which can be used as array indices

0 1 2 3 4

blockIdx.x

blockDim.x = 5

threadIdx.x

blockIdx.x*blockDim.x

+ threadIdx.x

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Minimal Kernels

__global__ void minimal( int* a_d, int value)

*a_d = value;

__global__ void assign( int* a_d, int value)

int idx = blockDim.x * blockIdx.x + threadIdx.x;

a_d[idx] = value;

Basics

Increment Array Example

CPU program CUDA program

void inc_cpu(int *a, int N)

int idx;

for (idx = 0; idx<N; idx++)

a[idx] = a[idx] + 1;

int main()

inc_cpu(a, N);

__global__ void inc_gpu(int *a, int N)

int idx = blockIdx.x * blockDim.x

+ threadIdx.x;

if (idx < N)

a[idx] = a[idx] + 1;

int main()

dim3 dimBlock (blocksize);

dim3 dimGrid( ceil( N / (float)blocksize) );

inc_gpu<<<dimGrid, dimBlock>>>(a, N);

Synchronization in CUDA

Host Synchronization

All kernel launches are asynchronouscontrol returns to CPU immediately

kernel executes after all previous CUDA calls have completed

cudaMemcpy() is synchronouscontrol returns to CPU after copy completes

copy starts after all previous CUDA calls have completed

cudaThreadSynchronize()blocks until all previous CUDA calls complete

Host Synchronization Example

// copy data from host to device

cudaMemcpy(a_d, a_h, numBytes, cudaMemcpyHostToDevice);

// execute the kernel

inc_gpu<<<ceil(N/(float)blocksize), blocksize>>>(a_d, N);

// run independent CPU code

run_cpu_stuff();

// copy data from device back to host

cudaMemcpy(a_h, a_d, numBytes, cudaMemcpyDeviceToHost);

Thread Synchronization• __syncthreads()

• barrier for threads within their block

• e.g. to avoid “memory hazard” when accessing shared memory

• __threadfence()

• interblock synchronization

• flushes global memory writes to make them visible to all threads

• CUDA C Programming Guide

• CUDA C Best Practices Guide

• CUDA Reference Manual

• API Reference, PTX ISA 2.2

• CUDA-GDB User Manual

• Visual Profiler Manual

• User Guides: CUBLAS, CUFFT, CUSPARSE, CURAND

http://developer.nvidia.com/object/gpucomputing.html

iPhD one more thingor two...

Life/Code Hacking #1Getting Things Done

Phase 1: Organize

Phase 2: DO

Phase 3: Review

• Notepad + Pen ;-)

• Gmail: labels, shorcuts, quick links and advanced search

• Lists: e.g. Remember the Milk

• Many more: Google “gtd tools”

slide by David Cox

Back pocket slides

GPUHistory

not true!

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4 cores

Libraries

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GPU:card, system

Application SoftwareIndustry Standard C Language

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CUDA Many-core + Multi-core supportCUDA Many-core + Multi-core support

C CUDA Application

Multi-core

CPU C code

Multi-core

gcc and

Many-core

PTX code

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Compiler

Many-core

--multicoreNVCC

Toolkit

CUDA Compiler: CUDA Compiler: nvccnvcc

Any source file containing CUDA language extensions (.cu)must be compiled with nvcc

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Toolkit

CUDA Compiler: CUDA Compiler: nvccnvcc

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-arch sm_13 Enable double precision ( on

compatible hardware)

-G Enable debug for device code

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--maxrregcount <N> Limit the number of registers

-use_fast_math Use fast math library

Toolkit

GPU ToolsGPU Tools

ProfilerAvailable now for all supported OSs

Command-line or GUI

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Memory access parameters

Execution (serialization, divergence)

DebuggerRuns on the GPU

Emulation modeCompile and execute in emulation on CPU

Allows CPU-style debugging in GPU source

Toolkit

CUDA API

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Device ManagementDevice Management

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[harvard cs264] 03 - introduction to gpu computing, cuda basics

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