hctm ece students

8/4/2019 HCTM ECE STUDENTS

1/22

VLSIDESIGN

Astt.Prof.Munish VermaECEDeptt.HaryanaCollegeofTechnology&Management


2/22

Ids versusVds relation

)()(arg

timetransitElectronQchannelininducedeChII csdds ==

)(

)(

vVelocity

LchannelofLength

sd

=

dsEvvelocitybut =

L

VE dsds =

L

V

v

ds=

)1(2

ds

sdV

Lthus

=

sec/240

sec/650

2

2

Vcm

Vcm

p

n

=

=


3/22


oinsgEareaunitechNow =/arg

The non-saturated region: Vds


4/22


( ) )3(2

2

=dsdstgsds

VVVVL

WKIor

thatsoL

WKAlsoor =,

( ) )1.3(2

2

= dsdstgsdsV

VVVIor

D

WL

Ccecapacichannelgate

oins

g

=

tan/

WL

CKhavewillwe

g=

( ) )2.3(2

2

2

=

dsdstgs

gds VVVV

L

CIthatso

WLCCAlso og =,

( ) )3.3(2

2

= dsdstgsodsV

VVVL

WCIthatso


5/22

Ids versusVds relationSaturated region: Vds=Vgs - Vt

( ))4(

2

2

tgs

ds

VV

L

WKI

=

( ) )1.4(22

tgsds VVIor =

( ) )2.4(2

2

2 tgs

g

ds VVL

CIor =

( ) )3.4(2

2

tgsods VVL

WCIor =


6/22

MOStransistortransconductancegm &O/Pconductancegds

Transconductance expresses the relationship between output current Ids& the inputvoltage Vgs. tconsV

V

Ig dsgs

dsm tan==

we know,

QcIds =

Thus change in currentds

dsQc

I

=

Now,ds

ds

V

L

2

=

Thus2

L

QcVI dsds

=

but change in chargegsgc VCQ

=

so that2

L

VVCI

dsgsg

ds

=

Now, 2L

VC

V

I

g

dsg

gs

ds

m

==


7/22

MOStransistortransconductancegm &O/Pconductancegds

In saturation

( )tgsg

m

tgsds

VVL

Cg

VVV

=

=

2

substituting forD

WLC oinsg =

)( tgsoins

m VVL

W

Dg =

The output conductance gds can be expressed as:

21

==

LV

Ig

gs

dsds


8/22

MOStransistorfigureofmerit o:

=== sdtgs

gmo VV

LC

g

1)(2

switching speed depends on gate voltage above threshold and on carrier mobility

and inversely as the square of channel length.


9/22

ThenMOSinverter

Vout

Vdd = 5V

VdspdVin

[Vthpu = -0.6Vdd = -3V]

[Vthpd = 0.2Vdd = +1V]

(W/L)pu

(W/L)pd

Vgspu

Vgspd

Vgspu= 0 always (nMOS)Gate tied to source

Vdspu

I

pullup tx :depletionmodetransistor (onatVgs=0V)pulldown tx :enhancementmodetransistor (offatVgs=0V,onatVgs>Vthpd)

Vth :devicethreshold(ON)voltage,valueofVgswhendevicebeginstoconductfromdraintosource


10/22

IdealInverterVoltageTransferCharacteristic

Ideal inverter characteristic :V

OH= V

dd(5V)

VOL = OV

Vout

Vdd

Vinv

o Vinv Vdd

Vinv (inverter switching threshold voltage) - point where Vout = Vin


11/22

PracticalInverterVoltageTransferCharacteristic

In practice the pull-down device behaves differently than an ideal switch.It generally exhibits a leakage current in the off state, a finite resistance

in the on state and a transition region where the switch can neither be

considered as ON or OFF. This deviation from the ideal leads to a nonideal transfer characteristics


12/22

In practice, nMOS inverter transfer characteristic is not idealVOL 0Slope < and is affected by ratio

..

..

..

..

dp

up

dp

up

Z

Z

LW

L

W

=


13/22

Zpu/Zpd ratiofornMOSinverterdrivenbyanothernMOS

inverter

For depletion mode devices, Vgs=0; V inv = 0.5VDD at this point both transistors are in saturation

In the depletion mode

In the enhancement mode

Equating (since currents are the same) we have

( )2

2tgsds

VV

L

WKI =

( ) 0sin2

2

..

.. == gstd

up

upds Vce

VLWKI

( ) invgstinvdp

dpds VVceVV

LWKI == sin

2

2

..

..

( ) ( )2..

..2

..

..td

up

uptinv

dp

dp VLWVV

LW =


14/22

Zpu/Zpd ratiofornMOSinverterdrivenbyanothernMOS

inverter

Define

We have

Whence

Substituting typical values

..

..

....

..

.. ; up

up

updp

dp

dp W

L

ZW

L

Z==

( ) ( )2..

2

..

11td

uptinv

dp

VZ

VVZ

=

dpup

tdtinv

ZZ

VVV

... /=

)arg(5.0

6.02.0 ;

insmequalforVV

VVVV

DDinv

DDtdDDt

=

==

dpup ZZ ... /6.02.05.0 +=

1/4/2/ ...... == dpupdpup ZZthusZZ


15/22

Zpu/Zpd ratiofornMOSinverterdriventhroughoneormore

passtransistors

connection of pass transistor will degrade the logic 1 level into inverter 2

Critical case is when A is at 0 volts.

Vdd Vdd

A B C

Inverter 1 Inverter 2

Vin1 Vout

Inverter 1 with input=VDD inverter 2 with input=VDD-Vtp


16/22

for the p.d. transistor

( )

=

2

21

11..

1.. ds

dstDDdp

dp

ds

VVVV

L

WKI

Therefore

==

2

11

11..

1..11

dstDDdp

dp

ds

ds

VVVW

L

KI

VR

Vds1 is small and Vds1/2 can be ignored. So,

= tDDdp VVZKR

111..1

for the p.u. transistor in saturation with Vgs=0

( )2

2

1..

1..

1td

up

up

ds

V

L

W

KII

==

The product I1R1=Vout1 ,Thus

( )2

1

2

1..

1..111 td

tDDup

dpout VVVZ

ZRIV

==


17/22

=

ttpDD

dpVVV

ZK

R)(

112..2

( )2

12

2..2

td

up

V

ZKI

=

Thus ( )2

1 2

2..

2..222

td

ttpDDup

dpout

V

VVVZ

ZRIV

==

For two outputs' to be equal Vout1=Vout2. therefore

( )( )ttpDD

tDD

dp

up

dp

up

VVV

VV

Z

Z

Z

Z

=

1..

1..

2..

2..

taking typical values DDtpDDt VVVV 3.0;2.0 ==

=5.0

8.0

1..

1..

2..

2..

dp

up

dp

up

Z

Z

Z

Z

1

82

1..

1..

2..

2..==

dp

up

dp

up

Z

Z

Z

Z


18/22

Vss

Vdd

Vo

Vin

R Pull-Up

Pull Down

Alternativeformofpullupckt:

Basic Inverter: Transistor with sourceconnected to ground and a load resistorconnected from the drain to the positive

supply railOutput is taken from the drain and controlinput connected between gate and ground

Resistors are not easily formed insilicon- they occupy too much area

Transistors can be used as the pull-updevice


19/22

Vdd

Vss

Vo

Vin

D

S

D

S

Pull-Up is always on Vgs = 0; depletion

Pull-Down turns on when Vin > Vt

With no current drawn from outputs, Idsfor both transistors is equal

NMOSDepletionModeTransistorPull Up:

Vin

VtV0 Vdd

Non-zero output


20/22

NMOSEnhancementModeTransistorPull Up:

Vss

Vo

Vin

S

D

S

Vdd

Vgg

Vt (pull down)

V0

VddVt (pull up)

Non zero output

Vin

Dissipation is high since current flows when Vin = 1

Vout can never reach Vdd (effect of channel)

If Vgg is higher than Vdd, and extra supply rail is required


21/22

Both On

Vout

Vin

VddVss

Vtn Vtp

P on

N off

N on

P off

1 2 3 4 5

Vin

1: Logic 0 : p on ; n off

5: Logic 1: p off ; n on

2: Vin > Vtn.Vdsn large n in saturationVdsp small p in resistiveSmall current from Vdd to Vss

4: same as 2 except reversed p and n

3: Both transistors are in saturationLarge instantaneous current flows

CMOStransistor


22/22

Current through n-channel pull-down transistor

( )22

tninn

dsn VVI =

Current through p-channel pull-up transistor

( )22

tpDDinp

dsp VVVI =

At logic threshold, Idsn= -Idsp

( ) ( )( )

( ) ( )( )

( )

tpDDtnp

n

p

n

in

tpDDintninp

n

tpDDinp

tninn

tpDDinp

tninn

VVVV

VVVVV

VVVVV

VVVVV

++=

+

++=

+=

+=

1

22

22

22

p

n

p

n

tntpDD

in

VVVV

+

++=

1

If n=p and Vtp= Vtn

2

DDin

VV =

n

nn

p

pp

L

W

L

W =

Mobilities are unequal : n = 2.5 p

n

n

p

p

L

W

L

W5.2=

CMOStransistor

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